Anna University (Syllabus) V Semester (EEE) Linear Integrated Circuits Two Marks
Anna University (Syllabus) V Semester (EEE) Linear Integrated Circuits Two Marks
Anna University (Syllabus) V Semester (EEE) Linear Integrated Circuits Two Marks
V Semester (EEE)
LINEAR INTEGRATED CIRCUITS
Two marks
UNIT II
5. Define CMRR.
Common Mode Rejection Ratio (CMRR) is defined as the ratio of difference
mode gain to common mode gain. Its ideal value is infinity, and it is given by,
CMRR = | Ad| / |Ac|.
Where Ad is difference mode gain and
Ac is common mode gain.
6. Define PSRR.
Power Supply Rejection Ratio (PSRR) is defined as the change in op-amp’s input
offset voltage due to variations in supply voltage. It is expressed in microvolt per volt or
in db.
8. Draw and explain the internal block diagram of typical op-amp circuit.
The internal block diagram of typical op-amp circuit is given below:
1. Differential
2. The buffer isamplifiers
usually anare used follower
emitter to provide high input
whose gain impedance is very high.
It prevents loading of high gain stage
3. The output driver is usually provided to give low output impedance
UNIT III
Analog multiplier and PLL
22. What will be the output frequency if a Phase Locked Loop (PLL) frequency
translator has a center frequency of ‘f’ and input frequency of ’f1’?
The output frequency is f+f1.
23. What are the main advantages of using low pass filter in PLL circuits?
Main advantages of using low pass filter:
1. The low pass filter used in PLL not only removes the high frequency
components and noise, but also controls the dynamic characteristics of
PLL.
2. The charge on the filter capacitor gives a short time memory to the
PLL. Thus, even if the signal becomes less than the noise for a few
cycles, the dc voltage on the capacitor continues to shift the frequency
of the VCO till it picks up the signal again.
24. Why is the capture range of PLL dependant upon low pass filter (LPF)
characteristics?
The capture range of PLL depends on low pass filter characteristics because it
removes the high frequency components and noise ,as the bandwidth reduces the
capture range of PLL is also get reduced.
UNIT II
UNIT – IV
Analog to digital and digital to analog converters
11. The input stage of any data acquisition system will be sample and hold circuit.
14. How many total number of clock pulses required for 8-bit successive-
approximation type A/D converter?
The total number of clock pulses required for 8-bit successive-approximation A/D
converter is 8.
UNIT V
SPECIAL FUNCTION ICs
22. Where does the thermal noise occur? What is the cause?
Thermal noise occurs in all passive resistors including the stray series
resistances of practical inductors and capacitors. Thermal noise is due to the random
thermal motion of electrons.