Formula Sheet - ECE 342 Midterm 2 - Summer 2 2003 Diode: Q KT V

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Formula Sheet – ECE 342 Midterm 2 – Summer 2 2003

Diode   kT
i D  I s e v D nVT  1 , where VT  q is 25 mV at room temperature

+ vD - rd

iD id
nVT
small-signal model: rd 
ID

MOSFET, large-signal characteristics

NMOS iD = PMOS
vGS  Vt 0 vGS  Vt
vGS  Vt ,  v2  vGS  Vt ,
k   vGS  Vt   v DS  DS 
v DS  vGS  Vt  2  v DS  vGS  Vt
vGS  Vt , k vGS  Vt ,
  vGS  Vt  2  1 |   v DS |
v DS  vGS  Vt 2 v DS  vGS  Vt

G G

D S S D
iD iD
Vt  Vt 0    
2 f  v SB  2 f , nmos
Vt  Vt 0   2 f  v SB  
2 f , pmos ( > 0, in accordance with standard practice)
W
k  k '
L
Digital Logic
Noise margins: NML = VIL – VOL, NMH = VOH - VIH

Power: P  PStatic  PDynamic ,


PStatic  VDD   p OL  I DD  OL   p OH   I DD  OH   ,
PDynamic  C L  f  V DD
2
where OL (OH) refers to the output low (high) state, p() refers to
probability, and f is the frequency at which the output switches.

1.7  C L 1.7  C L
CMOS inverter propagation delay: t PHL  ; t PLH 
k n  VDD k p  VDD
kn
VDD  Vtp   Vtn
kp
CMOS inverter switching threshold (VIN = VOUT = VM): VM 
kn
1
kp
MOSFET small-signal model
1 V g m
g m  k  VGS  Vt   2 k I D , ro   A , g mb 
  ID ID 2  | 2 f |  | V BS |

g d
+ gmvgs ro gmbvbs
vgs
- s
-
vbs
+
b

BJT, forward-active characteristics (for npn (pnp): vBE (vEB)  0.7 V, vCB (vBC)  0)
v BE v BE
VT  v  i
  I s e VT , i B  C ,  
 i
iC  I s e  1  CE , iE  C
 VA    1 

iC iE
iB iB

iE iC
npn pnp
BJT, small-signal model
ib ic
b c

+
r gmvbe ro
vbe
-

ie
e
IC  V V 
gm  , r  , ro  A , re  T 
VT gm IC I E gm

Hybrid- Model

c
ic
ie
ib
b

ie re

e
T-model
(ro may be connected between collector and emitter terminals, if significant.)

Differential amplifier
v v v
v I 1  vCM  D  VCM  vcm  d (assumed VD = 0), v I 2  VCM  vcm  d
2 2 2

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