Interconnection Structures

 A computer consists of a set of components

(CPU,memory,I/O) that communicate with
each other.
 The collection of paths connecting the
various modules is call the interconnection
structure.
 The design of this structure will depend on
the exchange that must be made between
modules.

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 Input/Output for each module
Read
Read
Write Memory
N Word Write Internal
0 Data Data
Address .
. Address External
Data . I/O Module Data
N-1 M Ports
Internal
Data
Interrupt
Signal
External
Data

Instructions
Data
Interrupt Signal CPU Control
Signal
Data
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Type of transfers
 Memory to CPU
 CPU to Memory
 I/O to CPU
 CPU to I/O
 I/O to or from Memory (DMA)

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Bus Interconnection
 A bus is a communication pathway
connecting two or more device.
 A key characteristic of a bus is that it is a
shared transmission medium.
 A bus consists of multiple pathways or lines.
 Each line is capable of transmitting signal
representing binary digit (1 or 0)

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Bus Interconnection
 A sequence of bits can be transmit across a
single line.
 Several lines can be used to transmit bits
simultaneously (in parallel).
 A bus that connects major components
(CPU,Memory,I/O) is called System Bus.
 The most common computer interconnection
structures are based on the use of one or
more system buses.

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Bus Structure
 A system bus consists of 50-100 lines.
 Each line is assigned a particular meaning or function.
 On any bus the lines can be classified into 3 groups
 Data lines
 Address lines
 Control lines

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Data Lines
 Provide a path for moving data between system
modules.
 These lines, collectively, are called the data bus
 The data bus typically consists of 8,16 or 32
separate lines, the numbers of lines being
transferred to as the width of the data bus.
 Each line carry only 1 bit at a time, the number of
lines determines how many bits can transferred at
a time - overall system performance.

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The Address Lines
 Used to designate the source or
destination of the data on the data bus
 The width of the address bus
determines the maximum possible
memory capacity of the system.

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The Control Lines
 Used to control the access to and the use
of the data and address lines.
 Typical control lines include
 Memory write
 Memory read
 Bus request
 I/O write  Bus grant
 I/O read  Interrupt request
 Clock  Interrupt ACK
 Reset  Transfer ACK

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The operation of the bus
If one module wishes to send data
 obtain the use of the bus
 transfer data via the bus
If one module wishes to request data
 obtain the use of the bus
 transfer request to the other module over the
control and address lines, then wait for that
second module to send the data.

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Physical Bus Architecture
 System bus is a number of
parallel electrical conductors.
 The conductors are metal
lines etched in a card or
printed circuit board.
 The bus extends across all of
the components tat taps into
the bus lines.

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Multiple-Bus Hierarchies
 More devices attached to bus, propagation
delays affect performance
 How to arbitration arbitration?

 Bottleneck as the aggregate data

transfer demand approaches capacity of
bus.
(e.g graphics & video controller)
 How to increase bus?

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 Traditional Bus Architecture
 Local bus
 CPU - Cache
 System bus
 Main memory - Cache
 Expansion bus
 I/O Modules - Main memory

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 High-Performance Architecture

 Local bus
 CPU - Cache/bridge
 System bus
 Cache/bridge - memory
 High-speed bus
 High-speed I/O module - Cache/bridge
 Expansion bus
 Low-speed I/O modules - Expansion interface
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 Bus Design
 Type  Method of Arbitration
 Dedicated  Centralized
 Multiplexed 
Distributed
 Bus Width  Data Transfer Type
 Address
 Read
 Data
 Write
 Timing  Read-modify-write
 Synchronous  Read-after-write
 Asynchronous
 Block
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Type
 Dedicated
permanent assigned bus either
to one function or to a physical
subset of computer components
 Multiplexed
use in the same bus for
multiple purpose (Time Multiplexing)

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Bus Width
 Address
the wider of address bus
has an impact on range of
locations that can be referenced
 Data
the wider of data bus
has an impact on the number
of bits transferred at one time

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Timing
 Synchronous  Asynchronous

occurrence occurrence
of events on the bus of one event
is determined by a follows and
clock (Clock Cycle or depends on the
Bus Cycle) which previous event.
includes line upon

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Method of Arbitration
 Centralized  Distributed
bus controller access control
(Arbiter), hardware
device,is responsible logic in each module
for allocating time act together to share
on the bus (daisy bus
chain)

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Data Transfer Type
 Read
Multiplexed bus is used to
specifying address and then for
transferring data after a wait while
data is being fetched
 Read
Dedicated address is put
on bus and remain there while data
are put on the data bus
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Data Transfer Type
 Write Multiplexed
bus is used to specifying address
and then transferring data (same as
read operation)
 Write Dedicated
data put on data bus as soon
as the address has stabilized

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Data Transfer Type
 Read-modify-write
address is broadcast once at beginning a
simply read is followed immediately by a write to
the same address
 Read-after-write
a write followed immediately by a read
from the same address,performed for checking
purposes

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Data Transfer Type
 Block
one address cycle is
followed by n data cycles.

The first data item is transferred to

or from the specified address;
remainder data items are
transferred to or from subsequent
addresses
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Data Transfer Type

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Samples of Bus
 ISA (Industry Standard Architecture)
 MCA (Micro Channel Architecture)
 EISA (Extended ISA)
 VL Bus (VESA Local Bus)
 PCI Bus (Peripheral Connection
Interface)

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Industry Standard Architecture
 ISA is a standard bus (computer
interconnection) architecture that is
associated with the IBM AT motherboard.
 It allows 16 bits at a time to flow
between the motherboard circuitry and
an expansion slot card and its associated
device(s).

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Industry Standard Architecture

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A "local bus" is a physical
path on which data flows at
almost the speed of the
microprocessor, increasing
total system performance.
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Micro Channel Architecture
 Developed by IBM for its line of PS/2 desktop
computers, MCA is an interface between a
computer (or multiple computers) and its
expansion cards and their associated devices.
 MCA was a distinct break from previous bus
architectures such as ISA.
 The pin connections in MCA are smaller than other
bus interfaces. For this and other reasons, MCA
does not support other bus architectures.

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Micro Channel Architecture
(cont.)
 Although MCA offers a number of
improvements over other bus
architectures, its proprietary,
nonstandard aspects did not encourage
other manufacturers to adopt it.
 It has influenced other bus designs and
it is still in use in PS/2s and in some
minicomputer systems.
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Extended Industry Standard
Architecture
 EISA is a standard bus architecture that
extends the ISA standard to a 32-bit
interface. It was developed in part as an
open alternative to the proprietary
Micro Channel Architecture (MCA) that
IBM introduced in its PS/2 computers.
 EISA data transfer can reach a peak of
33 megabytes per second
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VESA Local Bus
 VESA VL bus is a standard interface
between your computer and its expansion
slot that provides faster data flow between
the devices controlled by the expansion
cards and your computer's microprocessor.
 A "local bus" is a physical path on which
data flows at almost the speed of the
microprocessor, increasing total system
performance.
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VESA Local Bus (cont.)
 VESA Local Bus is particularly effective in
systems with advanced video cards and
supports 32-bit data flow at 50 MHz
 A VESA Local Bus is implemented by adding
a supplemental slot and card that aligns
with and augments an ISA expansion card.
(ISA is the most common expansion slot in
today's computers.)

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Peripheral Component
Interconnect
 PCI is an interconnection system
between a microprocessor and attached
devices in which expansion slot are
spaced closely for high speed operation.
 Using PCI, a computer can support both
new PCI cards while continuing to
support ISA expansion cards, currently
the most common kind of expansion
card.

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Peripheral Component Interconnect
(cont.)
 Designed by Intel, the original PCI was similar to the
VESA Local Bus.
 PCI2.0 is no longer a local bus and is designed to be
independent of microprocessor design.
 PCI is designed to be synchronized with the clock
speed of the microprocessor, in the range of 33 to
66 MHz.
Standard : Up to 64 data-lines at 66 MHz. Raw
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

transfer rate of 528 MBps or 4.224 Gbps.

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Peripheral Component Interconnect
(cont.)
 PCI is now installed on most new
desktop computers, not only those
based on Intel's Pentium processor but
also those based on the PowerPC.
 PCI transmits 32 bits at a time in a 124-
pin connection (the extra pins are for
power supply and grounding) and 64
bits in a 188-pin connection in an
expanded implementation. no

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Peripheral Component Interconnect
(cont.)
 PCI uses all active paths to transmit
both address and data signals, sending
the address on one clock cycle and data
on the next.
 PCI deliver better system performance
for high-speed I/O subsystems
e.g. graphic display adapters, network
interface controllers, disk controllers

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 PCI

A Single-processor System

A Multiprocessor System

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Interface
Port No port
 Serial  Infrared
 Parallel  Bluetooth
 PS/2

 PCMCIA

 USB

(Universal Serial
Bus)

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Universal Serial Bus
 Standard bus which is invented by a group of companies :
Compaq, DEC, IBM, Intel, Microsoft, NEC, Northern
Telecom, etc.
 Not change switch, jumper on board or other devices
 Can use the same cable
 Device that use USB can use power supply from PC.
 Up to 127 devices connected off single port
 Support real-time system
 Hot Plug-in
 Low cost

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Multi-System Buses

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Accelerated Graphics Port
 AGP is an interface specification that enables 3-D
graphics to display quickly on ordinary PC.
 AGP is an interface designed to convey 3-D images
(ex:-from Web sites or CD-ROMs) much more quickly
and smoothly than is possible today on any computer
other than an expensive graphics workstation.
 The interface uses your computer's main storage
(RAM) for refreshing the monitor image and to support
the texture mapping, z-buffering, and alpha blending
required for 3-D image display.

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no

Accelerated Graphics Port (cont.)

 The AGP main memory use is dynamic, meaning that when not
being used for accelerated graphics, main memory is restored
for use by the operating system or other applications.
 Intel, which has taken the lead in developing its specifications,
introduced AGP into a chipset for its Pentium microprocessor.
 The newer, faster microchips in Pentium line are designed to
work with the AGP chipset. Intel says the advanced floating
point unit and faster cache algorithm of the more advanced
Pentiums are better adapted for 3-dimensional applications.

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