Kerrynn de Roché

How Arizona close the gap for semiconductor workforce Today, semiconductors are the most indispensable commodity around the world. “No product is more central to international trade than semiconductors,” Chris Miller wrote in his 2022 book Chip War: The Fight for the World’s Most Critical Technology. Concern about the U.S.’s decades-long decline in its share of global semiconductor manufacturing has prompted bipartisan action at the highest levels of government. In response, some states have sprung into action. The types of innovations and partnerships taking root in the U.S. are prevalent in Arizona, the state that’s attracted the most semiconductor investment. A Robust Talent Pipeline With its vast expanses of open land, booming population, and minimal natural disasters, the Grand Canyon State offers near-perfect conditions for advanced manufacturing to thrive. It also boasts a robust semiconductor presence, with an established talent pipeline and supply chain. Arizona leads the nation in new semiconductor ecosystem investment, with more than $102 billion announced since the CHIPS Act took effect. During this time, companies have launched over 40 projects, generating more than 15,700 industry jobs. The state uses its networks and education assets to launch its many training programs, such as the Semiconductor Technician Quick Start program, a 10-day, 40-hour boot camp taught by industry professionals. Upon completion, students are guaranteed a job interview at one of the state’s industry leaders, including TSMC and Intel.

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Might be the heat or the lack of school for my daughter, but I find myself asking weird questions for an engineer lately, about sales and that stuff. Might also be because of the sector where I am, electronics, where open-source is starting to spearhead its way (and things like Altium selling to Renesas is pushing it). Might even be that as a software developer I am used to open-source programs and I almost always find the commercial option to be inferior in every aspect. But I wonder: how do salespeople from companies that sell expensive software manage to do their work when they know there are alternatives that are free and open source? I am not talking about cases where the commercial software is adding value over the open-source, as for example the case of TRAFOLO Magnetics - FEM Simulation Software I am talking about cases like KiCAD, FreeCAD, Blender, Verilator, etc., where the open-source alternative is as good as the commercial one (I would have loved to add OpenMagnetics there, but it’s not there. Yet. Soon). These salespeople must be aware they are asking money for something that others are giving away for free. How do they do it? They try to hide the FOSS option? They argue they offer better support (which is not true in most cases I have known)? Don’t get me wrong, I admire their tenacity and professionalism, the only reason I ask is because I believe that is one leg where the open-source software tends to lack (software engineers are not the most talented salespeople :D ) and that understanding the sales process of commercial software will help us create better products. Also, I always wanted an excuse to share one of my favorite scenes from the Simpsons :) So, in your experience, dear reader, how?

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At his keynote at the Cadence Design Systems Verification Day in Israel this week, Ziyad Hanna, reviewed the different new tools and applications where Cadence makes use of #ArtifitialIntelligence to automate and ease the life of Verification Engineers. Out of the many ideas, I'd like to highlight one that is not directly promoting a specific Cadence tool, but in my view gives great insights on #AI's opportunities and limitations: For Design RTL, GenAI tools currently give very poor results. Most output doesn't even compile, not to mention the poor quality of silicon (QoS). Therefore Ziyad suggested two possible paths: 1) Use GenAI to generate "hardware-friendly" C++ and then use a HLS tool to synthesize it. Not only GenAI does a better job with C++ than with other design languages, but also one can drive QoS results with the HLS of choice. 2) As an alternative, feed GenAI with an existing RTL and ask for modifications. The room for error is smaller in this case. As a matter of fact, this seems to be a good recipe for using AI in many other applications, not just #chipdesign: Get GenAI to make a first version and then use other tools (or manually) tune it. Alternatively, give #GenAI a first version you've done yourself and ask it to improve it for you. Dani Wunsh, Shayna Kessler and Cadence Israel team - congrats on a great event! (While at that, I looked for an AI app that would sharpen the text on my blurred picture below but couldn't find one...ideas?)

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Before I worked in the #semiconductorindustry, I worked as a civil engineer. I found this article about CalTrans using #AI to answer complex traffic-related questions fascinating. "Caltrans says the data generated from traffic sensors and cameras — coupled with the continuous velocity of data generation and the variety of videos, images, log files, third-party data streams and guidance — poses challenges for humans to digest and utilize." Sounds a bit like using #AI and #ML for smarter #scheduling in a #waferfab, doesn't it? More #industrialengineering than civil engineering.

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Here's a counterintuitive way to get more done. ✍🏼 Let me know how it works ♻️ Repost if you enjoyed it 🧲 Join 2.4K+ others in my RF engineering newsletter (link in bio/comments)

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When adding stitching vias to a PCB, strategic placement is crucial. It's essential to position them around the edges of critical components, high-speed signal traces, and ground planes. This ensures effective shielding and enhanced signal integrity. The appropriate size and spacing of stitching vias are chosen based on your application's specific requirements and the PCB's material. #PCBdesign

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I know I've been plugging a lot of Auto Scaling and Fleet launches lately (I didn't even get a chance to talk about more responsive target tracking, but it's also a fantastic enhancement: https://lnkd.in/gSNUC4Fd), but I have one more big announcement. It was a great honor to help lead the engineering team in innovating with Capacity Blocks for ML just over a year ago. Our senior leadership has listened to customer feedback on this offering over the past year and pushed us once again to further our goals around democratizing access to GPUs. And, once again, our team delivered. We are announcing 3 changes are massive wins for our customers: 1. Support for Capacity Blocks up to 6 months in duration 2. Support for extending Capacity Block purchases 3. The ability to buy a Capacity Block starting 30 minutes in the future (instead of being bound to the standard start time of 11:30 UTC) https://lnkd.in/gyhFTs6Z The fact that we were able to quickly resource these valuable requests (that will surely please our customers) showcases our organization's agility, and I'm so grateful for the incredible teams who made it happen. It was a privilege and a rewarding experience to get to collaborate with them on these releases. #EC2 #AWS #reInvent24 #reInvent2024 #CapacityBlocks #CapacityBlocksForML #p5 #p4 #p5e #trn1

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Silicon Carbide (SiC) is revolutionizing power electronics, but there's a big issue that researchers need to talk about: **trapped charges**. These little troublemakers have a big impact on SiC device performance and reliability, and they might just be the key to unlocking (or bottlenecking) the full potential of SiC technology. In a recent study, researchers looked into how these trapped charges affect SiC MOSFETs, especially influencing key electrical characteristics like threshold voltage () and on-resistance. These charges can lead to some unexpected behaviors, such as threshold voltage shifts and reduced efficiency, particularly under different operational stresses. The mechanisms behind these effects include interfacial trap charges and defects related to nitrogen—each adding another layer of complexity to managing device performance. One of the most critical findings was the significant shifts in threshold voltage. These shifts don’t just change the numbers on a datasheet; they fundamentally affect the reliability of SiC MOSFETs over time. For industries relying on SiC to power their high-efficiency applications, from electric vehicles to renewable energy converters, this is an area that simply cannot be ignored. It was also found that **thermal cycling** plays a huge role in driving these instabilities. The variability introduced by interfacial traps during dynamic operation leads to an increased risk of device failure modes. The latest analysis suggests that current fabrication processes need to evolve to stabilize these characteristics if SiC is going to meet its promise in power-hungry applications. If you’re working on SiC devices or researching similar challenges, I’d love to hear about your experiences. NO, really, Feel free to reach out! How are you tackling these trapped charge issues, or what strategies have you found effective in boosting SiC device reliability?

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Stitching vias, also known as via stitching, are a crucial design practice for PCBs. By placing a series of vias around the perimeter of a ground plane or signal trace, a continuous conductive path is created, connecting the top and bottom layers of the board. #PCBdesign #viastitching

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Actually, RAM=Read write Random Access Memory. It is volatile. ROM=Read only Random Access Memory. It is non-volatile. Clearly explained about the above fullforms.This post answers the question "Why RAM is called as Random access memory? " #memories #embeddedsystems #computers #volatileandnonvolatilememories #processors

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EMC emissions due to the clock line. It has been a long time since I wrote anything about how to fix EMC DIY. This article explains how you can fix narrowband emissions caused by clock lines. I hope you will like it. https://lnkd.in/eYbVgwTS #emc

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Well said, Andy Greenwell One of the most underrated skills, especially in the tech world, is #Documentation I insist on this skill to many techies and management. However, it is often prioritized on the lower side and ignored for various reasons. #TechSkills #Documentation #UnderratedSkills #SoftwareIndustry #Management #EngineeringManager #SoftwareDevelopment #staffengineer #architect #seniorengineer #technicallead

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Output impedance of a Wilson Current Mirror The Wilson current mirror was quite popular in the BJT era, but is now obsolete in the CMOS era, probably due to the relatively high voltage requirements. Nonetheless, computing its output impedance can be insightful in several ways. In the following video, I discuss about: - Identifying the kind of feedback in a system and how it helps our cause - Recognizing the blocks that we are already familiar with so that we can utilise our previous learnings to make our life as circuit designers easier. - Computing the output impedance of the Wilson Mirror - The worst case corner of a circuit (poll conducted previously) Link: https://lnkd.in/gt3Pw7g6 Follow Tejas Ketkar to stay updated with such content. #circuits #interview #vlsi #semiconductors #analog

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The future of hardware isn't just about building a product! Building a successful hardware company requires a strategic trifecta: IP, platform, and target market. Here’s what I’ve learned so far… 1️⃣ The Power of IP → Your design IP is the heart of your product, the unique innovation that sets you apart. It should directly address customer pain points and enhance their experience. For example, #Enphase 's microinverter IP focuses on distributed architecture and energy efficiency, while MOKKOMOTTO's patented Power sharing algorithm on GaN technology enables dynamic power distribution for efficient charging. → A strong IP portfolio can be leveraged to create a technology platform, a versatile foundation for a range of products within a specific category.  This allows for expansion into new markets and reduces development time for future products. → A platform approach, built on strong IP, promotes sustainable design practices by minimizing repetitive efforts and ensuring timely product launches to stay relevant in the market. 2️⃣ Leveraging Platform Architecture → While IP deepens into specific customer needs, a platform architecture broadens the scope. It becomes a reusable and scalable foundation for an entire product category. Think of Tata's ATLAS platform for vehicle safety, Ola's Gen3 for cost-effective performance, or Apple's M-series SOCs used across various devices. → A well-designed platform should be robust, thoroughly tested, and adaptable and customizable to meet evolving customer demands and tailor-make for specific market needs. 3️⃣Targeting the Right Market: → Understanding Needs: Identifying your target market is crucial. Deeply understand their needs and pain points to ensure your product resonates with them. →  Tailoring Solutions: Customize your offerings to meet the specific requirements of your target market. This could involve adapting your platform, adding features, or adjusting pricing strategies. For instance, based on consumer demand, companies like Enphase are leveraging platform-based design to create energy-efficient solutions and remote monitoring capabilities for solar energy systems. By aligning these three pillars – IP, platform, and target market – hardware companies can accelerate innovation, expand their product offerings, and position themselves for long-term success. Is there anything else that I have missed? #hardware #innovation #makeinindia #startups #platformdesign #mokkomotto

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Crystal Filter Technical Terms Simplified Intermodulation (IM) Explanation: Nonlinear filter behavior creates new frequencies (intermodulation products). Examples: - Out of Band IM: Stopband signals produce IM products in the passband (common in receivers). - In Band IM: Closely spaced signals within the bandpass cause IM products (common in transmitters). Lowpass Filters Function: Transmits frequencies below the cut-off (Fc), suppresses higher frequencies. Applications: - Suppresses harmonic and spurious outputs. - Protects sensitive equipment from high-frequency signals. Example: Ensures clear audio by filtering out unwanted high frequencies. Highpass Filters Function: Transmits frequencies above the cut-off (Fc), suppresses lower frequencies. Applications: - Blocks low-frequency noise in RF systems. Example: Maintains signal quality by filtering out low-frequency noise. Bandpass Filters Function: Transmits frequencies within a specified range (Fc1 to Fc2), suppresses others. Applications: - Suppresses harmonics and spurious outputs. Example: Enhances radio signal clarity by filtering out unwanted frequencies. Bandstop Filters Function: Suppresses frequencies within a specified range (Fr1 to Fr2), transmits others. Applications: - Superior for suppressing single carriers or narrow spectrums. Example: Blocks specific interference frequencies in communication systems. Diplexers Function: Combines or splits RF spectrum into different frequencies. Applications: - Connects receiver and transmitter to a common antenna. - Combines or splits signals for remote transport. Example: Combines signals from two transmitters for efficient transport. Duplexers Function: Isolates receiver from transmitter using a single antenna. Applications: - Protects receiver from transmitter noise. - Ensures same radiation pattern for both. Example: Enables simultaneous transmission and reception in two-way radios. For more detailed insights and high-quality crystal filters, visit www.DynamicEngineers.com. #TechMagic #CrystalFilters #SignalProcessing #ModernTech #Innovation #ElectronicsEngineering #FrequencyControl #ElectronicDevices #EverythingRF #OCXO #Oscillators #MicrowaveJournal #MicrowaveJournalCN #DynamicEngineers

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Interference mitigation is critical to successful ADAS deployment

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Gordon Moore once quipped, "Fab 9 in NM eats like an elephant and poops like a tit mouse". Now this is true throughout its virtual factory. They are utilizing less than 30% of it's sub 5nm capacity and it's yields are less than 15%. Total FAB Efficiency is 0.30x0.15 = 4.5% IFS will lose $11 to $13B in 2025. Fabs need to run at 40%+ efficiency to break even. TSM is running at a TFE of 75+% efficiency on its sub 5nm capacity.... TSM's 4nm Fab here in AZ has better yields than their fabs in Taiwan. Who says American can't compete? Pat's claiming 3nm is on track - by what measure? 90% of it's 3nm HPC parts are outsourced to TSMC. They won't eat their own dog food?! Process Integrators are reporting 18A is in worse shape than 3nm was at the same development phase.

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