Denis Brockus

Not every device has the same requirements, and even the best security needs to adapt.

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Here is a demonstration of why booting linux on a RISC-V core is unimpressive. https://lnkd.in/eA_HXd2A

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https://lnkd.in/gRiPD7tN Several career Intel Corporation ex-colleagues would be forced into layoffs in the next few days because of the mess that it has gotten into thanks to its top management for years, accelerated in last three years. An Intel Corporation representative Jeff Rittener told US senate recently, under oath, that Pat Gelsinger was paid 40% more in 2023 while Intel was in deep shit and gave employees 5% base pay cuts and other cuts to benefits and bonuses, than he was paid in 2021 when Intel was having some of its best times in recent history. So Pat took the revenue down some 1.4x over two years, while his own income from Intel increased 1.4x over the same two years. When Rittener was asked how Intel Corporation management has the gall to layoff so many Americans while taking US govt money, he replied "Intel hasn't taken any money" - I'm sure this would be news to many. In fact it got more ridiculous - when asked why has Intel continued to invest in Chinese AI and Semiconductors companies through it's venture arm, Rittener replied that Intel wants to benefit from developments in that nation. This when Pat Gelsinger can't be shut up about Semiconductors manufacturing imbalance between Asia and the west, when he is begging for CHIPS Act money. Somehow China isn't in Asia according to his Atlas. Either that or he thinks China having Semiconductors advances is preferable to US allies Taiwan and South Korea having those advances The whole video is here https://lnkd.in/gxrNJgZ5 and here https://lnkd.in/g5VSB3tp

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Looking to offload SYCL code to multiple GPUs? This step-by-step guide covers debugging applications that use Message Passing Interface (MPI) and GPU offload simultaneously with the Intel Distribution for GDB. #IAmIntel https://bit.ly/4dYb2ji

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Actually, RAM=Read write Random Access Memory. It is volatile. ROM=Read only Random Access Memory. It is non-volatile. Clearly explained about the above fullforms.This post answers the question "Why RAM is called as Random access memory? " #memories #embeddedsystems #computers #volatileandnonvolatilememories #processors

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Introducing #Micron G9 TLC NAND! ➡️ 99% better read than the competition. ➡️ Up to 88% better write. ➡️ Up to 73% denser NAND. ➡️ Up to 28% better space efficiency. #𝑀𝑖𝑐𝑟𝑜𝑛 𝑖𝑠 𝑡ℎ𝑒 𝑤𝑜𝑟𝑙𝑑'𝑠 𝑓𝑖𝑟𝑠𝑡 𝑡𝑜 𝑠ℎ𝑖𝑝 𝑡ℎ𝑒 𝑖𝑛𝑑𝑢𝑠𝑡𝑟𝑦'𝑠 9𝑡ℎ-𝑔𝑒𝑛𝑒𝑟𝑎𝑡𝑖𝑜𝑛 3𝐷 𝑇𝐿𝐶 𝑁𝐴𝑁𝐷 𝑖𝑛 𝑡ℎ𝑒 2650 𝑆𝑆𝐷, 𝑏𝑜𝑎𝑠𝑡𝑖𝑛𝑔 𝑡ℎ𝑒 𝑖𝑛𝑑𝑢𝑠𝑡𝑟𝑦’𝑠 𝑓𝑎𝑠𝑡𝑒𝑠𝑡 𝑁𝐴𝑁𝐷 𝑤𝑖𝑡ℎ 𝑎𝑛 𝐼/𝑂 𝑠𝑝𝑒𝑒𝑑 𝑜𝑓 3.6 𝐺𝐵/𝑠, 𝑤ℎ𝑖𝑐ℎ 𝑠𝑢𝑟𝑝𝑎𝑠𝑠𝑒𝑠 𝑐𝑜𝑚𝑝𝑒𝑡𝑖𝑛𝑔 𝑁𝐴𝑁𝐷 𝑠𝑝𝑒𝑒𝑑𝑠 𝑏𝑦 50%." Learn more about #Micron 9th-generation (G9) 3D NAND: https://lnkd.in/gQ8k494s Learn more about #Micron 2650 SSD: https://lnkd.in/gKvynzPq WATCH: https://lnkd.in/g4W8tmTX

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As everyone has heard Intel took a loss the last quarter and will now reduce headcounts by 15%. My thinking about this: - Fierce competition by AMD on desktop space. Ask gamers, they are choosing AMD more and more. - Gen 13/Gen 14 CPUs has a pesky bugg which keeps haunting Intel. Lets hope its fixed for gen 15. - Nvidia running laps around Intel in AI race. - In Datacenter ARM and AMD keeps the pressure on Intel. But I would say that even with all this against them there are light in the tunnel: - They are executing well on their new foundry processes - Intel 15th generation is on pair with AMD offering. - Finally, in 2025, we will see next generation graphics cards? (A guess by me) - In datacenter new Xeon will come out to battle AMD and ARMs chips. - Intel Altera will execute as their own buiness unit to give AMD/Xilinx a run for their money. But I do expect that Intel and AMD will not be able to charge as high premium on their datacenter chipsets as they are used to ARM will see to this. Datacenter profits will be down and probably never come up again.

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Introducing  M4, the next generation of #Apple Silicon! Including Apple’s most powerful Neural Engine ever. Accelerating AI workloads, capable of an astounding 38 trillion operations per second! Faster than the neural processing unit of any AI PC today. #m4 #applesilicon #ai #machinelearning #neuralengine #ipadpro #hiring

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New #Micron blog post | Why latency in data center SSDs matters and how Micron became best in class, by Steven Wells (Fellow, Architect Storage Systems) READ: https://lnkd.in/e2tbu443 #SSD #NAND #LatencyMitigation

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Nvidia and Intel go way back. They had kindof a truce where they stuck to their own markets. But PCIe decided otherwise. Xeon was using PCIe gen3 while AMD Epyc was already on PCIe gen4. Nvidia was used to integrate Xeons all the time. In return, Intel never brought out a discrete GPU to directly compete with Nvidia as AMD was doing. Then the PCIe thing happened, and if anything is crucial it is the bandwidth of the PCIe link between CPU and GPU. Similar to the stage where Intel wasn't interested in low power cpus (phones and tablets where ARM was allowed to grow into a giant), this truce hampered Intel. So they only started to develop a discrete GPU after the relationship took a hit. Of course they had the on chip gpu but that is just minimal in comparison with the beasts we got from AMD and Nvidia. In hindsight, everything is quite obvious, the truce worked for a long time. And not going low power probably made sense back then for whatever real reason. I'm just observing to understand more about the complex nature of semi giants and their strategies. For make benefit great person myself. https://lnkd.in/gqBMYDWi

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As far as the DFD is concerned, a scan dump does not directly correspond to a memory dump. Here’s why: Focus: In a circuit using scan chains, a dump of the data stored in flip-flops. On the other hand, memory dumps illustrate how contents of a dedicated memory block such as RAM or ROM can be captured. DFD Techniques:  Scan chains are a defined technique for debugging logic circuits within DFD. Nevertheless, techniques for memory testing in DFD might not necessarily involve creating of memory dumps. However there may be some overlaps between these concepts: Memory as part of Scan Chain: At times, memories blocks could be included in the design of scans chain structure. By doing this, it would be possible to capture both flop states and the content of those memories during one single scan dump. External Memory Debugging: Engineers sometimes resort to external tools that allow them to access and extract information from their devices’ memories when they want to debug it. This data about that specific circuit would be called s memory dump though it doesn’t have anything like the usual DFD techniques Below are key points here: Scan Dumps: These provide insight into the logic state of a circuit by capturing data from flip-flops on scan chain. Memory Dumps: These can capture all info inside any discrete custom-memory chip such as Random Access Memory (RAM) and Read Only Memory (ROM). DFD and Memory Dumps: DFD doesn't directly involve memory dumps, but memory testing techniques might exist within a specific DFD methodology. Overlap: In some cases, memory blocks might be part of a scan chain, allowing their contents to be captured in a scan dump. Additionally, external tools might be used to create memory dumps for debugging purposes. If you're interested in learning more about memory testing within DFD, I can provide some information on Boundary Scan (JTAG) which can be used to test memory devices on a circuit board.

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QUALCOMM's Potential Takeover of Intel - Should this occur, the technology sector would undergo a significant transformation. QUALCOMM, well-known for its leadership in mobile chipsets and telecommunications, would acquire Intel's substantial market share in processors for PCs, data centers, and cloud computing. This merger has the potential to elevate QUALCOMM into a dominant role in both mobile and traditional computing by combining Intel's advanced x86 processors with QUALCOMM's proficiency in ARM-based chipsets. It could also heighten competition with companies like AMD and NVIDIA, driving innovation in semiconductor technology. Despite the promise of creating a tech giant, the merger might encounter regulatory challenges due to its possible effects on competition in the global semiconductor market.

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AMD Surges Ahead: Robust Growth and Strategic Wins in Q1 🌟 Earnings Exceed Expectations: AMD’s Q1 earnings surpassed Wall Street forecasts, reflecting our team's dedication. 🔮 Consistent Revenue Forecast: We anticipate about 6% annual growth this quarter, which is in line with expectations and showcases our market stability. 💰 Net Income Turnaround: Our net income reached $123 million, reversing last year’s loss and demonstrating our financial health. 📈 Data Center Surge: Our Data Center segment grew by 80% to $2.3 billion, driven by strong AMD Instinct MI300 AI chip sales. 💡 AI Chip Demand: Sales of our AMD Instinct MI300 AI chip topped $1 billion since its launch, highlighting its market success. 🚀 Client Segment Recovery: Revenue from processors and PCs rose by 85%, signaling recovery and continued trust in AMD. 🧠 AI Enhancements: We’re enhancing our processors for AI applications, preparing for future Next-Gen AI PCs with AMD Ryzen AI. As part of the AMD family, we are excited to share these achievements and remain committed to pushing the boundaries of what's possible in technology. #AI #AMD #Ryzen #Radeon #EPYC #Instinct

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#JTalks Weekly WW46: As LLMs reason, hardware PRDs revise again. Starting my career as a software engineer in a #semiconductor company (Texas Instruments), I was fortunate to develop an intricate understanding of SoC architectures. Software gets complex workflows implemented through a series of microinstructions and register manipulations. This understanding helped me write software that extracted optimal performance from a given #SoC. As a product manager, this perspective was reversed. I was inclined to determine hardware configuration required to extract optimal performance for a new software workload. In the world of #AI, I am constantly following research in AI model architectures mainly to trace back impact to AI hardware and its roadmap. And this paper caught my attention ➡️ https://lnkd.in/gn-sTCKN Title: Scaling Scaling Laws with Board Games Author: Andy L Jones It’s a surprisingly brief paper in the world of AI research – just 6 pages! And 8 pages if you include references and appendix. IMO, it includes a profound insight for AI inference hardware. Key takeaway ➡️ The paper reports that train-time compute and test-time compute can be #substitutes (test-time compute refers to inference-time compute). An additional 15x test-time compute can eliminate 10x of train-time compute, depending on test-time complexity of the problem. The way around the AI Training wall... A full slide was dedicated to this paper in a talk by Naom Brown of OpenAI on #LLM reasoning. Naom Brown used this result to emphasize that with scaling laws hitting a wall w.r.t training data and training compute, scaling inference compute provides an answer to ‘scale’ these scaling laws. Advances in LLM reasoning will be driven by scaling inference compute for the next 2 years. As LLMs reason, AI hardware has to play catch-up again… What does this mean for AI inference hardware? 1️⃣ In broader enterprise circles, AI inference is still considered a CPU workload mainly due to single-batch operation. This will change soon. 2️⃣ Transformer ASICs can find wider application. 3️⃣ Edge AI cannot be satisfied with 100 TOPS AI compute. It needs to move faster.

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Quote: Using the whisper-medium model, an Altra Max M128-30 can do 375,415 transactions per second (TPS), and an Nvidia “Hopper” H100 GPU can do 395,500 TPS. If you cap the racks at 15 kilowatts – which is reasonable in an enterprise datacenter – then 2,400 servers using the Altra Max CPUs in 60 racks costs $17.2 million and delivers 901 million TPS. That works out to a price/performance of $18,979 per million TPS. At the same 60 racks of space at 15 kilowatts per rack, that is only one DGX H100 per rack, which ain’t that much. Those 60 DGX H100s would cost $27.3 million and deliver only 190 million TPS, but cost $143,684 per million TPS. The CPU inference has 7.6X better price/performance on Whisper. You can put four DGXs in each rack and buy 240 of them, for a total of $109.2 million, and drive 760 million TPS, but the price/performance doesn’t change. We suspect the Whisper model is using FP16 half precision data formats and processing, and by moving to FP8, Nvidia could cut that gap in half. But half the gaps is still a 3.8X difference in bang for the buck in favor of the Ampere Computing Arm CPU. https://lnkd.in/gSZcFnm3

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Big news today! The U.S. Department of Commerce and Samsung Electronics (Samsung) have signed a non-binding preliminary memorandum of terms (PMT) to provide up to $6.4 billion in direct funding under the CHIPS and Science Act to strengthen the resilience of the U.S - the only leading-edge semiconductor company that is a leader in both advanced memory and advanced logic technologies – is expected to invest more than $40 billion dollars in the region in the coming years, and the proposed investment would support the creation of over 20,000 jobs. The proposed investment would turn Samsung’s existing presence in Texas into a comprehensive ecosystem for the development and production of leading-edge chips in the United States, including two new leading-edge logic fabs, an R&D fab, and an advanced packaging facility in Taylor, as well as an expansion to their existing Austin facility. It also demonstrates Samsung’s ongoing commitment to the United States, where it has been manufacturing chips since 1996. By continuing to develop the technologies of the future in the United States, Samsung is taking steps that would work towards strengthening U.S. economic and national security and increasing the resilience of both the U.S. and global semiconductor supply chains. Because of investments like Samsung’s, the United States is projected to be on track to produce roughly 20% of the world’s leading-edge logic chips by 2030. Taylor, Texas: Construct a comprehensive advanced manufacturing ecosystem, ranging from leading-edge logic to advanced packaging to R&D, transforming the small municipality of Taylor into an expansive hub of leading-edge semiconductor manufacturing. This ecosystem would include two leading-edge logic foundry fabs focused on mass production of 4nm and 2nm process technologies, an R&D fab dedicated to development and research on technology generations ahead of nodes currently in production, and an advanced packaging facility producing 3D High Bandwidth Memory and 2.5D packaging, both of which have critical artificial intelligence applications. The semiconductors that are designed and manufactured in this ecosystem would serve a wide variety of end markets – from communications, automotive, and defense industries to high-performance computing and artificial intelligence. Austin, Texas: Expand a facility that has been an economic engine for Central Texas for nearly 30 years. This proposed investment would expand the existing facilities to support the production of leading fully depleted silicon-on-insulator (FD-SOI) process technologies for critical U.S. industries, including aerospace, defense, and automotive. This proposed investment also includes commitments to collaborate with the U.S. Department of Defense. https://lnkd.in/eKggskvt

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How tokens of floating point numbers become the next electricity. The next step in human development.

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