Orlando Moreira

IMEC and ASML are both 40 years old this year and the trust and partnership between our two organizations has created so much innovation and results that has contributed to advancing the semiconductor industry's golden goals of reducing the power consumption of chips, Improving their preformance and shrinking their size while reducing the carbon footprint of our industry and hence creating the chips that drive AI and contribute to a better world for all of us. Our partnership with ASML is a true testament to the power of collaboration and partnership. https://lnkd.in/gDfCaxGm

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imec patterns first #logic and #DRAM #transistors using High-NA litho tools A major breakthrough for #semiconductorindustry #Imec and ASML announced on Wednesday that they had made the industry’s logic and DRAM structures using ASML'sASML’sroduction Twinscan EXE:5000 EUV #lithography tool with a 0.55 numerical aperture, also known as a high-NA litho system. The successful demonstration of high-resolution patterning with the 0.55NA #EUV scanner marks an essential milestone in #microelectronics production. Imec achieved the patterning of random logic structures with 9.5nm dense metal lines (compared to a 13nm resolution in the case of currently used Low-NA tools), which corresponds to a 19nm pitch and a sub 20nm tip-to-tip dimensions, which is good enough to build logic on a 1.4nm-class process #technology using a single High-NA exposure. Additionally, Imec successfully created random vias with a 30nm center-to-center distance, showcasing good pattern fidelity and critical dimension uniformity. Furthermore, 2D features were patterned at a 22nm pitch, which is good enough for a 3nm-class fabrication process. Considering that the pre-production Twinscan EXE High-NA EUV litho system was assembled less than a year ago, the achievements of ASML and Imec at the joint High NA EUV Lithography Lab in #Veldhoven, #Netherlands, are impressive, to say the least. This follows printing 10nm dense lines using high-NA EUV in April. A big thank you again to Anton Shilov and Tom's Hardware for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/egAfmCJP #semiconductormanufacturing #innovation #tech #chip #chips #ic #ai #iot #memory #mobile #europe #icdesign #hbm #semiconductors #it

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#TSMC R&D Dr. Yuh-Jier showed in the IMEC ITF 2024 the difference between work done in #IMEC and implementation in the industry  If use the average of 9 years you'll get when we will see Complementary Field-Effect Transistor (CFET) 2029? It will be interested to see what GPT (Generative Pre-trained Transformer) / LLM (Large Language Model) will do to this cycle time?

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THANK YOU AND CONGRATULATIONS TO imec, ASML and ZEISS Group. Hello from the plane to Boston. I’m heading to the Massachusetts Institute of Technology for the spring meeting of IPSR-I, which Optica is supporting. More on this to follow. But the long journey gives me a chance to thank you for the many positive responses over the last few days as we’ve shared the outcomes of several important meetings affecting the photonics industry. Photonics21 AGM and the spectacular imec ITF2024, which drew 2000+ people to Antwerp, Belgium just over a week ago. Today, I’m sharing a fun last interview on child presence detection with Sharada Prasad Shantharam from imec the Netherlands, which symbolises the international character of this meeting. I’m also sharing some overall impressions. I noticed a marked improvement on many of the exhibition stands this year with live demos straight from the lab, many close or ready to manufacture. And people willing to share their excitement and insights. And as we learned at ITF, June 3, 2024 is an important date for both imec and ASML. Today they officially opened the High NA EUV Lithography Lab in Veldhoven, in the heart of the Brainport Eindhoven region. This state-of-the-art lab offers partners unparalleled access to the first prototype High NA EUV scanner. It marks a crucial step towards integrating High NA EUV technology into high-volume manufacturing, anticipated around 2025-2026. They will provide leading logic and memory chip manufacturers, as well as advanced materials and equipment suppliers, with access to this pioneering technology. Is this the most sophisticated demo ever? The lab aims to mitigate risks and develop practical applications before the scanners are widely available. In preparation since 2018, the milestones involve intensive collaboration with ZEISS Group to overcome technical challenges related to the scanner's source, optics, and precision. imec, alongside its supplier network, has been instrumental in developing the patterning ecosystem, including advanced resist materials and photomasks. Luc Van den hove, President and CEO of Imec, emphasized the significance of this milestone: “High NA EUV is a game-changer in optical lithography, promising advanced patterning capabilities that will push Moore’s Law into the ångström era. The High NA EUV Lithography Lab will enhance our 300 mm cleanroom capabilities in Leuven, driving the patterning ecosystem to new heights.” Definitely something to think about. Safe journeys....

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1200V 900A Hybrid module. With SiC SBD diode inside，the turn on switching loss is reduced to a very low level.

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imec researchers explained to EE Times Europe's Pat Brans at ITF World 2024 how they’re taking #silicon #spinqubits from lab to fab to prepare them for use on an industrial scale. ➡️Read his conversation with Sofie Beyne, project manager for quantum computing at imec, and Kristiaan De Greve, imec fellow and program director for #quantumcomputers. https://lnkd.in/dev68y4J #quantumcomputing #quantumtechnologies #electronspin #qubits #ITFWorld2024 #CMOS #semiconductorindustry

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Dual-core ARM Cortex-A55 SoM starting from $34 https://lnkd.in/eC4M4PUa

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Sofics: Low parasitic capacitance solutions For high-speed interfaces or high-bandwidth wireless applications the parasitic capacitance of the ESD cells need to be as low as possible. Sofics solutions typically have 30% to 50% lower capacitance compared to the foundry solutions with the same ESD robustness. https://lnkd.in/grrYrS3B

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Hello everyone, Today, we've decided to postpone our next demo presentation to delve into some remarkable images from IMEC showcasing High-NA EUV work for Logic and DRAM. A big thank you to Subhash KM for sharing these. While we don't currently have customers utilizing High-NA EUV tools, I took the initiative to run these images through our Measurement Utility (YieldPro 5.1.1). My goal was to see how our software handles the latest metrology challenges. In about 20 minutes, I was able to create a 22nm pitch 2D feature recipe for full cell segmentation. It wasn’t too challenging, but certainly not trivial. I used some Deep Learning pre-filtering along with simple contour extraction based on gradients to perform the segmentation. It's worth noting that the image had high SNR, making the use of Deep Learning somewhat excessive, but it was an interesting exercise nonetheless. I've attached a video showcasing the process—please take a look and share your thoughts! #gazadelendaest #deeplearning #resolution #beam #EHAR #DeepStructures #metrology #Fab #problemsolving #LVTailoring #innovation #measurement #SecondaryElectronDetection #BackScatteredElectronDetection #CriticalDimentionMetrology #noisereduction #artificialneuralnetworks #CAD2SEM #Die2DB #EPE #PSD #precision #accuracy #lithography #tmu #NoiselessPSD #TargetDesign #ai #BlindDenoising #DeepStructures #neuralnetworks #weave #MassMeas #defects #beam #SecondaryElectronDetection #Overlay #EPE #labview #python #noisereduction #appliedmaterials #hitachi #kla

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Are you ready to embark on an exciting journey into the cutting-edge world of semiconductors with world-class experts at imec? Today, the semiconductor industry is undergoing a profound transformation, and we invite you to be part of it Do not miss this chance and apply from October 15 – December 15 2024 for the PhD positions at imec. Topics: System technology co-optimization for high speed/high frequency chiplet and heterogeneous integration packaging

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Leveraging SEMulator3D from Lam Research to optimize new interconnect strategies will be a key focus to enable further scaling. This work in collaboration with IMEC highlights process parameters and corresponding process windows that need to be controlled in order to realize an 18nm metal pitch semi-damascene flow that will enable scaling beyond 2nm node. #LifestLam #LamLeads

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TDR equipment works only with fast pulses, and requires a wide band receiver VNA on the other hand works with narrow band receiver in the equipment, and as a result is more accurate and, for most systems a VNA can compute a TDR waveform on the equipment itself As a result may modern labs don't even have a separate TDR reflectometer, they just have a high frequency VNA analyser which is a more versatile equipment younger engineers may not know what TDR is or does as a result

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imec #ITF2024 - USING PHOTOACOUSTICS TO LOOK DEEPER INSIDE THE BODY: Let's continue our coverage of interesting optical technologies we saw at the recent imec ITF2024 two-day conference in the heart of #Antwerp. On day two, I wandered around the exhibition looking for demos – you know that I love demos. I renewed contact with Hilde Jans, who is R&D Project Manager at imec. Watch the video! She brings us up to date on what Optica Corporate member imec is doing in the field of photoacoustics for (mainly) biomedical applications. This is a non-invasive sensing technique for biomedical applications, such as tumour imaging or glucose sensing. It is based on the photoacoustic principle discovered by Alexander Graham Bell (yes, him), where incoming light is absorbed by a sample and generates sound waves. Looking deeper inside the body Because it focuses with sound, photoacoustics is able to image deeper in tissue than light-based alternatives. When imaging biological tissue, the choice of modality depends on the contrast used for imaging and the trade-off between resolution and depth. Light waves, e.g. used in endoscopy or microscopy, can generate high-resolution images but don’t travel far unperturbed. Deeper in tissue, the light gets scattered, resulting in blurry images. High-energy X-rays form a special case as they penetrate deep into the tissue and yield high-resolution images, but this ionizing radiation limits their use. To circumvent these drawbacks, other options that don’t rely on unperturbed light propagation have also been explored. Acoustic or sound waves are well known to safely monitor foetuses in the womb using ultrasound imaging. These mechanical waves are less scattered than electromagnetic waves of comparable frequencies or wavelengths, so they can reach objects deeper in the tissue. However, ultrasound images typically suffer from a low resolution. MRI images have greater detail than ultrasound images, but they are typically not real-time and static. In the soft spot between these established imaging methods emerges a novel technique with the resolution of light-based imaging and the good depth penetration of sound-based imaging, called photoacoustics (PA). It is capable of imaging finer blood vessels than other techniques without the need for contrast agents or X-ray. More info here: https://lnkd.in/dH2mNMb2

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𝗔𝗦𝗛𝗟𝗜𝗡𝗚 𝗔𝗡𝗗 𝗘𝗠𝗕𝗘𝗖𝗢𝗦𝗠 𝗧𝗢 𝗔𝗖𝗖𝗘𝗟𝗘𝗥𝗔𝗧𝗘 𝗥𝗜𝗦𝗖-𝗩 𝗩𝗘𝗖𝗧𝗢𝗥 𝗤𝗘𝗠𝗨 𝗘𝗠𝗨𝗟𝗔𝗧𝗜𝗢𝗡. Ashling and our partner Embecosm are working with the RISE (RISC-V Software Ecosystem) project to optimize RISC-V vector instructions emulation for QEMU the open-source emulator. Our goal is to ensure that RISC-V vector instruction powered binaries run at rocket 🚀 🚀 🚀 speed under QEMU by mapping the RISC-V vector instructions to the best hardware equivalents on the host, leveraging up to 256-bit SIMD vectors for maximum performance. The RISC-V Software Ecosystem (RISE) Project focuses on accelerating the development of open-source software for the RISC-V architecture. See: https://riseproject.dev/ #RISCV #QEMU

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Nice article but as per me the small capacitor will be do extra oscillation frequency with track practice capacitance and sometimes its very difficult to design this track impedance with RC network. As per me the best solution to solve this zitter/harmonic is to use the high speed ferrite bead in place of resistor.

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"Imec [...] presents patterned structures obtained after exposure with the 0.55NA EUV scanner in the joint ASML-imec High NA EUV Lithography Lab [...]. Random logic structures down to 9,5nm (19 nm pitch), random vias with 30nm center-to-center distance, 2D features at 22nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure, using materials and baseline processes that were optimized for High NA EUV by imec and its partners in the framework of imec’s Advanced Patterning Program. With these results, imec confirms the readiness of the ecosystem to enable single exposure high-resolution High NA EUV Lithography" #semicon #imec #lithography #EUV #ASML #Logic #DRAM

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A very interesting blog by Giuseppe Piccolboni of Weebit Nano Ltd about the use of our #ReRAM for #neuromorphic applications

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