51#define DEBUG_TYPE "x86-instr-info"
53#define GET_INSTRINFO_CTOR_DTOR
54#include "X86GenInstrInfo.inc"
58 cl::desc(
"Disable fusing of spill code into instructions"),
62 cl::desc(
"Print instructions that the allocator wants to"
63 " fuse, but the X86 backend currently can't"),
67 cl::desc(
"Re-materialize load from stub in PIC mode"),
71 cl::desc(
"Clearance between two register writes "
72 "for inserting XOR to avoid partial "
76 "undef-reg-clearance",
77 cl::desc(
"How many idle instructions we would like before "
78 "certain undef register reads"),
82void X86InstrInfo::anchor() {}
86 : X86::ADJCALLSTACKDOWN32),
87 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
88 : X86::ADJCALLSTACKUP32),
89 X86::CATCHRET, (STI.
is64Bit() ? X86::RET64 : X86::RET32)),
90 Subtarget(STI), RI(STI.getTargetTriple()) {}
99 if (!RC || !Subtarget.hasEGPR())
105 switch (RC->getID()) {
108 case X86::GR8RegClassID:
109 return &X86::GR8_NOREX2RegClass;
110 case X86::GR16RegClassID:
111 return &X86::GR16_NOREX2RegClass;
112 case X86::GR32RegClassID:
113 return &X86::GR32_NOREX2RegClass;
114 case X86::GR64RegClassID:
115 return &X86::GR64_NOREX2RegClass;
116 case X86::GR32_NOSPRegClassID:
117 return &X86::GR32_NOREX2_NOSPRegClass;
118 case X86::GR64_NOSPRegClassID:
119 return &X86::GR64_NOREX2_NOSPRegClass;
125 unsigned &SubIdx)
const {
126 switch (
MI.getOpcode()) {
129 case X86::MOVSX16rr8:
130 case X86::MOVZX16rr8:
131 case X86::MOVSX32rr8:
132 case X86::MOVZX32rr8:
133 case X86::MOVSX64rr8:
134 if (!Subtarget.is64Bit())
139 case X86::MOVSX32rr16:
140 case X86::MOVZX32rr16:
141 case X86::MOVSX64rr16:
142 case X86::MOVSX64rr32: {
143 if (
MI.getOperand(0).getSubReg() ||
MI.getOperand(1).getSubReg())
146 SrcReg =
MI.getOperand(1).getReg();
147 DstReg =
MI.getOperand(0).getReg();
148 switch (
MI.getOpcode()) {
151 case X86::MOVSX16rr8:
152 case X86::MOVZX16rr8:
153 case X86::MOVSX32rr8:
154 case X86::MOVZX32rr8:
155 case X86::MOVSX64rr8:
156 SubIdx = X86::sub_8bit;
158 case X86::MOVSX32rr16:
159 case X86::MOVZX32rr16:
160 case X86::MOVSX64rr16:
161 SubIdx = X86::sub_16bit;
163 case X86::MOVSX64rr32:
164 SubIdx = X86::sub_32bit;
174 if (
MI.mayLoad() ||
MI.mayStore())
179 if (
MI.isCopyLike() ||
MI.isInsertSubreg())
182 unsigned Opcode =
MI.getOpcode();
193 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
199 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
200 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
201 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
206 if (isBEXTR(Opcode) || isBZHI(Opcode))
209 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
210 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
213 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
214 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
220 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
228 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
231 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
241 switch (
MI.getOpcode()) {
254 case X86::IMUL64rmi32:
269 case X86::POPCNT16rm:
270 case X86::POPCNT32rm:
271 case X86::POPCNT64rm:
279 case X86::BLCFILL32rm:
280 case X86::BLCFILL64rm:
285 case X86::BLCMSK32rm:
286 case X86::BLCMSK64rm:
289 case X86::BLSFILL32rm:
290 case X86::BLSFILL64rm:
295 case X86::BLSMSK32rm:
296 case X86::BLSMSK64rm:
306 case X86::BEXTRI32mi:
307 case X86::BEXTRI64mi:
360 case X86::CVTTSD2SI64rm:
361 case X86::VCVTTSD2SI64rm:
362 case X86::VCVTTSD2SI64Zrm:
363 case X86::CVTTSD2SIrm:
364 case X86::VCVTTSD2SIrm:
365 case X86::VCVTTSD2SIZrm:
366 case X86::CVTTSS2SI64rm:
367 case X86::VCVTTSS2SI64rm:
368 case X86::VCVTTSS2SI64Zrm:
369 case X86::CVTTSS2SIrm:
370 case X86::VCVTTSS2SIrm:
371 case X86::VCVTTSS2SIZrm:
372 case X86::CVTSI2SDrm:
373 case X86::VCVTSI2SDrm:
374 case X86::VCVTSI2SDZrm:
375 case X86::CVTSI2SSrm:
376 case X86::VCVTSI2SSrm:
377 case X86::VCVTSI2SSZrm:
378 case X86::CVTSI642SDrm:
379 case X86::VCVTSI642SDrm:
380 case X86::VCVTSI642SDZrm:
381 case X86::CVTSI642SSrm:
382 case X86::VCVTSI642SSrm:
383 case X86::VCVTSI642SSZrm:
384 case X86::CVTSS2SDrm:
385 case X86::VCVTSS2SDrm:
386 case X86::VCVTSS2SDZrm:
387 case X86::CVTSD2SSrm:
388 case X86::VCVTSD2SSrm:
389 case X86::VCVTSD2SSZrm:
391 case X86::VCVTTSD2USI64Zrm:
392 case X86::VCVTTSD2USIZrm:
393 case X86::VCVTTSS2USI64Zrm:
394 case X86::VCVTTSS2USIZrm:
395 case X86::VCVTUSI2SDZrm:
396 case X86::VCVTUSI642SDZrm:
397 case X86::VCVTUSI2SSZrm:
398 case X86::VCVTUSI642SSZrm:
402 case X86::MOV8rm_NOREX:
406 case X86::MOVSX16rm8:
407 case X86::MOVSX32rm16:
408 case X86::MOVSX32rm8:
409 case X86::MOVSX32rm8_NOREX:
410 case X86::MOVSX64rm16:
411 case X86::MOVSX64rm32:
412 case X86::MOVSX64rm8:
413 case X86::MOVZX16rm8:
414 case X86::MOVZX32rm16:
415 case X86::MOVZX32rm8:
416 case X86::MOVZX32rm8_NOREX:
417 case X86::MOVZX64rm16:
418 case X86::MOVZX64rm8:
427 if (isFrameInstr(
MI)) {
430 if (!isFrameSetup(
MI))
441 for (
auto E =
MBB->
end();
I != E; ++
I) {
442 if (
I->getOpcode() == getCallFrameDestroyOpcode() ||
I->isCall())
448 if (
I->getOpcode() != getCallFrameDestroyOpcode())
451 return -(
I->getOperand(1).getImm());
456 switch (
MI.getOpcode()) {
475 int &FrameIndex)
const {
495 case X86::KMOVBkm_EVEX:
500 case X86::KMOVWkm_EVEX:
502 case X86::VMOVSHZrm_alt:
507 case X86::MOVSSrm_alt:
509 case X86::VMOVSSrm_alt:
511 case X86::VMOVSSZrm_alt:
513 case X86::KMOVDkm_EVEX:
519 case X86::MOVSDrm_alt:
521 case X86::VMOVSDrm_alt:
523 case X86::VMOVSDZrm_alt:
524 case X86::MMX_MOVD64rm:
525 case X86::MMX_MOVQ64rm:
527 case X86::KMOVQkm_EVEX:
542 case X86::VMOVAPSZ128rm:
543 case X86::VMOVUPSZ128rm:
544 case X86::VMOVAPSZ128rm_NOVLX:
545 case X86::VMOVUPSZ128rm_NOVLX:
546 case X86::VMOVAPDZ128rm:
547 case X86::VMOVUPDZ128rm:
548 case X86::VMOVDQU8Z128rm:
549 case X86::VMOVDQU16Z128rm:
550 case X86::VMOVDQA32Z128rm:
551 case X86::VMOVDQU32Z128rm:
552 case X86::VMOVDQA64Z128rm:
553 case X86::VMOVDQU64Z128rm:
556 case X86::VMOVAPSYrm:
557 case X86::VMOVUPSYrm:
558 case X86::VMOVAPDYrm:
559 case X86::VMOVUPDYrm:
560 case X86::VMOVDQAYrm:
561 case X86::VMOVDQUYrm:
562 case X86::VMOVAPSZ256rm:
563 case X86::VMOVUPSZ256rm:
564 case X86::VMOVAPSZ256rm_NOVLX:
565 case X86::VMOVUPSZ256rm_NOVLX:
566 case X86::VMOVAPDZ256rm:
567 case X86::VMOVUPDZ256rm:
568 case X86::VMOVDQU8Z256rm:
569 case X86::VMOVDQU16Z256rm:
570 case X86::VMOVDQA32Z256rm:
571 case X86::VMOVDQU32Z256rm:
572 case X86::VMOVDQA64Z256rm:
573 case X86::VMOVDQU64Z256rm:
576 case X86::VMOVAPSZrm:
577 case X86::VMOVUPSZrm:
578 case X86::VMOVAPDZrm:
579 case X86::VMOVUPDZrm:
580 case X86::VMOVDQU8Zrm:
581 case X86::VMOVDQU16Zrm:
582 case X86::VMOVDQA32Zrm:
583 case X86::VMOVDQU32Zrm:
584 case X86::VMOVDQA64Zrm:
585 case X86::VMOVDQU64Zrm:
597 case X86::KMOVBmk_EVEX:
602 case X86::KMOVWmk_EVEX:
611 case X86::KMOVDmk_EVEX:
619 case X86::MMX_MOVD64mr:
620 case X86::MMX_MOVQ64mr:
621 case X86::MMX_MOVNTQmr:
623 case X86::KMOVQmk_EVEX:
638 case X86::VMOVUPSZ128mr:
639 case X86::VMOVAPSZ128mr:
640 case X86::VMOVUPSZ128mr_NOVLX:
641 case X86::VMOVAPSZ128mr_NOVLX:
642 case X86::VMOVUPDZ128mr:
643 case X86::VMOVAPDZ128mr:
644 case X86::VMOVDQA32Z128mr:
645 case X86::VMOVDQU32Z128mr:
646 case X86::VMOVDQA64Z128mr:
647 case X86::VMOVDQU64Z128mr:
648 case X86::VMOVDQU8Z128mr:
649 case X86::VMOVDQU16Z128mr:
652 case X86::VMOVUPSYmr:
653 case X86::VMOVAPSYmr:
654 case X86::VMOVUPDYmr:
655 case X86::VMOVAPDYmr:
656 case X86::VMOVDQUYmr:
657 case X86::VMOVDQAYmr:
658 case X86::VMOVUPSZ256mr:
659 case X86::VMOVAPSZ256mr:
660 case X86::VMOVUPSZ256mr_NOVLX:
661 case X86::VMOVAPSZ256mr_NOVLX:
662 case X86::VMOVUPDZ256mr:
663 case X86::VMOVAPDZ256mr:
664 case X86::VMOVDQU8Z256mr:
665 case X86::VMOVDQU16Z256mr:
666 case X86::VMOVDQA32Z256mr:
667 case X86::VMOVDQU32Z256mr:
668 case X86::VMOVDQA64Z256mr:
669 case X86::VMOVDQU64Z256mr:
672 case X86::VMOVUPSZmr:
673 case X86::VMOVAPSZmr:
674 case X86::VMOVUPDZmr:
675 case X86::VMOVAPDZmr:
676 case X86::VMOVDQU8Zmr:
677 case X86::VMOVDQU16Zmr:
678 case X86::VMOVDQA32Zmr:
679 case X86::VMOVDQU32Zmr:
680 case X86::VMOVDQA64Zmr:
681 case X86::VMOVDQU64Zmr:
689 int &FrameIndex)
const {
696 unsigned &MemBytes)
const {
698 if (
MI.getOperand(0).getSubReg() == 0 && isFrameOperand(
MI, 1, FrameIndex))
699 return MI.getOperand(0).getReg();
704 int &FrameIndex)
const {
712 if (hasLoadFromStackSlot(
MI, Accesses)) {
714 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
716 return MI.getOperand(0).getReg();
723 int &FrameIndex)
const {
730 unsigned &MemBytes)
const {
733 isFrameOperand(
MI, 0, FrameIndex))
739 int &FrameIndex)
const {
747 if (hasStoreToStackSlot(
MI, Accesses)) {
749 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
762 bool isPICBase =
false;
764 if (
DefMI.getOpcode() != X86::MOVPC32r)
766 assert(!isPICBase &&
"More than one PIC base?");
774 switch (
MI.getOpcode()) {
780 case X86::IMPLICIT_DEF:
783 case X86::LOAD_STACK_GUARD:
790 case X86::AVX1_SETALLONES:
791 case X86::AVX2_SETALLONES:
792 case X86::AVX512_128_SET0:
793 case X86::AVX512_256_SET0:
794 case X86::AVX512_512_SET0:
795 case X86::AVX512_512_SETALLONES:
796 case X86::AVX512_FsFLD0SD:
797 case X86::AVX512_FsFLD0SH:
798 case X86::AVX512_FsFLD0SS:
799 case X86::AVX512_FsFLD0F128:
804 case X86::FsFLD0F128:
812 case X86::MOV32ImmSExti8:
817 case X86::MOV64ImmSExti8:
819 case X86::V_SETALLONES:
825 case X86::PTILEZEROV:
829 case X86::MOV8rm_NOREX:
834 case X86::MOVSSrm_alt:
836 case X86::MOVSDrm_alt:
844 case X86::VMOVSSrm_alt:
846 case X86::VMOVSDrm_alt:
853 case X86::VMOVAPSYrm:
854 case X86::VMOVUPSYrm:
855 case X86::VMOVAPDYrm:
856 case X86::VMOVUPDYrm:
857 case X86::VMOVDQAYrm:
858 case X86::VMOVDQUYrm:
859 case X86::MMX_MOVD64rm:
860 case X86::MMX_MOVQ64rm:
861 case X86::VBROADCASTSSrm:
862 case X86::VBROADCASTSSYrm:
863 case X86::VBROADCASTSDYrm:
865 case X86::VPBROADCASTBZ128rm:
866 case X86::VPBROADCASTBZ256rm:
867 case X86::VPBROADCASTBZrm:
868 case X86::VBROADCASTF32X2Z256rm:
869 case X86::VBROADCASTF32X2Zrm:
870 case X86::VBROADCASTI32X2Z128rm:
871 case X86::VBROADCASTI32X2Z256rm:
872 case X86::VBROADCASTI32X2Zrm:
873 case X86::VPBROADCASTWZ128rm:
874 case X86::VPBROADCASTWZ256rm:
875 case X86::VPBROADCASTWZrm:
876 case X86::VPBROADCASTDZ128rm:
877 case X86::VPBROADCASTDZ256rm:
878 case X86::VPBROADCASTDZrm:
879 case X86::VBROADCASTSSZ128rm:
880 case X86::VBROADCASTSSZ256rm:
881 case X86::VBROADCASTSSZrm:
882 case X86::VPBROADCASTQZ128rm:
883 case X86::VPBROADCASTQZ256rm:
884 case X86::VPBROADCASTQZrm:
885 case X86::VBROADCASTSDZ256rm:
886 case X86::VBROADCASTSDZrm:
888 case X86::VMOVSSZrm_alt:
890 case X86::VMOVSDZrm_alt:
892 case X86::VMOVSHZrm_alt:
893 case X86::VMOVAPDZ128rm:
894 case X86::VMOVAPDZ256rm:
895 case X86::VMOVAPDZrm:
896 case X86::VMOVAPSZ128rm:
897 case X86::VMOVAPSZ256rm:
898 case X86::VMOVAPSZ128rm_NOVLX:
899 case X86::VMOVAPSZ256rm_NOVLX:
900 case X86::VMOVAPSZrm:
901 case X86::VMOVDQA32Z128rm:
902 case X86::VMOVDQA32Z256rm:
903 case X86::VMOVDQA32Zrm:
904 case X86::VMOVDQA64Z128rm:
905 case X86::VMOVDQA64Z256rm:
906 case X86::VMOVDQA64Zrm:
907 case X86::VMOVDQU16Z128rm:
908 case X86::VMOVDQU16Z256rm:
909 case X86::VMOVDQU16Zrm:
910 case X86::VMOVDQU32Z128rm:
911 case X86::VMOVDQU32Z256rm:
912 case X86::VMOVDQU32Zrm:
913 case X86::VMOVDQU64Z128rm:
914 case X86::VMOVDQU64Z256rm:
915 case X86::VMOVDQU64Zrm:
916 case X86::VMOVDQU8Z128rm:
917 case X86::VMOVDQU8Z256rm:
918 case X86::VMOVDQU8Zrm:
919 case X86::VMOVUPDZ128rm:
920 case X86::VMOVUPDZ256rm:
921 case X86::VMOVUPDZrm:
922 case X86::VMOVUPSZ128rm:
923 case X86::VMOVUPSZ256rm:
924 case X86::VMOVUPSZ128rm_NOVLX:
925 case X86::VMOVUPSZ256rm_NOVLX:
926 case X86::VMOVUPSZrm: {
932 MI.isDereferenceableInvariantLoad()) {
934 if (BaseReg == 0 || BaseReg == X86::RIP)
1012 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
1022 unsigned ShiftAmtOperandIdx) {
1024 unsigned ShiftCountMask = (
MI.getDesc().TSFlags &
X86II::REX_W) ? 63 : 31;
1025 unsigned Imm =
MI.getOperand(ShiftAmtOperandIdx).getImm();
1026 return Imm & ShiftCountMask;
1037 return ShAmt < 4 && ShAmt > 0;
1045 bool &NoSignFlag,
bool &ClearsOverflowFlag) {
1046 if (!(CmpValDefInstr.
getOpcode() == X86::SUBREG_TO_REG &&
1047 CmpInstr.
getOpcode() == X86::TEST64rr) &&
1048 !(CmpValDefInstr.
getOpcode() == X86::COPY &&
1056 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1057 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1066 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1067 "is a user of COPY sub16bit.");
1069 if (CmpInstr.
getOpcode() == X86::TEST16rr) {
1078 if (!((VregDefInstr->
getOpcode() == X86::AND32ri ||
1079 VregDefInstr->
getOpcode() == X86::AND64ri32) &&
1084 if (CmpInstr.
getOpcode() == X86::TEST64rr) {
1098 assert(VregDefInstr &&
"Must have a definition (SSA)");
1108 if (X86::isAND(VregDefInstr->
getOpcode())) {
1128 if (Instr.modifiesRegister(X86::EFLAGS,
TRI))
1132 *AndInstr = VregDefInstr;
1153 ClearsOverflowFlag =
true;
1160 unsigned Opc,
bool AllowSP,
Register &NewSrc,
1166 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1168 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1171 isKill =
MI.killsRegister(SrcReg,
nullptr);
1175 if (Opc != X86::LEA64_32r) {
1177 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1193 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1223MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
unsigned MIOpc,
1227 bool Is8BitOp)
const {
1234 "Unexpected type for LEA transform");
1243 if (!Subtarget.is64Bit())
1246 unsigned Opcode = X86::LEA64_32r;
1262 bool IsDead =
MI.getOperand(0).isDead();
1263 bool IsKill =
MI.getOperand(1).isKill();
1264 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1265 assert(!
MI.getOperand(1).isUndef() &&
"Undef op doesn't need optimization");
1281 case X86::SHL16ri: {
1282 unsigned ShAmt =
MI.getOperand(2).getImm();
1299 case X86::ADD8ri_DB:
1301 case X86::ADD16ri_DB:
1305 case X86::ADD8rr_DB:
1307 case X86::ADD16rr_DB: {
1308 Src2 =
MI.getOperand(2).getReg();
1309 bool IsKill2 =
MI.getOperand(2).isKill();
1310 assert(!
MI.getOperand(2).isUndef() &&
"Undef op doesn't need optimization");
1314 addRegReg(MIB, InRegLEA,
true, InRegLEA,
false);
1316 if (Subtarget.is64Bit())
1317 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1319 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1322 ImpDef2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(X86::IMPLICIT_DEF),
1324 InsMI2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(TargetOpcode::COPY))
1327 addRegReg(MIB, InRegLEA,
true, InRegLEA2,
true);
1329 if (LV && IsKill2 && InsMI2)
1425 if (
MI.getNumOperands() > 2)
1426 if (
MI.getOperand(2).isReg() &&
MI.getOperand(2).isUndef())
1431 bool Is64Bit = Subtarget.is64Bit();
1433 bool Is8BitOp =
false;
1434 unsigned NumRegOperands = 2;
1435 unsigned MIOpc =
MI.getOpcode();
1439 case X86::SHL64ri: {
1440 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1447 Src.getReg(), &X86::GR64_NOSPRegClass))
1450 NewMI =
BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r))
1459 case X86::SHL32ri: {
1460 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1465 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1471 ImplicitOp, LV, LIS))
1481 if (ImplicitOp.
getReg() != 0)
1482 MIB.
add(ImplicitOp);
1486 if (LV && SrcReg != Src.getReg())
1493 case X86::SHL16ri: {
1494 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1498 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1502 assert(
MI.getNumOperands() >= 2 &&
"Unknown inc instruction!");
1503 unsigned Opc = MIOpc == X86::INC64r
1505 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1509 ImplicitOp, LV, LIS))
1515 if (ImplicitOp.
getReg() != 0)
1516 MIB.
add(ImplicitOp);
1521 if (LV && SrcReg != Src.getReg())
1527 assert(
MI.getNumOperands() >= 2 &&
"Unknown dec instruction!");
1528 unsigned Opc = MIOpc == X86::DEC64r
1530 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1535 ImplicitOp, LV, LIS))
1541 if (ImplicitOp.
getReg() != 0)
1542 MIB.
add(ImplicitOp);
1547 if (LV && SrcReg != Src.getReg())
1557 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1559 case X86::ADD64rr_DB:
1561 case X86::ADD32rr_DB: {
1562 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1564 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1567 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1573 ImplicitOp2, LV, LIS))
1578 if (Src.getReg() == Src2.
getReg()) {
1585 ImplicitOp, LV, LIS))
1590 if (ImplicitOp.
getReg() != 0)
1591 MIB.
add(ImplicitOp);
1592 if (ImplicitOp2.
getReg() != 0)
1593 MIB.
add(ImplicitOp2);
1595 NewMI =
addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1599 if (SrcReg2 != Src2.
getReg())
1601 if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
1608 case X86::ADD8rr_DB:
1612 case X86::ADD16rr_DB:
1613 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1614 case X86::ADD64ri32:
1615 case X86::ADD64ri32_DB:
1616 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1618 BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r)).add(Dest).add(Src),
1622 case X86::ADD32ri_DB: {
1623 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1624 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1629 ImplicitOp, LV, LIS))
1635 if (ImplicitOp.
getReg() != 0)
1636 MIB.
add(ImplicitOp);
1641 if (LV && SrcReg != Src.getReg())
1646 case X86::ADD8ri_DB:
1650 case X86::ADD16ri_DB:
1651 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1656 case X86::SUB32ri: {
1657 if (!
MI.getOperand(2).isImm())
1659 int64_t Imm =
MI.getOperand(2).getImm();
1660 if (!isInt<32>(-Imm))
1663 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1664 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1669 ImplicitOp, LV, LIS))
1675 if (ImplicitOp.
getReg() != 0)
1676 MIB.
add(ImplicitOp);
1681 if (LV && SrcReg != Src.getReg())
1686 case X86::SUB64ri32: {
1687 if (!
MI.getOperand(2).isImm())
1689 int64_t Imm =
MI.getOperand(2).getImm();
1690 if (!isInt<32>(-Imm))
1693 assert(
MI.getNumOperands() >= 3 &&
"Unknown sub instruction!");
1701 case X86::VMOVDQU8Z128rmk:
1702 case X86::VMOVDQU8Z256rmk:
1703 case X86::VMOVDQU8Zrmk:
1704 case X86::VMOVDQU16Z128rmk:
1705 case X86::VMOVDQU16Z256rmk:
1706 case X86::VMOVDQU16Zrmk:
1707 case X86::VMOVDQU32Z128rmk:
1708 case X86::VMOVDQA32Z128rmk:
1709 case X86::VMOVDQU32Z256rmk:
1710 case X86::VMOVDQA32Z256rmk:
1711 case X86::VMOVDQU32Zrmk:
1712 case X86::VMOVDQA32Zrmk:
1713 case X86::VMOVDQU64Z128rmk:
1714 case X86::VMOVDQA64Z128rmk:
1715 case X86::VMOVDQU64Z256rmk:
1716 case X86::VMOVDQA64Z256rmk:
1717 case X86::VMOVDQU64Zrmk:
1718 case X86::VMOVDQA64Zrmk:
1719 case X86::VMOVUPDZ128rmk:
1720 case X86::VMOVAPDZ128rmk:
1721 case X86::VMOVUPDZ256rmk:
1722 case X86::VMOVAPDZ256rmk:
1723 case X86::VMOVUPDZrmk:
1724 case X86::VMOVAPDZrmk:
1725 case X86::VMOVUPSZ128rmk:
1726 case X86::VMOVAPSZ128rmk:
1727 case X86::VMOVUPSZ256rmk:
1728 case X86::VMOVAPSZ256rmk:
1729 case X86::VMOVUPSZrmk:
1730 case X86::VMOVAPSZrmk:
1731 case X86::VBROADCASTSDZ256rmk:
1732 case X86::VBROADCASTSDZrmk:
1733 case X86::VBROADCASTSSZ128rmk:
1734 case X86::VBROADCASTSSZ256rmk:
1735 case X86::VBROADCASTSSZrmk:
1736 case X86::VPBROADCASTDZ128rmk:
1737 case X86::VPBROADCASTDZ256rmk:
1738 case X86::VPBROADCASTDZrmk:
1739 case X86::VPBROADCASTQZ128rmk:
1740 case X86::VPBROADCASTQZ256rmk:
1741 case X86::VPBROADCASTQZrmk: {
1746 case X86::VMOVDQU8Z128rmk:
1747 Opc = X86::VPBLENDMBZ128rmk;
1749 case X86::VMOVDQU8Z256rmk:
1750 Opc = X86::VPBLENDMBZ256rmk;
1752 case X86::VMOVDQU8Zrmk:
1753 Opc = X86::VPBLENDMBZrmk;
1755 case X86::VMOVDQU16Z128rmk:
1756 Opc = X86::VPBLENDMWZ128rmk;
1758 case X86::VMOVDQU16Z256rmk:
1759 Opc = X86::VPBLENDMWZ256rmk;
1761 case X86::VMOVDQU16Zrmk:
1762 Opc = X86::VPBLENDMWZrmk;
1764 case X86::VMOVDQU32Z128rmk:
1765 Opc = X86::VPBLENDMDZ128rmk;
1767 case X86::VMOVDQU32Z256rmk:
1768 Opc = X86::VPBLENDMDZ256rmk;
1770 case X86::VMOVDQU32Zrmk:
1771 Opc = X86::VPBLENDMDZrmk;
1773 case X86::VMOVDQU64Z128rmk:
1774 Opc = X86::VPBLENDMQZ128rmk;
1776 case X86::VMOVDQU64Z256rmk:
1777 Opc = X86::VPBLENDMQZ256rmk;
1779 case X86::VMOVDQU64Zrmk:
1780 Opc = X86::VPBLENDMQZrmk;
1782 case X86::VMOVUPDZ128rmk:
1783 Opc = X86::VBLENDMPDZ128rmk;
1785 case X86::VMOVUPDZ256rmk:
1786 Opc = X86::VBLENDMPDZ256rmk;
1788 case X86::VMOVUPDZrmk:
1789 Opc = X86::VBLENDMPDZrmk;
1791 case X86::VMOVUPSZ128rmk:
1792 Opc = X86::VBLENDMPSZ128rmk;
1794 case X86::VMOVUPSZ256rmk:
1795 Opc = X86::VBLENDMPSZ256rmk;
1797 case X86::VMOVUPSZrmk:
1798 Opc = X86::VBLENDMPSZrmk;
1800 case X86::VMOVDQA32Z128rmk:
1801 Opc = X86::VPBLENDMDZ128rmk;
1803 case X86::VMOVDQA32Z256rmk:
1804 Opc = X86::VPBLENDMDZ256rmk;
1806 case X86::VMOVDQA32Zrmk:
1807 Opc = X86::VPBLENDMDZrmk;
1809 case X86::VMOVDQA64Z128rmk:
1810 Opc = X86::VPBLENDMQZ128rmk;
1812 case X86::VMOVDQA64Z256rmk:
1813 Opc = X86::VPBLENDMQZ256rmk;
1815 case X86::VMOVDQA64Zrmk:
1816 Opc = X86::VPBLENDMQZrmk;
1818 case X86::VMOVAPDZ128rmk:
1819 Opc = X86::VBLENDMPDZ128rmk;
1821 case X86::VMOVAPDZ256rmk:
1822 Opc = X86::VBLENDMPDZ256rmk;
1824 case X86::VMOVAPDZrmk:
1825 Opc = X86::VBLENDMPDZrmk;
1827 case X86::VMOVAPSZ128rmk:
1828 Opc = X86::VBLENDMPSZ128rmk;
1830 case X86::VMOVAPSZ256rmk:
1831 Opc = X86::VBLENDMPSZ256rmk;
1833 case X86::VMOVAPSZrmk:
1834 Opc = X86::VBLENDMPSZrmk;
1836 case X86::VBROADCASTSDZ256rmk:
1837 Opc = X86::VBLENDMPDZ256rmbk;
1839 case X86::VBROADCASTSDZrmk:
1840 Opc = X86::VBLENDMPDZrmbk;
1842 case X86::VBROADCASTSSZ128rmk:
1843 Opc = X86::VBLENDMPSZ128rmbk;
1845 case X86::VBROADCASTSSZ256rmk:
1846 Opc = X86::VBLENDMPSZ256rmbk;
1848 case X86::VBROADCASTSSZrmk:
1849 Opc = X86::VBLENDMPSZrmbk;
1851 case X86::VPBROADCASTDZ128rmk:
1852 Opc = X86::VPBLENDMDZ128rmbk;
1854 case X86::VPBROADCASTDZ256rmk:
1855 Opc = X86::VPBLENDMDZ256rmbk;
1857 case X86::VPBROADCASTDZrmk:
1858 Opc = X86::VPBLENDMDZrmbk;
1860 case X86::VPBROADCASTQZ128rmk:
1861 Opc = X86::VPBLENDMQZ128rmbk;
1863 case X86::VPBROADCASTQZ256rmk:
1864 Opc = X86::VPBLENDMQZ256rmbk;
1866 case X86::VPBROADCASTQZrmk:
1867 Opc = X86::VPBLENDMQZrmbk;
1873 .
add(
MI.getOperand(2))
1875 .
add(
MI.getOperand(3))
1876 .
add(
MI.getOperand(4))
1877 .
add(
MI.getOperand(5))
1878 .
add(
MI.getOperand(6))
1879 .
add(
MI.getOperand(7));
1884 case X86::VMOVDQU8Z128rrk:
1885 case X86::VMOVDQU8Z256rrk:
1886 case X86::VMOVDQU8Zrrk:
1887 case X86::VMOVDQU16Z128rrk:
1888 case X86::VMOVDQU16Z256rrk:
1889 case X86::VMOVDQU16Zrrk:
1890 case X86::VMOVDQU32Z128rrk:
1891 case X86::VMOVDQA32Z128rrk:
1892 case X86::VMOVDQU32Z256rrk:
1893 case X86::VMOVDQA32Z256rrk:
1894 case X86::VMOVDQU32Zrrk:
1895 case X86::VMOVDQA32Zrrk:
1896 case X86::VMOVDQU64Z128rrk:
1897 case X86::VMOVDQA64Z128rrk:
1898 case X86::VMOVDQU64Z256rrk:
1899 case X86::VMOVDQA64Z256rrk:
1900 case X86::VMOVDQU64Zrrk:
1901 case X86::VMOVDQA64Zrrk:
1902 case X86::VMOVUPDZ128rrk:
1903 case X86::VMOVAPDZ128rrk:
1904 case X86::VMOVUPDZ256rrk:
1905 case X86::VMOVAPDZ256rrk:
1906 case X86::VMOVUPDZrrk:
1907 case X86::VMOVAPDZrrk:
1908 case X86::VMOVUPSZ128rrk:
1909 case X86::VMOVAPSZ128rrk:
1910 case X86::VMOVUPSZ256rrk:
1911 case X86::VMOVAPSZ256rrk:
1912 case X86::VMOVUPSZrrk:
1913 case X86::VMOVAPSZrrk: {
1918 case X86::VMOVDQU8Z128rrk:
1919 Opc = X86::VPBLENDMBZ128rrk;
1921 case X86::VMOVDQU8Z256rrk:
1922 Opc = X86::VPBLENDMBZ256rrk;
1924 case X86::VMOVDQU8Zrrk:
1925 Opc = X86::VPBLENDMBZrrk;
1927 case X86::VMOVDQU16Z128rrk:
1928 Opc = X86::VPBLENDMWZ128rrk;
1930 case X86::VMOVDQU16Z256rrk:
1931 Opc = X86::VPBLENDMWZ256rrk;
1933 case X86::VMOVDQU16Zrrk:
1934 Opc = X86::VPBLENDMWZrrk;
1936 case X86::VMOVDQU32Z128rrk:
1937 Opc = X86::VPBLENDMDZ128rrk;
1939 case X86::VMOVDQU32Z256rrk:
1940 Opc = X86::VPBLENDMDZ256rrk;
1942 case X86::VMOVDQU32Zrrk:
1943 Opc = X86::VPBLENDMDZrrk;
1945 case X86::VMOVDQU64Z128rrk:
1946 Opc = X86::VPBLENDMQZ128rrk;
1948 case X86::VMOVDQU64Z256rrk:
1949 Opc = X86::VPBLENDMQZ256rrk;
1951 case X86::VMOVDQU64Zrrk:
1952 Opc = X86::VPBLENDMQZrrk;
1954 case X86::VMOVUPDZ128rrk:
1955 Opc = X86::VBLENDMPDZ128rrk;
1957 case X86::VMOVUPDZ256rrk:
1958 Opc = X86::VBLENDMPDZ256rrk;
1960 case X86::VMOVUPDZrrk:
1961 Opc = X86::VBLENDMPDZrrk;
1963 case X86::VMOVUPSZ128rrk:
1964 Opc = X86::VBLENDMPSZ128rrk;
1966 case X86::VMOVUPSZ256rrk:
1967 Opc = X86::VBLENDMPSZ256rrk;
1969 case X86::VMOVUPSZrrk:
1970 Opc = X86::VBLENDMPSZrrk;
1972 case X86::VMOVDQA32Z128rrk:
1973 Opc = X86::VPBLENDMDZ128rrk;
1975 case X86::VMOVDQA32Z256rrk:
1976 Opc = X86::VPBLENDMDZ256rrk;
1978 case X86::VMOVDQA32Zrrk:
1979 Opc = X86::VPBLENDMDZrrk;
1981 case X86::VMOVDQA64Z128rrk:
1982 Opc = X86::VPBLENDMQZ128rrk;
1984 case X86::VMOVDQA64Z256rrk:
1985 Opc = X86::VPBLENDMQZ256rrk;
1987 case X86::VMOVDQA64Zrrk:
1988 Opc = X86::VPBLENDMQZrrk;
1990 case X86::VMOVAPDZ128rrk:
1991 Opc = X86::VBLENDMPDZ128rrk;
1993 case X86::VMOVAPDZ256rrk:
1994 Opc = X86::VBLENDMPDZ256rrk;
1996 case X86::VMOVAPDZrrk:
1997 Opc = X86::VBLENDMPDZrrk;
1999 case X86::VMOVAPSZ128rrk:
2000 Opc = X86::VBLENDMPSZ128rrk;
2002 case X86::VMOVAPSZ256rrk:
2003 Opc = X86::VBLENDMPSZ256rrk;
2005 case X86::VMOVAPSZrrk:
2006 Opc = X86::VBLENDMPSZrrk;
2012 .
add(
MI.getOperand(2))
2014 .
add(
MI.getOperand(3));
2024 for (
unsigned I = 0;
I < NumRegOperands; ++
I) {
2026 if (
Op.isReg() && (
Op.isDead() ||
Op.isKill()))
2053 unsigned SrcOpIdx2) {
2055 if (SrcOpIdx1 > SrcOpIdx2)
2058 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2064 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2066 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2068 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2077 unsigned Opc =
MI.getOpcode();
2086 "Intrinsic instructions can't commute operand 1");
2091 assert(Case < 3 &&
"Unexpected case number!");
2096 const unsigned Form132Index = 0;
2097 const unsigned Form213Index = 1;
2098 const unsigned Form231Index = 2;
2099 static const unsigned FormMapping[][3] = {
2104 {Form231Index, Form213Index, Form132Index},
2109 {Form132Index, Form231Index, Form213Index},
2114 {Form213Index, Form132Index, Form231Index}};
2116 unsigned FMAForms[3];
2122 for (
unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2123 if (Opc == FMAForms[FormIndex])
2124 return FMAForms[FormMapping[Case][FormIndex]];
2130 unsigned SrcOpIdx2) {
2134 assert(Case < 3 &&
"Unexpected case value!");
2137 static const uint8_t SwapMasks[3][4] = {
2138 {0x04, 0x10, 0x08, 0x20},
2139 {0x02, 0x10, 0x08, 0x40},
2140 {0x02, 0x04, 0x20, 0x40},
2143 uint8_t Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2145 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2146 SwapMasks[Case][2] | SwapMasks[Case][3]);
2148 if (Imm & SwapMasks[Case][0])
2149 NewImm |= SwapMasks[Case][1];
2150 if (Imm & SwapMasks[Case][1])
2151 NewImm |= SwapMasks[Case][0];
2152 if (Imm & SwapMasks[Case][2])
2153 NewImm |= SwapMasks[Case][3];
2154 if (Imm & SwapMasks[Case][3])
2155 NewImm |= SwapMasks[Case][2];
2156 MI.getOperand(
MI.getNumOperands() - 1).setImm(NewImm);
2162#define VPERM_CASES(Suffix) \
2163 case X86::VPERMI2##Suffix##Z128rr: \
2164 case X86::VPERMT2##Suffix##Z128rr: \
2165 case X86::VPERMI2##Suffix##Z256rr: \
2166 case X86::VPERMT2##Suffix##Z256rr: \
2167 case X86::VPERMI2##Suffix##Zrr: \
2168 case X86::VPERMT2##Suffix##Zrr: \
2169 case X86::VPERMI2##Suffix##Z128rm: \
2170 case X86::VPERMT2##Suffix##Z128rm: \
2171 case X86::VPERMI2##Suffix##Z256rm: \
2172 case X86::VPERMT2##Suffix##Z256rm: \
2173 case X86::VPERMI2##Suffix##Zrm: \
2174 case X86::VPERMT2##Suffix##Zrm: \
2175 case X86::VPERMI2##Suffix##Z128rrkz: \
2176 case X86::VPERMT2##Suffix##Z128rrkz: \
2177 case X86::VPERMI2##Suffix##Z256rrkz: \
2178 case X86::VPERMT2##Suffix##Z256rrkz: \
2179 case X86::VPERMI2##Suffix##Zrrkz: \
2180 case X86::VPERMT2##Suffix##Zrrkz: \
2181 case X86::VPERMI2##Suffix##Z128rmkz: \
2182 case X86::VPERMT2##Suffix##Z128rmkz: \
2183 case X86::VPERMI2##Suffix##Z256rmkz: \
2184 case X86::VPERMT2##Suffix##Z256rmkz: \
2185 case X86::VPERMI2##Suffix##Zrmkz: \
2186 case X86::VPERMT2##Suffix##Zrmkz:
2188#define VPERM_CASES_BROADCAST(Suffix) \
2189 VPERM_CASES(Suffix) \
2190 case X86::VPERMI2##Suffix##Z128rmb: \
2191 case X86::VPERMT2##Suffix##Z128rmb: \
2192 case X86::VPERMI2##Suffix##Z256rmb: \
2193 case X86::VPERMT2##Suffix##Z256rmb: \
2194 case X86::VPERMI2##Suffix##Zrmb: \
2195 case X86::VPERMT2##Suffix##Zrmb: \
2196 case X86::VPERMI2##Suffix##Z128rmbkz: \
2197 case X86::VPERMT2##Suffix##Z128rmbkz: \
2198 case X86::VPERMI2##Suffix##Z256rmbkz: \
2199 case X86::VPERMT2##Suffix##Z256rmbkz: \
2200 case X86::VPERMI2##Suffix##Zrmbkz: \
2201 case X86::VPERMT2##Suffix##Zrmbkz:
2214#undef VPERM_CASES_BROADCAST
2221#define VPERM_CASES(Orig, New) \
2222 case X86::Orig##Z128rr: \
2223 return X86::New##Z128rr; \
2224 case X86::Orig##Z128rrkz: \
2225 return X86::New##Z128rrkz; \
2226 case X86::Orig##Z128rm: \
2227 return X86::New##Z128rm; \
2228 case X86::Orig##Z128rmkz: \
2229 return X86::New##Z128rmkz; \
2230 case X86::Orig##Z256rr: \
2231 return X86::New##Z256rr; \
2232 case X86::Orig##Z256rrkz: \
2233 return X86::New##Z256rrkz; \
2234 case X86::Orig##Z256rm: \
2235 return X86::New##Z256rm; \
2236 case X86::Orig##Z256rmkz: \
2237 return X86::New##Z256rmkz; \
2238 case X86::Orig##Zrr: \
2239 return X86::New##Zrr; \
2240 case X86::Orig##Zrrkz: \
2241 return X86::New##Zrrkz; \
2242 case X86::Orig##Zrm: \
2243 return X86::New##Zrm; \
2244 case X86::Orig##Zrmkz: \
2245 return X86::New##Zrmkz;
2247#define VPERM_CASES_BROADCAST(Orig, New) \
2248 VPERM_CASES(Orig, New) \
2249 case X86::Orig##Z128rmb: \
2250 return X86::New##Z128rmb; \
2251 case X86::Orig##Z128rmbkz: \
2252 return X86::New##Z128rmbkz; \
2253 case X86::Orig##Z256rmb: \
2254 return X86::New##Z256rmb; \
2255 case X86::Orig##Z256rmbkz: \
2256 return X86::New##Z256rmbkz; \
2257 case X86::Orig##Zrmb: \
2258 return X86::New##Zrmb; \
2259 case X86::Orig##Zrmbkz: \
2260 return X86::New##Zrmbkz;
2278#undef VPERM_CASES_BROADCAST
2284 unsigned OpIdx2)
const {
2286 return std::exchange(NewMI,
false)
2287 ?
MI.getParent()->getParent()->CloneMachineInstr(&
MI)
2291 unsigned Opc =
MI.getOpcode();
2293#define CASE_ND(OP) \
2309#define FROM_TO_SIZE(A, B, S) \
2315 Opc = X86::B##_ND; \
2323 Opc = X86::A##_ND; \
2332 WorkingMI = CloneIfNew(
MI);
2341 WorkingMI = CloneIfNew(
MI);
2343 get(X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2345 case X86::BLENDPDrri:
2346 case X86::BLENDPSrri:
2347 case X86::VBLENDPDrri:
2348 case X86::VBLENDPSrri:
2350 if (
MI.getParent()->getParent()->getFunction().hasOptSize()) {
2351 unsigned Mask = (Opc == X86::BLENDPDrri || Opc == X86::VBLENDPDrri) ? 0x03: 0x0F;
2352 if ((
MI.getOperand(3).getImm() ^ Mask) == 1) {
2353#define FROM_TO(FROM, TO) \
2362 FROM_TO(VBLENDPDrri, VMOVSDrr)
2363 FROM_TO(VBLENDPSrri, VMOVSSrr)
2365 WorkingMI = CloneIfNew(
MI);
2373 case X86::PBLENDWrri:
2374 case X86::VBLENDPDYrri:
2375 case X86::VBLENDPSYrri:
2376 case X86::VPBLENDDrri:
2377 case X86::VPBLENDWrri:
2378 case X86::VPBLENDDYrri:
2379 case X86::VPBLENDWYrri: {
2384 case X86::BLENDPDrri:
2385 Mask = (int8_t)0x03;
2387 case X86::BLENDPSrri:
2388 Mask = (int8_t)0x0F;
2390 case X86::PBLENDWrri:
2391 Mask = (int8_t)0xFF;
2393 case X86::VBLENDPDrri:
2394 Mask = (int8_t)0x03;
2396 case X86::VBLENDPSrri:
2397 Mask = (int8_t)0x0F;
2399 case X86::VBLENDPDYrri:
2400 Mask = (int8_t)0x0F;
2402 case X86::VBLENDPSYrri:
2403 Mask = (int8_t)0xFF;
2405 case X86::VPBLENDDrri:
2406 Mask = (int8_t)0x0F;
2408 case X86::VPBLENDWrri:
2409 Mask = (int8_t)0xFF;
2411 case X86::VPBLENDDYrri:
2412 Mask = (int8_t)0xFF;
2414 case X86::VPBLENDWYrri:
2415 Mask = (int8_t)0xFF;
2421 int8_t Imm =
MI.getOperand(3).getImm() & Mask;
2422 WorkingMI = CloneIfNew(
MI);
2426 case X86::INSERTPSrri:
2427 case X86::VINSERTPSrri:
2428 case X86::VINSERTPSZrri: {
2429 unsigned Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2430 unsigned ZMask = Imm & 15;
2431 unsigned DstIdx = (Imm >> 4) & 3;
2432 unsigned SrcIdx = (Imm >> 6) & 3;
2436 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2439 assert(AltIdx < 4 &&
"Illegal insertion index");
2440 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2441 WorkingMI = CloneIfNew(
MI);
2450 case X86::VMOVSSrr: {
2458 Opc = X86::BLENDPDrri;
2462 Opc = X86::BLENDPSrri;
2466 Opc = X86::VBLENDPDrri;
2470 Opc = X86::VBLENDPSrri;
2475 WorkingMI = CloneIfNew(
MI);
2481 WorkingMI = CloneIfNew(
MI);
2486 case X86::SHUFPDrri: {
2488 assert(
MI.getOperand(3).getImm() == 0x02 &&
"Unexpected immediate!");
2489 WorkingMI = CloneIfNew(
MI);
2494 case X86::PCLMULQDQrri:
2495 case X86::VPCLMULQDQrri:
2496 case X86::VPCLMULQDQYrri:
2497 case X86::VPCLMULQDQZrri:
2498 case X86::VPCLMULQDQZ128rri:
2499 case X86::VPCLMULQDQZ256rri: {
2502 unsigned Imm =
MI.getOperand(3).getImm();
2503 unsigned Src1Hi = Imm & 0x01;
2504 unsigned Src2Hi = Imm & 0x10;
2505 WorkingMI = CloneIfNew(
MI);
2509 case X86::VPCMPBZ128rri:
2510 case X86::VPCMPUBZ128rri:
2511 case X86::VPCMPBZ256rri:
2512 case X86::VPCMPUBZ256rri:
2513 case X86::VPCMPBZrri:
2514 case X86::VPCMPUBZrri:
2515 case X86::VPCMPDZ128rri:
2516 case X86::VPCMPUDZ128rri:
2517 case X86::VPCMPDZ256rri:
2518 case X86::VPCMPUDZ256rri:
2519 case X86::VPCMPDZrri:
2520 case X86::VPCMPUDZrri:
2521 case X86::VPCMPQZ128rri:
2522 case X86::VPCMPUQZ128rri:
2523 case X86::VPCMPQZ256rri:
2524 case X86::VPCMPUQZ256rri:
2525 case X86::VPCMPQZrri:
2526 case X86::VPCMPUQZrri:
2527 case X86::VPCMPWZ128rri:
2528 case X86::VPCMPUWZ128rri:
2529 case X86::VPCMPWZ256rri:
2530 case X86::VPCMPUWZ256rri:
2531 case X86::VPCMPWZrri:
2532 case X86::VPCMPUWZrri:
2533 case X86::VPCMPBZ128rrik:
2534 case X86::VPCMPUBZ128rrik:
2535 case X86::VPCMPBZ256rrik:
2536 case X86::VPCMPUBZ256rrik:
2537 case X86::VPCMPBZrrik:
2538 case X86::VPCMPUBZrrik:
2539 case X86::VPCMPDZ128rrik:
2540 case X86::VPCMPUDZ128rrik:
2541 case X86::VPCMPDZ256rrik:
2542 case X86::VPCMPUDZ256rrik:
2543 case X86::VPCMPDZrrik:
2544 case X86::VPCMPUDZrrik:
2545 case X86::VPCMPQZ128rrik:
2546 case X86::VPCMPUQZ128rrik:
2547 case X86::VPCMPQZ256rrik:
2548 case X86::VPCMPUQZ256rrik:
2549 case X86::VPCMPQZrrik:
2550 case X86::VPCMPUQZrrik:
2551 case X86::VPCMPWZ128rrik:
2552 case X86::VPCMPUWZ128rrik:
2553 case X86::VPCMPWZ256rrik:
2554 case X86::VPCMPUWZ256rrik:
2555 case X86::VPCMPWZrrik:
2556 case X86::VPCMPUWZrrik:
2557 WorkingMI = CloneIfNew(
MI);
2561 MI.getOperand(
MI.getNumOperands() - 1).getImm() & 0x7));
2564 case X86::VPCOMUBri:
2566 case X86::VPCOMUDri:
2568 case X86::VPCOMUQri:
2570 case X86::VPCOMUWri:
2571 WorkingMI = CloneIfNew(
MI);
2576 case X86::VCMPSDZrri:
2577 case X86::VCMPSSZrri:
2578 case X86::VCMPPDZrri:
2579 case X86::VCMPPSZrri:
2580 case X86::VCMPSHZrri:
2581 case X86::VCMPPHZrri:
2582 case X86::VCMPPHZ128rri:
2583 case X86::VCMPPHZ256rri:
2584 case X86::VCMPPDZ128rri:
2585 case X86::VCMPPSZ128rri:
2586 case X86::VCMPPDZ256rri:
2587 case X86::VCMPPSZ256rri:
2588 case X86::VCMPPDZrrik:
2589 case X86::VCMPPSZrrik:
2590 case X86::VCMPPDZ128rrik:
2591 case X86::VCMPPSZ128rrik:
2592 case X86::VCMPPDZ256rrik:
2593 case X86::VCMPPSZ256rrik:
2594 WorkingMI = CloneIfNew(
MI);
2597 MI.getOperand(
MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2599 case X86::VPERM2F128rri:
2600 case X86::VPERM2I128rri:
2604 WorkingMI = CloneIfNew(
MI);
2607 case X86::MOVHLPSrr:
2608 case X86::UNPCKHPDrr:
2609 case X86::VMOVHLPSrr:
2610 case X86::VUNPCKHPDrr:
2611 case X86::VMOVHLPSZrr:
2612 case X86::VUNPCKHPDZ128rr:
2613 assert(Subtarget.
hasSSE2() &&
"Commuting MOVHLP/UNPCKHPD requires SSE2!");
2618 case X86::MOVHLPSrr:
2619 Opc = X86::UNPCKHPDrr;
2621 case X86::UNPCKHPDrr:
2622 Opc = X86::MOVHLPSrr;
2624 case X86::VMOVHLPSrr:
2625 Opc = X86::VUNPCKHPDrr;
2627 case X86::VUNPCKHPDrr:
2628 Opc = X86::VMOVHLPSrr;
2630 case X86::VMOVHLPSZrr:
2631 Opc = X86::VUNPCKHPDZ128rr;
2633 case X86::VUNPCKHPDZ128rr:
2634 Opc = X86::VMOVHLPSZrr;
2637 WorkingMI = CloneIfNew(
MI);
2643 WorkingMI = CloneIfNew(
MI);
2644 unsigned OpNo =
MI.getDesc().getNumOperands() - 1;
2649 case X86::VPTERNLOGDZrri:
2650 case X86::VPTERNLOGDZrmi:
2651 case X86::VPTERNLOGDZ128rri:
2652 case X86::VPTERNLOGDZ128rmi:
2653 case X86::VPTERNLOGDZ256rri:
2654 case X86::VPTERNLOGDZ256rmi:
2655 case X86::VPTERNLOGQZrri:
2656 case X86::VPTERNLOGQZrmi:
2657 case X86::VPTERNLOGQZ128rri:
2658 case X86::VPTERNLOGQZ128rmi:
2659 case X86::VPTERNLOGQZ256rri:
2660 case X86::VPTERNLOGQZ256rmi:
2661 case X86::VPTERNLOGDZrrik:
2662 case X86::VPTERNLOGDZ128rrik:
2663 case X86::VPTERNLOGDZ256rrik:
2664 case X86::VPTERNLOGQZrrik:
2665 case X86::VPTERNLOGQZ128rrik:
2666 case X86::VPTERNLOGQZ256rrik:
2667 case X86::VPTERNLOGDZrrikz:
2668 case X86::VPTERNLOGDZrmikz:
2669 case X86::VPTERNLOGDZ128rrikz:
2670 case X86::VPTERNLOGDZ128rmikz:
2671 case X86::VPTERNLOGDZ256rrikz:
2672 case X86::VPTERNLOGDZ256rmikz:
2673 case X86::VPTERNLOGQZrrikz:
2674 case X86::VPTERNLOGQZrmikz:
2675 case X86::VPTERNLOGQZ128rrikz:
2676 case X86::VPTERNLOGQZ128rmikz:
2677 case X86::VPTERNLOGQZ256rrikz:
2678 case X86::VPTERNLOGQZ256rmikz:
2679 case X86::VPTERNLOGDZ128rmbi:
2680 case X86::VPTERNLOGDZ256rmbi:
2681 case X86::VPTERNLOGDZrmbi:
2682 case X86::VPTERNLOGQZ128rmbi:
2683 case X86::VPTERNLOGQZ256rmbi:
2684 case X86::VPTERNLOGQZrmbi:
2685 case X86::VPTERNLOGDZ128rmbikz:
2686 case X86::VPTERNLOGDZ256rmbikz:
2687 case X86::VPTERNLOGDZrmbikz:
2688 case X86::VPTERNLOGQZ128rmbikz:
2689 case X86::VPTERNLOGQZ256rmbikz:
2690 case X86::VPTERNLOGQZrmbikz: {
2691 WorkingMI = CloneIfNew(
MI);
2697 WorkingMI = CloneIfNew(
MI);
2703 WorkingMI = CloneIfNew(
MI);
2712bool X86InstrInfo::findThreeSrcCommutedOpIndices(
const MachineInstr &
MI,
2713 unsigned &SrcOpIdx1,
2714 unsigned &SrcOpIdx2,
2715 bool IsIntrinsic)
const {
2718 unsigned FirstCommutableVecOp = 1;
2719 unsigned LastCommutableVecOp = 3;
2720 unsigned KMaskOp = -1U;
2743 FirstCommutableVecOp = 3;
2745 LastCommutableVecOp++;
2746 }
else if (IsIntrinsic) {
2749 FirstCommutableVecOp = 2;
2752 if (
isMem(
MI, LastCommutableVecOp))
2753 LastCommutableVecOp--;
2758 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2759 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2760 SrcOpIdx1 == KMaskOp))
2762 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2763 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2764 SrcOpIdx2 == KMaskOp))
2769 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2770 SrcOpIdx2 == CommuteAnyOperandIndex) {
2771 unsigned CommutableOpIdx2 = SrcOpIdx2;
2775 if (SrcOpIdx1 == SrcOpIdx2)
2778 CommutableOpIdx2 = LastCommutableVecOp;
2779 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2781 CommutableOpIdx2 = SrcOpIdx1;
2785 Register Op2Reg =
MI.getOperand(CommutableOpIdx2).getReg();
2787 unsigned CommutableOpIdx1;
2788 for (CommutableOpIdx1 = LastCommutableVecOp;
2789 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2791 if (CommutableOpIdx1 == KMaskOp)
2797 if (Op2Reg !=
MI.getOperand(CommutableOpIdx1).getReg())
2802 if (CommutableOpIdx1 < FirstCommutableVecOp)
2807 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
2816 unsigned &SrcOpIdx1,
2817 unsigned &SrcOpIdx2)
const {
2819 if (!
Desc.isCommutable())
2822 switch (
MI.getOpcode()) {
2827 case X86::VCMPSDrri:
2828 case X86::VCMPSSrri:
2829 case X86::VCMPPDrri:
2830 case X86::VCMPPSrri:
2831 case X86::VCMPPDYrri:
2832 case X86::VCMPPSYrri:
2833 case X86::VCMPSDZrri:
2834 case X86::VCMPSSZrri:
2835 case X86::VCMPPDZrri:
2836 case X86::VCMPPSZrri:
2837 case X86::VCMPSHZrri:
2838 case X86::VCMPPHZrri:
2839 case X86::VCMPPHZ128rri:
2840 case X86::VCMPPHZ256rri:
2841 case X86::VCMPPDZ128rri:
2842 case X86::VCMPPSZ128rri:
2843 case X86::VCMPPDZ256rri:
2844 case X86::VCMPPSZ256rri:
2845 case X86::VCMPPDZrrik:
2846 case X86::VCMPPSZrrik:
2847 case X86::VCMPPDZ128rrik:
2848 case X86::VCMPPSZ128rrik:
2849 case X86::VCMPPDZ256rrik:
2850 case X86::VCMPPSZ256rrik: {
2855 unsigned Imm =
MI.getOperand(3 + OpOffset).getImm() & 0x7;
2872 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2882 case X86::SHUFPDrri:
2884 if (
MI.getOperand(3).getImm() == 0x02)
2887 case X86::MOVHLPSrr:
2888 case X86::UNPCKHPDrr:
2889 case X86::VMOVHLPSrr:
2890 case X86::VUNPCKHPDrr:
2891 case X86::VMOVHLPSZrr:
2892 case X86::VUNPCKHPDZ128rr:
2896 case X86::VPTERNLOGDZrri:
2897 case X86::VPTERNLOGDZrmi:
2898 case X86::VPTERNLOGDZ128rri:
2899 case X86::VPTERNLOGDZ128rmi:
2900 case X86::VPTERNLOGDZ256rri:
2901 case X86::VPTERNLOGDZ256rmi:
2902 case X86::VPTERNLOGQZrri:
2903 case X86::VPTERNLOGQZrmi:
2904 case X86::VPTERNLOGQZ128rri:
2905 case X86::VPTERNLOGQZ128rmi:
2906 case X86::VPTERNLOGQZ256rri:
2907 case X86::VPTERNLOGQZ256rmi:
2908 case X86::VPTERNLOGDZrrik:
2909 case X86::VPTERNLOGDZ128rrik:
2910 case X86::VPTERNLOGDZ256rrik:
2911 case X86::VPTERNLOGQZrrik:
2912 case X86::VPTERNLOGQZ128rrik:
2913 case X86::VPTERNLOGQZ256rrik:
2914 case X86::VPTERNLOGDZrrikz:
2915 case X86::VPTERNLOGDZrmikz:
2916 case X86::VPTERNLOGDZ128rrikz:
2917 case X86::VPTERNLOGDZ128rmikz:
2918 case X86::VPTERNLOGDZ256rrikz:
2919 case X86::VPTERNLOGDZ256rmikz:
2920 case X86::VPTERNLOGQZrrikz:
2921 case X86::VPTERNLOGQZrmikz:
2922 case X86::VPTERNLOGQZ128rrikz:
2923 case X86::VPTERNLOGQZ128rmikz:
2924 case X86::VPTERNLOGQZ256rrikz:
2925 case X86::VPTERNLOGQZ256rmikz:
2926 case X86::VPTERNLOGDZ128rmbi:
2927 case X86::VPTERNLOGDZ256rmbi:
2928 case X86::VPTERNLOGDZrmbi:
2929 case X86::VPTERNLOGQZ128rmbi:
2930 case X86::VPTERNLOGQZ256rmbi:
2931 case X86::VPTERNLOGQZrmbi:
2932 case X86::VPTERNLOGDZ128rmbikz:
2933 case X86::VPTERNLOGDZ256rmbikz:
2934 case X86::VPTERNLOGDZrmbikz:
2935 case X86::VPTERNLOGQZ128rmbikz:
2936 case X86::VPTERNLOGQZ256rmbikz:
2937 case X86::VPTERNLOGQZrmbikz:
2938 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2);
2939 case X86::VPDPWSSDYrr:
2940 case X86::VPDPWSSDrr:
2941 case X86::VPDPWSSDSYrr:
2942 case X86::VPDPWSSDSrr:
2943 case X86::VPDPWUUDrr:
2944 case X86::VPDPWUUDYrr:
2945 case X86::VPDPWUUDSrr:
2946 case X86::VPDPWUUDSYrr:
2947 case X86::VPDPBSSDSrr:
2948 case X86::VPDPBSSDSYrr:
2949 case X86::VPDPBSSDrr:
2950 case X86::VPDPBSSDYrr:
2951 case X86::VPDPBUUDSrr:
2952 case X86::VPDPBUUDSYrr:
2953 case X86::VPDPBUUDrr:
2954 case X86::VPDPBUUDYrr:
2955 case X86::VPDPBSSDSZ128r:
2956 case X86::VPDPBSSDSZ128rk:
2957 case X86::VPDPBSSDSZ128rkz:
2958 case X86::VPDPBSSDSZ256r:
2959 case X86::VPDPBSSDSZ256rk:
2960 case X86::VPDPBSSDSZ256rkz:
2961 case X86::VPDPBSSDSZr:
2962 case X86::VPDPBSSDSZrk:
2963 case X86::VPDPBSSDSZrkz:
2964 case X86::VPDPBSSDZ128r:
2965 case X86::VPDPBSSDZ128rk:
2966 case X86::VPDPBSSDZ128rkz:
2967 case X86::VPDPBSSDZ256r:
2968 case X86::VPDPBSSDZ256rk:
2969 case X86::VPDPBSSDZ256rkz:
2970 case X86::VPDPBSSDZr:
2971 case X86::VPDPBSSDZrk:
2972 case X86::VPDPBSSDZrkz:
2973 case X86::VPDPBUUDSZ128r:
2974 case X86::VPDPBUUDSZ128rk:
2975 case X86::VPDPBUUDSZ128rkz:
2976 case X86::VPDPBUUDSZ256r:
2977 case X86::VPDPBUUDSZ256rk:
2978 case X86::VPDPBUUDSZ256rkz:
2979 case X86::VPDPBUUDSZr:
2980 case X86::VPDPBUUDSZrk:
2981 case X86::VPDPBUUDSZrkz:
2982 case X86::VPDPBUUDZ128r:
2983 case X86::VPDPBUUDZ128rk:
2984 case X86::VPDPBUUDZ128rkz:
2985 case X86::VPDPBUUDZ256r:
2986 case X86::VPDPBUUDZ256rk:
2987 case X86::VPDPBUUDZ256rkz:
2988 case X86::VPDPBUUDZr:
2989 case X86::VPDPBUUDZrk:
2990 case X86::VPDPBUUDZrkz:
2991 case X86::VPDPWSSDZ128r:
2992 case X86::VPDPWSSDZ128rk:
2993 case X86::VPDPWSSDZ128rkz:
2994 case X86::VPDPWSSDZ256r:
2995 case X86::VPDPWSSDZ256rk:
2996 case X86::VPDPWSSDZ256rkz:
2997 case X86::VPDPWSSDZr:
2998 case X86::VPDPWSSDZrk:
2999 case X86::VPDPWSSDZrkz:
3000 case X86::VPDPWSSDSZ128r:
3001 case X86::VPDPWSSDSZ128rk:
3002 case X86::VPDPWSSDSZ128rkz:
3003 case X86::VPDPWSSDSZ256r:
3004 case X86::VPDPWSSDSZ256rk:
3005 case X86::VPDPWSSDSZ256rkz:
3006 case X86::VPDPWSSDSZr:
3007 case X86::VPDPWSSDSZrk:
3008 case X86::VPDPWSSDSZrkz:
3009 case X86::VPDPWUUDZ128r:
3010 case X86::VPDPWUUDZ128rk:
3011 case X86::VPDPWUUDZ128rkz:
3012 case X86::VPDPWUUDZ256r:
3013 case X86::VPDPWUUDZ256rk:
3014 case X86::VPDPWUUDZ256rkz:
3015 case X86::VPDPWUUDZr:
3016 case X86::VPDPWUUDZrk:
3017 case X86::VPDPWUUDZrkz:
3018 case X86::VPDPWUUDSZ128r:
3019 case X86::VPDPWUUDSZ128rk:
3020 case X86::VPDPWUUDSZ128rkz:
3021 case X86::VPDPWUUDSZ256r:
3022 case X86::VPDPWUUDSZ256rk:
3023 case X86::VPDPWUUDSZ256rkz:
3024 case X86::VPDPWUUDSZr:
3025 case X86::VPDPWUUDSZrk:
3026 case X86::VPDPWUUDSZrkz:
3027 case X86::VPMADD52HUQrr:
3028 case X86::VPMADD52HUQYrr:
3029 case X86::VPMADD52HUQZ128r:
3030 case X86::VPMADD52HUQZ128rk:
3031 case X86::VPMADD52HUQZ128rkz:
3032 case X86::VPMADD52HUQZ256r:
3033 case X86::VPMADD52HUQZ256rk:
3034 case X86::VPMADD52HUQZ256rkz:
3035 case X86::VPMADD52HUQZr:
3036 case X86::VPMADD52HUQZrk:
3037 case X86::VPMADD52HUQZrkz:
3038 case X86::VPMADD52LUQrr:
3039 case X86::VPMADD52LUQYrr:
3040 case X86::VPMADD52LUQZ128r:
3041 case X86::VPMADD52LUQZ128rk:
3042 case X86::VPMADD52LUQZ128rkz:
3043 case X86::VPMADD52LUQZ256r:
3044 case X86::VPMADD52LUQZ256rk:
3045 case X86::VPMADD52LUQZ256rkz:
3046 case X86::VPMADD52LUQZr:
3047 case X86::VPMADD52LUQZrk:
3048 case X86::VPMADD52LUQZrkz:
3049 case X86::VFMADDCPHZr:
3050 case X86::VFMADDCPHZrk:
3051 case X86::VFMADDCPHZrkz:
3052 case X86::VFMADDCPHZ128r:
3053 case X86::VFMADDCPHZ128rk:
3054 case X86::VFMADDCPHZ128rkz:
3055 case X86::VFMADDCPHZ256r:
3056 case X86::VFMADDCPHZ256rk:
3057 case X86::VFMADDCPHZ256rkz:
3058 case X86::VFMADDCSHZr:
3059 case X86::VFMADDCSHZrk:
3060 case X86::VFMADDCSHZrkz: {
3061 unsigned CommutableOpIdx1 = 2;
3062 unsigned CommutableOpIdx2 = 3;
3068 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3071 if (!
MI.getOperand(SrcOpIdx1).isReg() || !
MI.getOperand(SrcOpIdx2).isReg())
3081 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2,
3088 unsigned CommutableOpIdx1 =
Desc.getNumDefs() + 1;
3089 unsigned CommutableOpIdx2 =
Desc.getNumDefs() + 2;
3092 if ((
MI.getDesc().getOperandConstraint(
Desc.getNumDefs(),
3107 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3111 if (!
MI.getOperand(SrcOpIdx1).isReg() ||
3112 !
MI.getOperand(SrcOpIdx2).isReg())
3124 unsigned Opcode =
MI->getOpcode();
3125 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3126 Opcode != X86::LEA64_32r)
3148 unsigned Opcode =
MI.getOpcode();
3149 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3177 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3178 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3179 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3201 return X86::isSETCC(
MI.getOpcode()) || X86::isSETZUCC(
MI.getOpcode())
3217 return X86::isCCMPCC(
MI.getOpcode()) || X86::isCTESTCC(
MI.getOpcode())
3248 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3279#define GET_X86_NF_TRANSFORM_TABLE
3280#define GET_X86_ND2NONND_TABLE
3281#include "X86GenInstrMapping.inc"
3286 return (
I == Table.
end() ||
I->OldOpc != Opc) ? 0U :
I->NewOpc;
3370std::pair<X86::CondCode, bool>
3373 bool NeedSwap =
false;
3374 switch (Predicate) {
3453 return std::make_pair(
CC, NeedSwap);
3462#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3556 switch (Imm & 0x3) {
3574 if (
Info.RegClass == X86::VR128RegClassID ||
3575 Info.RegClass == X86::VR128XRegClassID)
3577 if (
Info.RegClass == X86::VR256RegClassID ||
3578 Info.RegClass == X86::VR256XRegClassID)
3580 if (
Info.RegClass == X86::VR512RegClassID)
3587 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3588 (Reg >= X86::ST0 && Reg <= X86::ST7));
3596 if (
MI.isCall() ||
MI.isInlineAsm())
3620#ifdef EXPENSIVE_CHECKS
3622 "Got false negative from X86II::getMemoryOperandNo()!");
3630 unsigned NumOps =
Desc.getNumOperands();
3632#ifdef EXPENSIVE_CHECKS
3634 "Expected no operands to have OPERAND_MEMORY type!");
3643 if (IsMemOp(
Desc.operands()[
I])) {
3644#ifdef EXPENSIVE_CHECKS
3648 "Expected all five operands in the memory reference to have "
3649 "OPERAND_MEMORY type!");
3661 "Unexpected number of operands!");
3664 if (!Index.isReg() || Index.getReg() != X86::NoRegister)
3672 MI.getParent()->getParent()->getConstantPool()->getConstants();
3684 switch (
MI.getOpcode()) {
3685 case X86::TCRETURNdi:
3686 case X86::TCRETURNri:
3687 case X86::TCRETURNmi:
3688 case X86::TCRETURNdi64:
3689 case X86::TCRETURNri64:
3690 case X86::TCRETURNmi64:
3709 if (Symbol ==
"__x86_indirect_thunk_r11")
3714 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3715 TailCall.getOpcode() != X86::TCRETURNdi64) {
3733 TailCall.getOperand(1).getImm() != 0) {
3749 if (
I->isDebugInstr())
3752 assert(0 &&
"Can't find the branch to replace!");
3756 if (
CC != BranchCond[0].getImm())
3762 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3763 : X86::TCRETURNdi64cc;
3777 for (
const auto &
C : Clobbers) {
3782 I->eraseFromParent();
3796 if (Succ->isEHPad() || (Succ ==
TBB && FallthroughBB))
3799 if (FallthroughBB && FallthroughBB !=
TBB)
3801 FallthroughBB = Succ;
3803 return FallthroughBB;
3806bool X86InstrInfo::analyzeBranchImpl(
3817 if (
I->isDebugInstr())
3822 if (!isUnpredicatedTerminator(*
I))
3831 if (
I->getOpcode() == X86::JMP_1) {
3835 TBB =
I->getOperand(0).getMBB();
3848 I->eraseFromParent();
3850 UnCondBrIter =
MBB.
end();
3855 TBB =
I->getOperand(0).getMBB();
3866 if (
I->findRegisterUseOperand(X86::EFLAGS,
nullptr)->isUndef())
3872 TBB =
I->getOperand(0).getMBB();
3886 auto NewTBB =
I->getOperand(0).getMBB();
3887 if (OldBranchCode == BranchCode &&
TBB == NewTBB)
3893 if (
TBB == NewTBB &&
3926 Cond[0].setImm(BranchCode);
3937 bool AllowModify)
const {
3939 return analyzeBranchImpl(
MBB,
TBB, FBB,
Cond, CondBranches, AllowModify);
3945 assert(MemRefBegin >= 0 &&
"instr should have memory operand");
3957 if (!Reg.isVirtual())
3962 unsigned Opcode =
MI->getOpcode();
3963 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
3969 unsigned Opcode =
MI.getOpcode();
3972 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
3980 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
3982 if (!Reg.isVirtual())
3989 if (
Add->getOpcode() != X86::ADD64rr &&
Add->getOpcode() != X86::ADD32rr)
4002 MachineBranchPredicate &MBP,
4003 bool AllowModify)
const {
4004 using namespace std::placeholders;
4008 if (analyzeBranchImpl(
MBB, MBP.TrueDest, MBP.FalseDest,
Cond, CondBranches,
4012 if (
Cond.size() != 1)
4015 assert(MBP.TrueDest &&
"expected!");
4023 bool SingleUseCondition =
true;
4026 if (
MI.modifiesRegister(X86::EFLAGS,
TRI)) {
4031 if (
MI.readsRegister(X86::EFLAGS,
TRI))
4032 SingleUseCondition =
false;
4038 if (SingleUseCondition) {
4040 if (Succ->isLiveIn(X86::EFLAGS))
4041 SingleUseCondition =
false;
4044 MBP.ConditionDef = ConditionDef;
4045 MBP.SingleUseCondition = SingleUseCondition;
4052 const unsigned TestOpcode =
4053 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4055 if (ConditionDef->
getOpcode() == TestOpcode &&
4062 ? MachineBranchPredicate::PRED_NE
4063 : MachineBranchPredicate::PRED_EQ;
4071 int *BytesRemoved)
const {
4072 assert(!BytesRemoved &&
"code size not handled");
4079 if (
I->isDebugInstr())
4081 if (
I->getOpcode() != X86::JMP_1 &&
4085 I->eraseFromParent();
4099 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
4101 "X86 branch conditions have one component!");
4102 assert(!BytesAdded &&
"code size not handled");
4106 assert(!FBB &&
"Unconditional branch with multiple successors!");
4112 bool FallThru = FBB ==
nullptr;
4127 if (FBB ==
nullptr) {
4129 assert(FBB &&
"MBB cannot be the last block in function when the false "
4130 "body is a fall-through.");
4154 Register FalseReg,
int &CondCycles,
4155 int &TrueCycles,
int &FalseCycles)
const {
4159 if (
Cond.size() != 1)
4168 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
4173 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4174 X86::GR32RegClass.hasSubClassEq(RC) ||
4175 X86::GR64RegClass.hasSubClassEq(RC)) {
4196 assert(
Cond.size() == 1 &&
"Invalid Cond array");
4199 false , Subtarget.hasNDD());
4208 return X86::GR8_ABCD_HRegClass.contains(Reg);
4214 bool HasAVX = Subtarget.
hasAVX();
4216 bool HasEGPR = Subtarget.hasEGPR();
4223 if (X86::VK16RegClass.
contains(SrcReg)) {
4224 if (X86::GR64RegClass.
contains(DestReg)) {
4225 assert(Subtarget.hasBWI());
4226 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4228 if (X86::GR32RegClass.
contains(DestReg))
4229 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4230 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4238 if (X86::VK16RegClass.
contains(DestReg)) {
4239 if (X86::GR64RegClass.
contains(SrcReg)) {
4240 assert(Subtarget.hasBWI());
4241 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4243 if (X86::GR32RegClass.
contains(SrcReg))
4244 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4245 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4253 if (X86::GR64RegClass.
contains(DestReg)) {
4254 if (X86::VR128XRegClass.
contains(SrcReg))
4256 return HasAVX512 ? X86::VMOVPQIto64Zrr
4257 : HasAVX ? X86::VMOVPQIto64rr
4258 : X86::MOVPQIto64rr;
4259 if (X86::VR64RegClass.
contains(SrcReg))
4261 return X86::MMX_MOVD64from64rr;
4262 }
else if (X86::GR64RegClass.
contains(SrcReg)) {
4264 if (X86::VR128XRegClass.
contains(DestReg))
4265 return HasAVX512 ? X86::VMOV64toPQIZrr
4266 : HasAVX ? X86::VMOV64toPQIrr
4267 : X86::MOV64toPQIrr;
4269 if (X86::VR64RegClass.
contains(DestReg))
4270 return X86::MMX_MOVD64to64rr;
4276 if (X86::GR32RegClass.
contains(DestReg) &&
4277 X86::VR128XRegClass.contains(SrcReg))
4279 return HasAVX512 ? X86::VMOVPDI2DIZrr
4280 : HasAVX ? X86::VMOVPDI2DIrr
4283 if (X86::VR128XRegClass.
contains(DestReg) &&
4284 X86::GR32RegClass.contains(SrcReg))
4286 return HasAVX512 ? X86::VMOVDI2PDIZrr
4287 : HasAVX ? X86::VMOVDI2PDIrr
4296 bool RenamableDest,
bool RenamableSrc)
const {
4298 bool HasAVX = Subtarget.
hasAVX();
4299 bool HasVLX = Subtarget.hasVLX();
4300 bool HasEGPR = Subtarget.hasEGPR();
4302 if (X86::GR64RegClass.
contains(DestReg, SrcReg))
4304 else if (X86::GR32RegClass.
contains(DestReg, SrcReg))
4306 else if (X86::GR16RegClass.
contains(DestReg, SrcReg))
4308 else if (X86::GR8RegClass.
contains(DestReg, SrcReg)) {
4311 if ((
isHReg(DestReg) ||
isHReg(SrcReg)) && Subtarget.is64Bit()) {
4312 Opc = X86::MOV8rr_NOREX;
4315 "8-bit H register can not be copied outside GR8_NOREX");
4318 }
else if (X86::VR64RegClass.
contains(DestReg, SrcReg))
4319 Opc = X86::MMX_MOVQ64rr;
4320 else if (X86::VR128XRegClass.
contains(DestReg, SrcReg)) {
4322 Opc = X86::VMOVAPSZ128rr;
4323 else if (X86::VR128RegClass.
contains(DestReg, SrcReg))
4324 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4328 Opc = X86::VMOVAPSZrr;
4331 TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass);
4333 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4335 }
else if (X86::VR256XRegClass.
contains(DestReg, SrcReg)) {
4337 Opc = X86::VMOVAPSZ256rr;
4338 else if (X86::VR256RegClass.
contains(DestReg, SrcReg))
4339 Opc = X86::VMOVAPSYrr;
4343 Opc = X86::VMOVAPSZrr;
4346 TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass);
4348 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4350 }
else if (X86::VR512RegClass.
contains(DestReg, SrcReg))
4351 Opc = X86::VMOVAPSZrr;
4354 else if (X86::VK16RegClass.
contains(DestReg, SrcReg))
4355 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4356 : (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
4366 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4374 LLVM_DEBUG(
dbgs() <<
"Cannot copy " << RI.getName(SrcReg) <<
" to "
4375 << RI.getName(DestReg) <<
'\n');
4379std::optional<DestSourcePair>
4381 if (
MI.isMoveReg()) {
4385 if (
MI.getOperand(0).isUndef() &&
MI.getOperand(0).getSubReg())
4386 return std::nullopt;
4390 return std::nullopt;
4395 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4398 : STI.
hasAVX() ? X86::VMOVSSrm
4402 : STI.
hasAVX() ? X86::VMOVSSmr
4408 bool IsStackAligned,
4410 bool HasAVX = STI.
hasAVX();
4412 bool HasVLX = STI.hasVLX();
4413 bool HasEGPR = STI.hasEGPR();
4415 assert(RC !=
nullptr &&
"Invalid target register class");
4420 assert(X86::GR8RegClass.hasSubClassEq(RC) &&
"Unknown 1-byte regclass");
4424 if (
isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4425 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4426 return Load ? X86::MOV8rm : X86::MOV8mr;
4428 if (X86::VK16RegClass.hasSubClassEq(RC))
4429 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4430 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4431 assert(X86::GR16RegClass.hasSubClassEq(RC) &&
"Unknown 2-byte regclass");
4432 return Load ? X86::MOV16rm : X86::MOV16mr;
4434 if (X86::GR32RegClass.hasSubClassEq(RC))
4435 return Load ? X86::MOV32rm : X86::MOV32mr;
4436 if (X86::FR32XRegClass.hasSubClassEq(RC))
4437 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4438 : HasAVX ? X86::VMOVSSrm_alt
4440 : (HasAVX512 ? X86::VMOVSSZmr
4441 : HasAVX ? X86::VMOVSSmr
4443 if (X86::RFP32RegClass.hasSubClassEq(RC))
4444 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4445 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4446 assert(STI.hasBWI() &&
"KMOVD requires BWI");
4447 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4448 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4452 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4453 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4454 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4455 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4456 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4457 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4458 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4459 X86::FR16XRegClass.hasSubClassEq(RC))
4463 if (X86::GR64RegClass.hasSubClassEq(RC))
4464 return Load ? X86::MOV64rm : X86::MOV64mr;
4465 if (X86::FR64XRegClass.hasSubClassEq(RC))
4466 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4467 : HasAVX ? X86::VMOVSDrm_alt
4469 : (HasAVX512 ? X86::VMOVSDZmr
4470 : HasAVX ? X86::VMOVSDmr
4472 if (X86::VR64RegClass.hasSubClassEq(RC))
4473 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4474 if (X86::RFP64RegClass.hasSubClassEq(RC))
4475 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4476 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4477 assert(STI.hasBWI() &&
"KMOVQ requires BWI");
4478 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4479 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4483 assert(X86::RFP80RegClass.hasSubClassEq(RC) &&
"Unknown 10-byte regclass");
4484 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4486 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4489 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4490 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4491 : HasAVX ? X86::VMOVAPSrm
4493 : (HasVLX ? X86::VMOVAPSZ128mr
4494 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4495 : HasAVX ? X86::VMOVAPSmr
4498 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4499 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4500 : HasAVX ? X86::VMOVUPSrm
4502 : (HasVLX ? X86::VMOVUPSZ128mr
4503 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4504 : HasAVX ? X86::VMOVUPSmr
4510 assert(X86::VR256XRegClass.hasSubClassEq(RC) &&
"Unknown 32-byte regclass");
4513 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4514 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4516 : (HasVLX ? X86::VMOVAPSZ256mr
4517 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4520 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4521 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4523 : (HasVLX ? X86::VMOVUPSZ256mr
4524 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4527 assert(X86::VR512RegClass.hasSubClassEq(RC) &&
"Unknown 64-byte regclass");
4530 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4532 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4534 assert(X86::TILERegClass.hasSubClassEq(RC) &&
"Unknown 1024-byte regclass");
4535 assert(STI.hasAMXTILE() &&
"Using 8*1024-bit register requires AMX-TILE");
4536#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4539#undef GET_EGPR_IF_ENABLED
4541 assert(X86::TILEPAIRRegClass.hasSubClassEq(RC) &&
4542 "Unknown 2048-byte regclass");
4543 assert(STI.hasAMXTILE() &&
"Using 2048-bit register requires AMX-TILE");
4544 return Load ? X86::PTILEPAIRLOAD : X86::PTILEPAIRSTORE;
4548std::optional<ExtAddrMode>
4553 if (MemRefBegin < 0)
4554 return std::nullopt;
4559 if (!BaseOp.isReg())
4560 return std::nullopt;
4564 if (!DispMO.
isImm())
4565 return std::nullopt;
4591 ErrInfo =
"Scale factor in address must be 1, 2, 4 or 8";
4596 ErrInfo =
"Displacement in address must fit into 32-bit signed "
4606 int64_t &ImmVal)
const {
4612 if (
MI.isSubregToReg()) {
4616 if (!
MI.getOperand(1).isImm())
4618 unsigned FillBits =
MI.getOperand(1).getImm();
4619 unsigned SubIdx =
MI.getOperand(3).getImm();
4620 MovReg =
MI.getOperand(2).getReg();
4621 if (SubIdx != X86::sub_32bit || FillBits != 0)
4624 MovMI =
MRI.getUniqueVRegDef(MovReg);
4629 if (MovMI->
getOpcode() == X86::MOV32r0 &&
4635 if (MovMI->
getOpcode() != X86::MOV32ri &&
4649 if (!
MI->modifiesRegister(NullValueReg,
TRI))
4651 switch (
MI->getOpcode()) {
4658 assert(
MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() &&
4659 "expected for shift opcode!");
4660 return MI->getOperand(0).getReg() == NullValueReg &&
4661 MI->getOperand(1).getReg() == NullValueReg;
4666 return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
4680 if (MemRefBegin < 0)
4687 if (!BaseOp->
isReg())
4700 if (!DispMO.
isImm())
4705 if (!BaseOp->
isReg())
4708 OffsetIsScalable =
false;
4713 !
MemOp.memoperands_empty() ?
MemOp.memoperands().front()->getSize() : 0;
4720 bool IsStackAligned,
4735 case X86::TILELOADD:
4736 case X86::TILESTORED:
4737 case X86::TILELOADD_EVEX:
4738 case X86::TILESTORED_EVEX:
4739 case X86::PTILEPAIRLOAD:
4740 case X86::PTILEPAIRSTORE:
4747 unsigned Opc,
Register Reg,
int FrameIdx,
4748 bool isKill)
const {
4752 case X86::TILESTORED:
4753 case X86::TILESTORED_EVEX:
4754 case X86::PTILEPAIRSTORE: {
4767 case X86::TILELOADD:
4768 case X86::TILELOADD_EVEX:
4769 case X86::PTILEPAIRLOAD: {
4791 "Stack slot too small for store");
4793 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4815 "Load size exceeds stack slot");
4816 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4830 Register &SrcReg2, int64_t &CmpMask,
4831 int64_t &CmpValue)
const {
4832 switch (
MI.getOpcode()) {
4835 case X86::CMP64ri32:
4839 SrcReg =
MI.getOperand(0).getReg();
4841 if (
MI.getOperand(1).isImm()) {
4843 CmpValue =
MI.getOperand(1).getImm();
4845 CmpMask = CmpValue = 0;
4853 SrcReg =
MI.getOperand(1).getReg();
4862 SrcReg =
MI.getOperand(1).getReg();
4863 SrcReg2 =
MI.getOperand(2).getReg();
4871 SrcReg =
MI.getOperand(1).getReg();
4873 if (
MI.getOperand(2).isImm()) {
4875 CmpValue =
MI.getOperand(2).getImm();
4877 CmpMask = CmpValue = 0;
4884 SrcReg =
MI.getOperand(0).getReg();
4885 SrcReg2 =
MI.getOperand(1).getReg();
4893 SrcReg =
MI.getOperand(0).getReg();
4894 if (
MI.getOperand(1).getReg() != SrcReg)
4905bool X86InstrInfo::isRedundantFlagInstr(
const MachineInstr &FlagI,
4907 int64_t ImmMask, int64_t ImmValue,
4909 int64_t *ImmDelta)
const {
4924 OIMask != ImmMask || OIValue != ImmValue)
4926 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4930 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4936 case X86::CMP64ri32:
4947 case X86::TEST8rr: {
4954 SrcReg == OISrcReg && ImmMask == OIMask) {
4955 if (OIValue == ImmValue) {
4958 }
else if (
static_cast<uint64_t>(ImmValue) ==
4959 static_cast<uint64_t>(OIValue) - 1) {
4962 }
else if (
static_cast<uint64_t>(ImmValue) ==
4963 static_cast<uint64_t>(OIValue) + 1) {
4981 bool &ClearsOverflowFlag) {
4983 ClearsOverflowFlag =
false;
4989 if (
MI.getOpcode() == X86::ADD64rm ||
MI.getOpcode() == X86::ADD32rm) {
4990 unsigned Flags =
MI.getOperand(5).getTargetFlags();
4996 switch (
MI.getOpcode()) {
5092 case X86::LZCNT16rr:
5093 case X86::LZCNT16rm:
5094 case X86::LZCNT32rr:
5095 case X86::LZCNT32rm:
5096 case X86::LZCNT64rr:
5097 case X86::LZCNT64rm:
5098 case X86::POPCNT16rr:
5099 case X86::POPCNT16rm:
5100 case X86::POPCNT32rr:
5101 case X86::POPCNT32rm:
5102 case X86::POPCNT64rr:
5103 case X86::POPCNT64rm:
5104 case X86::TZCNT16rr:
5105 case X86::TZCNT16rm:
5106 case X86::TZCNT32rr:
5107 case X86::TZCNT32rm:
5108 case X86::TZCNT64rr:
5109 case X86::TZCNT64rm:
5155 case X86::BLSMSK32rr:
5156 case X86::BLSMSK32rm:
5157 case X86::BLSMSK64rr:
5158 case X86::BLSMSK64rm:
5163 case X86::BLCFILL32rr:
5164 case X86::BLCFILL32rm:
5165 case X86::BLCFILL64rr:
5166 case X86::BLCFILL64rm:
5171 case X86::BLCIC32rr:
5172 case X86::BLCIC32rm:
5173 case X86::BLCIC64rr:
5174 case X86::BLCIC64rm:
5175 case X86::BLCMSK32rr:
5176 case X86::BLCMSK32rm:
5177 case X86::BLCMSK64rr:
5178 case X86::BLCMSK64rm:
5183 case X86::BLSFILL32rr:
5184 case X86::BLSFILL32rm:
5185 case X86::BLSFILL64rr:
5186 case X86::BLSFILL64rm:
5187 case X86::BLSIC32rr:
5188 case X86::BLSIC32rm:
5189 case X86::BLSIC64rr:
5190 case X86::BLSIC64rm:
5195 case X86::T1MSKC32rr:
5196 case X86::T1MSKC32rm:
5197 case X86::T1MSKC64rr:
5198 case X86::T1MSKC64rm:
5199 case X86::TZMSK32rr:
5200 case X86::TZMSK32rm:
5201 case X86::TZMSK64rr:
5202 case X86::TZMSK64rm:
5206 ClearsOverflowFlag =
true;
5208 case X86::BEXTR32rr:
5209 case X86::BEXTR64rr:
5210 case X86::BEXTR32rm:
5211 case X86::BEXTR64rm:
5212 case X86::BEXTRI32ri:
5213 case X86::BEXTRI32mi:
5214 case X86::BEXTRI64ri:
5215 case X86::BEXTRI64mi:
5225 switch (
MI.getOpcode()) {
5233 case X86::LZCNT16rr:
5234 case X86::LZCNT32rr:
5235 case X86::LZCNT64rr:
5237 case X86::POPCNT16rr:
5238 case X86::POPCNT32rr:
5239 case X86::POPCNT64rr:
5241 case X86::TZCNT16rr:
5242 case X86::TZCNT32rr:
5243 case X86::TZCNT64rr:
5257 case X86::BLSMSK32rr:
5258 case X86::BLSMSK64rr:
5290 unsigned NewOpcode = 0;
5291#define FROM_TO(A, B) \
5292 CASE_ND(A) NewOpcode = X86::B; \
5316 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5317 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5325 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5331 assert(SrcRegDef &&
"Must have a definition (SSA)");
5336 bool NoSignFlag =
false;
5337 bool ClearsOverflowFlag =
false;
5338 bool ShouldUpdateCC =
false;
5339 bool IsSwapped =
false;
5341 int64_t ImmDelta = 0;
5354 if (&Inst == SrcRegDef) {
5377 NoSignFlag, ClearsOverflowFlag)) {
5386 if (Inst.modifiesRegister(X86::EFLAGS,
TRI)) {
5397 Inst.getOperand(1).getReg() == SrcReg) {
5398 ShouldUpdateCC =
true;
5409 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
5410 Inst, &IsSwapped, &ImmDelta)) {
5418 if (!Movr0Inst && Inst.
getOpcode() == X86::MOV32r0 &&
5419 Inst.registerDefIsDead(X86::EFLAGS,
TRI)) {
5444 bool FlagsMayLiveOut =
true;
5449 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS,
TRI);
5450 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS,
TRI);
5452 if (!UseEFLAGS && ModifyEFLAGS) {
5454 FlagsMayLiveOut =
false;
5457 if (!UseEFLAGS && !ModifyEFLAGS)
5488 if (!ClearsOverflowFlag)
5507 ReplacementCC = NewCC;
5513 }
else if (IsSwapped) {
5520 ShouldUpdateCC =
true;
5521 }
else if (ImmDelta != 0) {
5522 unsigned BitWidth =
TRI->getRegSizeInBits(*
MRI->getRegClass(SrcReg));
5532 if (ImmDelta != 1 || CmpValue == 0)
5542 if (ImmDelta != 1 || CmpValue == 0)
5569 ShouldUpdateCC =
true;
5572 if (ShouldUpdateCC && ReplacementCC != OldCC) {
5576 OpsToUpdate.
push_back(std::make_pair(&Instr, ReplacementCC));
5578 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS,
TRI)) {
5580 FlagsMayLiveOut =
false;
5587 if ((
MI !=
nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
5594 assert((
MI ==
nullptr || Sub ==
nullptr) &&
"Should not have Sub and MI set");
5595 Sub =
MI !=
nullptr ?
MI : Sub;
5601 if (&CmpMBB != SubBB)
5606 for (; InsertI != InsertE; ++InsertI) {
5608 if (!Instr->readsRegister(X86::EFLAGS,
TRI) &&
5609 Instr->modifiesRegister(X86::EFLAGS,
TRI)) {
5616 if (InsertI == InsertE)
5623 assert(FlagDef &&
"Unable to locate a def EFLAGS operand");
5629 for (
auto &
Op : OpsToUpdate) {
5652 DefMI =
MRI->getVRegDef(FoldAsLoadDefReg);
5654 bool SawStore =
false;
5660 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
5665 if (Reg != FoldAsLoadDefReg)
5672 if (SrcOperandIds.
empty())
5677 FoldAsLoadDefReg = 0;
5707#define FROM_TO(FROM, TO) \
5710 case X86::FROM##_ND: \
5711 return X86::TO##_ND;
5741#define FROM_TO(FROM, TO) \
5745 FROM_TO(CTEST64rr, CTEST64ri32)
5764 bool MakeChange)
const {
5771 if (
Reg.isVirtual())
5772 RC =
MRI->getRegClass(Reg);
5773 if ((
Reg.isPhysical() && X86::GR64RegClass.contains(Reg)) ||
5774 (
Reg.isVirtual() && X86::GR64RegClass.hasSubClassEq(RC))) {
5775 if (!isInt<32>(ImmVal))
5779 if (
UseMI.findRegisterUseOperand(Reg,
nullptr)->getSubReg())
5783 if (
UseMI.getMF()->getFunction().hasOptSize() &&
Reg.isVirtual() &&
5784 !
MRI->hasOneNonDBGUse(Reg))
5787 unsigned Opc =
UseMI.getOpcode();
5789 if (Opc == TargetOpcode::COPY) {
5793 RC =
MRI->getRegClass(ToReg);
5794 bool GR32Reg = (ToReg.
isVirtual() && X86::GR32RegClass.hasSubClassEq(RC)) ||
5795 (ToReg.
isPhysical() && X86::GR32RegClass.contains(ToReg));
5796 bool GR64Reg = (ToReg.
isVirtual() && X86::GR64RegClass.hasSubClassEq(RC)) ||
5797 (ToReg.
isPhysical() && X86::GR64RegClass.contains(ToReg));
5798 bool GR8Reg = (ToReg.
isVirtual() && X86::GR8RegClass.hasSubClassEq(RC)) ||
5799 (ToReg.
isPhysical() && X86::GR8RegClass.contains(ToReg));
5808 if (isUInt<32>(ImmVal))
5809 NewOpc = X86::MOV32ri64;
5811 NewOpc = X86::MOV64ri;
5812 }
else if (GR32Reg) {
5813 NewOpc = X86::MOV32ri;
5817 if (
UseMI.getParent()->computeRegisterLiveness(
5826 UseMI.removeOperand(
5827 UseMI.findRegisterUseOperandIdx(Reg,
nullptr));
5835 NewOpc = X86::MOV8ri;
5845 if ((NewOpc == X86::SUB64ri32 || NewOpc == X86::SUB32ri ||
5846 NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri ||
5847 NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND ||
5848 NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) &&
5849 UseMI.findRegisterUseOperandIdx(Reg,
nullptr) != 2)
5852 if (((NewOpc == X86::CMP64ri32 || NewOpc == X86::CMP32ri) ||
5853 (NewOpc == X86::CCMP64ri32 || NewOpc == X86::CCMP32ri)) &&
5854 UseMI.findRegisterUseOperandIdx(Reg,
nullptr) != 1)
5857 using namespace X86;
5858 if (isSHL(Opc) || isSHR(Opc) || isSAR(Opc) || isROL(Opc) || isROR(Opc) ||
5859 isRCL(Opc) || isRCR(Opc)) {
5860 unsigned RegIdx =
UseMI.findRegisterUseOperandIdx(Reg,
nullptr);
5863 if (!isInt<8>(ImmVal))
5870 UseMI.removeOperand(RegIdx);
5884 UseMI.registerDefIsDead(X86::EFLAGS,
nullptr)) {
5888 UseMI.setDesc(
get(TargetOpcode::COPY));
5889 UseMI.removeOperand(
5890 UseMI.findRegisterUseOperandIdx(Reg,
nullptr));
5891 UseMI.removeOperand(
5892 UseMI.findRegisterDefOperandIdx(X86::EFLAGS,
nullptr));
5893 UseMI.untieRegOperand(0);
5897 unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
5898 unsigned ImmOpNum = 2;
5899 if (!
UseMI.getOperand(0).isDef()) {
5903 if (Opc == TargetOpcode::COPY)
5907 commuteInstruction(
UseMI);
5911 UseMI.getOperand(ImmOpNum).ChangeToImmediate(ImmVal);
5915 if (
Reg.isVirtual() &&
MRI->use_nodbg_empty(Reg))
5929 return foldImmediateImpl(
UseMI, &
DefMI, Reg, ImmVal,
MRI,
true);
5941 assert(
Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.");
5961 assert(
Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.");
5979 MIB->
setDesc(
TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5991 assert(Imm != 0 &&
"Using push/pop for 0 is not efficient.");
5994 int StackAdjustment;
5996 if (Subtarget.is64Bit()) {
5998 MIB->
getOpcode() == X86::MOV32ImmSExti8);
6012 StackAdjustment = 8;
6018 StackAdjustment = 4;
6030 bool EmitCFI = !TFL->
hasFP(MF) && NeedsDwarfCFI;
6077 MIB->
getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
6089 const MCInstrDesc &BroadcastDesc,
unsigned SubIdx) {
6092 if (
TRI->getEncodingValue(DestReg) < 16) {
6099 DestReg =
TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
6111 const MCInstrDesc &ExtractDesc,
unsigned SubIdx) {
6114 if (
TRI->getEncodingValue(SrcReg) < 16) {
6121 SrcReg =
TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
6142 bool HasAVX = Subtarget.
hasAVX();
6144 switch (
MI.getOpcode()) {
6151 case X86::MOV32ImmSExti8:
6152 case X86::MOV64ImmSExti8:
6154 case X86::SETB_C32r:
6156 case X86::SETB_C64r:
6164 case X86::FsFLD0F128:
6166 case X86::AVX_SET0: {
6167 assert(HasAVX &&
"AVX not supported");
6170 Register XReg =
TRI->getSubReg(SrcReg, X86::sub_xmm);
6176 case X86::AVX512_128_SET0:
6177 case X86::AVX512_FsFLD0SH:
6178 case X86::AVX512_FsFLD0SS:
6179 case X86::AVX512_FsFLD0SD:
6180 case X86::AVX512_FsFLD0F128: {
6181 bool HasVLX = Subtarget.hasVLX();
6184 if (HasVLX ||
TRI->getEncodingValue(SrcReg) < 16)
6186 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
6189 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
6193 case X86::AVX512_256_SET0:
6194 case X86::AVX512_512_SET0: {
6195 bool HasVLX = Subtarget.hasVLX();
6198 if (HasVLX ||
TRI->getEncodingValue(SrcReg) < 16) {
6199 Register XReg =
TRI->getSubReg(SrcReg, X86::sub_xmm);
6205 if (
MI.getOpcode() == X86::AVX512_256_SET0) {
6208 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
6213 case X86::V_SETALLONES:
6215 get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6216 case X86::AVX2_SETALLONES:
6218 case X86::AVX1_SETALLONES: {
6225 case X86::AVX512_512_SETALLONES: {
6236 case X86::AVX512_512_SEXT_MASK_32:
6237 case X86::AVX512_512_SEXT_MASK_64: {
6241 unsigned Opc = (
MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64)
6242 ? X86::VPTERNLOGQZrrikz
6243 : X86::VPTERNLOGDZrrikz;
6244 MI.removeOperand(1);
6249 .
addReg(MaskReg, MaskState)
6255 case X86::VMOVAPSZ128rm_NOVLX:
6257 get(X86::VBROADCASTF32X4Zrm), X86::sub_xmm);
6258 case X86::VMOVUPSZ128rm_NOVLX:
6260 get(X86::VBROADCASTF32X4Zrm), X86::sub_xmm);
6261 case X86::VMOVAPSZ256rm_NOVLX:
6263 get(X86::VBROADCASTF64X4Zrm), X86::sub_ymm);
6264 case X86::VMOVUPSZ256rm_NOVLX:
6266 get(X86::VBROADCASTF64X4Zrm), X86::sub_ymm);
6267 case X86::VMOVAPSZ128mr_NOVLX:
6269 get(X86::VEXTRACTF32X4Zmri), X86::sub_xmm);
6270 case X86::VMOVUPSZ128mr_NOVLX:
6272 get(X86::VEXTRACTF32X4Zmri), X86::sub_xmm);
6273 case X86::VMOVAPSZ256mr_NOVLX:
6275 get(X86::VEXTRACTF64X4Zmri), X86::sub_ymm);
6276 case X86::VMOVUPSZ256mr_NOVLX:
6278 get(X86::VEXTRACTF64X4Zmri), X86::sub_ymm);
6279 case X86::MOV32ri64: {
6281 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
6282 MI.setDesc(
get(X86::MOV32ri));
6288 case X86::RDFLAGS32:
6289 case X86::RDFLAGS64: {
6290 unsigned Is64Bit =
MI.getOpcode() == X86::RDFLAGS64;
6294 get(Is64Bit ? X86::PUSHF64 : X86::PUSHF32))
6302 "Unexpected register in operand! Should be EFLAGS.");
6305 "Unexpected register in operand! Should be DF.");
6308 MIB->
setDesc(
get(Is64Bit ? X86::POP64r : X86::POP32r));
6312 case X86::WRFLAGS32:
6313 case X86::WRFLAGS64: {
6314 unsigned Is64Bit =
MI.getOpcode() == X86::WRFLAGS64;
6318 get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
6319 .
addReg(
MI.getOperand(0).getReg());
6321 get(Is64Bit ? X86::POPF64 : X86::POPF32));
6322 MI.eraseFromParent();
6345 case TargetOpcode::LOAD_STACK_GUARD:
6351 case X86::SHLDROT32ri:
6353 case X86::SHLDROT64ri:
6355 case X86::SHRDROT32ri:
6357 case X86::SHRDROT64ri:
6359 case X86::ADD8rr_DB:
6362 case X86::ADD16rr_DB:
6365 case X86::ADD32rr_DB:
6368 case X86::ADD64rr_DB:
6371 case X86::ADD8ri_DB:
6374 case X86::ADD16ri_DB:
6377 case X86::ADD32ri_DB:
6380 case X86::ADD64ri32_DB:
6404 bool ForLoadFold =
false) {
6406 case X86::CVTSI2SSrr:
6407 case X86::CVTSI2SSrm:
6408 case X86::CVTSI642SSrr:
6409 case X86::CVTSI642SSrm:
6410 case X86::CVTSI2SDrr:
6411 case X86::CVTSI2SDrm:
6412 case X86::CVTSI642SDrr:
6413 case X86::CVTSI642SDrm:
6416 return !ForLoadFold;
6417 case X86::CVTSD2SSrr:
6418 case X86::CVTSD2SSrm:
6419 case X86::CVTSS2SDrr:
6420 case X86::CVTSS2SDrm:
6427 case X86::RCPSSr_Int:
6428 case X86::RCPSSm_Int:
6429 case X86::ROUNDSDri:
6430 case X86::ROUNDSDmi:
6431 case X86::ROUNDSSri:
6432 case X86::ROUNDSSmi:
6435 case X86::RSQRTSSr_Int:
6436 case X86::RSQRTSSm_Int:
6439 case X86::SQRTSSr_Int:
6440 case X86::SQRTSSm_Int:
6443 case X86::SQRTSDr_Int:
6444 case X86::SQRTSDm_Int:
6446 case X86::VFCMULCPHZ128rm:
6447 case X86::VFCMULCPHZ128rmb:
6448 case X86::VFCMULCPHZ128rmbkz:
6449 case X86::VFCMULCPHZ128rmkz:
6450 case X86::VFCMULCPHZ128rr:
6451 case X86::VFCMULCPHZ128rrkz:
6452 case X86::VFCMULCPHZ256rm:
6453 case X86::VFCMULCPHZ256rmb:
6454 case X86::VFCMULCPHZ256rmbkz:
6455 case X86::VFCMULCPHZ256rmkz:
6456 case X86::VFCMULCPHZ256rr:
6457 case X86::VFCMULCPHZ256rrkz:
6458 case X86::VFCMULCPHZrm:
6459 case X86::VFCMULCPHZrmb:
6460 case X86::VFCMULCPHZrmbkz:
6461 case X86::VFCMULCPHZrmkz:
6462 case X86::VFCMULCPHZrr:
6463 case X86::VFCMULCPHZrrb:
6464 case X86::VFCMULCPHZrrbkz:
6465 case X86::VFCMULCPHZrrkz:
6466 case X86::VFMULCPHZ128rm:
6467 case X86::VFMULCPHZ128rmb:
6468 case X86::VFMULCPHZ128rmbkz:
6469 case X86::VFMULCPHZ128rmkz:
6470 case X86::VFMULCPHZ128rr:
6471 case X86::VFMULCPHZ128rrkz:
6472 case X86::VFMULCPHZ256rm:
6473 case X86::VFMULCPHZ256rmb:
6474 case X86::VFMULCPHZ256rmbkz:
6475 case X86::VFMULCPHZ256rmkz:
6476 case X86::VFMULCPHZ256rr:
6477 case X86::VFMULCPHZ256rrkz:
6478 case X86::VFMULCPHZrm:
6479 case X86::VFMULCPHZrmb:
6480 case X86::VFMULCPHZrmbkz:
6481 case X86::VFMULCPHZrmkz:
6482 case X86::VFMULCPHZrr:
6483 case X86::VFMULCPHZrrb:
6484 case X86::VFMULCPHZrrbkz:
6485 case X86::VFMULCPHZrrkz:
6486 case X86::VFCMULCSHZrm:
6487 case X86::VFCMULCSHZrmkz:
6488 case X86::VFCMULCSHZrr:
6489 case X86::VFCMULCSHZrrb:
6490 case X86::VFCMULCSHZrrbkz:
6491 case X86::VFCMULCSHZrrkz:
6492 case X86::VFMULCSHZrm:
6493 case X86::VFMULCSHZrmkz:
6494 case X86::VFMULCSHZrr:
6495 case X86::VFMULCSHZrrb:
6496 case X86::VFMULCSHZrrbkz:
6497 case X86::VFMULCSHZrrkz:
6498 return Subtarget.hasMULCFalseDeps();
6499 case X86::VPERMDYrm:
6500 case X86::VPERMDYrr:
6501 case X86::VPERMQYmi:
6502 case X86::VPERMQYri:
6503 case X86::VPERMPSYrm:
6504 case X86::VPERMPSYrr:
6505 case X86::VPERMPDYmi:
6506 case X86::VPERMPDYri:
6507 case X86::VPERMDZ256rm:
6508 case X86::VPERMDZ256rmb:
6509 case X86::VPERMDZ256rmbkz:
6510 case X86::VPERMDZ256rmkz:
6511 case X86::VPERMDZ256rr:
6512 case X86::VPERMDZ256rrkz:
6513 case X86::VPERMDZrm:
6514 case X86::VPERMDZrmb:
6515 case X86::VPERMDZrmbkz:
6516 case X86::VPERMDZrmkz:
6517 case X86::VPERMDZrr:
6518 case X86::VPERMDZrrkz:
6519 case X86::VPERMQZ256mbi:
6520 case X86::VPERMQZ256mbikz:
6521 case X86::VPERMQZ256mi:
6522 case X86::VPERMQZ256mikz:
6523 case X86::VPERMQZ256ri:
6524 case X86::VPERMQZ256rikz:
6525 case X86::VPERMQZ256rm:
6526 case X86::VPERMQZ256rmb:
6527 case X86::VPERMQZ256rmbkz:
6528 case X86::VPERMQZ256rmkz:
6529 case X86::VPERMQZ256rr:
6530 case X86::VPERMQZ256rrkz:
6531 case X86::VPERMQZmbi:
6532 case X86::VPERMQZmbikz:
6533 case X86::VPERMQZmi:
6534 case X86::VPERMQZmikz:
6535 case X86::VPERMQZri:
6536 case X86::VPERMQZrikz:
6537 case X86::VPERMQZrm:
6538 case X86::VPERMQZrmb:
6539 case X86::VPERMQZrmbkz:
6540 case X86::VPERMQZrmkz:
6541 case X86::VPERMQZrr:
6542 case X86::VPERMQZrrkz:
6543 case X86::VPERMPSZ256rm:
6544 case X86::VPERMPSZ256rmb:
6545 case X86::VPERMPSZ256rmbkz:
6546 case X86::VPERMPSZ256rmkz:
6547 case X86::VPERMPSZ256rr:
6548 case X86::VPERMPSZ256rrkz:
6549 case X86::VPERMPSZrm:
6550 case X86::VPERMPSZrmb:
6551 case X86::VPERMPSZrmbkz:
6552 case X86::VPERMPSZrmkz:
6553 case X86::VPERMPSZrr:
6554 case X86::VPERMPSZrrkz:
6555 case X86::VPERMPDZ256mbi:
6556 case X86::VPERMPDZ256mbikz:
6557 case X86::VPERMPDZ256mi:
6558 case X86::VPERMPDZ256mikz:
6559 case X86::VPERMPDZ256ri:
6560 case X86::VPERMPDZ256rikz:
6561 case X86::VPERMPDZ256rm:
6562 case X86::VPERMPDZ256rmb:
6563 case X86::VPERMPDZ256rmbkz:
6564 case X86::VPERMPDZ256rmkz:
6565 case X86::VPERMPDZ256rr:
6566 case X86::VPERMPDZ256rrkz:
6567 case X86::VPERMPDZmbi:
6568 case X86::VPERMPDZmbikz:
6569 case X86::VPERMPDZmi:
6570 case X86::VPERMPDZmikz:
6571 case X86::VPERMPDZri:
6572 case X86::VPERMPDZrikz:
6573 case X86::VPERMPDZrm:
6574 case X86::VPERMPDZrmb:
6575 case X86::VPERMPDZrmbkz:
6576 case X86::VPERMPDZrmkz:
6577 case X86::VPERMPDZrr:
6578 case X86::VPERMPDZrrkz:
6579 return Subtarget.hasPERMFalseDeps();
6580 case X86::VRANGEPDZ128rmbi:
6581 case X86::VRANGEPDZ128rmbikz:
6582 case X86::VRANGEPDZ128rmi:
6583 case X86::VRANGEPDZ128rmikz:
6584 case X86::VRANGEPDZ128rri:
6585 case X86::VRANGEPDZ128rrikz:
6586 case X86::VRANGEPDZ256rmbi:
6587 case X86::VRANGEPDZ256rmbikz:
6588 case X86::VRANGEPDZ256rmi:
6589 case X86::VRANGEPDZ256rmikz:
6590 case X86::VRANGEPDZ256rri:
6591 case X86::VRANGEPDZ256rrikz:
6592 case X86::VRANGEPDZrmbi:
6593 case X86::VRANGEPDZrmbikz:
6594 case X86::VRANGEPDZrmi:
6595 case X86::VRANGEPDZrmikz:
6596 case X86::VRANGEPDZrri:
6597 case X86::VRANGEPDZrrib:
6598 case X86::VRANGEPDZrribkz:
6599 case X86::VRANGEPDZrrikz:
6600 case X86::VRANGEPSZ128rmbi:
6601 case X86::VRANGEPSZ128rmbikz:
6602 case X86::VRANGEPSZ128rmi:
6603 case X86::VRANGEPSZ128rmikz:
6604 case X86::VRANGEPSZ128rri:
6605 case X86::VRANGEPSZ128rrikz:
6606 case X86::VRANGEPSZ256rmbi:
6607 case X86::VRANGEPSZ256rmbikz:
6608 case X86::VRANGEPSZ256rmi:
6609 case X86::VRANGEPSZ256rmikz:
6610 case X86::VRANGEPSZ256rri:
6611 case X86::VRANGEPSZ256rrikz:
6612 case X86::VRANGEPSZrmbi:
6613 case X86::VRANGEPSZrmbikz:
6614 case X86::VRANGEPSZrmi:
6615 case X86::VRANGEPSZrmikz:
6616 case X86::VRANGEPSZrri:
6617 case X86::VRANGEPSZrrib:
6618 case X86::VRANGEPSZrribkz:
6619 case X86::VRANGEPSZrrikz:
6620 case X86::VRANGESDZrmi:
6621 case X86::VRANGESDZrmikz:
6622 case X86::VRANGESDZrri:
6623 case X86::VRANGESDZrrib:
6624 case X86::VRANGESDZrribkz:
6625 case X86::VRANGESDZrrikz:
6626 case X86::VRANGESSZrmi:
6627 case X86::VRANGESSZrmikz:
6628 case X86::VRANGESSZrri:
6629 case X86::VRANGESSZrrib:
6630 case X86::VRANGESSZrribkz:
6631 case X86::VRANGESSZrrikz:
6632 return Subtarget.hasRANGEFalseDeps();
6633 case X86::VGETMANTSSZrmi:
6634 case X86::VGETMANTSSZrmikz:
6635 case X86::VGETMANTSSZrri:
6636 case X86::VGETMANTSSZrrib:
6637 case X86::VGETMANTSSZrribkz:
6638 case X86::VGETMANTSSZrrikz:
6639 case X86::VGETMANTSDZrmi:
6640 case X86::VGETMANTSDZrmikz:
6641 case X86::VGETMANTSDZrri:
6642 case X86::VGETMANTSDZrrib:
6643 case X86::VGETMANTSDZrribkz:
6644 case X86::VGETMANTSDZrrikz:
6645 case X86::VGETMANTSHZrmi:
6646 case X86::VGETMANTSHZrmikz:
6647 case X86::VGETMANTSHZrri:
6648 case X86::VGETMANTSHZrrib:
6649 case X86::VGETMANTSHZrribkz:
6650 case X86::VGETMANTSHZrrikz:
6651 case X86::VGETMANTPSZ128rmbi:
6652 case X86::VGETMANTPSZ128rmbikz:
6653 case X86::VGETMANTPSZ128rmi:
6654 case X86::VGETMANTPSZ128rmikz:
6655 case X86::VGETMANTPSZ256rmbi:
6656 case X86::VGETMANTPSZ256rmbikz:
6657 case X86::VGETMANTPSZ256rmi:
6658 case X86::VGETMANTPSZ256rmikz:
6659 case X86::VGETMANTPSZrmbi:
6660 case X86::VGETMANTPSZrmbikz:
6661 case X86::VGETMANTPSZrmi:
6662 case X86::VGETMANTPSZrmikz:
6663 case X86::VGETMANTPDZ128rmbi:
6664 case X86::VGETMANTPDZ128rmbikz:
6665 case X86::VGETMANTPDZ128rmi:
6666 case X86::VGETMANTPDZ128rmikz:
6667 case X86::VGETMANTPDZ256rmbi:
6668 case X86::VGETMANTPDZ256rmbikz:
6669 case X86::VGETMANTPDZ256rmi:
6670 case X86::VGETMANTPDZ256rmikz:
6671 case X86::VGETMANTPDZrmbi:
6672 case X86::VGETMANTPDZrmbikz:
6673 case X86::VGETMANTPDZrmi:
6674 case X86::VGETMANTPDZrmikz:
6675 return Subtarget.hasGETMANTFalseDeps();
6676 case X86::VPMULLQZ128rm:
6677 case X86::VPMULLQZ128rmb:
6678 case X86::VPMULLQZ128rmbkz:
6679 case X86::VPMULLQZ128rmkz:
6680 case X86::VPMULLQZ128rr:
6681 case X86::VPMULLQZ128rrkz:
6682 case X86::VPMULLQZ256rm:
6683 case X86::VPMULLQZ256rmb:
6684 case X86::VPMULLQZ256rmbkz:
6685 case X86::VPMULLQZ256rmkz:
6686 case X86::VPMULLQZ256rr:
6687 case X86::VPMULLQZ256rrkz:
6688 case X86::VPMULLQZrm:
6689 case X86::VPMULLQZrmb:
6690 case X86::VPMULLQZrmbkz:
6691 case X86::VPMULLQZrmkz:
6692 case X86::VPMULLQZrr:
6693 case X86::VPMULLQZrrkz:
6694 return Subtarget.hasMULLQFalseDeps();
6696 case X86::POPCNT32rm:
6697 case X86::POPCNT32rr:
6698 case X86::POPCNT64rm:
6699 case X86::POPCNT64rr:
6700 return Subtarget.hasPOPCNTFalseDeps();
6701 case X86::LZCNT32rm:
6702 case X86::LZCNT32rr:
6703 case X86::LZCNT64rm:
6704 case X86::LZCNT64rr:
6705 case X86::TZCNT32rm:
6706 case X86::TZCNT32rr:
6707 case X86::TZCNT64rm:
6708 case X86::TZCNT64rr:
6709 return Subtarget.hasLZCNTFalseDeps();
6726 if (Reg.isVirtual()) {
6727 if (MO.
readsReg() ||
MI.readsVirtualRegister(Reg))
6730 if (
MI.readsRegister(Reg,
TRI))
6745 bool ForLoadFold =
false) {
6748 case X86::MMX_PUNPCKHBWrr:
6749 case X86::MMX_PUNPCKHWDrr:
6750 case X86::MMX_PUNPCKHDQrr:
6751 case X86::MMX_PUNPCKLBWrr:
6752 case X86::MMX_PUNPCKLWDrr:
6753 case X86::MMX_PUNPCKLDQrr:
6754 case X86::MOVHLPSrr:
6755 case X86::PACKSSWBrr:
6756 case X86::PACKUSWBrr:
6757 case X86::PACKSSDWrr:
6758 case X86::PACKUSDWrr:
6759 case X86::PUNPCKHBWrr:
6760 case X86::PUNPCKLBWrr:
6761 case X86::PUNPCKHWDrr:
6762 case X86::PUNPCKLWDrr:
6763 case X86::PUNPCKHDQrr:
6764 case X86::PUNPCKLDQrr:
6765 case X86::PUNPCKHQDQrr:
6766 case X86::PUNPCKLQDQrr:
6767 case X86::SHUFPDrri:
6768 case X86::SHUFPSrri:
6774 return OpNum == 2 && !ForLoadFold;
6776 case X86::VMOVLHPSrr:
6777 case X86::VMOVLHPSZrr:
6778 case X86::VPACKSSWBrr:
6779 case X86::VPACKUSWBrr:
6780 case X86::VPACKSSDWrr:
6781 case X86::VPACKUSDWrr:
6782 case X86::VPACKSSWBZ128rr:
6783 case X86::VPACKUSWBZ128rr:
6784 case X86::VPACKSSDWZ128rr:
6785 case X86::VPACKUSDWZ128rr:
6786 case X86::VPERM2F128rri:
6787 case X86::VPERM2I128rri:
6788 case X86::VSHUFF32X4Z256rri:
6789 case X86::VSHUFF32X4Zrri:
6790 case X86::VSHUFF64X2Z256rri:
6791 case X86::VSHUFF64X2Zrri:
6792 case X86::VSHUFI32X4Z256rri:
6793 case X86::VSHUFI32X4Zrri:
6794 case X86::VSHUFI64X2Z256rri:
6795 case X86::VSHUFI64X2Zrri:
6796 case X86::VPUNPCKHBWrr:
6797 case X86::VPUNPCKLBWrr:
6798 case X86::VPUNPCKHBWYrr:
6799 case X86::VPUNPCKLBWYrr:
6800 case X86::VPUNPCKHBWZ128rr:
6801 case X86::VPUNPCKLBWZ128rr:
6802 case X86::VPUNPCKHBWZ256rr:
6803 case X86::VPUNPCKLBWZ256rr:
6804 case X86::VPUNPCKHBWZrr:
6805 case X86::VPUNPCKLBWZrr:
6806 case X86::VPUNPCKHWDrr:
6807 case X86::VPUNPCKLWDrr:
6808 case X86::VPUNPCKHWDYrr:
6809 case X86::VPUNPCKLWDYrr:
6810 case X86::VPUNPCKHWDZ128rr:
6811 case X86::VPUNPCKLWDZ128rr:
6812 case X86::VPUNPCKHWDZ256rr:
6813 case X86::VPUNPCKLWDZ256rr:
6814 case X86::VPUNPCKHWDZrr:
6815 case X86::VPUNPCKLWDZrr:
6816 case X86::VPUNPCKHDQrr:
6817 case X86::VPUNPCKLDQrr:
6818 case X86::VPUNPCKHDQYrr:
6819 case X86::VPUNPCKLDQYrr:
6820 case X86::VPUNPCKHDQZ128rr:
6821 case X86::VPUNPCKLDQZ128rr:
6822 case X86::VPUNPCKHDQZ256rr:
6823 case X86::VPUNPCKLDQZ256rr:
6824 case X86::VPUNPCKHDQZrr:
6825 case X86::VPUNPCKLDQZrr:
6826 case X86::VPUNPCKHQDQrr:
6827 case X86::VPUNPCKLQDQrr:
6828 case X86::VPUNPCKHQDQYrr:
6829 case X86::VPUNPCKLQDQYrr:
6830 case X86::VPUNPCKHQDQZ128rr:
6831 case X86::VPUNPCKLQDQZ128rr:
6832 case X86::VPUNPCKHQDQZ256rr:
6833 case X86::VPUNPCKLQDQZ256rr:
6834 case X86::VPUNPCKHQDQZrr:
6835 case X86::VPUNPCKLQDQZrr:
6839 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
6841 case X86::VCVTSI2SSrr:
6842 case X86::VCVTSI2SSrm:
6843 case X86::VCVTSI2SSrr_Int:
6844 case X86::VCVTSI2SSrm_Int:
6845 case X86::VCVTSI642SSrr:
6846 case X86::VCVTSI642SSrm:
6847 case X86::VCVTSI642SSrr_Int:
6848 case X86::VCVTSI642SSrm_Int:
6849 case X86::VCVTSI2SDrr:
6850 case X86::VCVTSI2SDrm:
6851 case X86::VCVTSI2SDrr_Int:
6852 case X86::VCVTSI2SDrm_Int:
6853 case X86::VCVTSI642SDrr:
6854 case X86::VCVTSI642SDrm:
6855 case X86::VCVTSI642SDrr_Int:
6856 case X86::VCVTSI642SDrm_Int:
6858 case X86::VCVTSI2SSZrr:
6859 case X86::VCVTSI2SSZrm:
6860 case X86::VCVTSI2SSZrr_Int:
6861 case X86::VCVTSI2SSZrrb_Int:
6862 case X86::VCVTSI2SSZrm_Int:
6863 case X86::VCVTSI642SSZrr:
6864 case X86::VCVTSI642SSZrm:
6865 case X86::VCVTSI642SSZrr_Int:
6866 case X86::VCVTSI642SSZrrb_Int:
6867 case X86::VCVTSI642SSZrm_Int:
6868 case X86::VCVTSI2SDZrr:
6869 case X86::VCVTSI2SDZrm:
6870 case X86::VCVTSI2SDZrr_Int:
6871 case X86::VCVTSI2SDZrm_Int:
6872 case X86::VCVTSI642SDZrr:
6873 case X86::VCVTSI642SDZrm:
6874 case X86::VCVTSI642SDZrr_Int:
6875 case X86::VCVTSI642SDZrrb_Int:
6876 case X86::VCVTSI642SDZrm_Int:
6877 case X86::VCVTUSI2SSZrr:
6878 case X86::VCVTUSI2SSZrm:
6879 case X86::VCVTUSI2SSZrr_Int:
6880 case X86::VCVTUSI2SSZrrb_Int:
6881 case X86::VCVTUSI2SSZrm_Int:
6882 case X86::VCVTUSI642SSZrr:
6883 case X86::VCVTUSI642SSZrm:
6884 case X86::VCVTUSI642SSZrr_Int:
6885 case X86::VCVTUSI642SSZrrb_Int:
6886 case X86::VCVTUSI642SSZrm_Int:
6887 case X86::VCVTUSI2SDZrr:
6888 case X86::VCVTUSI2SDZrm:
6889 case X86::VCVTUSI2SDZrr_Int:
6890 case X86::VCVTUSI2SDZrm_Int:
6891 case X86::VCVTUSI642SDZrr:
6892 case X86::VCVTUSI642SDZrm:
6893 case X86::VCVTUSI642SDZrr_Int:
6894 case X86::VCVTUSI642SDZrrb_Int:
6895 case X86::VCVTUSI642SDZrm_Int:
6896 case X86::VCVTSI2SHZrr:
6897 case X86::VCVTSI2SHZrm:
6898 case X86::VCVTSI2SHZrr_Int:
6899 case X86::VCVTSI2SHZrrb_Int:
6900 case X86::VCVTSI2SHZrm_Int:
6901 case X86::VCVTSI642SHZrr:
6902 case X86::VCVTSI642SHZrm:
6903 case X86::VCVTSI642SHZrr_Int:
6904 case X86::VCVTSI642SHZrrb_Int:
6905 case X86::VCVTSI642SHZrm_Int:
6906 case X86::VCVTUSI2SHZrr:
6907 case X86::VCVTUSI2SHZrm:
6908 case X86::VCVTUSI2SHZrr_Int:
6909 case X86::VCVTUSI2SHZrrb_Int:
6910 case X86::VCVTUSI2SHZrm_Int:
6911 case X86::VCVTUSI642SHZrr:
6912 case X86::VCVTUSI642SHZrm:
6913 case X86::VCVTUSI642SHZrr_Int:
6914 case X86::VCVTUSI642SHZrrb_Int:
6915 case X86::VCVTUSI642SHZrm_Int:
6918 return OpNum == 1 && !ForLoadFold;
6919 case X86::VCVTSD2SSrr:
6920 case X86::VCVTSD2SSrm:
6921 case X86::VCVTSD2SSrr_Int:
6922 case X86::VCVTSD2SSrm_Int:
6923 case X86::VCVTSS2SDrr:
6924 case X86::VCVTSS2SDrm:
6925 case X86::VCVTSS2SDrr_Int:
6926 case X86::VCVTSS2SDrm_Int:
6928 case X86::VRCPSSr_Int:
6930 case X86::VRCPSSm_Int:
6931 case X86::VROUNDSDri:
6932 case X86::VROUNDSDmi:
6933 case X86::VROUNDSDri_Int:
6934 case X86::VROUNDSDmi_Int:
6935 case X86::VROUNDSSri:
6936 case X86::VROUNDSSmi:
6937 case X86::VROUNDSSri_Int:
6938 case X86::VROUNDSSmi_Int:
6939 case X86::VRSQRTSSr:
6940 case X86::VRSQRTSSr_Int:
6941 case X86::VRSQRTSSm:
6942 case X86::VRSQRTSSm_Int:
6944 case X86::VSQRTSSr_Int:
6946 case X86::VSQRTSSm_Int:
6948 case X86::VSQRTSDr_Int:
6950 case X86::VSQRTSDm_Int:
6952 case X86::VCVTSD2SSZrr:
6953 case X86::VCVTSD2SSZrr_Int:
6954 case X86::VCVTSD2SSZrrb_Int:
6955 case X86::VCVTSD2SSZrm:
6956 case X86::VCVTSD2SSZrm_Int:
6957 case X86::VCVTSS2SDZrr:
6958 case X86::VCVTSS2SDZrr_Int:
6959 case X86::VCVTSS2SDZrrb_Int:
6960 case X86::VCVTSS2SDZrm:
6961 case X86::VCVTSS2SDZrm_Int:
6962 case X86::VGETEXPSDZr:
6963 case X86::VGETEXPSDZrb:
6964 case X86::VGETEXPSDZm:
6965 case X86::VGETEXPSSZr:
6966 case X86::VGETEXPSSZrb:
6967 case X86::VGETEXPSSZm:
6968 case X86::VGETMANTSDZrri:
6969 case X86::VGETMANTSDZrrib:
6970 case X86::VGETMANTSDZrmi:
6971 case X86::VGETMANTSSZrri:
6972 case X86::VGETMANTSSZrrib:
6973 case X86::VGETMANTSSZrmi:
6974 case X86::VRNDSCALESDZrri:
6975 case X86::VRNDSCALESDZrri_Int:
6976 case X86::VRNDSCALESDZrrib_Int:
6977 case X86::VRNDSCALESDZrmi:
6978 case X86::VRNDSCALESDZrmi_Int:
6979 case X86::VRNDSCALESSZrri:
6980 case X86::VRNDSCALESSZrri_Int:
6981 case X86::VRNDSCALESSZrrib_Int:
6982 case X86::VRNDSCALESSZrmi:
6983 case X86::VRNDSCALESSZrmi_Int:
6984 case X86::VRCP14SDZrr:
6985 case X86::VRCP14SDZrm:
6986 case X86::VRCP14SSZrr:
6987 case X86::VRCP14SSZrm:
6988 case X86::VRCPSHZrr:
6989 case X86::VRCPSHZrm:
6990 case X86::VRSQRTSHZrr:
6991 case X86::VRSQRTSHZrm:
6992 case X86::VREDUCESHZrmi:
6993 case X86::VREDUCESHZrri:
6994 case X86::VREDUCESHZrrib:
6995 case X86::VGETEXPSHZr:
6996 case X86::VGETEXPSHZrb:
6997 case X86::VGETEXPSHZm:
6998 case X86::VGETMANTSHZrri:
6999 case X86::VGETMANTSHZrrib:
7000 case X86::VGETMANTSHZrmi:
7001 case X86::VRNDSCALESHZrri:
7002 case X86::VRNDSCALESHZrri_Int:
7003 case X86::VRNDSCALESHZrrib_Int:
7004 case X86::VRNDSCALESHZrmi:
7005 case X86::VRNDSCALESHZrmi_Int:
7006 case X86::VSQRTSHZr:
7007 case X86::VSQRTSHZr_Int:
7008 case X86::VSQRTSHZrb_Int:
7009 case X86::VSQRTSHZm:
7010 case X86::VSQRTSHZm_Int:
7011 case X86::VRCP28SDZr:
7012 case X86::VRCP28SDZrb:
7013 case X86::VRCP28SDZm:
7014 case X86::VRCP28SSZr:
7015 case X86::VRCP28SSZrb:
7016 case X86::VRCP28SSZm:
7017 case X86::VREDUCESSZrmi:
7018 case X86::VREDUCESSZrri:
7019 case X86::VREDUCESSZrrib:
7020 case X86::VRSQRT14SDZrr:
7021 case X86::VRSQRT14SDZrm:
7022 case X86::VRSQRT14SSZrr:
7023 case X86::VRSQRT14SSZrm:
7024 case X86::VRSQRT28SDZr:
7025 case X86::VRSQRT28SDZrb:
7026 case X86::VRSQRT28SDZm:
7027 case X86::VRSQRT28SSZr:
7028 case X86::VRSQRT28SSZrb:
7029 case X86::VRSQRT28SSZm:
7030 case X86::VSQRTSSZr:
7031 case X86::VSQRTSSZr_Int:
7032 case X86::VSQRTSSZrb_Int:
7033 case X86::VSQRTSSZm:
7034 case X86::VSQRTSSZm_Int:
7035 case X86::VSQRTSDZr:
7036 case X86::VSQRTSDZr_Int:
7037 case X86::VSQRTSDZrb_Int:
7038 case X86::VSQRTSDZm:
7039 case X86::VSQRTSDZm_Int:
7040 case X86::VCVTSD2SHZrr:
7041 case X86::VCVTSD2SHZrr_Int:
7042 case X86::VCVTSD2SHZrrb_Int:
7043 case X86::VCVTSD2SHZrm:
7044 case X86::VCVTSD2SHZrm_Int:
7045 case X86::VCVTSS2SHZrr:
7046 case X86::VCVTSS2SHZrr_Int:
7047 case X86::VCVTSS2SHZrrb_Int:
7048 case X86::VCVTSS2SHZrm:
7049 case X86::VCVTSS2SHZrm_Int:
7050 case X86::VCVTSH2SDZrr:
7051 case X86::VCVTSH2SDZrr_Int:
7052 case X86::VCVTSH2SDZrrb_Int:
7053 case X86::VCVTSH2SDZrm:
7054 case X86::VCVTSH2SDZrm_Int:
7055 case X86::VCVTSH2SSZrr:
7056 case X86::VCVTSH2SSZrr_Int:
7057 case X86::VCVTSH2SSZrrb_Int:
7058 case X86::VCVTSH2SSZrm:
7059 case X86::VCVTSH2SSZrm_Int:
7061 case X86::VMOVSSZrrk:
7062 case X86::VMOVSDZrrk:
7063 return OpNum == 3 && !ForLoadFold;
7064 case X86::VMOVSSZrrkz:
7065 case X86::VMOVSDZrrkz:
7066 return OpNum == 2 && !ForLoadFold;
7098 Register Reg =
MI.getOperand(OpNum).getReg();
7100 if (
MI.killsRegister(Reg,
TRI))
7103 if (X86::VR128RegClass.
contains(Reg)) {
7106 unsigned Opc = Subtarget.
hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7110 MI.addRegisterKilled(Reg,
TRI,
true);
7111 }
else if (X86::VR256RegClass.
contains(Reg)) {
7114 Register XReg =
TRI->getSubReg(Reg, X86::sub_xmm);
7119 MI.addRegisterKilled(Reg,
TRI,
true);
7120 }
else if (X86::VR128XRegClass.
contains(Reg)) {
7122 if (!Subtarget.hasVLX())
7125 BuildMI(*
MI.getParent(),
MI,
MI.getDebugLoc(),
get(X86::VPXORDZ128rr), Reg)
7128 MI.addRegisterKilled(Reg,
TRI,
true);
7129 }
else if (X86::VR256XRegClass.
contains(Reg) ||
7130 X86::VR512RegClass.
contains(Reg)) {
7132 if (!Subtarget.hasVLX())
7136 Register XReg =
TRI->getSubReg(Reg, X86::sub_xmm);
7137 BuildMI(*
MI.getParent(),
MI,
MI.getDebugLoc(),
get(X86::VPXORDZ128rr), XReg)
7141 MI.addRegisterKilled(Reg,
TRI,
true);
7142 }
else if (X86::GR64RegClass.
contains(Reg)) {
7145 Register XReg =
TRI->getSubReg(Reg, X86::sub_32bit);
7150 MI.addRegisterKilled(Reg,
TRI,
true);
7151 }
else if (X86::GR32RegClass.
contains(Reg)) {
7155 MI.addRegisterKilled(Reg,
TRI,
true);
7160 int PtrOffset = 0) {
7161 unsigned NumAddrOps = MOs.
size();
7163 if (NumAddrOps < 4) {
7165 for (
unsigned i = 0; i != NumAddrOps; ++i)
7171 assert(MOs.
size() == 5 &&
"Unexpected memory operand list length");
7172 for (
unsigned i = 0; i != NumAddrOps; ++i) {
7174 if (i == 3 && PtrOffset != 0) {
7195 if (!Reg.isVirtual())
7198 auto *NewRC =
MRI.constrainRegClass(
7202 dbgs() <<
"WARNING: Unable to update register constraint for operand "
7203 <<
Idx <<
" of instruction:\n";
7222 unsigned NumOps =
MI.getDesc().getNumOperands() - 2;
7223 for (
unsigned i = 0; i != NumOps; ++i) {
7242 int PtrOffset = 0) {
7248 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
7251 assert(MO.
isReg() &&
"Expected to fold into reg operand!");
7275 MI.getDebugLoc(),
TII.get(Opcode));
7284 switch (
MI.getOpcode()) {
7285 case X86::INSERTPSrri:
7286 case X86::VINSERTPSrri:
7287 case X86::VINSERTPSZrri:
7291 unsigned Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
7292 unsigned ZMask =
Imm & 15;
7293 unsigned DstIdx = (
Imm >> 4) & 3;
7294 unsigned SrcIdx = (
Imm >> 6) & 3;
7298 unsigned RCSize =
TRI.getRegSizeInBits(*RC) / 8;
7299 if ((
Size == 0 ||
Size >= 16) && RCSize >= 16 &&
7300 (
MI.getOpcode() != X86::INSERTPSrri || Alignment >=
Align(4))) {
7301 int PtrOffset = SrcIdx * 4;
7302 unsigned NewImm = (DstIdx << 4) | ZMask;
7303 unsigned NewOpCode =
7304 (
MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
7305 : (
MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
7308 fuseInst(MF, NewOpCode, OpNum, MOs, InsertPt,
MI, *
this, PtrOffset);
7314 case X86::MOVHLPSrr:
7315 case X86::VMOVHLPSrr:
7316 case X86::VMOVHLPSZrr:
7323 unsigned RCSize =
TRI.getRegSizeInBits(*RC) / 8;
7324 if ((
Size == 0 ||
Size >= 16) && RCSize >= 16 && Alignment >=
Align(8)) {
7325 unsigned NewOpCode =
7326 (
MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm
7327 : (
MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm
7330 fuseInst(MF, NewOpCode, OpNum, MOs, InsertPt,
MI, *
this, 8);
7335 case X86::UNPCKLPDrr:
7342 unsigned RCSize =
TRI.getRegSizeInBits(*RC) / 8;
7343 if ((
Size == 0 ||
Size >= 16) && RCSize >= 16 && Alignment <
Align(16)) {
7345 fuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt,
MI, *
this);
7352 makeM0Inst(*
this, (
Size == 4) ? X86::MOV32mi : X86::MOV64mi32, MOs,
7364 !
MI.getOperand(1).isReg())
7372 if (
MI.getOperand(1).isUndef())
7381 unsigned Idx1)
const {
7382 unsigned Idx2 = CommuteAnyOperandIndex;
7386 bool HasDef =
MI.getDesc().getNumDefs();
7388 Register Reg1 =
MI.getOperand(Idx1).getReg();
7389 Register Reg2 =
MI.getOperand(Idx2).getReg();
7390 bool Tied1 = 0 ==
MI.getDesc().getOperandConstraint(Idx1,
MCOI::TIED_TO);
7391 bool Tied2 = 0 ==
MI.getDesc().getOperandConstraint(Idx2,
MCOI::TIED_TO);
7395 if ((HasDef && Reg0 == Reg1 && Tied1) || (HasDef && Reg0 == Reg2 && Tied2))
7398 return commuteInstruction(
MI,
false, Idx1, Idx2) ? Idx2 : Idx1;
7403 dbgs() <<
"We failed to fuse operand " <<
Idx <<
" in " <<
MI;
7409 unsigned Size,
Align Alignment,
bool AllowCommute)
const {
7410 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
7411 unsigned Opc =
MI.getOpcode();
7417 (Opc == X86::CALL32r || Opc == X86::CALL64r || Opc == X86::PUSH16r ||
7418 Opc == X86::PUSH32r || Opc == X86::PUSH64r))
7427 unsigned NumOps =
MI.getDesc().getNumOperands();
7428 bool IsTwoAddr = NumOps > 1 && OpNum < 2 &&
MI.getOperand(0).isReg() &&
7429 MI.getOperand(1).isReg() &&
7430 MI.getOperand(0).getReg() ==
MI.getOperand(1).getReg();
7434 if (Opc == X86::ADD32ri &&
7443 Opc != X86::ADD64rr)
7448 if (
MI.isCall() &&
MI.getCFIType())
7452 if (
auto *CustomMI = foldMemoryOperandCustom(MF,
MI, OpNum, MOs, InsertPt,
7468 unsigned Opcode =
I->DstOp;
7472 bool NarrowToMOV32rm =
false;
7476 unsigned RCSize =
TRI.getRegSizeInBits(*RC) / 8;
7484 if (Opcode != X86::MOV64rm || RCSize != 8 ||
Size != 4)
7486 if (
MI.getOperand(0).getSubReg() ||
MI.getOperand(1).getSubReg())
7488 Opcode = X86::MOV32rm;
7489 NarrowToMOV32rm =
true;
7499 :
fuseInst(MF, Opcode, OpNum, MOs, InsertPt,
MI, *
this);
7501 if (NarrowToMOV32rm) {
7517 unsigned CommuteOpIdx2 = commuteOperandsForFold(
MI, OpNum);
7518 if (CommuteOpIdx2 == OpNum) {
7528 commuteInstruction(
MI,
false, OpNum, CommuteOpIdx2);
7550 for (
auto Op : Ops) {
7555 if (
MI.getOpcode() == X86::MOV32r0 &&
SubReg == X86::sub_32bit)
7566 if (!RI.hasStackRealignment(MF))
7573 Size, Alignment,
true);
7575 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7576 unsigned NewOpc = 0;
7577 unsigned RCSize = 0;
7578 unsigned Opc =
MI.getOpcode();
7585 NewOpc = X86::CMP8ri;
7589 NewOpc = X86::CMP16ri;
7593 NewOpc = X86::CMP32ri;
7597 NewOpc = X86::CMP64ri32;
7606 MI.setDesc(
get(NewOpc));
7607 MI.getOperand(1).ChangeToImmediate(0);
7608 }
else if (Ops.
size() != 1)
7636 unsigned RegSize =
TRI.getRegSizeInBits(*RC);
7638 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
7639 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
7640 Opc == X86::VMOVSSZrm_alt) &&
7646 case X86::CVTSS2SDrr_Int:
7647 case X86::VCVTSS2SDrr_Int:
7648 case X86::VCVTSS2SDZrr_Int:
7649 case X86::VCVTSS2SDZrr_Intk:
7650 case X86::VCVTSS2SDZrr_Intkz:
7651 case X86::CVTSS2SIrr_Int:
7652 case X86::CVTSS2SI64rr_Int:
7653 case X86::VCVTSS2SIrr_Int:
7654 case X86::VCVTSS2SI64rr_Int:
7655 case X86::VCVTSS2SIZrr_Int:
7656 case X86::VCVTSS2SI64Zrr_Int:
7657 case X86::CVTTSS2SIrr_Int:
7658 case X86::CVTTSS2SI64rr_Int:
7659 case X86::VCVTTSS2SIrr_Int:
7660 case X86::VCVTTSS2SI64rr_Int:
7661 case X86::VCVTTSS2SIZrr_Int:
7662 case X86::VCVTTSS2SI64Zrr_Int:
7663 case X86::VCVTSS2USIZrr_Int:
7664 case X86::VCVTSS2USI64Zrr_Int:
7665 case X86::VCVTTSS2USIZrr_Int:
7666 case X86::VCVTTSS2USI64Zrr_Int:
7667 case X86::RCPSSr_Int:
7668 case X86::VRCPSSr_Int:
7669 case X86::RSQRTSSr_Int:
7670 case X86::VRSQRTSSr_Int:
7671 case X86::ROUNDSSri_Int:
7672 case X86::VROUNDSSri_Int:
7673 case X86::COMISSrr_Int:
7674 case X86::VCOMISSrr_Int:
7675 case X86::VCOMISSZrr_Int:
7676 case X86::UCOMISSrr_Int:
7677 case X86::VUCOMISSrr_Int:
7678 case X86::VUCOMISSZrr_Int:
7679 case X86::ADDSSrr_Int:
7680 case X86::VADDSSrr_Int:
7681 case X86::VADDSSZrr_Int:
7682 case X86::CMPSSrri_Int:
7683 case X86::VCMPSSrri_Int:
7684 case X86::VCMPSSZrri_Int:
7685 case X86::DIVSSrr_Int:
7686 case X86::VDIVSSrr_Int:
7687 case X86::VDIVSSZrr_Int:
7688 case X86::MAXSSrr_Int:
7689 case X86::VMAXSSrr_Int:
7690 case X86::VMAXSSZrr_Int:
7691 case X86::MINSSrr_Int:
7692 case X86::VMINSSrr_Int:
7693 case X86::VMINSSZrr_Int:
7694 case X86::MULSSrr_Int:
7695 case X86::VMULSSrr_Int:
7696 case X86::VMULSSZrr_Int:
7697 case X86::SQRTSSr_Int:
7698 case X86::VSQRTSSr_Int:
7699 case X86::VSQRTSSZr_Int:
7700 case X86::SUBSSrr_Int:
7701 case X86::VSUBSSrr_Int:
7702 case X86::VSUBSSZrr_Int:
7703 case X86::VADDSSZrr_Intk:
7704 case X86::VADDSSZrr_Intkz:
7705 case X86::VCMPSSZrri_Intk:
7706 case X86::VDIVSSZrr_Intk:
7707 case X86::VDIVSSZrr_Intkz:
7708 case X86::VMAXSSZrr_Intk:
7709 case X86::VMAXSSZrr_Intkz:
7710 case X86::VMINSSZrr_Intk:
7711 case X86::VMINSSZrr_Intkz:
7712 case X86::VMULSSZrr_Intk:
7713 case X86::VMULSSZrr_Intkz:
7714 case X86::VSQRTSSZr_Intk:
7715 case X86::VSQRTSSZr_Intkz:
7716 case X86::VSUBSSZrr_Intk:
7717 case X86::VSUBSSZrr_Intkz:
7718 case X86::VFMADDSS4rr_Int:
7719 case X86::VFNMADDSS4rr_Int:
7720 case X86::VFMSUBSS4rr_Int:
7721 case X86::VFNMSUBSS4rr_Int:
7722 case X86::VFMADD132SSr_Int:
7723 case X86::VFNMADD132SSr_Int:
7724 case X86::VFMADD213SSr_Int:
7725 case X86::VFNMADD213SSr_Int:
7726 case X86::VFMADD231SSr_Int:
7727 case X86::VFNMADD231SSr_Int:
7728 case X86::VFMSUB132SSr_Int:
7729 case X86::VFNMSUB132SSr_Int:
7730 case X86::VFMSUB213SSr_Int:
7731 case X86::VFNMSUB213SSr_Int:
7732 case X86::VFMSUB231SSr_Int:
7733 case X86::VFNMSUB231SSr_Int:
7734 case X86::VFMADD132SSZr_Int:
7735 case X86::VFNMADD132SSZr_Int:
7736 case X86::VFMADD213SSZr_Int:
7737 case X86::VFNMADD213SSZr_Int:
7738 case X86::VFMADD231SSZr_Int:
7739 case X86::VFNMADD231SSZr_Int:
7740 case X86::VFMSUB132SSZr_Int:
7741 case X86::VFNMSUB132SSZr_Int:
7742 case X86::VFMSUB213SSZr_Int:
7743 case X86::VFNMSUB213SSZr_Int:
7744 case X86::VFMSUB231SSZr_Int:
7745 case X86::VFNMSUB231SSZr_Int:
7746 case X86::VFMADD132SSZr_Intk:
7747 case X86::VFNMADD132SSZr_Intk:
7748 case X86::VFMADD213SSZr_Intk:
7749 case X86::VFNMADD213SSZr_Intk:
7750 case X86::VFMADD231SSZr_Intk:
7751 case X86::VFNMADD231SSZr_Intk:
7752 case X86::VFMSUB132SSZr_Intk:
7753 case X86::VFNMSUB132SSZr_Intk:
7754 case X86::VFMSUB213SSZr_Intk:
7755 case X86::VFNMSUB213SSZr_Intk:
7756 case X86::VFMSUB231SSZr_Intk:
7757 case X86::VFNMSUB231SSZr_Intk:
7758 case X86::VFMADD132SSZr_Intkz:
7759 case X86::VFNMADD132SSZr_Intkz:
7760 case X86::VFMADD213SSZr_Intkz:
7761 case X86::VFNMADD213SSZr_Intkz:
7762 case X86::VFMADD231SSZr_Intkz:
7763 case X86::VFNMADD231SSZr_Intkz:
7764 case X86::VFMSUB132SSZr_Intkz:
7765 case X86::VFNMSUB132SSZr_Intkz:
7766 case X86::VFMSUB213SSZr_Intkz:
7767 case X86::VFNMSUB213SSZr_Intkz:
7768 case X86::VFMSUB231SSZr_Intkz:
7769 case X86::VFNMSUB231SSZr_Intkz:
7770 case X86::VFIXUPIMMSSZrri:
7771 case X86::VFIXUPIMMSSZrrik:
7772 case X86::VFIXUPIMMSSZrrikz:
7773 case X86::VFPCLASSSSZri:
7774 case X86::VFPCLASSSSZrik:
7775 case X86::VGETEXPSSZr:
7776 case X86::VGETEXPSSZrk:
7777 case X86::VGETEXPSSZrkz:
7778 case X86::VGETMANTSSZrri:
7779 case X86::VGETMANTSSZrrik:
7780 case X86::VGETMANTSSZrrikz:
7781 case X86::VRANGESSZrri:
7782 case X86::VRANGESSZrrik:
7783 case X86::VRANGESSZrrikz:
7784 case X86::VRCP14SSZrr:
7785 case X86::VRCP14SSZrrk:
7786 case X86::VRCP14SSZrrkz:
7787 case X86::VRCP28SSZr:
7788 case X86::VRCP28SSZrk:
7789 case X86::VRCP28SSZrkz:
7790 case X86::VREDUCESSZrri:
7791 case X86::VREDUCESSZrrik:
7792 case X86::VREDUCESSZrrikz:
7793 case X86::VRNDSCALESSZrri_Int:
7794 case X86::VRNDSCALESSZrri_Intk:
7795 case X86::VRNDSCALESSZrri_Intkz:
7796 case X86::VRSQRT14SSZrr:
7797 case X86::VRSQRT14SSZrrk:
7798 case X86::VRSQRT14SSZrrkz:
7799 case X86::VRSQRT28SSZr:
7800 case X86::VRSQRT28SSZrk:
7801 case X86::VRSQRT28SSZrkz:
7802 case X86::VSCALEFSSZrr:
7803 case X86::VSCALEFSSZrrk:
7804 case X86::VSCALEFSSZrrkz:
7811 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
7812 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
7813 Opc == X86::VMOVSDZrm_alt) &&
7819 case X86::CVTSD2SSrr_Int:
7820 case X86::VCVTSD2SSrr_Int:
7821 case X86::VCVTSD2SSZrr_Int:
7822 case X86::VCVTSD2SSZrr_Intk:
7823 case X86::VCVTSD2SSZrr_Intkz:
7824 case X86::CVTSD2SIrr_Int:
7825 case X86::CVTSD2SI64rr_Int:
7826 case X86::VCVTSD2SIrr_Int:
7827 case X86::VCVTSD2SI64rr_Int:
7828 case X86::VCVTSD2SIZrr_Int:
7829 case X86::VCVTSD2SI64Zrr_Int:
7830 case X86::CVTTSD2SIrr_Int:
7831 case X86::CVTTSD2SI64rr_Int:
7832 case X86::VCVTTSD2SIrr_Int:
7833 case X86::VCVTTSD2SI64rr_Int:
7834 case X86::VCVTTSD2SIZrr_Int:
7835 case X86::VCVTTSD2SI64Zrr_Int:
7836 case X86::VCVTSD2USIZrr_Int:
7837 case X86::VCVTSD2USI64Zrr_Int:
7838 case X86::VCVTTSD2USIZrr_Int:
7839 case X86::VCVTTSD2USI64Zrr_Int:
7840 case X86::ROUNDSDri_Int:
7841 case X86::VROUNDSDri_Int:
7842 case X86::COMISDrr_Int:
7843 case X86::VCOMISDrr_Int:
7844 case X86::VCOMISDZrr_Int:
7845 case X86::UCOMISDrr_Int:
7846 case X86::VUCOMISDrr_Int:
7847 case X86::VUCOMISDZrr_Int:
7848 case X86::ADDSDrr_Int:
7849 case X86::VADDSDrr_Int:
7850 case X86::VADDSDZrr_Int:
7851 case X86::CMPSDrri_Int:
7852 case X86::VCMPSDrri_Int:
7853 case X86::VCMPSDZrri_Int:
7854 case X86::DIVSDrr_Int:
7855 case X86::VDIVSDrr_Int:
7856 case X86::VDIVSDZrr_Int:
7857 case X86::MAXSDrr_Int:
7858 case X86::VMAXSDrr_Int:
7859 case X86::VMAXSDZrr_Int:
7860 case X86::MINSDrr_Int:
7861 case X86::VMINSDrr_Int:
7862 case X86::VMINSDZrr_Int:
7863 case X86::MULSDrr_Int:
7864 case X86::VMULSDrr_Int:
7865 case X86::VMULSDZrr_Int:
7866 case X86::SQRTSDr_Int:
7867 case X86::VSQRTSDr_Int:
7868 case X86::VSQRTSDZr_Int:
7869 case X86::SUBSDrr_Int:
7870 case X86::VSUBSDrr_Int:
7871 case X86::VSUBSDZrr_Int:
7872 case X86::VADDSDZrr_Intk:
7873 case X86::VADDSDZrr_Intkz:
7874 case X86::VCMPSDZrri_Intk:
7875 case X86::VDIVSDZrr_Intk:
7876 case X86::VDIVSDZrr_Intkz:
7877 case X86::VMAXSDZrr_Intk:
7878 case X86::VMAXSDZrr_Intkz:
7879 case X86::VMINSDZrr_Intk:
7880 case X86::VMINSDZrr_Intkz:
7881 case X86::VMULSDZrr_Intk:
7882 case X86::VMULSDZrr_Intkz:
7883 case X86::VSQRTSDZr_Intk:
7884 case X86::VSQRTSDZr_Intkz:
7885 case X86::VSUBSDZrr_Intk:
7886 case X86::VSUBSDZrr_Intkz:
7887 case X86::VFMADDSD4rr_Int:
7888 case X86::VFNMADDSD4rr_Int:
7889 case X86::VFMSUBSD4rr_Int:
7890 case X86::VFNMSUBSD4rr_Int:
7891 case X86::VFMADD132SDr_Int:
7892 case X86::VFNMADD132SDr_Int:
7893 case X86::VFMADD213SDr_Int:
7894 case X86::VFNMADD213SDr_Int:
7895 case X86::VFMADD231SDr_Int:
7896 case X86::VFNMADD231SDr_Int:
7897 case X86::VFMSUB132SDr_Int:
7898 case X86::VFNMSUB132SDr_Int:
7899 case X86::VFMSUB213SDr_Int:
7900 case X86::VFNMSUB213SDr_Int:
7901 case X86::VFMSUB231SDr_Int:
7902 case X86::VFNMSUB231SDr_Int:
7903 case X86::VFMADD132SDZr_Int:
7904 case X86::VFNMADD132SDZr_Int:
7905 case X86::VFMADD213SDZr_Int:
7906 case X86::VFNMADD213SDZr_Int:
7907 case X86::VFMADD231SDZr_Int:
7908 case X86::VFNMADD231SDZr_Int:
7909 case X86::VFMSUB132SDZr_Int:
7910 case X86::VFNMSUB132SDZr_Int:
7911 case X86::VFMSUB213SDZr_Int:
7912 case X86::VFNMSUB213SDZr_Int:
7913 case X86::VFMSUB231SDZr_Int:
7914 case X86::VFNMSUB231SDZr_Int:
7915 case X86::VFMADD132SDZr_Intk:
7916 case X86::VFNMADD132SDZr_Intk:
7917 case X86::VFMADD213SDZr_Intk:
7918 case X86::VFNMADD213SDZr_Intk:
7919 case X86::VFMADD231SDZr_Intk:
7920 case X86::VFNMADD231SDZr_Intk:
7921 case X86::VFMSUB132SDZr_Intk:
7922 case X86::VFNMSUB132SDZr_Intk:
7923 case X86::VFMSUB213SDZr_Intk:
7924 case X86::VFNMSUB213SDZr_Intk:
7925 case X86::VFMSUB231SDZr_Intk:
7926 case X86::VFNMSUB231SDZr_Intk:
7927 case X86::VFMADD132SDZr_Intkz:
7928 case X86::VFNMADD132SDZr_Intkz:
7929 case X86::VFMADD213SDZr_Intkz:
7930 case X86::VFNMADD213SDZr_Intkz:
7931 case X86::VFMADD231SDZr_Intkz:
7932 case X86::VFNMADD231SDZr_Intkz:
7933 case X86::VFMSUB132SDZr_Intkz:
7934 case X86::VFNMSUB132SDZr_Intkz:
7935 case X86::VFMSUB213SDZr_Intkz:
7936 case X86::VFNMSUB213SDZr_Intkz:
7937 case X86::VFMSUB231SDZr_Intkz:
7938 case X86::VFNMSUB231SDZr_Intkz:
7939 case X86::VFIXUPIMMSDZrri:
7940 case X86::VFIXUPIMMSDZrrik:
7941 case X86::VFIXUPIMMSDZrrikz:
7942 case X86::VFPCLASSSDZri:
7943 case X86::VFPCLASSSDZrik:
7944 case X86::VGETEXPSDZr:
7945 case X86::VGETEXPSDZrk:
7946 case X86::VGETEXPSDZrkz:
7947 case X86::VGETMANTSDZrri:
7948 case X86::VGETMANTSDZrrik:
7949 case X86::VGETMANTSDZrrikz:
7950 case X86::VRANGESDZrri:
7951 case X86::VRANGESDZrrik:
7952 case X86::VRANGESDZrrikz:
7953 case X86::VRCP14SDZrr:
7954 case X86::VRCP14SDZrrk:
7955 case X86::VRCP14SDZrrkz:
7956 case X86::VRCP28SDZr:
7957 case X86::VRCP28SDZrk:
7958 case X86::VRCP28SDZrkz:
7959 case X86::VREDUCESDZrri:
7960 case X86::VREDUCESDZrrik:
7961 case X86::VREDUCESDZrrikz:
7962 case X86::VRNDSCALESDZrri_Int:
7963 case X86::VRNDSCALESDZrri_Intk:
7964 case X86::VRNDSCALESDZrri_Intkz:
7965 case X86::VRSQRT14SDZrr:
7966 case X86::VRSQRT14SDZrrk:
7967 case X86::VRSQRT14SDZrrkz:
7968 case X86::VRSQRT28SDZr:
7969 case X86::VRSQRT28SDZrk:
7970 case X86::VRSQRT28SDZrkz:
7971 case X86::VSCALEFSDZrr:
7972 case X86::VSCALEFSDZrrk:
7973 case X86::VSCALEFSDZrrkz:
7980 if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) &&
RegSize > 16) {
7985 case X86::VADDSHZrr_Int:
7986 case X86::VCMPSHZrri_Int:
7987 case X86::VDIVSHZrr_Int:
7988 case X86::VMAXSHZrr_Int:
7989 case X86::VMINSHZrr_Int:
7990 case X86::VMULSHZrr_Int:
7991 case X86::VSUBSHZrr_Int:
7992 case X86::VADDSHZrr_Intk:
7993 case X86::VADDSHZrr_Intkz:
7994 case X86::VCMPSHZrri_Intk:
7995 case X86::VDIVSHZrr_Intk:
7996 case X86::VDIVSHZrr_Intkz:
7997 case X86::VMAXSHZrr_Intk:
7998 case X86::VMAXSHZrr_Intkz:
7999 case X86::VMINSHZrr_Intk:
8000 case X86::VMINSHZrr_Intkz:
8001 case X86::VMULSHZrr_Intk:
8002 case X86::VMULSHZrr_Intkz:
8003 case X86::VSUBSHZrr_Intk:
8004 case X86::VSUBSHZrr_Intkz:
8005 case X86::VFMADD132SHZr_Int:
8006 case X86::VFNMADD132SHZr_Int:
8007 case X86::VFMADD213SHZr_Int:
8008 case X86::VFNMADD213SHZr_Int:
8009 case X86::VFMADD231SHZr_Int:
8010 case X86::VFNMADD231SHZr_Int:
8011 case X86::VFMSUB132SHZr_Int:
8012 case X86::VFNMSUB132SHZr_Int:
8013 case X86::VFMSUB213SHZr_Int:
8014 case X86::VFNMSUB213SHZr_Int:
8015 case X86::VFMSUB231SHZr_Int:
8016 case X86::VFNMSUB231SHZr_Int:
8017 case X86::VFMADD132SHZr_Intk:
8018 case X86::VFNMADD132SHZr_Intk:
8019 case X86::VFMADD213SHZr_Intk:
8020 case X86::VFNMADD213SHZr_Intk:
8021 case X86::VFMADD231SHZr_Intk:
8022 case X86::VFNMADD231SHZr_Intk:
8023 case X86::VFMSUB132SHZr_Intk:
8024 case X86::VFNMSUB132SHZr_Intk:
8025 case X86::VFMSUB213SHZr_Intk:
8026 case X86::VFNMSUB213SHZr_Intk:
8027 case X86::VFMSUB231SHZr_Intk:
8028 case X86::VFNMSUB231SHZr_Intk:
8029 case X86::VFMADD132SHZr_Intkz:
8030 case X86::VFNMADD132SHZr_Intkz:
8031 case X86::VFMADD213SHZr_Intkz:
8032 case X86::VFNMADD213SHZr_Intkz:
8033 case X86::VFMADD231SHZr_Intkz:
8034 case X86::VFNMADD231SHZr_Intkz:
8035 case X86::VFMSUB132SHZr_Intkz:
8036 case X86::VFNMSUB132SHZr_Intkz:
8037 case X86::VFMSUB213SHZr_Intkz:
8038 case X86::VFNMSUB213SHZr_Intkz:
8039 case X86::VFMSUB231SHZr_Intkz:
8040 case X86::VFNMSUB231SHZr_Intkz:
8057 for (
auto Op : Ops) {
8058 if (
MI.getOperand(
Op).getSubReg())
8088 case X86::AVX512_512_SET0:
8089 case X86::AVX512_512_SETALLONES:
8090 Alignment =
Align(64);
8092 case X86::AVX2_SETALLONES:
8093 case X86::AVX1_SETALLONES:
8095 case X86::AVX512_256_SET0:
8096 Alignment =
Align(32);
8099 case X86::V_SETALLONES:
8100 case X86::AVX512_128_SET0:
8101 case X86::FsFLD0F128:
8102 case X86::AVX512_FsFLD0F128:
8103 Alignment =
Align(16);
8107 case X86::AVX512_FsFLD0SD:
8108 Alignment =
Align(8);
8111 case X86::AVX512_FsFLD0SS:
8112 Alignment =
Align(4);
8115 case X86::AVX512_FsFLD0SH:
8116 Alignment =
Align(2);
8121 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8122 unsigned NewOpc = 0;
8123 switch (
MI.getOpcode()) {
8127 NewOpc = X86::CMP8ri;
8130 NewOpc = X86::CMP16ri;
8133 NewOpc = X86::CMP32ri;
8136 NewOpc = X86::CMP64ri32;
8140 MI.setDesc(
get(NewOpc));
8141 MI.getOperand(1).ChangeToImmediate(0);
8142 }
else if (Ops.
size() != 1)
8154 case X86::V_SETALLONES:
8155 case X86::AVX2_SETALLONES:
8156 case X86::AVX1_SETALLONES:
8158 case X86::AVX512_128_SET0:
8159 case X86::AVX512_256_SET0:
8160 case X86::AVX512_512_SET0:
8161 case X86::AVX512_512_SETALLONES:
8163 case X86::AVX512_FsFLD0SH:
8165 case X86::AVX512_FsFLD0SD:
8167 case X86::AVX512_FsFLD0SS:
8168 case X86::FsFLD0F128:
8169 case X86::AVX512_FsFLD0F128: {
8178 unsigned PICBase = 0;
8181 if (Subtarget.is64Bit()) {
8194 bool IsAllOnes =
false;
8197 case X86::AVX512_FsFLD0SS:
8201 case X86::AVX512_FsFLD0SD:
8204 case X86::FsFLD0F128:
8205 case X86::AVX512_FsFLD0F128:
8209 case X86::AVX512_FsFLD0SH:
8212 case X86::AVX512_512_SETALLONES:
8215 case X86::AVX512_512_SET0:
8219 case X86::AVX1_SETALLONES:
8220 case X86::AVX2_SETALLONES:
8223 case X86::AVX512_256_SET0:
8233 case X86::V_SETALLONES:
8237 case X86::AVX512_128_SET0:
8255 case X86::VPBROADCASTBZ128rm:
8256 case X86::VPBROADCASTBZ256rm:
8257 case X86::VPBROADCASTBZrm:
8258 case X86::VBROADCASTF32X2Z256rm:
8259 case X86::VBROADCASTF32X2Zrm:
8260 case X86::VBROADCASTI32X2Z128rm:
8261 case X86::VBROADCASTI32X2Z256rm:
8262 case X86::VBROADCASTI32X2Zrm:
8266#define FOLD_BROADCAST(SIZE) \
8267 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, \
8268 LoadMI.operands_begin() + NumOps); \
8269 return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, SIZE, \
8271 case X86::VPBROADCASTWZ128rm:
8272 case X86::VPBROADCASTWZ256rm:
8273 case X86::VPBROADCASTWZrm:
8275 case X86::VPBROADCASTDZ128rm:
8276 case X86::VPBROADCASTDZ256rm:
8277 case X86::VPBROADCASTDZrm:
8278 case X86::VBROADCASTSSZ128rm:
8279 case X86::VBROADCASTSSZ256rm:
8280 case X86::VBROADCASTSSZrm:
8282 case X86::VPBROADCASTQZ128rm:
8283 case X86::VPBROADCASTQZ256rm:
8284 case X86::VPBROADCASTQZrm:
8285 case X86::VBROADCASTSDZ256rm:
8286 case X86::VBROADCASTSDZrm:
8299 0, Alignment,
true);
8306 unsigned BitsSize,
bool AllowCommute)
const {
8310 ?
fuseInst(MF,
I->DstOp, OpNum, MOs, InsertPt,
MI, *
this)
8316 unsigned CommuteOpIdx2 = commuteOperandsForFold(
MI, OpNum);
8317 if (CommuteOpIdx2 == OpNum) {
8322 foldMemoryBroadcast(MF,
MI, CommuteOpIdx2, MOs, InsertPt, BitsSize,
8327 commuteInstruction(
MI,
false, OpNum, CommuteOpIdx2);
8342 if (!MMO->isStore()) {
8360 if (!MMO->isStore())
8363 if (!MMO->isLoad()) {
8381 assert((SpillSize == 64 || STI.hasVLX()) &&
8382 "Can't broadcast less than 64 bytes without AVX512VL!");
8384#define CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64) \
8386 switch (SpillSize) { \
8388 llvm_unreachable("Unknown spill size"); \
8422 unsigned Opc =
I->DstOp;
8426 if (UnfoldLoad && !FoldedLoad)
8428 UnfoldLoad &= FoldedLoad;
8429 if (UnfoldStore && !FoldedStore)
8431 UnfoldStore &= FoldedStore;
8438 if (!
MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8439 Subtarget.isUnalignedMem16Slow())
8448 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
8452 else if (
Op.isReg() &&
Op.isImplicit())
8468 unsigned Alignment = std::max<uint32_t>(
TRI.getSpillSize(*RC), 16);
8469 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8513 case X86::CMP64ri32:
8524 case X86::CMP64ri32:
8525 NewOpc = X86::TEST64rr;
8528 NewOpc = X86::TEST32rr;
8531 NewOpc = X86::TEST16rr;
8534 NewOpc = X86::TEST8rr;
8548 unsigned Alignment = std::max<uint32_t>(
TRI.getSpillSize(*DstRC), 16);
8549 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8565 if (!
N->isMachineOpcode())
8571 unsigned Opc =
I->DstOp;
8579 unsigned NumDefs = MCID.
NumDefs;
8580 std::vector<SDValue> AddrOps;
8581 std::vector<SDValue> BeforeOps;
8582 std::vector<SDValue> AfterOps;
8584 unsigned NumOps =
N->getNumOperands();
8585 for (
unsigned i = 0; i != NumOps - 1; ++i) {
8588 AddrOps.push_back(
Op);
8589 else if (i < Index - NumDefs)
8590 BeforeOps.push_back(
Op);
8591 else if (i > Index - NumDefs)
8592 AfterOps.push_back(
Op);
8594 SDValue Chain =
N->getOperand(NumOps - 1);
8595 AddrOps.push_back(Chain);
8600 EVT VT = *
TRI.legalclasstypes_begin(*RC);
8602 if (MMOs.empty() && RC == &X86::VR128RegClass &&
8603 Subtarget.isUnalignedMem16Slow())
8613 unsigned Alignment = std::max<uint32_t>(
TRI.getSpillSize(*RC), 16);
8614 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8626 std::vector<EVT> VTs;
8630 VTs.push_back(*
TRI.legalclasstypes_begin(*DstRC));
8632 for (
unsigned i = 0, e =
N->getNumValues(); i != e; ++i) {
8633 EVT VT =
N->getValueType(i);
8634 if (VT != MVT::Other && i >= (
unsigned)MCID.
getNumDefs())
8638 BeforeOps.push_back(
SDValue(Load, 0));
8644 case X86::CMP64ri32:
8652 case X86::CMP64ri32:
8653 Opc = X86::TEST64rr;
8656 Opc = X86::TEST32rr;
8659 Opc = X86::TEST16rr;
8665 BeforeOps[1] = BeforeOps[0];
8674 AddrOps.push_back(
SDValue(NewNode, 0));
8675 AddrOps.push_back(Chain);
8677 if (MMOs.empty() && RC == &X86::VR128RegClass &&
8678 Subtarget.isUnalignedMem16Slow())
8683 unsigned Alignment = std::max<uint32_t>(
TRI.getSpillSize(*RC), 16);
8684 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
8687 dl, MVT::Other, AddrOps);
8700 unsigned *LoadRegIndex)
const {
8706 if (UnfoldLoad && !FoldedLoad)
8708 if (UnfoldStore && !FoldedStore)
8717 int64_t &Offset2)
const {
8721 auto IsLoadOpcode = [&](
unsigned Opcode) {
8733 case X86::MOVSSrm_alt:
8735 case X86::MOVSDrm_alt:
8736 case X86::MMX_MOVD64rm:
8737 case X86::MMX_MOVQ64rm:
8746 case X86::VMOVSSrm_alt:
8748 case X86::VMOVSDrm_alt:
8749 case X86::VMOVAPSrm:
8750 case X86::VMOVUPSrm:
8751 case X86::VMOVAPDrm:
8752 case X86::VMOVUPDrm:
8753 case X86::VMOVDQArm:
8754 case X86::VMOVDQUrm:
8755 case X86::VMOVAPSYrm:
8756 case X86::VMOVUPSYrm:
8757 case X86::VMOVAPDYrm:
8758 case X86::VMOVUPDYrm:
8759 case X86::VMOVDQAYrm:
8760 case X86::VMOVDQUYrm:
8762 case X86::VMOVSSZrm:
8763 case X86::VMOVSSZrm_alt:
8764 case X86::VMOVSDZrm:
8765 case X86::VMOVSDZrm_alt:
8766 case X86::VMOVAPSZ128rm:
8767 case X86::VMOVUPSZ128rm:
8768 case X86::VMOVAPSZ128rm_NOVLX:
8769 case X86::VMOVUPSZ128rm_NOVLX:
8770 case X86::VMOVAPDZ128rm:
8771 case X86::VMOVUPDZ128rm:
8772 case X86::VMOVDQU8Z128rm:
8773 case X86::VMOVDQU16Z128rm:
8774 case X86::VMOVDQA32Z128rm:
8775 case X86::VMOVDQU32Z128rm:
8776 case X86::VMOVDQA64Z128rm:
8777 case X86::VMOVDQU64Z128rm:
8778 case X86::VMOVAPSZ256rm:
8779 case X86::VMOVUPSZ256rm:
8780 case X86::VMOVAPSZ256rm_NOVLX:
8781 case X86::VMOVUPSZ256rm_NOVLX:
8782 case X86::VMOVAPDZ256rm:
8783 case X86::VMOVUPDZ256rm:
8784 case X86::VMOVDQU8Z256rm:
8785 case X86::VMOVDQU16Z256rm:
8786 case X86::VMOVDQA32Z256rm:
8787 case X86::VMOVDQU32Z256rm:
8788 case X86::VMOVDQA64Z256rm:
8789 case X86::VMOVDQU64Z256rm:
8790 case X86::VMOVAPSZrm:
8791 case X86::VMOVUPSZrm:
8792 case X86::VMOVAPDZrm:
8793 case X86::VMOVUPDZrm:
8794 case X86::VMOVDQU8Zrm:
8795 case X86::VMOVDQU16Zrm:
8796 case X86::VMOVDQA32Zrm:
8797 case X86::VMOVDQU32Zrm:
8798 case X86::VMOVDQA64Zrm:
8799 case X86::VMOVDQU64Zrm:
8801 case X86::KMOVBkm_EVEX:
8803 case X86::KMOVWkm_EVEX:
8805 case X86::KMOVDkm_EVEX:
8807 case X86::KMOVQkm_EVEX:
8817 auto HasSameOp = [&](
int I) {
8833 if (!Disp1 || !Disp2)
8836 Offset1 = Disp1->getSExtValue();
8837 Offset2 = Disp2->getSExtValue();
8842 int64_t Offset1, int64_t Offset2,
8843 unsigned NumLoads)
const {
8844 assert(Offset2 > Offset1);
8845 if ((Offset2 - Offset1) / 8 > 64)
8859 case X86::MMX_MOVD64rm:
8860 case X86::MMX_MOVQ64rm:
8869 if (Subtarget.is64Bit()) {
8872 }
else if (NumLoads) {
8895 unsigned Opcode =
MI.getOpcode();
8896 if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
8897 Opcode == X86::PLDTILECFGV)
8910 assert(
Cond.size() == 1 &&
"Invalid X86 branch condition!");
8920 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
8921 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
8922 RC == &X86::RFP80RegClass);
8934 if (GlobalBaseReg != 0)
8935 return GlobalBaseReg;
8941 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
8943 return GlobalBaseReg;
8951 for (
const uint16_t(&Row)[3] : Table)
8952 if (Row[domain - 1] == opcode)
8960 for (
const uint16_t(&Row)[4] : Table)
8961 if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode))
8968 unsigned NewWidth,
unsigned *pNewMask =
nullptr) {
8969 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
8970 "Illegal blend mask scale");
8971 unsigned NewMask = 0;
8973 if ((OldWidth % NewWidth) == 0) {
8974 unsigned Scale = OldWidth / NewWidth;
8975 unsigned SubMask = (1u << Scale) - 1;
8976 for (
unsigned i = 0; i != NewWidth; ++i) {
8977 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
8979 NewMask |= (1u << i);
8980 else if (Sub != 0x0)
8984 unsigned Scale = NewWidth / OldWidth;
8985 unsigned SubMask = (1u << Scale) - 1;
8986 for (
unsigned i = 0; i != OldWidth; ++i) {
8987 if (OldMask & (1 << i)) {
8988 NewMask |= (SubMask << (i * Scale));
8994 *pNewMask = NewMask;
8999 unsigned Opcode =
MI.getOpcode();
9000 unsigned NumOperands =
MI.getDesc().getNumOperands();
9002 auto GetBlendDomains = [&](
unsigned ImmWidth,
bool Is256) {
9004 if (
MI.getOperand(NumOperands - 1).isImm()) {
9005 unsigned Imm =
MI.getOperand(NumOperands - 1).getImm();
9007 validDomains |= 0x2;
9009 validDomains |= 0x4;
9010 if (!Is256 || Subtarget.
hasAVX2())
9011 validDomains |= 0x8;
9013 return validDomains;
9017 case X86::BLENDPDrmi:
9018 case X86::BLENDPDrri:
9019 case X86::VBLENDPDrmi:
9020 case X86::VBLENDPDrri:
9021 return GetBlendDomains(2,
false);
9022 case X86::VBLENDPDYrmi:
9023 case X86::VBLENDPDYrri:
9024 return GetBlendDomains(4,
true);
9025 case X86::BLENDPSrmi:
9026 case X86::BLENDPSrri:
9027 case X86::VBLENDPSrmi:
9028 case X86::VBLENDPSrri:
9029 case X86::VPBLENDDrmi:
9030 case X86::VPBLENDDrri:
9031 return GetBlendDomains(4,
false);
9032 case X86::VBLENDPSYrmi:
9033 case X86::VBLENDPSYrri:
9034 case X86::VPBLENDDYrmi:
9035 case X86::VPBLENDDYrri:
9036 return GetBlendDomains(8,
true);
9037 case X86::PBLENDWrmi:
9038 case X86::PBLENDWrri:
9039 case X86::VPBLENDWrmi:
9040 case X86::VPBLENDWrri:
9042 case X86::VPBLENDWYrmi:
9043 case X86::VPBLENDWYrri:
9044 return GetBlendDomains(8,
false);
9045 case X86::VPANDDZ128rr:
9046 case X86::VPANDDZ128rm:
9047 case X86::VPANDDZ256rr:
9048 case X86::VPANDDZ256rm:
9049 case X86::VPANDQZ128rr:
9050 case X86::VPANDQZ128rm:
9051 case X86::VPANDQZ256rr:
9052 case X86::VPANDQZ256rm:
9053 case X86::VPANDNDZ128rr:
9054 case X86::VPANDNDZ128rm:
9055 case X86::VPANDNDZ256rr:
9056 case X86::VPANDNDZ256rm:
9057 case X86::VPANDNQZ128rr:
9058 case X86::VPANDNQZ128rm:
9059 case X86::VPANDNQZ256rr:
9060 case X86::VPANDNQZ256rm:
9061 case X86::VPORDZ128rr:
9062 case X86::VPORDZ128rm:
9063 case X86::VPORDZ256rr:
9064 case X86::VPORDZ256rm:
9065 case X86::VPORQZ128rr:
9066 case X86::VPORQZ128rm:
9067 case X86::VPORQZ256rr:
9068 case X86::VPORQZ256rm:
9069 case X86::VPXORDZ128rr:
9070 case X86::VPXORDZ128rm:
9071 case X86::VPXORDZ256rr:
9072 case X86::VPXORDZ256rm:
9073 case X86::VPXORQZ128rr:
9074 case X86::VPXORQZ128rm:
9075 case X86::VPXORQZ256rr:
9076 case X86::VPXORQZ256rm:
9079 if (Subtarget.hasDQI())
9082 if (RI.getEncodingValue(
MI.getOperand(0).getReg()) >= 16)
9084 if (RI.getEncodingValue(
MI.getOperand(1).getReg()) >= 16)
9087 if (NumOperands == 3 &&
9088 RI.getEncodingValue(
MI.getOperand(2).getReg()) >= 16)
9093 case X86::MOVHLPSrr:
9100 if (
MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg() &&
9101 MI.getOperand(0).getSubReg() == 0 &&
9102 MI.getOperand(1).getSubReg() == 0 &&
MI.getOperand(2).getSubReg() == 0)
9105 case X86::SHUFPDrri:
9111#include "X86ReplaceableInstrs.def"
9117 assert(dom &&
"Not an SSE instruction");
9119 unsigned Opcode =
MI.getOpcode();
9120 unsigned NumOperands =
MI.getDesc().getNumOperands();
9122 auto SetBlendDomain = [&](
unsigned ImmWidth,
bool Is256) {
9123 if (
MI.getOperand(NumOperands - 1).isImm()) {
9124 unsigned Imm =
MI.getOperand(NumOperands - 1).getImm() & 255;
9125 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
9126 unsigned NewImm = Imm;
9128 const uint16_t *table =
lookup(Opcode, dom, ReplaceableBlendInstrs);
9130 table =
lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
9134 }
else if (
Domain == 2) {
9136 }
else if (
Domain == 3) {
9139 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
9140 table =
lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
9144 assert(!Is256 &&
"128-bit vector expected");
9149 assert(table && table[
Domain - 1] &&
"Unknown domain op");
9151 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
9157 case X86::BLENDPDrmi:
9158 case X86::BLENDPDrri:
9159 case X86::VBLENDPDrmi:
9160 case X86::VBLENDPDrri:
9161 return SetBlendDomain(2,
false);
9162 case X86::VBLENDPDYrmi:
9163 case X86::VBLENDPDYrri:
9164 return SetBlendDomain(4,
true);
9165 case X86::BLENDPSrmi:
9166 case X86::BLENDPSrri:
9167 case X86::VBLENDPSrmi:
9168 case X86::VBLENDPSrri:
9169 case X86::VPBLENDDrmi:
9170 case X86::VPBLENDDrri:
9171 return SetBlendDomain(4,
false);
9172 case X86::VBLENDPSYrmi:
9173 case X86::VBLENDPSYrri:
9174 case X86::VPBLENDDYrmi:
9175 case X86::VPBLENDDYrri:
9176 return SetBlendDomain(8,
true);
9177 case X86::PBLENDWrmi:
9178 case X86::PBLENDWrri:
9179 case X86::VPBLENDWrmi:
9180 case X86::VPBLENDWrri:
9181 return SetBlendDomain(8,
false);
9182 case X86::VPBLENDWYrmi:
9183 case X86::VPBLENDWYrri:
9184 return SetBlendDomain(16,
true);
9185 case X86::VPANDDZ128rr:
9186 case X86::VPANDDZ128rm:
9187 case X86::VPANDDZ256rr:
9188 case X86::VPANDDZ256rm:
9189 case X86::VPANDQZ128rr:
9190 case X86::VPANDQZ128rm:
9191 case X86::VPANDQZ256rr:
9192 case X86::VPANDQZ256rm:
9193 case X86::VPANDNDZ128rr:
9194 case X86::VPANDNDZ128rm:
9195 case X86::VPANDNDZ256rr:
9196 case X86::VPANDNDZ256rm:
9197 case X86::VPANDNQZ128rr:
9198 case X86::VPANDNQZ128rm:
9199 case X86::VPANDNQZ256rr:
9200 case X86::VPANDNQZ256rm:
9201 case X86::VPORDZ128rr:
9202 case X86::VPORDZ128rm:
9203 case X86::VPORDZ256rr:
9204 case X86::VPORDZ256rm:
9205 case X86::VPORQZ128rr:
9206 case X86::VPORQZ128rm:
9207 case X86::VPORQZ256rr:
9208 case X86::VPORQZ256rm:
9209 case X86::VPXORDZ128rr:
9210 case X86::VPXORDZ128rm:
9211 case X86::VPXORDZ256rr:
9212 case X86::VPXORDZ256rm:
9213 case X86::VPXORQZ128rr:
9214 case X86::VPXORQZ128rm:
9215 case X86::VPXORQZ256rr:
9216 case X86::VPXORQZ256rm: {
9218 if (Subtarget.hasDQI())
9222 lookupAVX512(
MI.getOpcode(), dom, ReplaceableCustomAVX512LogicInstrs);
9223 assert(table &&
"Instruction not found in table?");
9226 if (
Domain == 3 && (dom == 1 || table[3] ==
MI.getOpcode()))
9231 case X86::UNPCKHPDrr:
9232 case X86::MOVHLPSrr:
9235 MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg() &&
9236 MI.getOperand(0).getSubReg() == 0 &&
9237 MI.getOperand(1).getSubReg() == 0 &&
9238 MI.getOperand(2).getSubReg() == 0) {
9239 commuteInstruction(
MI,
false);
9243 if (Opcode == X86::MOVHLPSrr)
9246 case X86::SHUFPDrri: {
9248 unsigned Imm =
MI.getOperand(3).getImm();
9249 unsigned NewImm = 0x44;
9254 MI.getOperand(3).setImm(NewImm);
9255 MI.setDesc(
get(X86::SHUFPSrri));
9263std::pair<uint16_t, uint16_t>
9266 unsigned opcode =
MI.getOpcode();
9272 return std::make_pair(domain, validDomains);
9274 if (
lookup(opcode, domain, ReplaceableInstrs)) {
9276 }
else if (
lookup(opcode, domain, ReplaceableInstrsAVX2)) {
9277 validDomains = Subtarget.
hasAVX2() ? 0xe : 0x6;
9278 }
else if (
lookup(opcode, domain, ReplaceableInstrsFP)) {
9280 }
else if (
lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
9284 return std::make_pair(0, 0);
9286 }
else if (
lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
9288 }
else if (Subtarget.hasDQI() &&
9289 lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
9291 }
else if (Subtarget.hasDQI()) {
9293 lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQMasked)) {
9294 if (domain == 1 || (domain == 3 && table[3] == opcode))
9301 return std::make_pair(domain, validDomains);
9307 assert(dom &&
"Not an SSE instruction");
9316 "256-bit vector operations only available in AVX2");
9317 table =
lookup(
MI.getOpcode(), dom, ReplaceableInstrsAVX2);
9320 table =
lookup(
MI.getOpcode(), dom, ReplaceableInstrsFP);
9322 "Can only select PackedSingle or PackedDouble");
9326 "256-bit insert/extract only available in AVX2");
9327 table =
lookup(
MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
9331 table =
lookupAVX512(
MI.getOpcode(), dom, ReplaceableInstrsAVX512);
9333 if (table &&
Domain == 3 && table[3] ==
MI.getOpcode())
9337 assert((Subtarget.hasDQI() ||
Domain >= 3) &&
"Requires AVX-512DQ");
9338 table =
lookupAVX512(
MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
9341 if (table &&
Domain == 3 && (dom == 1 || table[3] ==
MI.getOpcode()))
9345 assert((Subtarget.hasDQI() ||
Domain >= 3) &&
"Requires AVX-512DQ");
9346 table =
lookupAVX512(
MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
9347 if (table &&
Domain == 3 && (dom == 1 || table[3] ==
MI.getOpcode()))
9350 assert(table &&
"Cannot change domain");
9376 case X86::DIVSDrm_Int:
9378 case X86::DIVSDrr_Int:
9380 case X86::DIVSSrm_Int:
9382 case X86::DIVSSrr_Int:
9388 case X86::SQRTSDm_Int:
9390 case X86::SQRTSDr_Int:
9392 case X86::SQRTSSm_Int:
9394 case X86::SQRTSSr_Int:
9398 case X86::VDIVPDYrm:
9399 case X86::VDIVPDYrr:
9402 case X86::VDIVPSYrm:
9403 case X86::VDIVPSYrr:
9405 case X86::VDIVSDrm_Int:
9407 case X86::VDIVSDrr_Int:
9409 case X86::VDIVSSrm_Int:
9411 case X86::VDIVSSrr_Int:
9414 case X86::VSQRTPDYm:
9415 case X86::VSQRTPDYr:
9418 case X86::VSQRTPSYm:
9419 case X86::VSQRTPSYr:
9421 case X86::VSQRTSDm_Int:
9423 case X86::VSQRTSDr_Int:
9425 case X86::VSQRTSSm_Int:
9427 case X86::VSQRTSSr_Int:
9429 case X86::VDIVPDZ128rm:
9430 case X86::VDIVPDZ128rmb:
9431 case X86::VDIVPDZ128rmbk:
9432 case X86::VDIVPDZ128rmbkz:
9433 case X86::VDIVPDZ128rmk:
9434 case X86::VDIVPDZ128rmkz:
9435 case X86::VDIVPDZ128rr:
9436 case X86::VDIVPDZ128rrk:
9437 case X86::VDIVPDZ128rrkz:
9438 case X86::VDIVPDZ256rm:
9439 case X86::VDIVPDZ256rmb:
9440 case X86::VDIVPDZ256rmbk:
9441 case X86::VDIVPDZ256rmbkz:
9442 case X86::VDIVPDZ256rmk:
9443 case X86::VDIVPDZ256rmkz:
9444 case X86::VDIVPDZ256rr:
9445 case X86::VDIVPDZ256rrk:
9446 case X86::VDIVPDZ256rrkz:
9447 case X86::VDIVPDZrrb:
9448 case X86::VDIVPDZrrbk:
9449 case X86::VDIVPDZrrbkz:
9450 case X86::VDIVPDZrm:
9451 case X86::VDIVPDZrmb:
9452 case X86::VDIVPDZrmbk:
9453 case X86::VDIVPDZrmbkz:
9454 case X86::VDIVPDZrmk:
9455 case X86::VDIVPDZrmkz:
9456 case X86::VDIVPDZrr:
9457 case X86::VDIVPDZrrk:
9458 case X86::VDIVPDZrrkz:
9459 case X86::VDIVPSZ128rm:
9460 case X86::VDIVPSZ128rmb:
9461 case X86::VDIVPSZ128rmbk:
9462 case X86::VDIVPSZ128rmbkz:
9463 case X86::VDIVPSZ128rmk:
9464 case X86::VDIVPSZ128rmkz:
9465 case X86::VDIVPSZ128rr:
9466 case X86::VDIVPSZ128rrk:
9467 case X86::VDIVPSZ128rrkz:
9468 case X86::VDIVPSZ256rm:
9469 case X86::VDIVPSZ256rmb:
9470 case X86::VDIVPSZ256rmbk:
9471 case X86::VDIVPSZ256rmbkz:
9472 case X86::VDIVPSZ256rmk:
9473 case X86::VDIVPSZ256rmkz:
9474 case X86::VDIVPSZ256rr:
9475 case X86::VDIVPSZ256rrk:
9476 case X86::VDIVPSZ256rrkz:
9477 case X86::VDIVPSZrrb:
9478 case X86::VDIVPSZrrbk:
9479 case X86::VDIVPSZrrbkz:
9480 case X86::VDIVPSZrm:
9481 case X86::VDIVPSZrmb:
9482 case X86::VDIVPSZrmbk:
9483 case X86::VDIVPSZrmbkz:
9484 case X86::VDIVPSZrmk:
9485 case X86::VDIVPSZrmkz:
9486 case X86::VDIVPSZrr:
9487 case X86::VDIVPSZrrk:
9488 case X86::VDIVPSZrrkz:
9489 case X86::VDIVSDZrm:
9490 case X86::VDIVSDZrr:
9491 case X86::VDIVSDZrm_Int:
9492 case X86::VDIVSDZrm_Intk:
9493 case X86::VDIVSDZrm_Intkz:
9494 case X86::VDIVSDZrr_Int:
9495 case X86::VDIVSDZrr_Intk:
9496 case X86::VDIVSDZrr_Intkz:
9497 case X86::VDIVSDZrrb_Int:
9498 case X86::VDIVSDZrrb_Intk:
9499 case X86::VDIVSDZrrb_Intkz:
9500 case X86::VDIVSSZrm:
9501 case X86::VDIVSSZrr:
9502 case X86::VDIVSSZrm_Int:
9503 case X86::VDIVSSZrm_Intk:
9504 case X86::VDIVSSZrm_Intkz:
9505 case X86::VDIVSSZrr_Int:
9506 case X86::VDIVSSZrr_Intk:
9507 case X86::VDIVSSZrr_Intkz:
9508 case X86::VDIVSSZrrb_Int:
9509 case X86::VDIVSSZrrb_Intk:
9510 case X86::VDIVSSZrrb_Intkz:
9511 case X86::VSQRTPDZ128m:
9512 case X86::VSQRTPDZ128mb:
9513 case X86::VSQRTPDZ128mbk:
9514 case X86::VSQRTPDZ128mbkz:
9515 case X86::VSQRTPDZ128mk:
9516 case X86::VSQRTPDZ128mkz:
9517 case X86::VSQRTPDZ128r:
9518 case X86::VSQRTPDZ128rk:
9519 case X86::VSQRTPDZ128rkz:
9520 case X86::VSQRTPDZ256m:
9521 case X86::VSQRTPDZ256mb:
9522 case X86::VSQRTPDZ256mbk:
9523 case X86::VSQRTPDZ256mbkz:
9524 case X86::VSQRTPDZ256mk:
9525 case X86::VSQRTPDZ256mkz:
9526 case X86::VSQRTPDZ256r:
9527 case X86::VSQRTPDZ256rk:
9528 case X86::VSQRTPDZ256rkz:
9529 case X86::VSQRTPDZm:
9530 case X86::VSQRTPDZmb:
9531 case X86::VSQRTPDZmbk:
9532 case X86::VSQRTPDZmbkz:
9533 case X86::VSQRTPDZmk:
9534 case X86::VSQRTPDZmkz:
9535 case X86::VSQRTPDZr:
9536 case X86::VSQRTPDZrb:
9537 case X86::VSQRTPDZrbk:
9538 case X86::VSQRTPDZrbkz:
9539 case X86::VSQRTPDZrk:
9540 case X86::VSQRTPDZrkz:
9541 case X86::VSQRTPSZ128m:
9542 case X86::VSQRTPSZ128mb:
9543 case X86::VSQRTPSZ128mbk:
9544 case X86::VSQRTPSZ128mbkz:
9545 case X86::VSQRTPSZ128mk:
9546 case X86::VSQRTPSZ128mkz:
9547 case X86::VSQRTPSZ128r:
9548 case X86::VSQRTPSZ128rk:
9549 case X86::VSQRTPSZ128rkz:
9550 case X86::VSQRTPSZ256m:
9551 case X86::VSQRTPSZ256mb:
9552 case X86::VSQRTPSZ256mbk:
9553 case X86::VSQRTPSZ256mbkz:
9554 case X86::VSQRTPSZ256mk:
9555 case X86::VSQRTPSZ256mkz:
9556 case X86::VSQRTPSZ256r:
9557 case X86::VSQRTPSZ256rk:
9558 case X86::VSQRTPSZ256rkz:
9559 case X86::VSQRTPSZm:
9560 case X86::VSQRTPSZmb:
9561 case X86::VSQRTPSZmbk:
9562 case X86::VSQRTPSZmbkz:
9563 case X86::VSQRTPSZmk:
9564 case X86::VSQRTPSZmkz:
9565 case X86::VSQRTPSZr:
9566 case X86::VSQRTPSZrb:
9567 case X86::VSQRTPSZrbk:
9568 case X86::VSQRTPSZrbkz:
9569 case X86::VSQRTPSZrk:
9570 case X86::VSQRTPSZrkz:
9571 case X86::VSQRTSDZm:
9572 case X86::VSQRTSDZm_Int:
9573 case X86::VSQRTSDZm_Intk:
9574 case X86::VSQRTSDZm_Intkz:
9575 case X86::VSQRTSDZr:
9576 case X86::VSQRTSDZr_Int:
9577 case X86::VSQRTSDZr_Intk:
9578 case X86::VSQRTSDZr_Intkz:
9579 case X86::VSQRTSDZrb_Int:
9580 case X86::VSQRTSDZrb_Intk:
9581 case X86::VSQRTSDZrb_Intkz:
9582 case X86::VSQRTSSZm:
9583 case X86::VSQRTSSZm_Int:
9584 case X86::VSQRTSSZm_Intk:
9585 case X86::VSQRTSSZm_Intkz:
9586 case X86::VSQRTSSZr:
9587 case X86::VSQRTSSZr_Int:
9588 case X86::VSQRTSSZr_Intk:
9589 case X86::VSQRTSSZr_Intkz:
9590 case X86::VSQRTSSZrb_Int:
9591 case X86::VSQRTSSZrb_Intk:
9592 case X86::VSQRTSSZrb_Intkz:
9594 case X86::VGATHERDPDYrm:
9595 case X86::VGATHERDPDZ128rm:
9596 case X86::VGATHERDPDZ256rm:
9597 case X86::VGATHERDPDZrm:
9598 case X86::VGATHERDPDrm:
9599 case X86::VGATHERDPSYrm:
9600 case X86::VGATHERDPSZ128rm:
9601 case X86::VGATHERDPSZ256rm:
9602 case X86::VGATHERDPSZrm:
9603 case X86::VGATHERDPSrm:
9604 case X86::VGATHERPF0DPDm:
9605 case X86::VGATHERPF0DPSm:
9606 case X86::VGATHERPF0QPDm:
9607 case X86::VGATHERPF0QPSm:
9608 case X86::VGATHERPF1DPDm:
9609 case X86::VGATHERPF1DPSm:
9610 case X86::VGATHERPF1QPDm:
9611 case X86::VGATHERPF1QPSm:
9612 case X86::VGATHERQPDYrm:
9613 case X86::VGATHERQPDZ128rm:
9614 case X86::VGATHERQPDZ256rm:
9615 case X86::VGATHERQPDZrm:
9616 case X86::VGATHERQPDrm:
9617 case X86::VGATHERQPSYrm:
9618 case X86::VGATHERQPSZ128rm:
9619 case X86::VGATHERQPSZ256rm:
9620 case X86::VGATHERQPSZrm:
9621 case X86::VGATHERQPSrm:
9622 case X86::VPGATHERDDYrm:
9623 case X86::VPGATHERDDZ128rm:
9624 case X86::VPGATHERDDZ256rm:
9625 case X86::VPGATHERDDZrm:
9626 case X86::VPGATHERDDrm:
9627 case X86::VPGATHERDQYrm:
9628 case X86::VPGATHERDQZ128rm:
9629 case X86::VPGATHERDQZ256rm:
9630 case X86::VPGATHERDQZrm:
9631 case X86::VPGATHERDQrm:
9632 case X86::VPGATHERQDYrm:
9633 case X86::VPGATHERQDZ128rm:
9634 case X86::VPGATHERQDZ256rm:
9635 case X86::VPGATHERQDZrm:
9636 case X86::VPGATHERQDrm:
9637 case X86::VPGATHERQQYrm:
9638 case X86::VPGATHERQQZ128rm:
9639 case X86::VPGATHERQQZ256rm:
9640 case X86::VPGATHERQQZrm:
9641 case X86::VPGATHERQQrm:
9642 case X86::VSCATTERDPDZ128mr:
9643 case X86::VSCATTERDPDZ256mr:
9644 case X86::VSCATTERDPDZmr:
9645 case X86::VSCATTERDPSZ128mr:
9646 case X86::VSCATTERDPSZ256mr:
9647 case X86::VSCATTERDPSZmr:
9648 case X86::VSCATTERPF0DPDm:
9649 case X86::VSCATTERPF0DPSm:
9650 case X86::VSCATTERPF0QPDm:
9651 case X86::VSCATTERPF0QPSm:
9652 case X86::VSCATTERPF1DPDm:
9653 case X86::VSCATTERPF1DPSm:
9654 case X86::VSCATTERPF1QPDm:
9655 case X86::VSCATTERPF1QPSm:
9656 case X86::VSCATTERQPDZ128mr:
9657 case X86::VSCATTERQPDZ256mr:
9658 case X86::VSCATTERQPDZmr:
9659 case X86::VSCATTERQPSZ128mr:
9660 case X86::VSCATTERQPSZ256mr:
9661 case X86::VSCATTERQPSZmr:
9662 case X86::VPSCATTERDDZ128mr:
9663 case X86::VPSCATTERDDZ256mr:
9664 case X86::VPSCATTERDDZmr:
9665 case X86::VPSCATTERDQZ128mr:
9666 case X86::VPSCATTERDQZ256mr:
9667 case X86::VPSCATTERDQZmr:
9668 case X86::VPSCATTERQDZ128mr:
9669 case X86::VPSCATTERQDZ256mr:
9670 case X86::VPSCATTERQDZmr:
9671 case X86::VPSCATTERQQZ128mr:
9672 case X86::VPSCATTERQQZ256mr:
9673 case X86::VPSCATTERQQZmr:
9683 unsigned UseIdx)
const {
9690 Inst.
getNumDefs() <= 2 &&
"Reassociation needs binary operators");
9700 assert((Inst.
getNumDefs() == 1 || FlagDef) &&
"Implicit def isn't flags?");
9701 if (FlagDef && !FlagDef->
isDead())
9712 bool Invert)
const {
9764 case X86::VPANDDZ128rr:
9765 case X86::VPANDDZ256rr:
9766 case X86::VPANDDZrr:
9767 case X86::VPANDQZ128rr:
9768 case X86::VPANDQZ256rr:
9769 case X86::VPANDQZrr:
9772 case X86::VPORDZ128rr:
9773 case X86::VPORDZ256rr:
9775 case X86::VPORQZ128rr:
9776 case X86::VPORQZ256rr:
9780 case X86::VPXORDZ128rr:
9781 case X86::VPXORDZ256rr:
9782 case X86::VPXORDZrr:
9783 case X86::VPXORQZ128rr:
9784 case X86::VPXORQZ256rr:
9785 case X86::VPXORQZrr:
9788 case X86::VANDPDYrr:
9789 case X86::VANDPSYrr:
9790 case X86::VANDPDZ128rr:
9791 case X86::VANDPSZ128rr:
9792 case X86::VANDPDZ256rr:
9793 case X86::VANDPSZ256rr:
9794 case X86::VANDPDZrr:
9795 case X86::VANDPSZrr:
9800 case X86::VORPDZ128rr:
9801 case X86::VORPSZ128rr:
9802 case X86::VORPDZ256rr:
9803 case X86::VORPSZ256rr:
9808 case X86::VXORPDYrr:
9809 case X86::VXORPSYrr:
9810 case X86::VXORPDZ128rr:
9811 case X86::VXORPSZ128rr:
9812 case X86::VXORPDZ256rr:
9813 case X86::VXORPSZ256rr:
9814 case X86::VXORPDZrr:
9815 case X86::VXORPSZrr:
9836 case X86::VPADDBYrr:
9837 case X86::VPADDWYrr:
9838 case X86::VPADDDYrr:
9839 case X86::VPADDQYrr:
9840 case X86::VPADDBZ128rr:
9841 case X86::VPADDWZ128rr:
9842 case X86::VPADDDZ128rr:
9843 case X86::VPADDQZ128rr:
9844 case X86::VPADDBZ256rr:
9845 case X86::VPADDWZ256rr:
9846 case X86::VPADDDZ256rr:
9847 case X86::VPADDQZ256rr:
9848 case X86::VPADDBZrr:
9849 case X86::VPADDWZrr:
9850 case X86::VPADDDZrr:
9851 case X86::VPADDQZrr:
9852 case X86::VPMULLWrr:
9853 case X86::VPMULLWYrr:
9854 case X86::VPMULLWZ128rr:
9855 case X86::VPMULLWZ256rr:
9856 case X86::VPMULLWZrr:
9857 case X86::VPMULLDrr:
9858 case X86::VPMULLDYrr:
9859 case X86::VPMULLDZ128rr:
9860 case X86::VPMULLDZ256rr:
9861 case X86::VPMULLDZrr:
9862 case X86::VPMULLQZ128rr:
9863 case X86::VPMULLQZ256rr:
9864 case X86::VPMULLQZrr:
9865 case X86::VPMAXSBrr:
9866 case X86::VPMAXSBYrr:
9867 case X86::VPMAXSBZ128rr:
9868 case X86::VPMAXSBZ256rr:
9869 case X86::VPMAXSBZrr:
9870 case X86::VPMAXSDrr:
9871 case X86::VPMAXSDYrr:
9872 case X86::VPMAXSDZ128rr:
9873 case X86::VPMAXSDZ256rr:
9874 case X86::VPMAXSDZrr:
9875 case X86::VPMAXSQZ128rr:
9876 case X86::VPMAXSQZ256rr:
9877 case X86::VPMAXSQZrr:
9878 case X86::VPMAXSWrr:
9879 case X86::VPMAXSWYrr:
9880 case X86::VPMAXSWZ128rr:
9881 case X86::VPMAXSWZ256rr:
9882 case X86::VPMAXSWZrr:
9883 case X86::VPMAXUBrr:
9884 case X86::VPMAXUBYrr:
9885 case X86::VPMAXUBZ128rr:
9886 case X86::VPMAXUBZ256rr:
9887 case X86::VPMAXUBZrr:
9888 case X86::VPMAXUDrr:
9889 case X86::VPMAXUDYrr:
9890 case X86::VPMAXUDZ128rr:
9891 case X86::VPMAXUDZ256rr:
9892 case X86::VPMAXUDZrr:
9893 case X86::VPMAXUQZ128rr:
9894 case X86::VPMAXUQZ256rr:
9895 case X86::VPMAXUQZrr:
9896 case X86::VPMAXUWrr:
9897 case X86::VPMAXUWYrr:
9898 case X86::VPMAXUWZ128rr:
9899 case X86::VPMAXUWZ256rr:
9900 case X86::VPMAXUWZrr:
9901 case X86::VPMINSBrr:
9902 case X86::VPMINSBYrr:
9903 case X86::VPMINSBZ128rr:
9904 case X86::VPMINSBZ256rr:
9905 case X86::VPMINSBZrr:
9906 case X86::VPMINSDrr:
9907 case X86::VPMINSDYrr:
9908 case X86::VPMINSDZ128rr:
9909 case X86::VPMINSDZ256rr:
9910 case X86::VPMINSDZrr:
9911 case X86::VPMINSQZ128rr:
9912 case X86::VPMINSQZ256rr:
9913 case X86::VPMINSQZrr:
9914 case X86::VPMINSWrr:
9915 case X86::VPMINSWYrr:
9916 case X86::VPMINSWZ128rr:
9917 case X86::VPMINSWZ256rr:
9918 case X86::VPMINSWZrr:
9919 case X86::VPMINUBrr:
9920 case X86::VPMINUBYrr:
9921 case X86::VPMINUBZ128rr:
9922 case X86::VPMINUBZ256rr:
9923 case X86::VPMINUBZrr:
9924 case X86::VPMINUDrr:
9925 case X86::VPMINUDYrr:
9926 case X86::VPMINUDZ128rr:
9927 case X86::VPMINUDZ256rr:
9928 case X86::VPMINUDZrr:
9929 case X86::VPMINUQZ128rr:
9930 case X86::VPMINUQZ256rr:
9931 case X86::VPMINUQZrr:
9932 case X86::VPMINUWrr:
9933 case X86::VPMINUWYrr:
9934 case X86::VPMINUWZ128rr:
9935 case X86::VPMINUWZ256rr:
9936 case X86::VPMINUWZrr:
9948 case X86::VMAXCPDrr:
9949 case X86::VMAXCPSrr:
9950 case X86::VMAXCPDYrr:
9951 case X86::VMAXCPSYrr:
9952 case X86::VMAXCPDZ128rr:
9953 case X86::VMAXCPSZ128rr:
9954 case X86::VMAXCPDZ256rr:
9955 case X86::VMAXCPSZ256rr:
9956 case X86::VMAXCPDZrr:
9957 case X86::VMAXCPSZrr:
9958 case X86::VMAXCSDrr:
9959 case X86::VMAXCSSrr:
9960 case X86::VMAXCSDZrr:
9961 case X86::VMAXCSSZrr:
9962 case X86::VMINCPDrr:
9963 case X86::VMINCPSrr:
9964 case X86::VMINCPDYrr:
9965 case X86::VMINCPSYrr:
9966 case X86::VMINCPDZ128rr:
9967 case X86::VMINCPSZ128rr:
9968 case X86::VMINCPDZ256rr:
9969 case X86::VMINCPSZ256rr:
9970 case X86::VMINCPDZrr:
9971 case X86::VMINCPSZrr:
9972 case X86::VMINCSDrr:
9973 case X86::VMINCSSrr:
9974 case X86::VMINCSDZrr:
9975 case X86::VMINCSSZrr:
9976 case X86::VMAXCPHZ128rr:
9977 case X86::VMAXCPHZ256rr:
9978 case X86::VMAXCPHZrr:
9979 case X86::VMAXCSHZrr:
9980 case X86::VMINCPHZ128rr:
9981 case X86::VMINCPHZ256rr:
9982 case X86::VMINCPHZrr:
9983 case X86::VMINCSHZrr:
9995 case X86::VADDPDYrr:
9996 case X86::VADDPSYrr:
9997 case X86::VADDPDZ128rr:
9998 case X86::VADDPSZ128rr:
9999 case X86::VADDPDZ256rr:
10000 case X86::VADDPSZ256rr:
10001 case X86::VADDPDZrr:
10002 case X86::VADDPSZrr:
10003 case X86::VADDSDrr:
10004 case X86::VADDSSrr:
10005 case X86::VADDSDZrr:
10006 case X86::VADDSSZrr:
10007 case X86::VMULPDrr:
10008 case X86::VMULPSrr:
10009 case X86::VMULPDYrr:
10010 case X86::VMULPSYrr:
10011 case X86::VMULPDZ128rr:
10012 case X86::VMULPSZ128rr:
10013 case X86::VMULPDZ256rr:
10014 case X86::VMULPSZ256rr:
10015 case X86::VMULPDZrr:
10016 case X86::VMULPSZrr:
10017 case X86::VMULSDrr:
10018 case X86::VMULSSrr:
10019 case X86::VMULSDZrr:
10020 case X86::VMULSSZrr:
10021 case X86::VADDPHZ128rr:
10022 case X86::VADDPHZ256rr:
10023 case X86::VADDPHZrr:
10024 case X86::VADDSHZrr:
10025 case X86::VMULPHZ128rr:
10026 case X86::VMULPHZ256rr:
10027 case X86::VMULPHZrr:
10028 case X86::VMULSHZrr:
10039static std::optional<ParamLoadedValue>
10042 Register DestReg =
MI.getOperand(0).getReg();
10043 Register SrcReg =
MI.getOperand(1).getReg();
10048 if (DestReg == DescribedReg)
10053 if (
unsigned SubRegIdx =
TRI->getSubRegIndex(DestReg, DescribedReg)) {
10054 Register SrcSubReg =
TRI->getSubReg(SrcReg, SubRegIdx);
10064 if (
MI.getOpcode() == X86::MOV8rr ||
MI.getOpcode() == X86::MOV16rr ||
10065 !
TRI->isSuperRegister(DestReg, DescribedReg))
10066 return std::nullopt;
10068 assert(
MI.getOpcode() == X86::MOV32rr &&
"Unexpected super-register case");
10072std::optional<ParamLoadedValue>
10079 switch (
MI.getOpcode()) {
10082 case X86::LEA64_32r: {
10084 if (!
TRI->isSuperRegisterEq(
MI.getOperand(0).getReg(), Reg))
10085 return std::nullopt;
10089 if (!
MI.getOperand(4).isImm() || !
MI.getOperand(2).isImm())
10090 return std::nullopt;
10099 if ((Op1.
isReg() && Op1.
getReg() ==
MI.getOperand(0).getReg()) ||
10100 Op2.
getReg() ==
MI.getOperand(0).getReg())
10101 return std::nullopt;
10102 else if ((Op1.
isReg() && Op1.
getReg() != X86::NoRegister &&
10103 TRI->regsOverlap(Op1.
getReg(),
MI.getOperand(0).getReg())) ||
10104 (Op2.
getReg() != X86::NoRegister &&
10105 TRI->regsOverlap(Op2.
getReg(),
MI.getOperand(0).getReg())))
10106 return std::nullopt;
10108 int64_t Coef =
MI.getOperand(2).getImm();
10109 int64_t
Offset =
MI.getOperand(4).getImm();
10112 if ((Op1.
isReg() && Op1.
getReg() != X86::NoRegister)) {
10114 }
else if (Op1.
isFI())
10117 if (
Op &&
Op->isReg() &&
Op->getReg() == Op2.
getReg() && Coef > 0) {
10122 if (
Op && Op2.
getReg() != X86::NoRegister) {
10123 int dwarfReg =
TRI->getDwarfRegNum(Op2.
getReg(),
false);
10125 return std::nullopt;
10126 else if (dwarfReg < 32) {
10127 Ops.
push_back(dwarf::DW_OP_breg0 + dwarfReg);
10146 if (((Op1.
isReg() && Op1.
getReg() != X86::NoRegister) || Op1.
isFI()) &&
10147 Op2.
getReg() != X86::NoRegister) {
10160 return std::nullopt;
10163 case X86::MOV64ri32:
10166 if (!
TRI->isSuperRegisterEq(
MI.getOperand(0).getReg(), Reg))
10167 return std::nullopt;
10174 case X86::XOR32rr: {
10177 if (!
TRI->isSuperRegisterEq(
MI.getOperand(0).getReg(), Reg))
10178 return std::nullopt;
10179 if (
MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg())
10181 return std::nullopt;
10183 case X86::MOVSX64rr32: {
10190 if (!
TRI->isSubRegisterEq(
MI.getOperand(0).getReg(), Reg))
10191 return std::nullopt;
10200 if (Reg ==
MI.getOperand(0).getReg())
10203 assert(X86MCRegisterClasses[X86::GR32RegClassID].
contains(Reg) &&
10204 "Unhandled sub-register case for MOVSX64rr32");
10209 assert(!
MI.isMoveImmediate() &&
"Unexpected MoveImm instruction");
10226 assert(!OldFlagDef1 == !OldFlagDef2 &&
10227 "Unexpected instruction type for reassociation");
10229 if (!OldFlagDef1 || !OldFlagDef2)
10233 "Must have dead EFLAGS operand in reassociable instruction");
10240 assert(NewFlagDef1 && NewFlagDef2 &&
10241 "Unexpected operand in reassociable instruction");
10251std::pair<unsigned, unsigned>
10253 return std::make_pair(TF, 0u);
10258 using namespace X86II;
10259 static const std::pair<unsigned, const char *> TargetFlags[] = {
10260 {MO_GOT_ABSOLUTE_ADDRESS,
"x86-got-absolute-address"},
10261 {MO_PIC_BASE_OFFSET,
"x86-pic-base-offset"},
10262 {MO_GOT,
"x86-got"},
10263 {MO_GOTOFF,
"x86-gotoff"},
10264 {MO_GOTPCREL,
"x86-gotpcrel"},
10265 {MO_GOTPCREL_NORELAX,
"x86-gotpcrel-norelax"},
10266 {MO_PLT,
"x86-plt"},
10267 {MO_TLSGD,
"x86-tlsgd"},
10268 {MO_TLSLD,
"x86-tlsld"},
10269 {MO_TLSLDM,
"x86-tlsldm"},
10270 {MO_GOTTPOFF,
"x86-gottpoff"},
10271 {MO_INDNTPOFF,
"x86-indntpoff"},
10272 {MO_TPOFF,
"x86-tpoff"},
10273 {MO_DTPOFF,
"x86-dtpoff"},
10274 {MO_NTPOFF,
"x86-ntpoff"},
10275 {MO_GOTNTPOFF,
"x86-gotntpoff"},
10276 {MO_DLLIMPORT,
"x86-dllimport"},
10277 {MO_DARWIN_NONLAZY,
"x86-darwin-nonlazy"},
10278 {MO_DARWIN_NONLAZY_PIC_BASE,
"x86-darwin-nonlazy-pic-base"},
10279 {MO_TLVP,
"x86-tlvp"},
10280 {MO_TLVP_PIC_BASE,
"x86-tlvp-pic-base"},
10281 {MO_SECREL,
"x86-secrel"},
10282 {MO_COFFSTUB,
"x86-coffstub"}};
10299 if (!TM->isPositionIndependent())
10306 if (GlobalBaseReg == 0)
10318 PC =
RegInfo.createVirtualRegister(&X86::GR32RegClass);
10320 PC = GlobalBaseReg;
10322 if (STI.is64Bit()) {
10375 StringRef getPassName()
const override {
10376 return "X86 PIC Global Base Reg Initialization";
10405 &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
10416 bool Changed =
false;
10421 switch (
I->getOpcode()) {
10422 case X86::TLS_base_addr32:
10423 case X86::TLS_base_addr64:
10424 if (TLSBaseAddrReg)
10425 I = ReplaceTLSBaseAddrCall(*
I, TLSBaseAddrReg);
10427 I = SetRegister(*
I, &TLSBaseAddrReg);
10436 for (
auto &
I : *
Node) {
10437 Changed |= VisitNode(
I, TLSBaseAddrReg);
10446 unsigned TLSBaseAddrReg) {
10449 const bool is64Bit = STI.is64Bit();
10455 TII->get(TargetOpcode::COPY),
is64Bit ? X86::RAX : X86::EAX)
10456 .
addReg(TLSBaseAddrReg);
10459 I.eraseFromParent();
10469 const bool is64Bit = STI.is64Bit();
10474 *TLSBaseAddrReg =
RegInfo.createVirtualRegister(
10475 is64Bit ? &X86::GR64RegClass : &X86::GR32RegClass);
10480 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
10486 StringRef getPassName()
const override {
10487 return "Local Dynamic TLS Access Clean-up";
10498char LDTLSCleanup::ID = 0;
10500 return new LDTLSCleanup();
10533std::optional<std::unique_ptr<outliner::OutlinedFunction>>
10536 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
10537 unsigned MinRepeats)
const {
10538 unsigned SequenceSize = 0;
10539 for (
auto &
MI : RepeatedSequenceLocs[0]) {
10543 if (
MI.isDebugInstr() ||
MI.isKill())
10550 unsigned CFICount = 0;
10551 for (
auto &
I : RepeatedSequenceLocs[0]) {
10552 if (
I.isCFIInstruction())
10562 std::vector<MCCFIInstruction> CFIInstructions =
10563 C.getMF()->getFrameInstructions();
10565 if (CFICount > 0 && CFICount != CFIInstructions.size())
10566 return std::nullopt;
10570 if (RepeatedSequenceLocs[0].back().isTerminator()) {
10574 return std::make_unique<outliner::OutlinedFunction>(
10575 RepeatedSequenceLocs, SequenceSize,
10582 return std::nullopt;
10587 return std::make_unique<outliner::OutlinedFunction>(
10606 if (!OutlineFromLinkOnceODRs &&
F.hasLinkOnceODRLinkage())
10616 unsigned Flags)
const {
10620 if (
MI.isTerminator())
10634 if (
MI.modifiesRegister(X86::RSP, &RI) ||
MI.readsRegister(X86::RSP, &RI) ||
10635 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
10636 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
10640 if (
MI.readsRegister(X86::RIP, &RI) ||
10641 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
10642 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
10646 if (
MI.isCFIInstruction())
10672 .addGlobalAddress(M.getNamedValue(MF.
getName())));
10676 .addGlobalAddress(M.getNamedValue(MF.
getName())));
10685 bool AllowSideEffects)
const {
10690 if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
10694 if (
TRI.isGeneralPurposeRegister(MF, Reg)) {
10699 if (!AllowSideEffects)
10706 }
else if (X86::VR128RegClass.
contains(Reg)) {
10715 }
else if (X86::VR256RegClass.
contains(Reg)) {
10724 }
else if (X86::VR512RegClass.
contains(Reg)) {
10726 if (!ST.hasAVX512())
10733 }
else if (X86::VK1RegClass.
contains(Reg) || X86::VK2RegClass.
contains(Reg) ||
10735 X86::VK16RegClass.
contains(Reg)) {
10740 unsigned Op = ST.hasBWI() ? X86::KXORQkk : X86::KXORWkk;
10749 bool DoRegPressureReduce)
const {
10752 case X86::VPDPWSSDrr:
10753 case X86::VPDPWSSDrm:
10754 case X86::VPDPWSSDYrr:
10755 case X86::VPDPWSSDYrm: {
10756 if (!Subtarget.hasFastDPWSSD()) {
10762 case X86::VPDPWSSDZ128r:
10763 case X86::VPDPWSSDZ128m:
10764 case X86::VPDPWSSDZ256r:
10765 case X86::VPDPWSSDZ256m:
10766 case X86::VPDPWSSDZr:
10767 case X86::VPDPWSSDZm: {
10768 if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) {
10776 Patterns, DoRegPressureReduce);
10788 unsigned AddOpc = 0;
10789 unsigned MaddOpc = 0;
10792 assert(
false &&
"It should not reach here");
10798 case X86::VPDPWSSDrr:
10799 MaddOpc = X86::VPMADDWDrr;
10800 AddOpc = X86::VPADDDrr;
10802 case X86::VPDPWSSDrm:
10803 MaddOpc = X86::VPMADDWDrm;
10804 AddOpc = X86::VPADDDrr;
10806 case X86::VPDPWSSDZ128r:
10807 MaddOpc = X86::VPMADDWDZ128rr;
10808 AddOpc = X86::VPADDDZ128rr;
10810 case X86::VPDPWSSDZ128m:
10811 MaddOpc = X86::VPMADDWDZ128rm;
10812 AddOpc = X86::VPADDDZ128rr;
10818 case X86::VPDPWSSDYrr:
10819 MaddOpc = X86::VPMADDWDYrr;
10820 AddOpc = X86::VPADDDYrr;
10822 case X86::VPDPWSSDYrm:
10823 MaddOpc = X86::VPMADDWDYrm;
10824 AddOpc = X86::VPADDDYrr;
10826 case X86::VPDPWSSDZ256r:
10827 MaddOpc = X86::VPMADDWDZ256rr;
10828 AddOpc = X86::VPADDDZ256rr;
10830 case X86::VPDPWSSDZ256m:
10831 MaddOpc = X86::VPMADDWDZ256rm;
10832 AddOpc = X86::VPADDDZ256rr;
10838 case X86::VPDPWSSDZr:
10839 MaddOpc = X86::VPMADDWDZrr;
10840 AddOpc = X86::VPADDDZrr;
10842 case X86::VPDPWSSDZm:
10843 MaddOpc = X86::VPMADDWDZrm;
10844 AddOpc = X86::VPADDDZrr;
10856 InstrIdxForVirtReg.
insert(std::make_pair(NewReg, 0));
10878 DelInstrs, InstrIdxForVirtReg);
10882 InstrIdxForVirtReg);
10892 M.Base.FrameIndex = FI;
10893 M.getFullAddress(Ops);
10896#define GET_INSTRINFO_HELPERS
10897#include "X86GenInstrInfo.inc"
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineOutlinerClass
Constants defining how certain sequences should be outlined.
@ MachineOutlinerTailCall
Emit a save, restore, call, and return.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
static bool lookup(const GsymReader &GR, DataExtractor &Data, uint64_t &Offset, uint64_t BaseAddr, uint64_t Addr, SourceLocations &SrcLocs, llvm::Error &Err)
A Lookup helper functions.
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Provides some synthesis utilities to produce sequences of values.
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
#define FROM_TO(FROM, TO)
static bool is64Bit(const char *name)
#define GET_EGPR_IF_ENABLED(OPC)
static bool isLEA(unsigned Opcode)
static void addOperands(MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)
static std::optional< ParamLoadedValue > describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg, const TargetRegisterInfo *TRI)
If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible,...
static cl::opt< unsigned > PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)
static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF, MachineInstr &MI)
static bool isConvertibleLEA(MachineInstr *MI)
static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)
static bool isAMXOpcode(unsigned Opc)
static int getJumpTableIndexFromReg(const MachineRegisterInfo &MRI, Register Reg)
static void updateOperandRegConstraints(MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII)
static bool findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, const MachineRegisterInfo *MRI, MachineInstr **AndInstr, const TargetRegisterInfo *TRI, bool &NoSignFlag, bool &ClearsOverflowFlag)
static int getJumpTableIndexFromAddr(const MachineInstr &MI)
static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr)
static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)
static unsigned getNewOpcFromTable(ArrayRef< X86TableEntry > Table, unsigned Opc)
static unsigned getStoreRegOpcode(Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
#define FOLD_BROADCAST(SIZE)
static cl::opt< unsigned > UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)
#define CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64)
static bool isTruncatedShiftCountForLEA(unsigned ShAmt)
Check whether the given shift count is appropriate can be represented by a LEA instruction.
static cl::opt< bool > ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static SmallVector< MachineMemOperand *, 2 > extractLoadMMOs(ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static MachineInstr * fuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)
static void printFailMsgforFold(const MachineInstr &MI, unsigned Idx)
static bool canConvert2Copy(unsigned Opc)
static cl::opt< bool > NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)
static bool expandNOVLXStore(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)
static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes)
static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, Register Reg)
Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
#define VPERM_CASES_BROADCAST(Suffix)
static X86::CondCode isUseDefConvertible(const MachineInstr &MI)
Check whether the use can be converted to remove a comparison against zero.
static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
static unsigned getLoadRegOpcode(Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum, bool ForLoadFold=false)
static MachineInstr * makeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)
#define GET_ND_IF_ENABLED(OPC)
static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold=false)
Return true for all instructions that only update the first 32 or 64-bits of the destination register...
static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)
static const uint16_t * lookupAVX512(unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)
static unsigned getLoadStoreRegOpcode(Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load)
#define VPERM_CASES(Suffix)
#define FROM_TO_SIZE(A, B, S)
static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes)
static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag, bool &ClearsOverflowFlag)
Check whether the definition can be converted to remove a comparison against zero.
static bool isHReg(unsigned Reg)
Test if the given register is a physical h register.
static MachineInstr * fuseInst(MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)
static X86::CondCode getSwappedCondition(X86::CondCode CC)
Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such t...
static unsigned getCommutedVPERMV3Opcode(unsigned Opcode)
static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static MachineBasicBlock * getFallThroughMBB(MachineBasicBlock *MBB, MachineBasicBlock *TBB)
static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses content...
static unsigned getLoadStoreOpcodeForFP16(bool Load, const X86Subtarget &STI)
static cl::opt< bool > PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)
static bool expandNOVLXLoad(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)
static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
This determines which of three possible cases of a three source commute the source indexes correspond...
static bool isX87Reg(unsigned Reg)
Return true if the Reg is X87 register.
static void genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)
static unsigned getTruncatedShiftCount(const MachineInstr &MI, unsigned ShiftAmtOperandIdx)
Check whether the shift count for a machine operand is non-zero.
static SmallVector< MachineMemOperand *, 2 > extractStoreMMOs(ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static unsigned getBroadcastOpcode(const X86FoldTableEntry *I, const TargetRegisterClass *RC, const X86Subtarget &STI)
static unsigned convertALUrr2ALUri(unsigned Opc)
Convert an ALUrr opcode to corresponding ALUri opcode.
static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI)
Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
static bool isCommutableVPERMV3Instruction(unsigned Opcode)
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesCFG()
This function should be called by the pass, iff they do not:
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
This is an important base class in LLVM.
static Constant * getAllOnesValue(Type *Ty)
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendExt(const DIExpression *Expr, unsigned FromSize, unsigned ToSize, bool Signed)
Append a zero- or sign-extension to Expr.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Base class for the actual dominator tree node.
DomTreeNodeBase< NodeT > * getRootNode()
getRootNode - This returns the entry node for the CFG of the function.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
FunctionPass class - This class is used to implement most global optimizations.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveInterval & getInterval(Register Reg)
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
A set of physical registers with utility functions to track liveness when walking backward/forward th...
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * > > &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
bool usesWindowsCFI() const
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Instances of this class represent a single low-level machine instruction.
void setOpcode(unsigned Op)
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
Wrapper class representing physical registers. Should be passed by value.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
unsigned pred_size() const
MachineInstrBundleIterator< const MachineInstr > const_iterator
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
pred_iterator pred_begin()
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< succ_iterator > successors()
reverse_iterator rbegin()
@ LQR_Dead
Register is known to be fully dead.
bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
This class is a data container for one entry in a MachineConstantPool.
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
union llvm::MachineConstantPoolEntry::@204 Val
The constant itself.
const Constant * ConstVal
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
const MachineBasicBlock & front() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
mop_iterator operands_begin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isImplicitDef() const
const MachineBasicBlock * getParent() const
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
unsigned getNumDefs() const
Returns the total number of definitions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
This class contains meta information specific to a module.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void setImplicit(bool Val=true)
void setImm(int64_t immVal)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
static MachineOperand CreateImm(int64_t Val)
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
int64_t getOffset() const
Return the offset from the symbol in this operand.
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const TargetRegisterInfo * getTargetRegisterInfo() const
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
MachineFunction & getMachineFunction() const
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
bool hasFP(const MachineFunction &MF) const
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
virtual void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
bool isPositionIndependent() const
CodeModel::Model getCodeModel() const
Returns the code model.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Provide an instruction scheduling machine model to CodeGen passes.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
static Type * getDoubleTy(LLVMContext &C)
static Type * getFP128Ty(LLVMContext &C)
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
SlotIndex def
The index of the defining instruction.
LLVM Value Representation.
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Wraps up getting a CFI index and building a MachineInstr for it.
void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Check if there exists an earlier instruction that operates on the same source operands and sets eflag...
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying...
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
X86InstrInfo(X86Subtarget &STI)
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Fold a load or store of the specified stack slot into the specified machine instruction for the speci...
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions ...
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
bool isUnconditionalTailCall(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
int getJumpTableIndex(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
bool isHighLatencyDef(int opc) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
Try to remove the load by folding it to a register operand at the use.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Register getGlobalBaseReg() const
int getTCReturnAddrDelta() const
void setGlobalBaseReg(Register Reg)
unsigned getNumLocalDynamicTLSAccesses() const
bool getUsesRedZone() const
bool canRealignStack(const MachineFunction &MF) const override
bool isPICStyleGOT() const
bool isTargetWin64() const
const X86InstrInfo * getInstrInfo() const override
const X86RegisterInfo * getRegisterInfo() const override
const X86FrameLowering * getFrameLowering() const override
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ X86
Windows x64, Windows Itanium (IA-64)
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
@ SSEDomainShift
Execution domain for SSE instructions.
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool canUseApxExtendedReg(const MCInstrDesc &Desc)
bool isPseudo(uint64_t TSFlags)
bool isKMasked(uint64_t TSFlags)
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
CondCode getCondFromBranch(const MachineInstr &MI)
CondCode getCondFromCFCMov(const MachineInstr &MI)
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
int getFirstAddrOperandIdx(const MachineInstr &MI)
Return the index of the instruction's first address operand, if it has a memory reference,...
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
unsigned getNonNDVariant(unsigned Opc)
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
CondCode getCondFromSETCC(const MachineInstr &MI)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
CondCode getCondFromCCMP(const MachineInstr &MI)
int getCCMPCondFlagsFromCondCode(CondCode CC)
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)
Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getNFVariant(unsigned Opc)
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
CondCode getCondFromCMov(const MachineInstr &MI)
initializer< Ty > init(const Ty &Val)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
int popcount(T Value) noexcept
Count the number of set bits in a value.
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
static bool isMem(const MachineInstr &MI, unsigned Op)
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
unsigned getDeadRegState(bool B)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
MaybeAlign getAlign(const Function &F, unsigned Index)
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
const X86FoldTableEntry * lookupBroadcastFoldTable(unsigned RegOp, unsigned OpNum)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
const X86InstrFMA3Group * getFMA3Group(unsigned Opcode, uint64_t TSFlags)
Returns a reference to a group of FMA3 opcodes to where the given Opcode is included.
auto reverse(ContainerTy &&C)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset],...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const X86FoldTableEntry * lookupTwoAddrFoldTable(unsigned RegOp)
static const MachineInstrBuilder & addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2)
addRegReg - This function is used to add a memory reference of the form: [Reg + Reg].
static const MachineInstrBuilder & addOffset(const MachineInstrBuilder &MIB, int Offset)
unsigned getUndefRegState(bool B)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
unsigned getDefRegState(bool B)
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
const X86FoldTableEntry * lookupUnfoldTable(unsigned MemOp)
constexpr unsigned BitWidth
bool matchBroadcastSize(const X86FoldTableEntry &Entry, unsigned BroadcastBits)
const X86FoldTableEntry * lookupFoldTable(unsigned RegOp, unsigned OpNum)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
This represents a simple continuous liveness interval for a value.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
X86AddressMode - This struct holds a generalized full x86 address mode.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
unsigned get213Opcode() const
Returns the 213 form of FMA opcode.
unsigned get231Opcode() const
Returns the 231 form of FMA opcode.
bool isIntrinsic() const
Returns true iff the group of FMA opcodes holds intrinsic opcodes.
unsigned get132Opcode() const
Returns the 132 form of FMA opcode.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.
unsigned FrameConstructionID
Target-defined identifier for constructing a frame for this function.