LLVM 20.0.0git
RISCVMachineFunctionInfo.h
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1//=- RISCVMachineFunctionInfo.h - RISC-V machine function info ----*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISCV-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
15
16#include "RISCVSubtarget.h"
20
21namespace llvm {
22
23class RISCVMachineFunctionInfo;
24
25namespace yaml {
29
32
33 void mappingImpl(yaml::IO &YamlIO) override;
35};
36
38 static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
39 YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex);
40 YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize);
41 }
42};
43} // end namespace yaml
44
45/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
46/// and contains private RISCV-specific information for each MachineFunction.
48private:
49 /// FrameIndex for start of varargs area
50 int VarArgsFrameIndex = 0;
51 /// Size of the save area used for varargs
52 int VarArgsSaveSize = 0;
53 /// FrameIndex used for transferring values between 64-bit FPRs and a pair
54 /// of 32-bit GPRs via the stack.
55 int MoveF64FrameIndex = -1;
56 /// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
57 int BranchRelaxationScratchFrameIndex = -1;
58 /// Size of any opaque stack adjustment due to save/restore libcalls.
59 unsigned LibCallStackSize = 0;
60 /// Size of RVV stack.
61 uint64_t RVVStackSize = 0;
62 /// Alignment of RVV stack.
63 Align RVVStackAlign;
64 /// Padding required to keep RVV stack aligned within the main stack.
65 uint64_t RVVPadding = 0;
66 /// Size of stack frame to save callee saved registers
67 unsigned CalleeSavedStackSize = 0;
68 /// Is there any vector argument or return?
69 bool IsVectorCall = false;
70
71 /// Registers that have been sign extended from i32.
72 SmallVector<Register, 8> SExt32Registers;
73
74 /// Size of stack frame for Zcmp PUSH/POP
75 unsigned RVPushStackSize = 0;
76 unsigned RVPushRegs = 0;
78
79 int64_t StackProbeSize = 0;
80
81public:
83
87 const override;
88
89 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
90 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
91
92 unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
93 void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
94
96 if (MoveF64FrameIndex == -1)
97 MoveF64FrameIndex =
98 MF.getFrameInfo().CreateStackObject(8, Align(8), false);
99 return MoveF64FrameIndex;
100 }
101
103 return BranchRelaxationScratchFrameIndex;
104 }
106 BranchRelaxationScratchFrameIndex = Index;
107 }
108
109 unsigned getReservedSpillsSize() const {
110 return LibCallStackSize + RVPushStackSize;
111 }
112
113 unsigned getLibCallStackSize() const { return LibCallStackSize; }
114 void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; }
115
117 // We cannot use fixed locations for the callee saved spill slots if the
118 // function uses a varargs save area, or is an interrupt handler.
119 return !isPushable(MF) &&
120 MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
121 VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
122 !MF.getFunction().hasFnAttribute("interrupt");
123 }
124
125 uint64_t getRVVStackSize() const { return RVVStackSize; }
126 void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
127
128 Align getRVVStackAlign() const { return RVVStackAlign; }
129 void setRVVStackAlign(Align StackAlign) { RVVStackAlign = StackAlign; }
130
131 uint64_t getRVVPadding() const { return RVVPadding; }
132 void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
133
134 unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
135 void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
136
137 bool isPushable(const MachineFunction &MF) const {
138 // We cannot use fixed locations for the callee saved spill slots if the
139 // function uses a varargs save area.
140 // TODO: Use a separate placement for vararg registers to enable Zcmp.
141 return MF.getSubtarget<RISCVSubtarget>().hasStdExtZcmp() &&
143 VarArgsSaveSize == 0;
144 }
145
146 int getRVPushRlist() const { return RVPushRlist; }
147 void setRVPushRlist(int Rlist) { RVPushRlist = Rlist; }
148
149 unsigned getRVPushRegs() const { return RVPushRegs; }
150 void setRVPushRegs(unsigned Regs) { RVPushRegs = Regs; }
151
152 unsigned getRVPushStackSize() const { return RVPushStackSize; }
153 void setRVPushStackSize(unsigned Size) { RVPushStackSize = Size; }
154
156
158 bool isSExt32Register(Register Reg) const;
159
160 bool isVectorCall() const { return IsVectorCall; }
161 void setIsVectorCall() { IsVectorCall = true; }
162};
163
164} // end namespace llvm
165
166#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
uint32_t Index
uint64_t Size
IO & YamlIO
Definition: ELFYAML.cpp:1312
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned Reg
Basic Register Allocator
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:731
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasTailCall() const
Returns true if the function contains a tail call.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isPushable(const MachineFunction &MF) const
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI)
bool isSExt32Register(Register Reg) const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
int getMoveF64FrameIndex(MachineFunction &MF)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI)
void mappingImpl(yaml::IO &YamlIO) override