LLVM 20.0.0git
HexagonDisassembler.cpp
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1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoderOps.h"
17#include "llvm/MC/MCDisassembler/MCDisassembler.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/raw_ostream.h"
27#include <cassert>
28#include <cstddef>
29#include <cstdint>
30#include <memory>
31
32#define DEBUG_TYPE "hexagon-disassembler"
33
34using namespace llvm;
35using namespace Hexagon;
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41/// Hexagon disassembler for all Hexagon platforms.
42class HexagonDisassembler : public MCDisassembler {
43public:
44 std::unique_ptr<MCInstrInfo const> const MCII;
45 std::unique_ptr<MCInst *> CurrentBundle;
46 mutable MCInst const *CurrentExtender;
47
48 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
49 MCInstrInfo const *MCII)
50 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
51 CurrentExtender(nullptr) {}
52
53 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream, bool &Complete) const;
56 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const override;
59 void remapInstruction(MCInst &Instr) const;
60};
61
62static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
63 int64_t Value) {
64 MCInstrInfo MCII = *Disassembler.MCII;
65 if (!Disassembler.CurrentExtender ||
66 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
67 return Value;
68 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
69 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
70 int64_t Bits;
71 bool Success =
72 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
73 Bits);
74 assert(Success);
75 (void)Success;
76 uint64_t Upper26 = static_cast<uint64_t>(Bits);
77 uint64_t Operand = Upper26 | Lower6;
78 return Operand;
79}
80static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
81 return *static_cast<HexagonDisassembler const *>(Decoder);
82}
83template <size_t T>
84static void signedDecoder(MCInst &MI, unsigned tmp,
85 const MCDisassembler *Decoder) {
86 HexagonDisassembler const &Disassembler = disassembler(Decoder);
87 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
88 int64_t Extended = SignExtend64<32>(FullValue);
89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
90}
91}
92
93// Forward declare these because the auto-generated code will reference them.
94// Definitions are further down.
95
96static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus
100DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const MCDisassembler *Decoder);
103static DecodeStatus
104DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
105 const MCDisassembler *Decoder);
106static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
108 const MCDisassembler *Decoder);
109static DecodeStatus
110DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
111 const MCDisassembler *Decoder);
112static DecodeStatus
113DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
114 uint64_t Address,
115 const MCDisassembler *Decoder);
116static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
117 uint64_t Address,
118 const MCDisassembler *Decoder);
119static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder);
122static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
123 uint64_t Address,
124 const MCDisassembler *Decoder);
125static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
126 uint64_t Address,
127 const MCDisassembler *Decoder);
128static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
129 uint64_t Address,
130 const MCDisassembler *Decoder);
131static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder);
134static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus
144DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149
150static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
151 uint64_t Address,
152 const MCDisassembler *Decoder);
153static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
154 uint64_t /*Address*/,
155 const MCDisassembler *Decoder);
156static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
157 const MCDisassembler *Decoder);
158#include "HexagonDepDecoders.inc"
159#include "HexagonGenDisassemblerTables.inc"
160
161static MCDisassembler *createHexagonDisassembler(const Target &T,
162 const MCSubtargetInfo &STI,
163 MCContext &Ctx) {
164 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
165}
166
167extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() {
168 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
169 createHexagonDisassembler);
170}
171
172DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
173 ArrayRef<uint8_t> Bytes,
174 uint64_t Address,
175 raw_ostream &cs) const {
176 DecodeStatus Result = DecodeStatus::Success;
177 bool Complete = false;
178 Size = 0;
179
180 *CurrentBundle = &MI;
181 MI.setOpcode(Hexagon::BUNDLE);
182 MI.addOperand(MCOperand::createImm(0));
183 while (Result == Success && !Complete) {
184 if (Bytes.size() < HEXAGON_INSTR_SIZE)
185 return MCDisassembler::Fail;
186 MCInst *Inst = getContext().createMCInst();
187 Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete);
188 MI.addOperand(MCOperand::createInst(Inst));
189 Size += HEXAGON_INSTR_SIZE;
190 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
191 }
192 if (Result == MCDisassembler::Fail)
193 return Result;
194 if (Size > HEXAGON_MAX_PACKET_SIZE)
195 return MCDisassembler::Fail;
196
197 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
198 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
199 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
200 *getContext().getRegisterInfo(), false);
201 if (!Checker.check())
202 return MCDisassembler::Fail;
203 remapInstruction(MI);
204 return MCDisassembler::Success;
205}
206
207void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
208 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
209 auto &MI = const_cast<MCInst &>(*I.getInst());
210 switch (MI.getOpcode()) {
211 case Hexagon::S2_allocframe:
212 if (MI.getOperand(0).getReg() == Hexagon::R29) {
213 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
214 MI.erase(MI.begin () + 1);
215 MI.erase(MI.begin ());
216 }
217 break;
218 case Hexagon::L2_deallocframe:
219 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
220 MI.getOperand(1).getReg() == Hexagon::R30) {
221 MI.setOpcode(L6_deallocframe_map_to_raw);
222 MI.erase(MI.begin () + 1);
223 MI.erase(MI.begin ());
224 }
225 break;
226 case Hexagon::L4_return:
227 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
228 MI.getOperand(1).getReg() == Hexagon::R30) {
229 MI.setOpcode(L6_return_map_to_raw);
230 MI.erase(MI.begin () + 1);
231 MI.erase(MI.begin ());
232 }
233 break;
234 case Hexagon::L4_return_t:
235 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
236 MI.getOperand(2).getReg() == Hexagon::R30) {
237 MI.setOpcode(L4_return_map_to_raw_t);
238 MI.erase(MI.begin () + 2);
239 MI.erase(MI.begin ());
240 }
241 break;
242 case Hexagon::L4_return_f:
243 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
244 MI.getOperand(2).getReg() == Hexagon::R30) {
245 MI.setOpcode(L4_return_map_to_raw_f);
246 MI.erase(MI.begin () + 2);
247 MI.erase(MI.begin ());
248 }
249 break;
250 case Hexagon::L4_return_tnew_pt:
251 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
252 MI.getOperand(2).getReg() == Hexagon::R30) {
253 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
254 MI.erase(MI.begin () + 2);
255 MI.erase(MI.begin ());
256 }
257 break;
258 case Hexagon::L4_return_fnew_pt:
259 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
260 MI.getOperand(2).getReg() == Hexagon::R30) {
261 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
262 MI.erase(MI.begin () + 2);
263 MI.erase(MI.begin ());
264 }
265 break;
266 case Hexagon::L4_return_tnew_pnt:
267 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
268 MI.getOperand(2).getReg() == Hexagon::R30) {
269 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
270 MI.erase(MI.begin () + 2);
271 MI.erase(MI.begin ());
272 }
273 break;
274 case Hexagon::L4_return_fnew_pnt:
275 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
276 MI.getOperand(2).getReg() == Hexagon::R30) {
277 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
278 MI.erase(MI.begin () + 2);
279 MI.erase(MI.begin ());
280 }
281 break;
282 }
283 }
284}
285
286static void adjustDuplex(MCInst &MI, MCContext &Context) {
287 switch (MI.getOpcode()) {
288 case Hexagon::SA1_setin1:
289 MI.insert(MI.begin() + 1,
290 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
291 break;
292 case Hexagon::SA1_dec:
293 MI.insert(MI.begin() + 2,
294 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
295 break;
296 default:
297 break;
298 }
299}
300
301DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
302 ArrayRef<uint8_t> Bytes,
303 uint64_t Address,
304 raw_ostream &cs,
305 bool &Complete) const {
306 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
307
308 uint32_t Instruction = support::endian::read32le(Bytes.data());
309
310 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
311 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
312 HexagonII::INST_PARSE_LOOP_END) {
313 if (BundleSize == 0)
314 HexagonMCInstrInfo::setInnerLoop(MCB);
315 else if (BundleSize == 1)
316 HexagonMCInstrInfo::setOuterLoop(MCB);
317 else
318 return DecodeStatus::Fail;
319 }
320
321 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
322 MCB, HexagonMCInstrInfo::bundleSize(MCB));
323
324 DecodeStatus Result = DecodeStatus::Fail;
325 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
326 HexagonII::INST_PARSE_DUPLEX) {
327 unsigned duplexIClass;
328 uint8_t const *DecodeLow, *DecodeHigh;
329 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
330 switch (duplexIClass) {
331 default:
332 return MCDisassembler::Fail;
333 case 0:
334 DecodeLow = DecoderTableSUBINSN_L132;
335 DecodeHigh = DecoderTableSUBINSN_L132;
336 break;
337 case 1:
338 DecodeLow = DecoderTableSUBINSN_L232;
339 DecodeHigh = DecoderTableSUBINSN_L132;
340 break;
341 case 2:
342 DecodeLow = DecoderTableSUBINSN_L232;
343 DecodeHigh = DecoderTableSUBINSN_L232;
344 break;
345 case 3:
346 DecodeLow = DecoderTableSUBINSN_A32;
347 DecodeHigh = DecoderTableSUBINSN_A32;
348 break;
349 case 4:
350 DecodeLow = DecoderTableSUBINSN_L132;
351 DecodeHigh = DecoderTableSUBINSN_A32;
352 break;
353 case 5:
354 DecodeLow = DecoderTableSUBINSN_L232;
355 DecodeHigh = DecoderTableSUBINSN_A32;
356 break;
357 case 6:
358 DecodeLow = DecoderTableSUBINSN_S132;
359 DecodeHigh = DecoderTableSUBINSN_A32;
360 break;
361 case 7:
362 DecodeLow = DecoderTableSUBINSN_S232;
363 DecodeHigh = DecoderTableSUBINSN_A32;
364 break;
365 case 8:
366 DecodeLow = DecoderTableSUBINSN_S132;
367 DecodeHigh = DecoderTableSUBINSN_L132;
368 break;
369 case 9:
370 DecodeLow = DecoderTableSUBINSN_S132;
371 DecodeHigh = DecoderTableSUBINSN_L232;
372 break;
373 case 10:
374 DecodeLow = DecoderTableSUBINSN_S132;
375 DecodeHigh = DecoderTableSUBINSN_S132;
376 break;
377 case 11:
378 DecodeLow = DecoderTableSUBINSN_S232;
379 DecodeHigh = DecoderTableSUBINSN_S132;
380 break;
381 case 12:
382 DecodeLow = DecoderTableSUBINSN_S232;
383 DecodeHigh = DecoderTableSUBINSN_L132;
384 break;
385 case 13:
386 DecodeLow = DecoderTableSUBINSN_S232;
387 DecodeHigh = DecoderTableSUBINSN_L232;
388 break;
389 case 14:
390 DecodeLow = DecoderTableSUBINSN_S232;
391 DecodeHigh = DecoderTableSUBINSN_S232;
392 break;
393 }
394 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
395 MCInst *MILow = getContext().createMCInst();
396 MCInst *MIHigh = getContext().createMCInst();
397 auto TmpExtender = CurrentExtender;
398 CurrentExtender =
399 nullptr; // constant extenders in duplex must always be in slot 1
400 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
401 this, STI);
402 CurrentExtender = TmpExtender;
403 if (Result != DecodeStatus::Success)
404 return DecodeStatus::Fail;
405 adjustDuplex(*MILow, getContext());
406 Result = decodeInstruction(
407 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
408 if (Result != DecodeStatus::Success)
409 return DecodeStatus::Fail;
410 adjustDuplex(*MIHigh, getContext());
411 MCOperand OPLow = MCOperand::createInst(MILow);
412 MCOperand OPHigh = MCOperand::createInst(MIHigh);
413 MI.addOperand(OPLow);
414 MI.addOperand(OPHigh);
415 Complete = true;
416 } else {
417 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
418 HexagonII::INST_PARSE_PACKET_END)
419 Complete = true;
420
421 if (CurrentExtender != nullptr)
422 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
423 Address, this, STI);
424
425 if (Result != MCDisassembler::Success)
426 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
427 STI);
428
429 if (Result != MCDisassembler::Success &&
430 STI.hasFeature(Hexagon::ExtensionHVX))
431 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
432 Address, this, STI);
433
434 }
435
436 switch (MI.getOpcode()) {
437 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
438 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
439 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
440 case Hexagon::J4_cmpeqn1_fp0_jump_t:
441 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
442 case Hexagon::J4_cmpeqn1_fp1_jump_t:
443 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
444 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
445 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
446 case Hexagon::J4_cmpeqn1_tp0_jump_t:
447 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
448 case Hexagon::J4_cmpeqn1_tp1_jump_t:
449 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
450 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
451 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
452 case Hexagon::J4_cmpgtn1_fp0_jump_t:
453 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
454 case Hexagon::J4_cmpgtn1_fp1_jump_t:
455 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
456 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
457 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
458 case Hexagon::J4_cmpgtn1_tp0_jump_t:
459 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
460 case Hexagon::J4_cmpgtn1_tp1_jump_t:
461 MI.insert(MI.begin() + 1,
462 MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
463 break;
464 default:
465 break;
466 }
467
468 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
469 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
470 MCOperand &MCO = MI.getOperand(OpIndex);
471 assert(MCO.isReg() && "New value consumers must be registers");
472 unsigned Register =
473 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
474 if ((Register & 0x6) == 0)
475 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
476 return MCDisassembler::Fail;
477 unsigned Lookback = (Register & 0x6) >> 1;
478 unsigned Offset = 1;
479 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
480 bool PrevVector = false;
481 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
482 auto i = Instructions.end() - 1;
483 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
484 if (i == n)
485 // Couldn't find producer
486 return MCDisassembler::Fail;
487 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
488 if (Vector && !CurrentVector)
489 // Skip scalars when calculating distances for vectors
490 ++Lookback;
491 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
492 ++Lookback;
493 PrevVector = CurrentVector;
494 if (Offset == Lookback)
495 break;
496 }
497 auto const &Inst = *i->getInst();
498 bool SubregBit = (Register & 0x1) != 0;
499 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
500 // If subreg bit is set we're selecting the second produced newvalue
501 MCRegister Producer =
502 SubregBit
503 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
504 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
505 assert(Producer != Hexagon::NoRegister);
506 MCO.setReg(Producer);
507 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
508 MCRegister Producer =
509 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
510
511 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
512 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
513 const unsigned ProdPairIndex =
514 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
515 if (Rev)
516 SubregBit = !SubregBit;
517 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
518 } else if (SubregBit)
519 // Hexagon PRM 10.11 New-value operands
520 // Nt[0] is reserved and should always be encoded as zero.
521 return MCDisassembler::Fail;
522 assert(Producer != Hexagon::NoRegister);
523 MCO.setReg(Producer);
524 } else
525 return MCDisassembler::Fail;
526 }
527
528 if (CurrentExtender != nullptr) {
529 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
530 ? *MI.getOperand(1).getInst()
531 : MI;
532 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
533 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
534 return MCDisassembler::Fail;
535 }
536 return Result;
537}
538
539static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
540 ArrayRef<MCPhysReg> Table) {
541 if (RegNo < Table.size()) {
542 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
543 return MCDisassembler::Success;
544 }
545
546 return MCDisassembler::Fail;
547}
548
549static DecodeStatus
550DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
551 const MCDisassembler *Decoder) {
552 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
553}
554
555static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
556 uint64_t Address,
557 const MCDisassembler *Decoder) {
558 static const MCPhysReg IntRegDecoderTable[] = {
559 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
560 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
561 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
562 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
563 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
564 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
565 Hexagon::R30, Hexagon::R31};
566
567 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
568}
569
570static DecodeStatus
571DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
572 uint64_t Address,
573 const MCDisassembler *Decoder) {
574 static const MCPhysReg GeneralSubRegDecoderTable[] = {
575 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
576 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
577 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
578 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
579 };
580
581 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
582}
583
584static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
585 uint64_t /*Address*/,
586 const MCDisassembler *Decoder) {
587 static const MCPhysReg HvxVRDecoderTable[] = {
588 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
589 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
590 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
591 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
592 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
593 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
594 Hexagon::V30, Hexagon::V31};
595
596 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
597}
598
599static DecodeStatus
600DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
601 uint64_t /*Address*/,
602 const MCDisassembler *Decoder) {
603 static const MCPhysReg DoubleRegDecoderTable[] = {
604 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
605 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
606 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
607 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
608
609 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
610}
611
612static DecodeStatus
613DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
614 uint64_t /*Address*/,
615 const MCDisassembler *Decoder) {
616 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
617 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
618 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
619
620 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
621}
622
623static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
624 uint64_t /*Address*/,
625 const MCDisassembler *Decoder) {
626 static const MCPhysReg HvxWRDecoderTable[] = {
627 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
628 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
629 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
630 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
631 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
632 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
633 Hexagon::W15, Hexagon::WR15,
634 };
635
636 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
637}
638
639LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
640 static DecodeStatus
641 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
642 uint64_t /*Address*/,
643 const MCDisassembler *Decoder) {
644 static const MCPhysReg HvxVQRDecoderTable[] = {
645 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
646 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
647
648 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
649}
650
651static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
652 uint64_t /*Address*/,
653 const MCDisassembler *Decoder) {
654 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
655 Hexagon::P2, Hexagon::P3};
656
657 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
658}
659
660static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
661 uint64_t /*Address*/,
662 const MCDisassembler *Decoder) {
663 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
664 Hexagon::Q2, Hexagon::Q3};
665
666 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
667}
668
669static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
670 uint64_t /*Address*/,
671 const MCDisassembler *Decoder) {
672 using namespace Hexagon;
673
674 static const MCPhysReg CtrlRegDecoderTable[] = {
675 /* 0 */ SA0, LC0, SA1, LC1,
676 /* 4 */ P3_0, C5, M0, M1,
677 /* 8 */ USR, PC, UGP, GP,
678 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
679 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
680 /* 20 */ 0, 0, 0, 0,
681 /* 24 */ 0, 0, 0, 0,
682 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
683 };
684
685 if (RegNo >= std::size(CtrlRegDecoderTable))
686 return MCDisassembler::Fail;
687
688 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
689 if (CtrlRegDecoderTable[RegNo] == NoRegister)
690 return MCDisassembler::Fail;
691
692 unsigned Register = CtrlRegDecoderTable[RegNo];
693 Inst.addOperand(MCOperand::createReg(Register));
694 return MCDisassembler::Success;
695}
696
697static DecodeStatus
698DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
699 const MCDisassembler *Decoder) {
700 using namespace Hexagon;
701
702 static const MCPhysReg CtrlReg64DecoderTable[] = {
703 /* 0 */ C1_0, 0, C3_2, 0,
704 /* 4 */ C5_4, 0, C7_6, 0,
705 /* 8 */ C9_8, 0, C11_10, 0,
706 /* 12 */ CS, 0, UPCYCLE, 0,
707 /* 16 */ C17_16, 0, PKTCOUNT, 0,
708 /* 20 */ 0, 0, 0, 0,
709 /* 24 */ 0, 0, 0, 0,
710 /* 28 */ 0, 0, UTIMER, 0
711 };
712
713 if (RegNo >= std::size(CtrlReg64DecoderTable))
714 return MCDisassembler::Fail;
715
716 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
717 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
718 return MCDisassembler::Fail;
719
720 unsigned Register = CtrlReg64DecoderTable[RegNo];
721 Inst.addOperand(MCOperand::createReg(Register));
722 return MCDisassembler::Success;
723}
724
725static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
726 uint64_t /*Address*/,
727 const MCDisassembler *Decoder) {
728 unsigned Register = 0;
729 switch (RegNo) {
730 case 0:
731 Register = Hexagon::M0;
732 break;
733 case 1:
734 Register = Hexagon::M1;
735 break;
736 default:
737 return MCDisassembler::Fail;
738 }
739 Inst.addOperand(MCOperand::createReg(Register));
740 return MCDisassembler::Success;
741}
742
743static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
744 uint64_t /*Address*/,
745 const MCDisassembler *Decoder) {
746 HexagonDisassembler const &Disassembler = disassembler(Decoder);
747 int64_t FullValue = fullValue(Disassembler, MI, tmp);
748 assert(FullValue >= 0 && "Negative in unsigned decoder");
749 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
750 return MCDisassembler::Success;
751}
752
753static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
754 uint64_t /*Address*/,
755 const MCDisassembler *Decoder) {
756 HexagonDisassembler const &Disassembler = disassembler(Decoder);
757 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
758 tmp = SignExtend64(tmp, Bits);
759 signedDecoder<32>(MI, tmp, Decoder);
760 return MCDisassembler::Success;
761}
762
763// custom decoder for various jump/call immediates
764static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
765 const MCDisassembler *Decoder) {
766 HexagonDisassembler const &Disassembler = disassembler(Decoder);
767 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
768 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
769 if (Bits == 0)
770 Bits = 15;
771 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
772 uint32_t Extended = FullValue + Address;
773 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
774 4))
775 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
776 return MCDisassembler::Success;
777}
778
779static const uint16_t SysRegDecoderTable[] = {
780 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
781 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
782 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
783 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
784 Hexagon::S12, Hexagon::S13, Hexagon::S14,
785 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
786 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
787 Hexagon::VID, Hexagon::S22, Hexagon::S23,
788 Hexagon::S24, Hexagon::S25, Hexagon::S26,
789 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
790 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
791 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
792 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
793 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
794 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
795 Hexagon::S45, Hexagon::S46, Hexagon::S47,
796 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
797 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
798 Hexagon::S54, Hexagon::S55, Hexagon::S56,
799 Hexagon::S57, Hexagon::S58, Hexagon::S59,
800 Hexagon::S60, Hexagon::S61, Hexagon::S62,
801 Hexagon::S63, Hexagon::S64, Hexagon::S65,
802 Hexagon::S66, Hexagon::S67, Hexagon::S68,
803 Hexagon::S69, Hexagon::S70, Hexagon::S71,
804 Hexagon::S72, Hexagon::S73, Hexagon::S74,
805 Hexagon::S75, Hexagon::S76, Hexagon::S77,
806 Hexagon::S78, Hexagon::S79, Hexagon::S80,
807};
808
809static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
810 uint64_t /*Address*/,
811 const MCDisassembler *Decoder) {
812 if (RegNo >= std::size(SysRegDecoderTable))
813 return MCDisassembler::Fail;
814
815 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
816 return MCDisassembler::Fail;
817
818 unsigned Register = SysRegDecoderTable[RegNo];
819 Inst.addOperand(MCOperand::createReg(Register));
820 return MCDisassembler::Success;
821}
822
823static const uint16_t SysReg64DecoderTable[] = {
824 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
825 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
826 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
827 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
828 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
829 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
830 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
831 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
832 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
833 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
834};
835
836static DecodeStatus
837DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
838 const MCDisassembler *Decoder) {
839 RegNo = RegNo >> 1;
840 if (RegNo >= std::size(SysReg64DecoderTable))
841 return MCDisassembler::Fail;
842
843 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
844 return MCDisassembler::Fail;
845
846 unsigned Register = SysReg64DecoderTable[RegNo];
847 Inst.addOperand(MCOperand::createReg(Register));
848 return MCDisassembler::Success;
849}
850
851static DecodeStatus
852DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
853 const MCDisassembler *Decoder) {
854 using namespace Hexagon;
855
856 static const MCPhysReg GuestRegDecoderTable[] = {
857 /* 0 */ GELR, GSR, GOSP, G3,
858 /* 4 */ G4, G5, G6, G7,
859 /* 8 */ G8, G9, G10, G11,
860 /* 12 */ G12, G13, G14, G15,
861 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
862 /* 20 */ G20, G21, G22, G23,
863 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
864 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
865 };
866
867 if (RegNo >= std::size(GuestRegDecoderTable))
868 return MCDisassembler::Fail;
869 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
870 return MCDisassembler::Fail;
871
872 unsigned Register = GuestRegDecoderTable[RegNo];
873 Inst.addOperand(MCOperand::createReg(Register));
874 return MCDisassembler::Success;
875}
876
877static DecodeStatus
878DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
879 uint64_t /*Address*/,
880 const MCDisassembler *Decoder) {
881 using namespace Hexagon;
882
883 static const MCPhysReg GuestReg64DecoderTable[] = {
884 /* 0 */ G1_0, 0, G3_2, 0,
885 /* 4 */ G5_4, 0, G7_6, 0,
886 /* 8 */ G9_8, 0, G11_10, 0,
887 /* 12 */ G13_12, 0, G15_14, 0,
888 /* 16 */ G17_16, 0, G19_18, 0,
889 /* 20 */ G21_20, 0, G23_22, 0,
890 /* 24 */ G25_24, 0, G27_26, 0,
891 /* 28 */ G29_28, 0, G31_30, 0
892 };
893
894 if (RegNo >= std::size(GuestReg64DecoderTable))
895 return MCDisassembler::Fail;
896 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
897 return MCDisassembler::Fail;
898
899 unsigned Register = GuestReg64DecoderTable[RegNo];
900 Inst.addOperand(MCOperand::createReg(Register));
901 return MCDisassembler::Success;
902}
Success
#define Success
Definition: AArch64Disassembler.cpp:220
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:282
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:550
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:852
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:669
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:764
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:651
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:753
LLVMInitializeHexagonDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition: HexagonDisassembler.cpp:167
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:641
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:743
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:584
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: HexagonDisassembler.cpp:161
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:837
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:725
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition: HexagonDisassembler.cpp:823
adjustDuplex
static void adjustDuplex(MCInst &MI, MCContext &Context)
Definition: HexagonDisassembler.cpp:286
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition: HexagonDisassembler.cpp:539
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:809
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:600
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition: HexagonDisassembler.cpp:779
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:571
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:623
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:555
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:660
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:698
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:613
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:878
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
OpIndex
unsigned OpIndex
Definition: SPIRVModuleAnalysis.cpp:63
IntRegDecoderTable
static const unsigned IntRegDecoderTable[]
Definition: SparcDisassembler.cpp:60
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:165
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:198
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:33
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:222
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:163
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition: MCInst.h:76
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:62
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:70
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:170
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
uint8_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition: HexagonMCInstrInfo.cpp:699
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:340
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Definition: HexagonMCInstrInfo.cpp:670
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Definition: HexagonMCInstrInfo.cpp:379
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