Manoharan Ramalingam

Project 13: Serial Adder (108 Advanced RTL Projects) 1. Project Overview A serial adder processes binary numbers sequentially, performing bit-by-bit addition over multiple clock cycles. 2. Teammates Gati Goyal Ayush Jain NIKUNJ AGRAWAL 3. Low Area & Power Efficiency Consumes fewer hardware resources (gates, flip-flops) compared to parallel adders, making it ideal for low-power designs. 4. Operation Utilizes a full adder with shift registers and a clock signal to sequentially add operands and propagate carry. 5. SystemVerilog Design RTL design implemented in SystemVerilog, leveraging modular components like full adders and registers. 6. Test Bench Testbench validates the serial adder's functionality with various binary inputs and tests for correct carry propagation. 7. Simulation Results Simulation waveforms demonstrate bitwise addition and the sequential carry-forward mechanism. 8. Synthesis The synthesized design shows optimized resource usage, highlighting minimal gate count and power consumption. 9. Applications Commonly used in embedded systems, signal processing units, and low-cost IoT devices. 10. Industry Use Widely adopted by companies such as Intel Corporation , Arm , Texas Instruments Silicon Labs , and AMD for power-sensitive designs. Tags: #SerialAdder #RTLDesign #SystemVerilog #DigitalLogic #LowPowerDesign #EmbeddedSystems #VLSIDesign #FPGA #Synthesis

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4G LTE Basics: Tracking area planning . . . . #RF #RNO #RFEngineering #KnowledgeSharing #RFOptimization #RNP #LTE #4G

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Following the tradition we have every year, Linux kernel team at Qualcomm has posted upstream Linux kernel patches for Snapdragon 8 Elite based on Oryon CPU within few hours of Announcement. Link: https://lnkd.in/g9NtjRHv These patches include boot to shell support along with various features like clocks, interconnect, pin control etc; More features will be posted in coming months. Thanks to Melody Olvera and other Engineers at Qualcomm who contributes to upstream Linux kernel. Linux ARM MSM kernel community is growing with various community contributions from Mobile , Compute to Auto and IOT SOCs and platforms support. Thanks to everyone who contributes in reviewing, testing and merging these patches. https://lnkd.in/gbhCVgzp

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Watch Gen AI in action generating the RTL code for SHA-256 HW implementation ----------------------------------------------- In my course, Generative AI for Algorithm-to-Silicon Mapping, we’re diving into intersting experiments with Gen AI. In this session, I generate RTL Verilog code for part of the architecture design of SHA-256 algorithm, showcasing how today’s Gen AI tools can produce high-quality RTL code along with test stimulus, almost autonomously. This is amazing to experiment that how Gen AI optimizes circuits within the complex space of digital design —watch the code generation in action with Gen AI tools. For years, digital system design and verification have steadily evolved, with the abstraction level pushed higher and higher. But now, generative AI, large language models (LLMs), and agentic approaches are setting entirely new standards—enabling complex digital designs to be realized and verified with minimal manual coding effort. By thoughtfully architecting designs with systematic planning and phased execution, we're able to streamline intricate digital projects like never before.

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Will the Qualcomm 5G chipset announced yesterday aimed at making an affordable device at USD 99/Rs 8000 really increase migration of 2G and 4G users to 5G? As I have been saying it may bring in some churn but I seriously doubt if it will be a game changer which many are expecting it to be. While I have written a lot about it earlier in my posts( https://lnkd.in/ghCTTKwR) let me add some more points. 1. The issue with Sub Rs 8000 devices is maintaining the quality of hardware. Remember the fate of devices run on Android One and Android Go developed by Google from the software side to drive entry level phones with much fanfare, but with nothing much to write home about in terms of sales. The issue was hardware.The issue will continue as brands could cut corners to achieve a very tight price point. 2. The potential customers they would be looking at would be the existing users of <Rs 8000 4G devices or 2G device holders . 5G has no specific use case over 4G to make it the only reason for these 4G user to migrate to 5G at the same price point. 4G serves the purpose for them. Why should they shift unless they want to buy a new phone? And if they want to buy a new phone in line with the premiumisation trend, wouldn't they like to upgrade to a phone in the Rs 10000 to Rs 15000 price segment? For 2G users the price gap between a 2G feature phone is too high for them to shift to 5G. For them at best it would be the Jio Bharat smart feature phone. 4. The increase in mobile tariffs in the range of 10-27% by Jio, Airtel and Voda would be a further deterrent for 2G users to upgrade to 5G. All in all I am not very optimistic on the huge volumes that chip vendors/brands are expecting from this segment. Qualcomm India Xiaomi India

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Almost all research agencies, chipset vendors and Brands were gung ho on the demand (except me 😉 ) for entry-level smartphones below Rs 8000 till days back. The segment was enthused with the launch of an affordable 5G chipset by Qualcomm, with market leader Xiaomi announcing plans to introduce a budget 5G handset by the end of the year. It was said that other chipset vendors were also working on a solution to make the project viable. It just took one IDC report which came out a couple of days back for all to change their opinion. IDC showed the segment declining by 36% YoY. To put things in perspective, the segment accounted for 14% of total sales, down from 22% a year ago and around 40% in the pre-Covid-19 years before 2020. What are the reasons being given? 1. 'Whether it is worth it entering this segment since there are now few takers for these handsets. Brands have all moved to higher price tiers and it will be counterproductive to go back to the entry-level segment in a significant way." Some say 2. A survey conducted by Canalys showing that about half the consumers shifting from feature phones to smartphones are choosing a second-hand phone of much more premium quality from the unorganised market. A smaller section is opting for a ₹15,000-20,000 device using financing options, while only about 25% users are opting for an entry-level device. Well if the segment remains challenged at least this year despite efforts around launching affordable 5G smartphones there is no way it will take off next year. 3. Even if you manage to launch a 5G device in the entry-level segment, you have to compromise on some aspects of the experience that the consumer wants. The hardware becomes a lot better if consumers can spend ₹2,000 more, making the entry-level segment a lot more unattractive than before say some others. 4. Others say the handset makers are being pushed by their component suppliers and telecom operators to launch cheap 5G phones, so that they can leverage higher volumes to shore up their respective balance sheets. 5. And if course there are those who feel retailers are more prone to push for mid-range or premium smartphones where dealer margins are higher. I would like my readers to go back to my two posts on why 5G phones below Rs 8000 may not excite the market. Here is the link to my last post which also has an inserted link of a previous post https://lnkd.in/g4JcMhzs. Sometimes common sense works better than data it seems.😉 Qualcomm MediaTek Xiaomi India

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EEE Series :- 👇 What is the Full Form of EEE? The full form of EEE is Electrical and Electronics Engineering.Jan 1, 2024 https://lnkd.in/gKpgpZYX 👇 Electrical engineering is divided into a wide range of different fields, including computer engineering, systems engineering, power engineering, telecommunications, radio-frequency engineering, signal processing, instrumentation, photovoltaic cells, electronics, and optics and photonics. Wikipedia 👇 FAQs 1. What is optical networking? Optical networking in optical fiber technology uses light to send data via fiber cables at light speed, making it perfect for long-distance connections with low latency in the middle mile. An optical network’s fiber cables consist of a core encased in a glass cladding, which traps light inside the cable. Connections to far-off data centers or other sources of data wouldn’t be as quick as they are now without optical networks. The worldwide reach of the internet depends on optical networking to guarantee that a user in the United States can connect to a server in Japan as quickly as physics permits. Large-scale data centers also link through optical networking. However, this essay will pay more attention to the technology enabling long-haul connections. 2. What is OTN? OTN, or the Optical Transport Network is a fiber optic technology used in communications industry as standard protocol to switch and multiplex various services onto high-capacity wavelengths throughout the optical network. It is defined in a number of ITU Recommendations, including G.709 and G.798. To increase resilience, streamline operations, improve Service-Level Agreements (SLA), extend reach with Forward Error Correction (FEC), efficiently maximize wavelength fill, and ensure end-to-end service delivery, network providers today rely on OTN-enabled technology in their optical networks. 3. Which benefits does OTN offer the operator? The enormous benefits provided by fiber optic technology OTN today give operators a competitive edge. These benefits include increased performance using Forward Error Correction (FEC), streamlined operations, quicker service turn-up, maximized efficiencies, and differentiating services. Operators can thus quickly adjust to today’s erratic bandwidth needs by utilizing next-generation technologies across a programmable optical infrastructure. 4. What is wavelength-division multiplexing? With the use of several laser light wavelengths, or “colors,” wavelength-division multiplexing, or WDM, is a technique used in fiber-optic communications to multiplex a number of optical carrier signals onto a single optical fiber. 👇 Puresciencepurifies Wearescience 👇 Conversational Science Communication ( #CSC) Global Scientificlinguistics ( #GSL) Copyright : #ershadspeak

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SVA: Data change @negedge, check stable until posedge https://lnkd.in/gAWJHypv You have a signal “data” being driven in a nonblocking manner at negedge clk. Thus, @(negedge clk) data<=some_value; Data may change after the clock edge. You want to check that “data” is stable from the next posedge to the next negedge. https://lnkd.in/geKYPETW code https://lnkd.in/gH5AY3yE wave  task automatic t();   int v; bit fail, pass;   fork    begin      @(posedge clk) v=data;     wait(data != v); fail=1;    end    begin @(negedge clk) pass=1; end   join_any   am_data: assert(fail==0) p1++; else f1++;     endtask //automatic  always @(negedge clk) fork t(); join_none     property signal_change_check;   bit[2:0] v;   @(posedge clk )     (1, v= data) |=> @(negedge clk) v == data;  endproperty ap_signal_change_check: assert property(signal_change_check) p2++; else f2++;

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📣 #CCSL’s recent work “MA-DRL for Distributed Codebook Design in #RIS-aided #CFmMIMO Networks” has been accepted for publication in IEEE #TCOM. 🎯 A significant challenge in leveraging #RISs in #mmWave #CFmMIMO networks lies in the cooperative beam training across multiple access points (APs) and RISs, complicated by the passive nature of reflective elements and the complexity of #CSI acquisition. 💡 Our multi-agent #DRL framework addresses these challenges through a joint design of beamforming and reflection codebooks for distributed APs and RISs, eliminating the need for CSI and relying solely on #RSSI feedback. The master problem is decomposed into two sub-problems: one for beam codebook design at APs and another for sequential reflection codebook design at RISs. We employ transfer learning to speed up learning convergence and reduce computational complexity for training multiple RISs. Additionally, we introduce an AP and RIS selection scheme that improves overall energy efficiency and reduces backhaul overhead. 📉 Extensive simulations demonstrate that our proposed MA-DRL approach curtails number of beams significantly, thereby outperforming the widely adopted #DFT codebooks by achieving an 84% reduction in beam training overhead.🔋Our findings also suggest that increasing the number of passive RISs allows putting more APs into idle mode,  leading to substantial savings in hardware and energy costs. To be more specific, reducing 4 APs to a single AP and using 4 more RISs instead of single one can deliver almost the same performance while saving 75% energy. 👥 Asmaa Abdallah, Ph.D, Abdulkadir Çelik, M. Mansour, Ahmed Eltawil 🏛 KAUST CEMSE, KAUST (King Abdullah University of Science and Technology) 🔗 https://lnkd.in/ehTU9ajQ IEEE IEEE Communications Society IEEE Computer Society IEEE Xplore IEEE ComSoc Young Professionals IEEE Signal Processing Society ACM, Association for Computing Machinery ACM arXiv Machine Learning Research at arXiv IEEE Communications Society IEEE Access IEEE The Institute Proceedings of the IEEE Computer Engineering Computer Science Computer Networking Computer Literacy Shannon Wireless Huawei Ericsson 6G-life Wireless Networking Wireless Communications Systems Huawei Wireless 6G Flagship telecomhall International Telecommunication Union

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Difference Between I/O Mapped I/O and Memory Mapped I/O I/O Mapped I/O (Port-Mapped I/O) and Memory Mapped I/O are two different methods of interfacing input/output devices with a CPU in a computer system. I/O Mapped I/O (Port-Mapped I/O) Separate Address Space: Uses a separate, dedicated address space distinct from the memory address space. I/O devices are accessed using specific I/O instructions (like IN and OUT in x86 assembly). Limited Address Space: Typically has a smaller address space compared to memory mapped I/O. Example: x86 architecture provides 64KB of I/O address space. Access Methods: Special instructions are used for I/O operations (e.g., IN, OUT in x86). Different from the instructions used to access memory. Speed and Complexity: Can be slower due to the need for special instructions. Adds complexity to the instruction set and programming model. Example Architectures: Common in older microprocessors and microcontrollers like the Intel 8085 and 8051. Memory Mapped I/O Unified Address Space: Uses the same address space for both memory and I/O devices. I/O devices are treated as if they are memory locations. Larger Address Space: Can utilize the entire address space available to the processor, which is typically larger than the dedicated I/O space. Example: 32-bit address space allows for 4GB of addressable space, shared between memory and I/O. Access Methods: Standard memory instructions (like LOAD and STORE) are used to access I/O devices. No need for special I/O instructions. Speed and Simplicity: Can be faster due to the use of regular memory access instructions. Simplifies the instruction set and programming model. Example Architectures: Common in modern microprocessors and microcontrollers like ARM, MIPS, and RISC-V. Applications and Considerations I/O Mapped I/O Applications: Typically used in systems where a small number of I/O devices are present. Common in older or simpler microcontroller designs. Memory Mapped I/O Applications: Used in systems requiring a large number of I/O devices. Common in modern microprocessors and embedded systems where I/O devices need to be accessed frequently and quickly. Considerations for Choosing Between Them: Speed Requirements: Memory mapped I/O can be faster due to the use of regular memory access instructions. Complexity: I/O mapped I/O requires special instructions, which can add complexity to the instruction set and programming. #Capacitor #Electronics #PassiveComponents #Capacitance #ElectricalEngineering #Resistor #PassiveComponents #Resistance #Inductor #Inductance #ElectronicsDesign #CircuitDesign #PCBDesign #HardwareDesign #PCB #PCBLayout #CircuitLayout #ElectronicsLayout #ElectricalEngineering #EmbeddedSystems #TechDesign #Engineering

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For the first time, I am truly content with the students of India. I feel I missed learning VLSI, RISC-V, and Embedded Systems in a structured way where all three are connected using the VSDSquadron Mini boards. As part of the VSDSquadron Mini internship program, participants from various backgrounds, institutes, startups, and corporations can connect specifications to product development. They can utilize their existing knowledge from their engineering institutes or other training programs effectively. Having an educational RISC-V board in hand is a boon for learning VLSI, RISC-V, and Embedded Systems. It sparks the right interest among students. It’s proven that not all engineering students are solely interested in VLSI; some are passionate about RISC-V, some about Embedded Systems, and some about a combination of VLSI and Embedded Systems. Registration for the next VSD-VLSI-RISC-V Embedded internship closes in 2 days. https://lnkd.in/gx7Et3s4 Encourage your college students to enroll and get a board in hand for exploring all aspects of VLSI, RISC-V, and Embedded Systems design at the most affordable cost. RISC-V International VLSI System Design

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#Intel is another example of a seemingly infallible incumbent in trouble due to complacency (after my last post about #Samsung in India last week. Link in comments) #Intel stock price:  2020> ~$68; 2024> ~$23. #Nvidia stock price: 2020>~$13; 2024> ~$125 On top, #Qualcomm is potentially making a bid to acquire Intel. The shift to #AI has led to Intel’s chips sitting on shelves. (strange how a company whose founder coined the rule of thumb formula for the pace of growth in computing power of chips could not see this coming) Its first blunder was to give up the chance to build a chip for the #iPhone. Intel actually started losing its mojo since 2020 itself. And it has shown a fair bit of complacency (& suffered some bad luck) 🔹 Allowed Asian rivals such as TSMC & Samsung to start making faster performing chips. 🔹 Failed to understand how the #AI trend would pan out. 🔹Talks to consolidate and buy out a large chipmaker (#GlobalFoundries) for $ 30bn fizzled out. 🔹$ 5bn deal to acquire Tower Semiconductor failed to get Chinese regulatory approval. This has now left Intel muddling through its struggles. 🔹Laid thousands of employees in 2022 🔹Slashed dividend payouts and on its way to completely scrap dividends. 🔹Plans to lay off another 15k people by 2025 Even if the above helps its margins, the fundamental problem of core chip business recovering will not resolve quickly. There are some positives, like a deal with #Amazon to power #AWS with intel chips and another one with the US govt for a defence & intelligence project Tech changes used to kill the small fish earlier. In today’s world, it’s started swallowing even the stalwarts. A complete shakeup of the world order. #technology #change #competition #brands #smartphones #marketshare #mintwealth #business #LIGHTPILLAR.

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I'm thrilled to share that my review paper on optimization techniques in Network-on-Chip (NoC) architecture has been published in IEEE Xplore! 🎉 This paper reviews recent advances in network-on-chip (NoC) optimization techniques, focusing on addressing challenges related to fault tolerance and congestion management in multicore systems. It explores innovative strategies that enhance the resilience and efficiency of NoC systems, including fault-tolerant routing algorithms, wireless NoC congestion control mechanisms, dynamic voltage scaling techniques, and design methodologies for heterogeneous architectures. The effectiveness of these strategies is evaluated in terms of network latency, energy efficiency, and system reliability. This comprehensive overview provides valuable insights into the current state of the art and future directions in NoC optimization, serving as a resource for researchers and practitioners in the field. Check out the full paper here. https://lnkd.in/dj7UEDBn #NoC #NetworkOnChip #Optimization #FaultTolerance #CongestionManagement #MulticoreSystems #IEEE #Research

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Looking forward to speaking (virtually) at IEEE AP-S IITK/UP CHAPTER on "𝑨𝒏𝒕𝒆𝒏𝒏𝒂 𝑴𝒐𝒅𝒆𝒍𝒊𝒏𝒈 𝒂𝒏𝒅 𝑺𝒊𝒎𝒖𝒍𝒂𝒕𝒊𝒐𝒏 𝑻𝒆𝒄𝒉𝒏𝒊𝒒𝒖𝒆𝒔" Date: 9 September 2024 Time: 8 AM EST/ 5:30PM IST Join the meeting at: https://lnkd.in/gxuA7XvW 𝐀𝐛𝐬𝐭𝐫𝐚𝐜𝐭 𝐨𝐟 𝐭𝐡𝐞 𝐭𝐚𝐥𝐤:  Now-a-days antennas have become an integral and important part of almost any wireless communication system. In the field of antenna engineering, theoretical analysis is of paramount importance in understanding the basics of the antenna radiation characteristics. While the basic concept of antennas is well known, closed form, exact analytical solutions to many antenna problems are not practical and impossible in many cases. Advances in electromagnetic (EM) simulations have significantly impacted the antenna design process by providing exact solutions by solving Maxwell’s equations using numerical methods. It is a common practice now in academia and industry to use various commercially available EM simulation tools for antenna design process. In this talk, we will introduce basics of antenna modelling and simulation process with pros and cons of various numerical methods, such as Method of Moments (MoM), Multilevel Fast Multipole Method (MLFMM), Finite Element Method (FEM), Finite Difference Time Domain (FDTD), Physical Optics (PO), Ray Lunching Geometrical Optics (RL-GO), and Uniform Theory of Diffraction (UTD). We will then discuss modelling and simulation of various antenna types, starting from simple configurations such as dipoles and loops and eventually leading to more complicated and practical designs such as microstrip patches and high-gain reflector antennas. Thanks to RISHI MISHRA, Chair, IEEE AP-S IITK/UP CHAPTER and Prachi Choubey, Vice Chair, IEEE AP-S IITK/UP CHAPTER for organizing the talk. #IEEE #IEEEAPS #antennas #propagation #AltairFeko #emsimulationsoftware

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D I G I T A L _ P O W E R _ E L E C T R O N I C S DIGITAL DSP CONTROLLED SMPS (Switch Mode Power Supplies) I am writing this from my experience of designing high power DSP Controlled SMPS for High End Application The demand for Real Time DSP controlled Power Supplies Is growing every day , for high end applications From Radar Transmitters and Receivers or Very Long Range RF Modems The Switch Mode Power Supply must be able to change its mode of operation in Real Time in a very short time of a few Microseconds ill maximum of a 1-2 Milliseconds To be able of compensating for Switching Load changing its profile from No load to Maximum load in different frequencies and PRF's Analog Power Supply can't do it , and if you are using an Analog Controlled SMPS you wil have to compromise the performance of your system (Radar , range issues , specially in small sized targets) But when you change to Real Time DSP Digital control You can control anything by SW so updates are SW only and no need to Recall the Energy Units for updated its HW You can achieve features and performance you did not think can be made The first design is very hard thinking and very demanding. Because in Old Technology of Analog Controlled SMPS You just need to adjust it's feedback loop , so some good PCB layout And good grounding , and all the hard work been done by its limited performance controller, and you are chasing the problems when you have the complete system working and now you are changing this capacitor this resistor this wire In DSP controlled power supplies also you have to do a good PCB layout But all the rest are SW controlled In my first design ( and there were many of such a design) I have solved an EMI issue with SW update , solved a switching load issue in SW update , reduce noise for sensitive receiver in sw update. Now you have a very High Performance DSP's than can handle such a complex mission and you can always add an FPGA for extreme performance issue , And i am talking about High Power SMPS DC-DC , AC-DC , DC-AC , AC-AC mainly for High End Application because its a very hard work if its your first Digital Power Design , but after that you can't thing of getting back to a pure Analog Design just because it easier to design. JUST THINK ABOUT THAT While its working you can get Real Time Information using a communication Chanel to/from the SMPS and know what is happening in your Load in your system 100% of its working time and debug issues you didn't know exists and now you can handle it ITS a BIG CHANGE IN THINKING because a lot of SMPS designers Are Analog Designers and have some fear from the Digital World And will tell you "there is no need for that" its too complex but when you solve to the first big issue of a very complex and expensive system only with SW change , then some of them are open to understand the new technology. its good only for designers open minded , new way of thinking (Motor control is Digital for many years)