This paper presents a detailed study of the impact of SEUs in the configuration RAM (CRAM) of SRAM based FPGAs. Since modern SRAM based FPGAs support scrubbing of the CRAM, a new, intermittent CRAM SEU fault model is presented. This fault model is implemented both in simulation and on an emulation platform for an embedded processor design. The criticality of CRAM bits is studied based on their logic function, the duration of the SEU, and the workload running on the processor. These results provide new insight into the overall effectiveness of CRAM scrubbing mechanisms.