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2020 – today
- 2024
[j38]Jakub Husa
, Lukás Sekanina:
Semantic mutation operator for a fast and efficient design of bent Boolean functions. Genet. Program. Evolvable Mach. 25(1): 3 (2024)- [c156]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE 2024: 1-6 - [c155]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS 2024: 1-6 - [c154]Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. IJCNN 2024: 1-8 - [i13]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR abs/2404.05368 (2024) - [i12]Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR abs/2404.08002 (2024) - 2023
- [j37]Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina:
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 212-224 (2023) - [c153]Martin Hurta, Jana Schwarzerova, Thomas Nägele, Wolfram Weckwerth, Valentine Provazník, Lukás Sekanina:
Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. BIBM 2023: 3782-3787 - [c152]Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina:
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE 2023: 1-2 - [c151]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS 2023: 45-50 - [c150]Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina:
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS 2023: 155-160 - [c149]Tadeas Juza, Lukás Sekanina:
GPAM: Genetic Programming with Associative Memory. EuroGP 2023: 68-83 - [c148]Marek Sedlacek, Lukás Sekanina:
Evolution of Editing Scripts From Examples. GECCO Companion 2023: 803-806 - [c147]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD 2023: 1-9 - [i11]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR abs/2303.04734 (2023) - 2022
- [j36]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. 23(3): 351-374 (2022) - [j35]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69: 100986 (2022) - [c146]Martin Hurta, Michaela Drahosova, Lukás Sekanina, Stephen L. Smith, Jane E. Alty:
Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. EuroGP 2022: 85-101 - [c145]Matej Valek, Lukás Sekanina:
Evolutionary Approximation in Non-Local Means Image Filters. SMC 2022: 2762-2769 - 2021
- [j34]Lukás Sekanina:
Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access 9: 151337-151362 (2021) - [j33]Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun:
Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. 124: 54-55 (2021) - [c144]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP 2021: 82-97 - [e7]Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek:
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3595-6 [contents] - [i10]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR abs/2101.11883 (2021) - [i9]Lukás Sekanina:
Evolutionary Algorithms in Approximate Computing: A Survey. CoRR abs/2108.07000 (2021) - 2020
- [j32]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95: 106466 (2020) - [j31]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 406-418 (2020) - [j30]Ting Hu, Miguel Nicolau, Lukás Sekanina:
Special issue on highlights of genetic programming 2019 events. Genet. Program. Evolvable Mach. 21(3): 283-285 (2020) - [j29]Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han:
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 317-328 (2020) - [c143]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS 2020: 243-247 - [c142]David Grochol, Lukás Sekanina:
Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. CEC 2020: 1-8 - [c141]Jakub Husa, Lukás Sekanina:
Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. CEC 2020: 1-8 - [c140]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020: 1-6 - [c139]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE 2020: 294-297 - [c138]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [i8]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR abs/2002.09481 (2020) - [i7]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR abs/2003.02491 (2020) - [i6]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR abs/2004.10483 (2020) - [i5]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR abs/2004.10502 (2020)
2010 – 2019
- 2019
- [j28]Michaela Drahosova, Lukás Sekanina, Michal Wiglasz:
Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. Evol. Comput. 27(3): 497-523 (2019) - [j27]Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda:
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2734-2744 (2019) - [c137]Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC 2019: 123 - [c136]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Circuit Approximation Method Driven by Data Distribution. DATE 2019: 96-101 - [c135]Petr Rek, Lukás Sekanina:
TypeCNN: CNN Development Framework With Flexible Data Types. DATE 2019: 292-295 - [c134]Ondrej Koncal, Lukás Sekanina:
Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. EuroGP 2019: 98-113 - [c133]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique:
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD 2019: 1-8 - [c132]Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - [c131]Filip Badan, Lukás Sekanina:
Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. TPNC 2019: 109-121 - [p8]Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek:
Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits 2019: 175-203 - [e6]Lukás Sekanina, Ting Hu, Nuno Lourenço, Hendrik Richter, Pablo García-Sánchez:
Genetic Programming - 22nd European Conference, EuroGP 2019, Held as Part of EvoStar 2019, Leipzig, Germany, April 24-26, 2019, Proceedings. Lecture Notes in Computer Science 11451, Springer 2019, ISBN 978-3-030-16669-4 [contents] - [i4]Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR abs/1902.10807 (2019) - [i3]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Circuit Approximation Method Driven by Data Distribution. CoRR abs/1903.04188 (2019) - [i2]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique:
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR abs/1907.07229 (2019) - [i1]Filip Badan, Lukás Sekanina:
Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. CoRR abs/1910.06854 (2019) - 2018
- [j26]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han:
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2572-2576 (2018) - [c130]David Grochol, Lukás Sekanina:
Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. AHS 2018: 257-263 - [c129]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS 2018: 264-271 - [c128]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
ADAC: Automated Design of Approximate Circuits. CAV (1) 2018: 612-620 - [c127]David Grochol, Lukás Sekanina:
Multi-objective Evolution of Ultra-Fast General-Purpose Hash Functions. EuroGP 2018: 187-202 - [c126]Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas:
Evolving boolean functions for fast and efficient randomness testing. GECCO 2018: 1302-1309 - [c125]Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek:
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS 2018: 377-380 - [c124]Michal Wiglasz, Lukás Sekanina:
Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. SSCI 2018: 1313-1320 - [c123]Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo:
Special session: How approximate computing impacts verification, test and reliability. VTS 2018: 1 - [e5]Mauro Castelli, Lukás Sekanina, Mengjie Zhang, Stefano Cagnoni, Pablo García-Sánchez:
Genetic Programming - 21st European Conference, EuroGP 2018, Parma, Italy, April 4-6, 2018, Proceedings. Lecture Notes in Computer Science 10781, Springer 2018, ISBN 978-3-319-77552-4 [contents] - 2017
- [j25]Roland Dobai, Jan Korenek, Lukás Sekanina:
Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. 56: 173-181 (2017) - [c122]David Grochol, Lukás Sekanina:
Multi-objective evolution of hash functions for high speed networks. CEC 2017: 1533-1540 - [c121]Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina:
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE 2017: 258-261 - [c120]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Towards low power approximate DCT architecture for HEVC standard. DATE 2017: 1576-1581 - [c119]Filip Kesner, Lukás Sekanina, Milan Brazdil:
Modular framework for detection of inter-ictal spikes in iEEG. EMBC 2017: 418-421 - [c118]Milos Minarik, Lukás Sekanina:
On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. EuroGP 2017: 343-358 - [c117]Michal Wiglasz, Lukás Sekanina:
Evolutionary approximation of gradient orientation module in HOG-based human detection system. GlobalSIP 2017: 1300-1304 - [c116]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD 2017: 416-423 - [c115]Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek:
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI 2017: 627-632 - [e4]James McDermott, Mauro Castelli, Lukás Sekanina, Evert Haasdijk, Pablo García-Sánchez:
Genetic Programming - 20th European Conference, EuroGP 2017, Amsterdam, The Netherlands, April 19-21, 2017, Proceedings. Lecture Notes in Computer Science 10196, 2017, ISBN 978-3-319-55695-6 [contents] - 2016
- [j24]David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek, Vlastimil Kosar:
Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. 38: 933-941 (2016) - [j23]Zdenek Vasícek, Lukás Sekanina:
Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. 17(2): 169-192 (2016) - [j22]Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina:
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. 65(4): 1871-1883 (2016) - [c114]Lukás Sekanina:
Introduction to approximate computing: Embedded tutorial. DDECS 2016: 90-95 - [c113]Petr Dvoracek, Lukás Sekanina:
Evolutionary Approximation of Edge Detection Circuits. EuroGP 2016: 19-34 - [c112]Zdenek Vasícek, Lukás Sekanina:
Search-based synthesis of approximate circuits implemented into FPGAs. FPL 2016: 1-4 - [c111]David Grochol, Lukás Sekanina:
Evolutionary Design of Fast High-quality Hash Functions for Network Applications. GECCO 2016: 901-908 - [c110]Lukás Sekanina, Vlastimil Kapusta:
Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. GECCO (Companion) 2016: 1411-1418 - [c109]Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy:
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD 2016: 81 - [c108]Roland Dobai, Jan Korenek, Lukás Sekanina:
Adaptive development of hash functions in FPGA-based network routers. SSCI 2016: 1-8 - [c107]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI 2016: 1-8 - [c106]Filip Vaverka, Radek Hrbacek, Lukás Sekanina:
Evolving component library for approximate high level synthesis. SSCI 2016: 1-8 - 2015
- [j21]Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. 19(3): 432-444 (2015) - [j20]Roland Dobai, Lukás Sekanina:
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3): 20:1-20:24 (2015) - [c105]Michaela Sikulová, Jiri Hulva, Lukás Sekanina:
Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. EuroGP 2015: 113-125 - [c104]Zdenek Vasícek, Lukás Sekanina:
Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP 2015: 217-229 - [c103]David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek:
A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. EvoApplications 2015: 67-78 - [c102]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) 2015: 795-801 - [c101]Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) 2015: 1505-1506 - [c100]Jiri Petrlik, Lukás Sekanina:
Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. ITSC 2015: 2231-2236 - [p7]Lukás Sekanina, Zdenek Vasícek:
Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware 2015: 175-189 - [p6]Lukás Sekanina:
Principles and Applications of Polymorphic Circuits. Evolvable Hardware 2015: 209-224 - 2014
- [c99]Lukás Sekanina, Zdenek Vasícek:
On Evolutionary Approximation of Logic Circuits. Computing with New Resources 2014: 367-378 - [c98]Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek:
Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation 2014: 2901-2908 - [c97]Jiri Petrlik, Otto Fucík, Lukás Sekanina:
Multiobjective selection of input sensors for travel times forecasting using support vector regression. CIVTS 2014: 14-21 - [c96]Zdenek Vasícek, Lukás Sekanina:
Evolutionary design of approximate multipliers under different error metrics. DDECS 2014: 135-140 - [c95]Milos Minarik, Lukás Sekanina:
Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. EuroGP 2014: 112-123 - [c94]Radek Hrbacek, Lukás Sekanina:
Towards highly optimized cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. GECCO 2014: 1015-1022 - [c93]Roland Dobai, Kyrre Glette, Jim Tørresen, Lukás Sekanina:
Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. ICES 2014: 85-92 - [c92]Zdenek Vasícek, Lukás Sekanina:
How to evolve complex combinational circuits from scratch? ICES 2014: 133-140 - [c91]Michaela Sikulová, Gergely Komjathy, Lukás Sekanina:
Towards compositional coevolution in evolutionary circuit design. ICES 2014: 157-164 - [c90]Jiri Petrlik, Otto Fucík, Lukás Sekanina:
Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. PPSN 2014: 802-811 - 2013
- [j19]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek:
Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. 42(1): 7-14 (2013) - [j18]Pavol Korcek, Lukás Sekanina, Otto Fucík:
Advanced Approach to Calibration of Traffic Microsimulation Models Using Travel Times. J. Cell. Autom. 8(5-6): 457-467 (2013) - [j17]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina:
Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. 17(11): 2163-2180 (2013) - [j16]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [j15]Lukás Sekanina:
Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. Ubiquity 2013(February): 2:1-2:7 (2013) - [c89]Roland Dobai, Lukás Sekanina:
Image filter evolution on the Xilinx Zynq Platform. AHS 2013: 164-171 - [c88]Jiri Petrlik, Lukás Sekanina:
Multiobjective evolution of approximate multiple constant multipliers. DDECS 2013: 116-119 - [c87]Lukás Sekanina, Zdenek Vasícek:
Approximate circuit design by means of evolvable hardware. ICES 2013: 21-28 - [c86]Milos Minarik, Lukás Sekanina:
Concurrent evolution of hardware and software for application-specific microprogrammed systems. ICES 2013: 43-50 - [c85]Roland Dobai, Lukás Sekanina:
Towards evolvable systems based on the Xilinx Zynq platform. ICES 2013: 89-95 - [e3]Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 [contents] - 2012
- [j14]Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná:
pecial CAI Section Devoted to MEMICS '11: Preface. Comput. Informatics 31(3): 481- (2012) - [j13]Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocess. Microsystems 36(5): 427-438 (2012) - [j12]Ludek Zaloudek, Lukás Sekanina:
Cellular automata-based systems with fault-tolerance. Nat. Comput. 11(4): 673-685 (2012) - [c84]Pavol Korcek, Lukás Sekanina, Otto Fucík:
Calibration of Traffic Simulation Models Using Vehicle Travel Times. ACRI 2012: 807-816 - [c83]Lukás Sekanina, Vojtech Salajka, Zdenek Vasícek:
Two-step evolution of polymorphic circuits for image multi-filtering. IEEE Congress on Evolutionary Computation 2012: 1-8 - [c82]Zdenek Vasícek, Lukás Sekanina:
On area minimization of complex combinational circuits using cartesian genetic programming. IEEE Congress on Evolutionary Computation 2012: 1-8 - [c81]Lukás Sekanina, Zdenek Vasícek:
A SAT-based fitness function for evolutionary optimization of polymorphic circuits. DATE 2012: 715-720 - [c80]Lukás Sekanina, Vojtech Salajka:
Towards new applications of multi-function logic: Image multi-filtering. DATE 2012: 824-827 - [c79]Michaela Sikulová, Lukás Sekanina:
Coevolution in Cartesian Genetic Programming. EuroGP 2012: 182-193 - [c78]Tobiás Smolka, Petr Svenda, Lukás Sekanina, Vashek Matyás:
Evolutionary Design of Message Efficient Secrecy Amplification Protocols. EuroGP 2012: 194-205 - [c77]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - [c76]Pavol Korcek, Lukás Sekanina, Otto Fucík:
Evolutionary approach to calibration of cellular automaton based traffic simulation models. ITSC 2012: 122-129 - [c75]Jiri Petrlik, Pavol Korcek, Otto Fucík, Marian Beszédes, Lukás Sekanina:
Estimation of missing values in traffic density maps. ITSC 2012: 632-637 - [c74]Michaela Sikulová, Lukás Sekanina:
Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. PPSN (1) 2012: 163-172 - [p5]Lukás Sekanina:
Evolvable Hardware. Handbook of Natural Computing 2012: 1657-1705 - [e2]Zdenek Kotásek, Jan Bouda, Ivana Cerná, Lukás Sekanina, Tomás Vojnar, David Antos:
Mathematical and Engineering Methods in Computer Science - 7th International Doctoral Workshop, MEMICS 2011, Lednice, Czech Republic, October 14-16, 2011, Revised Selected Papers. Lecture Notes in Computer Science 7119, Springer 2012, ISBN 978-3-642-25928-9 [contents] - 2011
- [j11]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP J. Adv. Signal Process. 2011 (2011) - [j10]Zdenek Vasícek, Lukás Sekanina:
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evolvable Mach. 12(3): 305-327 (2011) - [j9]Lukás Sekanina, Tomas Komenda:
Global Control in Polymorphic Cellular Automata. J. Cell. Autom. 6(4-5): 301-321 (2011) - [j8]Zbysek Gajda, Lukás Sekanina:
On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. J. Multiple Valued Log. Soft Comput. 17(5-6): 607-631 (2011) - [c73]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c72]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Kyrre Glette:
Evolutionary design of efficient and robust switching image filters. AHS 2011: 192-199 - [c71]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c70]Zdenek Vasícek, Lukás Sekanina:
A global postsynthesis optimization method for combinational circuits. DATE 2011: 1525-1528 - [c69]Richard Ruzicka, Václav Simek, Lukás Sekanina:
Behavior of CMOS polymorphic circuits in high temperature environment. DDECS 2011: 447-452 - [c68]Lukás Sekanina:
Evolution of digital circuits. GECCO (Companion) 2011: 1343-1360 - [c67]Pavol Korcek, Lukás Sekanina, Otto Fucík:
A scalable cellular automata based microscopic traffic simulation. Intelligent Vehicles Symposium 2011: 13-18 - [c66]Milos Minarik, Lukás Sekanina:
Evolution of Iterative Formulas Using Cartesian Genetic Programming. KES (1) 2011: 11-20 - [c65]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169 - [c64]Ludek Zaloudek, Lukás Sekanina:
Increasing Fault-Tolerance in Cellular Automata-Based Systems. UC 2011: 234-245 - [p4]Lukás Sekanina, James Alfred Walker, Paul Kaufmann, Marco Platzner:
Evolution of Electronic Circuits. Cartesian Genetic Programming 2011: 125-179 - [p3]Lukás Sekanina, Simon L. Harding, Wolfgang Banzhaf, Taras Kowaliw:
Image Processing and CGP. Cartesian Genetic Programming 2011: 181-215 - [p2]Lukás Sekanina, Zdenek Vasícek:
CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming 2011: 217-230 - 2010
- [c63]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. AHS 2010: 171-178 - [c62]Zdenek Vasícek, Lukás Sekanina, Michal Bidlo:
A method for design of impulse bursts noise filters optimized for FPGA implementations. DATE 2010: 1731-1736 - [c61]Lukás Sekanina:
Evolutionary circuit design: Tutorial. DDECS 2010: 5 - [c60]Václav Simek, Richard Ruzicka, Lukás Sekanina:
On analysis of fabricated polymorphic circuits. DDECS 2010: 281-284 - [c59]Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina:
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS 2010: 346-351 - [c58]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. DSD 2010: 96-103 - [c57]Zbysek Gajda, Lukás Sekanina:
When does Cartesian genetic programming minimize the phenotype size implicitly? GECCO 2010: 983-984 - [c56]Zbysek Gajda, Lukás Sekanina:
An Efficient Selection Strategy for Digital Circuit Evolution. ICES 2010: 13-24 - [c55]Jirí Simácek, Lukás Sekanina, Lukás Starecek:
Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. ICES 2010: 214-225
2000 – 2009
- 2009
- [c54]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Jim Tørresen, Kyrre Glette, Marcus Furuholmen:
Evolution of Impulse Bursts Noise Filters. AHS 2009: 27-34 - [c53]Lukás Sekanina, Richard Ruzicka, Zbysek Gajda:
Polymorphic FIR Filters with Backup Mode Enabling Power Savings. AHS 2009: 43-50 - [c52]Zbysek Gajda, Lukás Sekanina:
Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. IEEE Congress on Evolutionary Computation 2009: 1599-1604 - [c51]Lukás Sekanina:
Evolvable Hardware: From Applications to Implications for the Theory of Computation. UC 2009: 24-36 - [c50]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik:
REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH 2009: 39-46 - [c49]Petr Svenda, Lukás Sekanina, Václav Matyás:
Evolutionary design of secrecy amplification protocols for wireless sensor networks. WISEC 2009: 225-236 - 2008
- [j7]Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda:
Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. 4(2): 125-142 (2008) - [j6]Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek:
Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13(3): 54:1-54:21 (2008) - [c48]Zdenek Vasícek, Ladislav Capka, Lukás Sekanina:
Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. AHS 2008: 3-10 - [c47]Zdenek Vasícek, Lukás Sekanina:
Novel Hardware Implementation of Adaptive Median Filters. DDECS 2008: 110-115 - [c46]Lukás Starecek, Lukás Sekanina, Zdenek Kotásek:
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268 - [c45]Zdenek Vasícek, Lukás Sekanina:
Hardware Accelerators for Cartesian Genetic Programming. EuroGP 2008: 230-241 - [c44]Lukás Sekanina, Petr Mikusek:
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. EvoWorkshops 2008: 144-153 - [c43]Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola:
On Evolutionary Synthesis of Linear Transforms in FPGA. ICES 2008: 141-152 - [c42]Ludek Zaloudek, Lukás Sekanina:
Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator. ICES 2008: 320-331 - [c41]Richard Ruzicka, Lukás Sekanina, Roman Prokop:
Physical Demonstration of Polymorphic Self-Checking Circuits. IOLTS 2008: 31-36 - [c40]Mircea Gh. Negoita, Lukás Sekanina, Adrian Stoica:
Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. KES (3) 2008: 310-318 - [e1]Gregory Hornby, Lukás Sekanina, Pauline C. Haddow:
Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings. Lecture Notes in Computer Science 5216, Springer 2008, ISBN 978-3-540-85856-0 [contents] - 2007
- [j5]Lukás Sekanina:
Evolutionary functional recovery in virtual reconfigurable circuits. ACM J. Emerg. Technol. Comput. Syst. 3(2): 8 (2007) - [j4]Lukás Sekanina:
Evolved Computing Devices and the Implementation Problem. Minds Mach. 17(3): 311-329 (2007) - [c39]Zdenek Vasícek, Lukás Sekanina:
Evaluation of a New Platform For Image Filter Evolution. AHS 2007: 577-586 - [c38]Lukás Sekanina, Tomas Hruska, Tomás Vojnar, Dusan Kolár, Jan Cernocký:
On Some Directions in Security-Oriented Research. BLISS 2007: 141-144 - [c37]Lukás Sekanina:
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. DDECS 2007: 243-246 - [c36]Karel Slaný, Lukás Sekanina:
Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. EuroGP 2007: 311-320 - [c35]Zdenek Vasícek, Lukás Sekanina:
An area-efficient alternative to adaptive median filtering in FPGAs. FPL 2007: 216-221 - [c34]Zbysek Gajda, Lukás Sekanina:
Reducing the number of transistors in digital circuits using gate-level evolutionary design. GECCO 2007: 245-252 - [c33]Lukás Sekanina:
Evolvable hardware. GECCO (Companion) 2007: 3627-3644 - [c32]Lukás Sekanina:
Evolution of Polymorphic Self-checking Circuits. ICES 2007: 186-197 - [c31]Zdenek Vasícek, Lukás Sekanina:
Reducing the Area on a Chip Using a Bank of Evolved Filters. ICES 2007: 222-232 - 2006
- [c30]Lukás Sekanina:
Evolutionary Design of Digital Circuits: Where Are Current Limits? AHS 2006: 171-178 - [c29]Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek:
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193 - [c28]Lukás Sekanina, Tomás Martínek, Zbysek Gajda:
Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. IEEE Congress on Evolutionary Computation 2006: 2771-2778 - [c27]Lukás Sekanina:
On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits. Conf. Computing Frontiers 2006: 221-228 - [c26]Lukás Sekanina, Lukás Starecek, Zdenek Kotásek:
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86 - [c25]Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289 - [c24]Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514 - [c23]Lukás Sekanina, Zdenek Vasícek:
On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. EvoWorkshops 2006: 344-355 - [c22]Richard Ruzicka, Lukás Sekanina:
Evolutionary circuit design in REPOMO - reconfigurable polymorphic module. Computational Intelligence 2006: 239-244 - [p1]Ricardo Salem Zebulum, Didier Keymeulen, Rajeshuni Ramesham, Lukás Sekanina, James Mao, Nikhil Kumar, Adrian Stoica:
Characterization and Synthesis of Circuits at Extreme Low Temperatures. Evolvable Hardware 2006: 161-172 - 2005
- [j3]Lukás Sekanina, Michal Bidlo:
Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genet. Program. Evolvable Mach. 6(3): 319-347 (2005) - [j2]Lukás Sekanina, Tughrul Arslan:
Evolvable Components-From Theory to Hardware Implementations. Genet. Program. Evolvable Mach. 6(4): 461-462 (2005) - [c21]Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58 - [c20]Lukás Sekanina, Ricardo Salem Zebulum:
Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level. Evolvable Hardware 2005: 73-78 - [c19]Lukás Sekanina:
Evolutionary Design of Gate-Level Polymorphic Digital Circuits. EvoWorkshops 2005: 185-194 - [c18]Michal Bidlo, Lukás Sekanina:
Providing information from the environment for growing electronic circuits through polymorphic gates. GECCO Workshops 2005: 242-248 - [c17]Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Lukás Sekanina, Rajeshuni Ramesham, Xin Guo:
Evolvable Hardware System at Extreme Low Temperatures. ICES 2005: 37-45 - [c16]Jan Korenek, Lukás Sekanina:
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. ICES 2005: 46-55 - [c15]Tomás Martínek, Lukás Sekanina:
An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. ICES 2005: 76-85 - [c14]Lukás Sekanina, Ricardo Salem Zebulum:
Intrinsic Evolution of Controllable Oscillators in FPTA-2. ICES 2005: 98-107 - 2004
- [b1]Lukás Sekanina:
Evolvable components - from theory to hardware implementations. Natural computing series, Springer 2004, ISBN 978-3-540-40377-7, pp. I-XVI, 1-194 - [j1]Lukás Sekanina, Stepan Friedl:
An Evolvable Combinational Unit for FPGAs. Comput. Artif. Intell. 23(5): 461-486 (2004) - [c13]Lukás Sekanina, Vladimír Drábek:
Theory and Applications of Evolvable Embedded Systems. ECBS 2004: 186-194 - [c12]Lukás Sekanina, Stepan Friedl:
On Routine Implementation of Virtual Evolvable Devices Using COMBO6. Evolvable Hardware 2004: 63-70 - [c11]Lukás Sekanina:
Evolutionary Design Space Exploration for Median Circuits. EvoWorkshops 2004: 240-249 - [c10]Jim Tørresen, Jorgen W. Bakke, Lukás Sekanina:
Recognizing Speed Limit Sign Numbers by Evolvable Hardware. PPSN 2004: 682-691 - [c9]Lukás Sekanina:
Evolving Constructors for Infinitely Growing Sorting Networks and Medians. SOFSEM 2004: 314-323 - 2003
- [c8]Lukás Sekanina, Richard Ruzicka:
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. Evolvable Hardware 2003: 135-144 - [c7]Lukás Sekanina:
Towards Evolvable IP Cores for FPGAs. Evolvable Hardware 2003: 145-154 - [c6]Lukás Sekanina:
From Implementations to a General Concept of Evolvable Machines. EuroGP 2003: 424-433 - [c5]Lukás Sekanina:
Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. ICES 2003: 186-197 - 2002
- [c4]Lukás Sekanina, Jim Tørresen:
Detection of Norwegian Speed Limit Signs. ESM 2002: 337-340 - [c3]Lukás Sekanina:
Image Filter Design with Evolvable Hardware. EvoWorkshops 2002: 255-266 - 2000
- [c2]Lukás Sekanina, Azeddien M. Sllame:
Toward Uniform Approach to Design of Evolvable Hardware Based Systems. FPL 2000: 814-817 - [c1]Lukás Sekanina, Vladimír Drábek:
Relation between Fault Tolerance and Reconfiguration in Cellular Systems. IOLTW 2000: 25-30
Coauthor Index
[c156] [c155] [i13] [j37] [c147] [i11] [j35] [j32] [j31] [j29] [c143] [c140] [c139] [c138] [i8] [i7] [i6] [i5] [c137] [c136] [c133] [p8] [i4] [i3] [i2] [j26] [c129] [c128] [c126] [c125] [c123] [c121] [c120] [c116] [c115] [j23] [c112] [c109] [c107] [j21] [c104] [c102] [c101] [p7] [c99] [c98] [c96] [c92] [j19] [j17] [c87] [c83] [c82] [c81] [j10] [c72] [c70] [p2] [c62] [c59] [c54] [c50] [c48] [c47] [c45] [c43] [c39] [c35] [c31] [c23]
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