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2020 – today
- 2022
[j80]Arda Uran
, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Emilie C. M. Revol, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher:
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. IEEE J. Solid State Circuits 57(9): 2752-2763 (2022)- 2021
- [j79]Firat Celik, Ayca Akkaya, Yusuf Leblebici:
A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI. Microelectron. J. 108: 104967 (2021) - [j78]Ayca Akkaya, Firat Celik, Yusuf Leblebici:
An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2766-2774 (2021) - [j77]Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1132-1140 (2021) - [c211]Arda Uran, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher:
A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS. CICC 2021: 1-2 - 2020
- [j76]Bilal Demir, Selman Ergünay, Gokcen Nurlu, Vladan Popovic, Beat Ott, Peter Wellig, Jean-Philippe Thiran, Yusuf Leblebici:
Real-time high-resolution omnidirectional imaging platform for drone detection and tracking. J. Real Time Image Process. 17(5): 1625-1635 (2020) - [j75]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf:
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020) - [c210]Duygu Kostak, Yusuf Leblebici:
Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL. ICECS 2020: 1-4 - [c209]Ayca Akkaya, Firat Celik, Yusuf Leblebici:
A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS. ISCAS 2020: 1-5 - [c208]Duygu Kostak, Yusuf Leblebici:
Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c207]Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici:
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC 2019: 219-222 - [c206]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c205]Bilal Demir, Jean-Philippe Thiran, Yusuf Leblebici:
Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System. DSD 2019: 69-73 - [c204]Irem Boybat, Cecilia Giovinazzo, Elmira Shahrabi, Igor Krawczuk, Iason Giannopoulos, Christophe Piveteau, Manuel Le Gallo, Carlo Ricciardi, Abu Sebastian, Evangelos Eleftheriou, Yusuf Leblebici:
Multi-ReRAM Synapses for Artificial Neural Network Training. ISCAS 2019: 1-5 - [c203]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - [c202]Gain Kim, Woohyun Kwon, Thomas Toifl, Yusuf Leblebici, Hyeon-Min Bae:
Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link. MWSCAS 2019: 1147-1150 - [c201]Behnoush Attarimashalkoubeh, Yusuf Leblebici:
Novel 3D architecture of 1S1R. NANOARCH 2019: 1-2 - [c200]Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS 2019: 1-4 - [c199]Ayca Akkaya, Firat Celik, Yusuf Leblebici:
Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs. NORCAS 2019: 1-7 - [c198]Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler:
Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. NVMTS 2019: 1-6 - [c197]Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici:
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME 2019: 101-104 - [p1]Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli:
Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks 2019: 1021-1064 - 2018
- [j74]Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl:
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits 53(3): 861-872 (2018) - [j73]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [j72]Cosimo Aprile, Kerim Türe, Luca Baldassarre, Mahsa Shoaran, Gürkan Yilmaz, Franco Maloberti, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher:
Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3929-3941 (2018) - [j71]Kerem Seyid, Andrea Richaud, Raffaele Capoccia, Yusuf Leblebici:
FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation. IEEE Trans. Circuits Syst. Video Technol. 28(1): 206-216 (2018) - [c196]Cosimo Aprile, Johannes Wüthrich, Luca Baldassarre, Yusuf Leblebici, Volkan Cevher:
An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems. CF 2018: 228-231 - [c195]Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou:
Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition. IJCNN 2018: 1-9 - [c194]Selman Ergünay, Yusuf Leblebici:
Hardware Implementation of a Smart Camera with Keypoint Detection and Description. ISCAS 2018: 1-4 - [c193]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici:
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS 2018: 1-5 - [c192]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC 2018: 266-268 - [c191]Mustafa Kilic, Yusuf Leblebici:
A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC. NEWCAS 2018: 273-276 - [c190]Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici:
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS 2018: 1-6 - [c189]Mustafa Kilic, Selman Ergünay, Yusuf Leblebici:
A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs. NORCAS 2018: 1-5 - [c188]Irem Boybat, S. R. Nandakumar, Manuel Le Gallo, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou:
Impact of conductance drift on multi-PCM synaptic architectures. NVMTS 2018: 1-4 - [c187]Arda Uran, Mustafa Kilic, Yusuf Leblebici:
Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs. PRIME 2018: 21-24 - [c186]Alessandro Caratelli, Simone Scarfi, Davide Ceresa, Kostas Kloukinas, Yusuf Leblebici:
System Level simulation framework for the ASICs development of a novel particle physics detector. PRIME 2018: 49-52 - [c185]Elmira Shahrabi, Cecilia Giovinazzo, Jury Sandrini, Yusuf Leblebici:
The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance. PRIME 2018: 69-72 - [i3]Kyong Hwan Jin, Gain Kim, Yusuf Leblebici, Jong Chul Ye, Michael Unser:
Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals. CoRR abs/1809.07188 (2018) - 2017
- [j70]Can Baltaci, Yusuf Leblebici:
Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies. Integr. 58: 421-429 (2017) - [j69]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [j68]Omer Cogal, Yusuf Leblebici:
An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging. IEEE Trans. Biomed. Circuits Syst. 11(1): 212-224 (2017) - [j67]Stanislaw Wozniak, Angeliki Pantazi, Severin Sidler, Nikolaos Papandreou, Yusuf Leblebici, Evangelos Eleftheriou:
Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1342-1346 (2017) - [j66]Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1387-1391 (2017) - [j65]Gain Kim, Thierry Barailler, Chen Cao, Kiarash Gharibdoust, Yusuf Leblebici:
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3192-3201 (2017) - [c184]Cosimo Aprile, Johannes Wüthrich, Luca Baldassarre, Yusuf Leblebici, Volkan Cevher:
DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems. Conf. Computing Frontiers 2017: 391-394 - [c183]B. Attarimashalkoubeh, Jury Sandrini, Elmira Shahrabi, Yusuf Leblebici:
Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs. ESSDERC 2017: 152-155 - [c182]Severin Sidler, Angeliki Pantazi, Stanislaw Wozniak, Yusuf Leblebici, Evangelos Eleftheriou:
Unsupervised Learning Using Phase-Change Synapses and Complementary Patterns. ICANN (1) 2017: 281-288 - [c181]Irem Boybat, Carmelo di Nolfo, Stefano Ambrogio, Martina Bodini, Nathan C. P. Farinha, Robert M. Shelby, Pritish Narayanan, Severin Sidler, Hsinyu Tsai, Yusuf Leblebici, Geoffrey W. Burr:
Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. ICRC 2017: 1-8 - [c180]Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou:
Feature Learning Using Synaptic Competition in a Dynamically-Sized Neuromorphic Architecture. ICRC 2017: 1-7 - [c179]Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou:
Neuromorphic system with phase-change synapses for pattern learning and feature extraction. IJCNN 2017: 3724-3732 - [c178]Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr:
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. ISCAS 2017: 1-4 - [c177]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - [c176]Mohammad Nasr Esfahani, Yusuf Leblebici, B. Erdem Alaca:
Piezoresistivity characterization of silicon nanowires through monolithic MEMS. NEMS 2017: 77-80 - [c175]Themistoklis G. Mavrogordatos, Mustafa Kilic, Yusuf Leblebici:
A hybrid CDAC - threshold configuring SAR ADC in 28nm FDSOI CMOS. NEWCAS 2017: 213-216 - [c174]Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou:
An efficient synaptic architecture for artificial neural networks. NVMTS 2017: 1-4 - [i2]Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Thomas P. Parnell, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou:
Neuromorphic computing with multi-memristive synapses. CoRR abs/1711.06507 (2017) - 2016
- [j64]Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici:
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 339-351 (2016) - [j63]Adela-Diana Almasi, Stanislaw Wozniak, Valentin Cristea, Yusuf Leblebici, Ton Engbersen:
Review of advances in neural networks: Neural design technology stack. Neurocomputing 174: 31-41 (2016) - [j62]Vladan Popovic, Kerem Seyid, Eliéva Pignat, Ömer Çogal, Yusuf Leblebici:
Multi-camera platform for panoramic real-time HDR video construction and rendering. J. Real Time Image Process. 12(4): 697-708 (2016) - [j61]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits 51(3): 636-648 (2016) - [j60]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. IEEE J. Solid State Circuits 51(4): 992-1002 (2016) - [j59]Giulia Beanato, Kiarash Gharibdoust, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. Microelectron. J. 48: 50-59 (2016) - [j58]Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. Microelectron. J. 51: 38-45 (2016) - [j57]Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1126-1130 (2016) - [c173]S. E. Kucuk Eroglu, W. Y. Choo, Yusuf Leblebici:
Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique. 3DIC 2016: 1-5 - [c172]Gain Kim, Yusuf Leblebici:
Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links. APCCAS 2016: 164-167 - [c171]Severin Sidler, Irem Boybat, Robert M. Shelby, Pritish Narayanan, Jun-Woo Jang, Alessandro Fumarola, Kibong Moon, Yusuf Leblebici, Hyunsang Hwang, Geoffrey W. Burr:
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. ESSDERC 2016: 440-443 - [c170]Yusuf Leblebici:
Design and Implementation of Real-Time Multi-sensor Vision Systems. ACM Great Lakes Symposium on VLSI 2016: 3 - [c169]Cosimo Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher:
Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition. ACM Great Lakes Symposium on VLSI 2016: 433-438 - [c168]Kerem Seyid, Andrea Richaud, Raffaele Capoccia, Yusuf Leblebici:
Block matching based real-time optical flow hardware implementation. ISCAS 2016: 2206-2209 - [c167]Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici:
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. ISCAS 2016: 2905 - [c166]Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata:
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC 2016: 492-494 - [c165]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. NEWCAS 2016: 1-4 - [c164]Mahsa Shoaran, Masoud Shahshahani, Masoud Farivar, Joyel Almajano, Amirhossein Shahshahani, Alexandre Schmid, Anatol Bragin, Yusuf Leblebici, Azita Emami:
A 16-channel 1.1mm2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j56]Nikola Katic, Mahdad Hosseini Kamal, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
Compressive image acquisition in modern CMOS IC design. Int. J. Circuit Theory Appl. 43(6): 722-741 (2015) - [j55]Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici:
A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. Int. J. Circuit Theory Appl. 43(11): 1597-1614 (2015) - [j54]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. IEEE J. Solid State Circuits 50(12): 3133-3144 (2015) - [j53]Nikola Katic, Alexandre Schmid, Yusuf Leblebici:
A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process. Microelectron. J. 46(11): 997-1001 (2015) - [j52]Nikola Katic, Radisav Cojbasic, Alexandre Schmid, Yusuf Leblebici:
A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder. Microelectron. J. 46(12): 1343-1350 (2015) - [j51]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici:
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 458-467 (2015) - [j50]Kerem Seyid, Vladan Popovic, Omer Cogal, Abdulkadir Akin, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
A Real-Time Multiaperture Omnidirectional Visual Sensor Based on an Interconnected Network of Smart Cameras. IEEE Trans. Circuits Syst. Video Technol. 25(2): 314-324 (2015) - [c163]Luca Baldassarre, Cosimo Aprile, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher:
Structured sampling and recovery of iEEG signals. CAMSAP 2015: 269-272 - [c162]Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE 2015: 1203-1208 - [c161]Selman Ergünay, Vladan Popovic, Kerem Seyid, Yusuf Leblebici:
A novel hybrid architecture for real-time omnidirectional image reconstruction. ICDSC 2015: 152-157 - [c160]Vladan Popovic, Yusuf Leblebici:
A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images. ICIP 2015: 4411-4415 - [c159]Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici:
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. ISCAS 2015: 9-12 - [c158]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS 2015: 157-160 - [c157]Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici:
Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware. ISCAS 2015: 1908 - [c156]Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici:
Real-time free viewpoint synthesis using three-camera disparity estimation hardware. ISCAS 2015: 2525-2528 - [c155]Radisav Cojbasic, Yusuf Leblebici:
Design of high-temperature SRAM for reliable operation beyond 250°C. ISCAS 2015: 2545-2548 - [c154]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. ISSCC 2015: 1-3 - [c153]Hasene Gulperi Ozsema, Tugba Demirci, Yusuf Leblebici:
3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation. NORCAS 2015: 1-4 - [c152]Hasene Gulperi Ozsema, Duygu Kostak, Tugba Demirci, Yusuf Leblebici:
Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology. NORCAS 2015: 1-4 - [c151]Vladan Popovic, Yusuf Leblebici:
FIR filters for hardware-based real-time multi-band image blending. Real-Time Image and Video Processing 2015: 94000D - [c150]Gain Kim, Raffaele Capoccia, Yusuf Leblebici:
Design optimization of polyphase digital down converters for extremely high frequency wireless communications. VLSI-SoC 2015: 207-212 - [c149]Kerem Seyid, Sebastien Blanc, Yusuf Leblebici:
Hardware implementation of real-time multiple frame super-resolution. VLSI-SoC 2015: 219-224 - [c148]Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Ipek Baz, Alexandre Schmid, Yusuf Leblebici:
Trinocular adaptive window size disparity estimation algorithm and its real-time hardware. VLSI-DAT 2015: 1-4 - [c147]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. VLSIC 2015: 180- - [c146]Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, U. Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl:
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC 2015: 228- - 2014
- [j49]Abdulkadir Akin, Ipek Baz, Alexandre Schmid, Yusuf Leblebici:
Dynamically adaptive real-time disparity estimation hardware using iterative refinement. Integr. 47(3): 365-376 (2014) - [j48]Vladan Popovic, Eliéva Pignat, Yusuf Leblebici:
Performance Optimization and FPGA Implementation of Real-Time Tone Mapping. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 803-807 (2014) - [j47]Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli:
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3155-3164 (2014) - [j46]Vladan Popovic, Kerem Seyid, Abdulkadir Akin, Ömer Çogal, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
Image Blending in a High Frame Rate FPGA-based Multi-Camera System. J. Signal Process. Syst. 76(2): 169-184 (2014) - [c145]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. A-SSCC 2014: 89-92 - [c144]Gozen Koklu, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara:
Programmable active pixel sensor for low-light biomedical applications. BioCAS 2014: 655-658 - [c143]Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
3D serial TSV link for low-power chip-to-chip communication. ICICDT 2014: 1-4 - [c142]Luis Manuel Gaemperle, Kerem Seyid, Vladan Popovic, Yusuf Leblebici:
An Immersive Telepresence System Using a Real-Time Omnidirectional Camera and a Virtual Reality Head-Mounted Display. ISM 2014: 175-178 - [c141]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC 2014: 378-379 - [c140]Somayyeh Rahimian Omam, Yusuf Leblebici, Giovanni De Micheli:
Parallel vs. serial inter-plane communication using TSVs. LASCAS 2014: 1-5 - [c139]Nikola Katic, Alexandre Schmid, Yusuf Leblebici:
A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors. MWSCAS 2014: 683-686 - [c138]Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici:
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. NORCHIP 2014: 1-4 - [c137]Vladan Popovic, Yusuf Leblebici:
Reconfigurable forward homography estimation system for real-time applications. VLSI-SoC 2014: 1-6 - [c136]Kerem Seyid, Ömer Çogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras. VLSI-SoC (Selected Papers) 2014: 170-197 - 2013
- [j45]Abdulkadir Akin, Omer Cogal, Kerem Seyid, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(2): 137-144 (2013) - [j44]Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA. J. Low Power Electron. 9(1): 1-8 (2013) - [j43]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits 48(12): 3049-3058 (2013) - [j42]Hossein Afshari, Laurent Jacques, Luigi Bagnato, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
The PANOPTIC Camera: A Plenoptic Sensor with Real-Time Omnidirectional Capability. J. Signal Process. Syst. 70(3): 305-328 (2013) - [c135]Yassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel:
Integration of intra chip stack fluidic cooling using thin-layer solder bonding. 3DIC 2013: 1-8 - [c134]Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici:
FireBird: PowerPC e200 based SoC for high temperature operation. CICC 2013: 1-4 - [c133]Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici:
A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding. CICC 2013: 1-4 - [c132]Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Towards structured ASICs using polarity-tunable Si nanowire transistors. DAC 2013: 123:1-123:4 - [c131]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c130]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. DATE 2013: 625-630 - [c129]Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici:
3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. DATE 2013: 1241-1246 - [c128]Mahdad Hosseini Kamal, Hossein Afshari, Yusuf Leblebici, Alexandre Schmid, Pierre Vandergheynst:
Interconnected network of cameras. Sensors, Cameras, and Systems for Industrial and Scientific Applications 2013: 86590P - [c127]Abdulkadir Akin, Ipek Baz, Baris Atakan, Irem Boybat, Alexandre Schmid, Yusuf Leblebici:
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware. ACM Great Lakes Symposium on VLSI 2013: 155-160 - [c126]Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]. ACM Great Lakes Symposium on VLSI 2013: 313-314 - [c125]Vladan Popovic, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici:
Real-time hardware implementation of multi-resolution image blending. ICASSP 2013: 2741-2745 - [c124]Mahdad Hosseini Kamal, Mahsa Shoaran, Yusuf Leblebici, Alexandre Schmid, Pierre Vandergheynst:
Compressive multichannel cortical signal recording. ICASSP 2013: 4305-4309 - [c123]Gozen Koklu, Ralph Etienne-Cummings, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara:
Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices. ISCAS 2013: 1075-1078 - [c122]Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid:
A low-power area-efficient compressive sensing approach for multi-channel neural recording. ISCAS 2013: 2191-2194 - [c121]Omer Cogal, Vladan Popovic, Yusuf Leblebici:
Spherical Panorama Construction Using Multi Sensor Registration Priors and Its Real-Time Hardware. ISM 2013: 171-178 - [c120]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC 2013: 468-469 - [c119]Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
Power-efficient CMOS image acquisition system based on compressive sampling. MWSCAS 2013: 1367-1370 - [c118]Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
Column-separated compressive sampling scheme for low power CMOS image sensors. NEWCAS 2013: 1-4 - [c117]Abdulkadir Akin, Luis Manuel Gaemperle, Halima Najibi, Alexandre Schmid, Yusuf Leblebici:
Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware. VLSI-SoC (Selected Papers) 2013: 227-248 - [c116]Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid, Yusuf Leblebici:
Compressed look-up-table based real-time rectification hardware. VLSI-SoC 2013: 272-277 - 2012
- [j41]Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici:
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 295-306 (2012) - [j40]Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici:
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review. Proc. IEEE 100(6): 2008-2020 (2012) - [j39]Omer Can Akgun, Joachim Neves Rodrigues, Yusuf Leblebici, Viktor Öwall:
High-Level Energy Estimation in the Sub-V$_{{\rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector. IEEE Trans. Biomed. Circuits Syst. 6(1): 15-27 (2012) - [j38]Armin Tajalli, Yusuf Leblebici:
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 903-907 (2012) - [j37]Hossein Afshari, Vladan Popovic, Tugce Tasci, Alexandre Schmid, Yusuf Leblebici:
A spherical multi-camera system with real-time omnidirectional video acquisition capability. IEEE Trans. Consumer Electron. 58(4): 1110-1118 (2012) - [c115]Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli:
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. DAC 2012: 42-47 - [c114]Hossein Afshari, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici:
Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry. Diagrams 2012: 297-299 - [c113]Abdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware. DSD 2012: 907-914 - [c112]Mahsa Shoaran, Claudio Pollo, Yusuf Leblebici, Alexandre Schmid:
Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization. EMBC 2012: 5150-5153 - [c111]Gozen Koklu, Julien Ghaye, Rene Beuchat, Giovanni De Micheli, Yusuf Leblebici, Sandro Carrara:
Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications. ISCAS 2012: 2063-2066 - [c110]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH 2012: 55-60 - [c109]Hossein Afshari, Abdulkadir Akin, Vladan Popovic, Alexandre Schmid, Yusuf Leblebici:
Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera. SiPS 2012: 49-54 - [c108]Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini:
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. VLSI-SoC 2012: 30-35 - [c107]Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli:
GMS: Generic memristive structure for non-volatile FPGAs. VLSI-SoC 2012: 94-98 - [c106]Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini:
Configurable Low-Latency Interconnect for Multi-core Clusters. VLSI-SoC (Selected Papers) 2012: 107-124 - [c105]Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici, Jan M. Rabaey:
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements. VLSIC 2012: 36-37 - 2011
- [j36]Neil Joye, Alexandre Schmid, Yusuf Leblebici:
Amplitude modulation based readout for very dense active microelectrode arrays. IEICE Electron. Express 8(1): 38-44 (2011) - [j35]Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing. J. Low Power Electron. 7(2): 285-293 (2011) - [j34]Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici:
Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor. IEEE Trans. Biomed. Circuits Syst. 5(3): 262-271 (2011) - [j33]Armin Tajalli, Yusuf Leblebici:
Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 159-163 (2011) - [j32]Armin Tajalli, Yusuf Leblebici:
Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2189-2200 (2011) - [c104]Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici:
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019 - [c103]Mohamed M. Sabry, Arvind Sridhar, David Atienza, Yuksel Temiz, Yusuf Leblebici, S. Szczukiewicz, Navid Borhani, John Richard Thome, Thomas Brunschwiler, Bruno Michel:
Towards thermally-aware design of 3D MPSoCs with inter-tier cooling. DATE 2011: 1466-1471 - [c102]Armin Tajalli, Yusuf Leblebici:
Design trade-offs in ultra-low-power CMOS and STSCL digital systems. ECCTD 2011: 544-547 - [c101]Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano:
PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. FMCO 2011: 277-293 - [c100]Wayne P. Burleson, Yusuf Leblebici:
Hardware security in VLSI. ACM Great Lakes Symposium on VLSI 2011: 447-448 - [c99]Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici:
Alternative design methodologies for the next generation logic switch. ICCAD 2011: 231-234 - [c98]Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg:
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. ISCAS 2011: 1772-1775 - 2010
- [j31]Deniz Karakoyunlu, Frank Kagan Gürkaynak, Berk Sunar, Yusuf Leblebici:
Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. IET Inf. Secur. 4(1): 30-43 (2010) - [j30]Armin Tajalli, Yusuf Leblebici:
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. J. Low Power Electron. 6(1): 211-217 (2010) - [j29]Massimo Alioto, Stéphane Badel, Yusuf Leblebici:
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. Microelectron. J. 41(10): 669-679 (2010) - [j28]Sandro Carrara, Andrea Cavallini, Yusuf Leblebici, Giovanni De Micheli, Vijayender Bhalla, Francesco Valle, Bruno Samorì, Luca Benini, Bruno Riccò, Inger Vikholm-Lundin, Tony Munter:
Capacitance DNA bio-chips improved by new probe immobilization strategies. Microelectron. J. 41(11): 711-717 (2010) - [c97]Carlotta Guiducci, Yuksel Temiz, Yusuf Leblebici, Enrico Accastelli, Anna Ferretti, Giulia Cappi, Elena Bianchi:
Integrating bio-sensing functions on CMOS chips. APCCAS 2010: 548-551 - [c96]Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. DATE 2010: 339-344 - [c95]Armin Tajalli, Yusuf Leblebici:
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. DATE 2010: 711-716 - [c94]Armin Tajalli, Yusuf Leblebici:
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ESSCIRC 2010: 174-177 - [c93]Armin Tajalli, Yusuf Leblebici:
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. ESSCIRC 2010: 242-245 - [c92]Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici:
Memristive devices fabricated with silicon nanowire schottky barrier transistors. ISCAS 2010: 9-12 - [c91]Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici:
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ISCAS 2010: 1715-1718 - [c90]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Selective redundancy-based design techniques for the minimization of local delay variations. ISCAS 2010: 2486-2489 - [c89]Vahid Majidzadeh, Laurent Jacques, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici:
A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing. ISCAS 2010: 2956-2959 - [c88]Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing. PATMOS 2010: 170-179 - [c87]Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici:
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC 2010: 149-154 - [c86]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation. VLSI-SoC 2010: 328-334
2000 – 2009
- 2009
- [j27]Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici:
A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. Int. J. Circuit Theory Appl. 37(2): 203-220 (2009) - [j26]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
On the Reliability of Post-CMOS and SET Systems. Int. J. Nanotechnol. Mol. Comput. 1(2): 43-57 (2009) - [j25]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici:
A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. Int. J. Nanotechnol. Mol. Comput. 1(2): 80-92 (2009) - [j24]Neil Joye, Alexandre Schmid, Yusuf Leblebici:
Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays. Neurocomputing 73(1-3): 250-259 (2009) - [j23]Armin Tajalli, Yusuf Leblebici:
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits 44(2): 538-548 (2009) - [j22]Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici:
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. 40(6): 973-978 (2009) - [j21]Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 127-131 (2009) - [j20]Armin Tajalli, Yusuf Leblebici:
Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 374-378 (2009) - [j19]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4: 230-243 (2009) - [j18]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [c85]Thomas Brunschwiler, Stephan Paredes, Ute Drechsler, Bruno Michel, W. Cesar, G. Töral, Yuksel Temiz, Yusuf Leblebici:
Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. 3DIC 2009: 1-10 - [c84]M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. ASP-DAC 2009: 835-840 - [c83]M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli:
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. CASES 2009: 11-16 - [c82]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c81]Armin Tajalli, Yusuf Leblebici:
A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. CICC 2009: 593-596 - [c80]M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli:
Decoding nanowire arrays fabricated with the multi-spacer patterning technique. DAC 2009: 77-82 - [c79]Ayse K. Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici:
Dynamic thermal management in 3D multicore architectures. DATE 2009: 1410-1415 - [c78]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). DFT 2009: 340-348 - [c77]Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici:
A micropower neural recording amplifier with improved noise efficiency factor. ECCTD 2009: 319-322 - [c76]Armin Tajalli, Yusuf Leblebici:
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. ESSCIRC 2009: 164-167 - [c75]Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici:
A fully on-chip LDO voltage regulator for remotely powered cortical implants. ESSCIRC 2009: 424-427 - [c74]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c73]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c72]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - [c71]Laurent Jacques, Pierre Vandergheynst, Alexandre Bibet, Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici:
CMOS compressed imaging by Random Convolution. ICASSP 2009: 1113-1116 - [c70]Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696 - [c69]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya:
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN 2009: 1600-1605 - [c68]Kanber Mithat Silay, Denis Dondi, Luca Larcher, Michel J. Declercq, Luca Benini, Yusuf Leblebici, Catherine Dehollain:
Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants. ISCAS 2009: 533-536 - [c67]Massimo Alioto, Stéphane Badel, Yusuf Leblebici:
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. ISCAS 2009: 1285-1288 - [c66]Armin Tajalli, Yusuf Leblebici:
Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. ISCAS 2009: 2553-2556 - [c65]Massimo Alioto, Yusuf Leblebici:
Analysis and Design of Ultra-low Power Subthreshold MCML Gates. ISCAS 2009: 2557-2560 - [c64]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. NanoNet 2009: 70-75 - [c63]José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici:
Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet 2009: 90-98 - [c62]Yusuf Leblebici:
Subthreshold Circuit Design for Ultra-Low-Power Applications. PATMOS 2009: 3 - [c61]Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall:
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. PATMOS 2009: 347-356 - 2008
- [j17]Omer Can Akgun, Yusuf Leblebici:
Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime. J. Low Power Electron. 4(3): 320-336 (2008) - [j16]Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz:
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits 43(7): 1699-1710 (2008) - [j15]Stéphane Badel, Alexandre Schmid, Yusuf Leblebici:
CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications. Microelectron. J. 39(12): 1817-1828 (2008) - [j14]M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli:
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2053-2067 (2008) - [c60]Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici:
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. APCCAS 2008: 21-24 - [c59]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c58]M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
Programmable logic circuits based on ambipolar CNFET. DAC 2008: 339-340 - [c57]Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici:
A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE 2008: 843-848 - [c56]Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici:
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE 2008: 1328-1333 - [c55]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - [c54]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - [c53]Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. PATMOS 2008: 11-20 - [c52]Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici:
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30 - 2007
- [j13]Armin Tajalli, Paul Muller, Yusuf Leblebici:
Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. J. Low Power Electron. 3(3): 345-354 (2007) - [j12]Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. IEEE J. Solid State Circuits 42(7): 1593-1606 (2007) - [j11]Armin Tajalli, Paul Muller, Yusuf Leblebici:
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE J. Solid State Circuits 42(10): 2235-2244 (2007) - [c51]Omer Can Akgun, Yusuf Leblebici, Eric A. Vittoz:
Current sensing completion detection for subthreshold asynchronous circuits. ECCTD 2007: 376-379 - [c50]Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer:
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC 2007: 304-307 - [c49]Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI 2007: 204-207 - [c48]M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli:
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD 2007: 765-772 - [c47]Stéphane Badel, Yusuf Leblebici:
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. ISCAS 2007: 1871-1874 - [c46]Milos Stanisavljevic, Frank Kagan Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. Nano-Net 2007: 4 - [c45]Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214 - [c44]Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64 - [c43]I. Hatyrnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici:
Predictable system interconnects through accurate early wire characterization. SoCC 2007: 287-290 - [i1]Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. CoRR abs/0710.4727 (2007) - 2006
- [j10]Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici:
Analysis and Optimization of MPSoC Reliability. J. Low Power Electron. 2(1): 56-69 (2006) - [c42]Ayse K. Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli:
A simulation methodology for reliability analysis in multi-core SoCs. ACM Great Lakes Symposium on VLSI 2006: 95-99 - [c41]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. IJCNN 2006: 2771-2778 - [c40]Omer Can Akgun, Yusuf Leblebici:
Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. ISCAS 2006 - [c39]Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici:
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS 2006 - [c38]Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS 2006 - [c37]Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC 2006: 152-157 - [c36]Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. VLSI-SoC (Selected Papers) 2006: 217-240 - [c35]Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer:
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC 2006: 234-238 - [c34]Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. VLSI-SoC 2006: 379-384 - 2005
- [j9]Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya:
On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express 2(3): 76-80 (2005) - [c33]Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267 - [c32]Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE 2005: 258-263 - [c31]Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici:
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. ESSCIRC 2005: 193-196 - [c30]Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici:
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTIMedia 2005: 135-140 - [c29]Paul Muller, Yusuf Leblebici:
Jitter Tolerance Analysis of Clock and Data Recovery Circuits. FDL 2005: 143-147 - [c28]Zeynep Toprak Deniz, Yusuf Leblebici:
Low-power current mode logic for improved DPA-resistance in embedded systems. ISCAS (2) 2005: 1059-1062 - [c27]Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) 2005: 1782-1785 - [c26]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici:
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538 - [c25]Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED 2005: 107-110 - [c24]Paul Muller, Yusuf Leblebici:
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs. SoCC 2005: 193-196 - [c23]Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. VLSI-SoC 2005: 111-125 - 2004
- [j8]Alexandre Schmid, Yusuf Leblebici:
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1156-1166 (2004) - [c22]Alexandre Schmid, Yusuf Leblebici:
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. DFT 2004: 39-47 - [c21]Paul Muller, Yusuf Leblebici, Matthew K. Emsley, M. Selim Ünlü:
A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications]. ESSCIRC 2004: 491-494 - [c20]Elizabeth J. Brauer, Yusuf Leblebici:
Low noise MCML prefix adders using 0.18 µm CMOS technology. Circuits, Signals, and Systems 2004: 467-470 - [c19]Elizabeth J. Brauer, Yusuf Leblebici:
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. Circuits, Signals, and Systems 2004: 483-487 - [c18]Ilhan Hatirnaz, Yusuf Leblebici:
Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. ISCAS (5) 2004: 185-188 - [c17]Alexandre Schmid, Yusuf Leblebici:
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. ISCAS (3) 2004: 685-688 - [c16]Stéphane Badel, Alexandre Schmid, Yusuf Leblebici:
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. ISCAS (5) 2004: 780-783 - [c15]Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. SoC 2004: 37-40 - 2003
- [c14]Stéphane Badel, Alexandre Schmid, Yusuf Leblebici:
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. ESANN 2003: 445-450 - [c13]Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici:
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. ISCAS (5) 2003: 453-456 - [c12]Zeynep Toprak Deniz, Yusuf Leblebici:
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. ISCAS (1) 2003: 841-844 - [c11]Ilhan Hatirnaz, Yusuf Leblebici:
Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. SoC 2003: 93-96 - 2000
- [j7]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design 11(2): 115-128 (2000) - [c10]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for high-speed binary sorting. ICASSP 2000: 3339-3342 - [c9]Frank K. Gürkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness:
Higher radix Kogge-Stone parallel prefix adder architectures. ISCAS 2000: 609-612 - [c8]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS 2000: 685-688
1990 – 1999
- 1999
- [c7]Alexandre Schmid, Yusuf Leblebici, Daniel Mlynek:
A two-stage charge-based analog/digital neuron circuit with adjustable weights. IJCNN 1999: 2357-2362 - [c6]Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici:
A novel analog-digital flash converter architecture based on capacitive threshold gates. ISCAS (2) 1999: 172-175 - [c5]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438 - 1996
- [j6]Yusuf Leblebici:
Design considerations for CMOS digital circuits with improved hot-carrier reliability. IEEE J. Solid State Circuits 31(7): 1014-1024 (1996) - [j5]Hakan Özdemir, Asim Kepkep, Banu Pamir, Yusuf Leblebici, Ugur Çilingiroglu:
A capacitive threshold-logic gate. IEEE J. Solid State Circuits 31(8): 1141-1150 (1996) - [j4]Yusuf Leblebici, Hakan Özdemir, Asim Kepkep, Ugur Çilingiroglu:
A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates. IEEE J. Solid State Circuits 31(8): 1177-1183 (1996) - 1993
- [j3]Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1387-1402 (1993) - 1992
- [j2]Yusuf Leblebici, Sung-Mo Kang:
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 235-246 (1992) - 1991
- [b1]Yusuf Leblebici:
Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability. University of Illinois Urbana-Champaign, USA, 1991 - [j1]Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici:
An accurate analytical delay model for BiCMOS driver circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 577-588 (1991) - [c4]Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
New Simulation Methods for MOS VLSI Timing and Reliability. ICCAD 1991: 162-165 - 1990
- [c3]Yusuf Leblebici, Sung-Mo Kang:
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. ICCAD 1990: 400-403
1980 – 1989
- 1989
- [c2]Yusuf Leblebici, Sung-Mo Kang:
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. ICCD 1989: 492-495 - 1988
- [c1]Sung-Mo Kang, Yusuf Leblebici:
An efficient method for circuit sensitivity calculation using piecewise linear waveform models. ICCAD 1988: 24-27
Coauthor Index
Frank K. Gürkaynak
aka: Frank Kagan Gürkaynak
aka: Frank Kagan Gürkaynak
[c164] [j56] [j55] [j53] [j52] [j51] [j50] [c157] [c156] [c148] [j49] [j46] [c139] [c138] [c136] [j45] [j42] [c133] [c128] [c127] [c126] [c125] [c124] [c122] [c119] [c118] [c117] [c116] [j37] [c114] [c113] [c112] [c109] [c105] [j36] [j34] [c90] [c89] [c86] [j26] [j25] [j24] [c78] [c77] [c75] [c71] [c69] [c64] [j15] [c56] [c49] [c46] [c41] [j9] [c33] [c26] [c23] [j8] [c22] [c17] [c16] [c14] [c7] [c6]
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