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ORCIDDavide Sacchetto
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2020 – today
- 2022
[c11]Cosimo Calò, Kaoutar Benyahya, Haïk Mardoyan, Philippe Charbonnier, Davide Sacchetto, Michael Zervas, Karim Mekhazni, Delphine Lanteri, Harry Gariah, Catherine Fortin, Nicolas Vaissière, Antoine Elias, Olivier Parillaud, Franck Mallecot, Jean Decobert, Frédéric Pommereau, Jérémie Renaudier:
Hybrid InP-SiN microring-resonator based tunable laser with high output power and narrow linewidth for high capacity coherent systems. OFC 2022: 1-3
2010 – 2019
- 2019
- [p1]Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli:
Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks 2019: 1021-1064 - 2016
- [j3]Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici:
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 339-351 (2016) - 2015
- [c10]Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE 2015: 1203-1208 - [c9]Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici:
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. ISCAS 2015: 9-12 - 2014
- [j2]Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg
, Giovanni De Micheli:
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3155-3164 (2014) - 2013
- [c8]Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Towards structured ASICs using polarity-tunable Si nanowire transistors. DAC 2013: 123:1-123:4 - [c7]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. DATE 2013: 625-630 - [c6]Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli:
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS 2013: 1-4 - 2012
- [j1]Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici:
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review. Proc. IEEE 100(6): 2008-2020 (2012) - [c5]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH 2012: 55-60 - [c4]Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli:
GMS: Generic memristive structure for non-volatile FPGAs. VLSI-SoC 2012: 94-98 - 2011
- [c3]Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici:
Alternative design methodologies for the next generation logic switch. ICCAD 2011: 231-234 - 2010
- [c2]Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici:
Memristive devices fabricated with silicon nanowire schottky barrier transistors. ISCAS 2010: 9-12 - [c1]Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici:
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ISCAS 2010: 1715-1718
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