Microprocessor, Microcontroller and

Applications
Course Code: CSE2PM02A Credits: 3 TH

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 1

 Syllabus
Unit 3: Pentium Processor: Protection and Task Management
Mechanism:
Protection by segmentation, privilege-levels, rules of inter-
privilege level transfer for data and code segments, page level
protection.

Task Management, support registers, related data structures, Task

switching.

Unit 3 MMA-CSE2PM02A 2024-25 S3 2

9/25/2024
 Learning Resources:
Text Books:
1. James Antonakos, “The Pentium Microprocessor”, 2004, Pearson
Education ISBN – 81-7808- 545-3.
2. K. J. Ayala" The 8051 Microcontroller “ISBN 9788131511053.
3. Datasheet of LPC2294 ARM Based Microcontroller
Reference Books:
1. Intel architecture software developer's manual volume 3.
2. Intel architecture software developer's manual volume 1.
3. Intel 8051 datasheet.
4. User Manual of LPC2294 ARM Based Microcontroller
MOOCs:
https://nptel.ac.in/courses/108/105/108105102/
Unit 3 MMA-CSE2PM02A 2024-25 S3 3
9/25/2024
 Course Objectives:
By participating in and understanding all facets of this Course a student
will be able:

1.To learn the architecture and programming of Pentium Microprocessor

2.To understand the operating modes and memory management mechanism
of Pentium Processor.
3.To provide insight to protection and multitasking environment of Pentium
Processor.
4.To understand the internal architecture of 8051 Microcontrollers.
5.To learn and implement the architectural Features of 8051
Microcontroller.

Unit 3 MMA-CSE2PM02A 2024-25 S3 4

9/25/2024
 Course Outcome:
After completion of the course the students will be able to: -

1.Describe the Pentium features, system architecture thoroughly and

develop 80x86 Assembly language programs for various applications.
2.Illustrate the working of memory management unit in protected mode of
Pentium.
3.Interpret the mechanism of Protection and Task Management in Pentium.
4.Demonstrate the knowledge of the 8051-microcontroller instruction set
and addressing Modes.
5.Interpret the features of the 8051 Microcontroller for various
applications.

Unit 3 MMA-CSE2PM02A 2024-25 S3 5

9/25/2024
 Protection
⮚Each reference to memory is checked by the hardware to
verify that it satisfies the protection criteria.
⮚All these checks are made before the memory cycle is
started.
⮚Any violation prevents that cycle from starting and results in an
exception.
⮚Invalid attempts to access memory result in an exception.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 6

 Field and Flag in Protection system

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 7

 Field and Flag in Protection system
Different fields and flags are used in segment level protection mechanism:---
⮚Descriptor type (S) flag: Bit no 12 (in the second double word of seg. descriptor ), defines is it a system segment
or Code/Data segment.
⮚Type Field: Bit 8-11, determines type of code/data or system segment ( Read/write)
⮚E flag : Bit 10
⮚Limit Filed: Bit 0-19, determine size of segment along with G and E flag.
⮚G flag: Bit 23
⮚Descriptor Privilege level (DPL): bit 13-14, determines the privilege level of the segment described by the
segment descriptor
⮚Requested Privilege level (RPL): bit 0-1, of any segment selector, Specifies the RPL of segment
selector.
⮚Current Privilege Level(CPL): bit 0-1 of CS segment register, indicates the privilege level of
currently executing program or procedure.

9/25/2024 8
Unit 3 MMA-CSE2PM02A 2024-25 S3
 Data Segment Descriptor

Base G B 0 A Seg. P DPL S Base Base Segment

Addr. V Limit TYPE Addr Addr Limit
L 19:16 23:16 15:00 15:00
31:24 ‘1’ 0 E W A

Code Segment Descriptor

Base G D 0 A Seg. P DPL S Base Base Segment

Addr. V Limit TYPE Addr Addr Limit
L 19:16 23:16 15:00 15:00
31:24 ‘1’ 1 C R A

System Segment Descriptor

Base G 0 Seg. P DPL S Base Base Segment

Limit Addr Addr Limit
Addr. 19:16
TYPE
31:24 ‘0 23:16 15:00 15:00
’

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 9

 Segment Level Protection
⮚ All five aspects of protection apply to segment translation:
1. Type checking.
2. Limit checking.
3. Restriction of addressable domain.
4. Restriction of procedure entry points.
5. Restriction of instruction set.
⮚ The segment is the unit of protection, and segment descriptors store protection parameters.
⮚ Protection checks are performed automatically by the CPU when the selector of a segment
descriptor is loaded into a segment register and with every segment access.
⮚ Segment registers hold the protection parameters of the currently addressable segments.
⮚ The protection parameters are placed in the descriptor by systems software at the time a
descriptor is created.
⮚ Any violation of these protection checks results in an exception.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 10
 1. Type Checking
Segment descriptors contain type information in two places:
1. The S (descriptor type) flag.
2. The type field: Used to determine whether the current memory access
(Read/Write/Execute) is allowed.

Some examples of typical operations where type checking is performed-

⮚ The CS register only can be loaded with a selector for a code segment.
⮚ The LDTR can only be loaded with a selector for an LDT.
⮚ No instruction may write into an executable segment/read only data
segment.
⮚ No instruction may read from an executable only segment.
⮚ The LLDT instruction must reference a segment descriptor for an LDT.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 11
 2. Limit Checking
⮚ The limit field of a segment descriptor is used by the processor to prevent programs
from addressing outside the segment.
⮚ The processor's interpretation of the limit depends on the setting of the G (granularity)
bit.
⮚ When G=0, the actual limit is the value of the 20-bit limit field as it appears in the
descriptor. (Number of bytes)
⮚ When G=1, the actual limit may range from 0FFFH (212-1 or 4 KByte) to
0FFFFFFFFH(232-1 or 4 GByte). (Number of 4 Kilobytes)
⮚ Limit checking catches programming errors such as runaway subscripts and invalid
pointer calculations.
⮚ In addition to checking segment limits, the processor also checks descriptor table
limits.
⮚ Null Segment Selector Checking.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 12
 Privilege
Pentium checks that the application is privileged enough to:
1. Execute certain instructions.
2. Reference data other than its own.
3. Transfer control to code other than its own.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 13

 Privilege Levels

⮚Privilege level – the

authority of the program
with which it can access /
use resources of the system.
⮚Processor segment
protection Mechanism
recognizes 4 privilege levels File system manipulation
Error handling
form 0 to 3 with 0 as high device drivers

and 3 as low privilege. programs

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 14

 Privilege Levels
⮚Level 0- Level zero is the highest privilege level. Typically,
only the OS kernel will run with privilege level zero. This
permits it to perform any operation.
⮚Level 1 - Level one is the next privilege level. It is typically
assigned to high-priority device drivers and OS services. It
could also be assigned to debuggers to protect them from
alteration by low-priority device drivers and applications
programs.
⮚Level 2 - Level two is typically assigned to lower-priority
device drivers.
⮚Level 3 - Level three is the lowest priority and is typically
assigned to applications programs.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 15
 Privilege Levels
⮚The center is reserved for most privilege code/data and
stacks, used in critical software, usually kernel of
operating system.
⮚Outer rings are less critical section / less privileged
⮚Processor limits the access from low privilege
program or task to access high privilege program,
except under controlled situation.
⮚When processor detects privilege level violation is
generates General-Protection exception (#GP)
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 16
 Terminology
⮚PL: Privilege Level.
⮚RPL: Requested Privilege Level.
⮚DPL: Descriptor Privilege Level.
⮚CPL: Current Privilege Level.
⮚Task:
❖One instance of the execution of a program.
❖Tasks are also referred to as processes.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 17
 DPL, CPL, RPL
⮚ Privilege level – the authority of the program with which it can access / use
resources of the system.
⮚DPL – Descriptor’s privilege level
Privilege level of the segment described by the segment descriptor
⮚CPL – Current Privilege level
It is the privilege level of the program presently in execution
⮚RPL – Requestor’s privilege level
It is the privilege level as defined in the selector

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 18

 Privilege Checking Prog. A cannot access
Prog. X since no call
gate available for A to
Prog. C can access
access program at PL0
Prog. X since call
gate available for C A
to access program
at PL0 B Prog. B can access
C
Prog. X since call
PL3 PL2 PL1 gate available for B to
Call PL0
access program at PL0
Gate
for X X

An application program running

Call
Gate
at PL = 3 may call an operating
for X system routine at PL = 1 or 0
(via a gate) which would cause
the task's CPL to be set to 1
until the operating system
routine was finished.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 19

 CPL- Current Privilege Level
⮚ It is the level of currently executing program or task.
⮚ It is stored in bit 0 and 1 of segment registers CS and SS.
⮚ CPL is equal to the privilege level of Code Segment from which instruction is executed.
⮚ Processor changes the CPL when program control is transferred to Code Segment with
Different privilege level.
⮚ A task's CPL may only be changed by control transfers through gate descriptors to a code
segment with a different privilege level.
⮚ An application program running at PL = 3 may call an operating system routine at PL = 1
(via a gate) which would cause the task's CPL to be set to 1 until the operating system
routine was finished.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 20

 Requested Privilege Level (RPL)

⮚The privilege level of the original supplier of the selector.

⮚RPL is determined by the least two significant bits of a selector of
data or code segment to be accessed.
⮚The processor checks the RPL along with the CPL to determine
if access to a segment is allowed.
⮚If the RPL > CPL, then the RPL overrides the CPL and vice versa.
⮚RPL is used to insure that privileged code does not access a
segment on behalf of Application program, unless the program
itself has access privilege to that segment.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 21
 Requested Privilege Level (RPL)
⮚RPL of a segment selector for a data segment is under
software control.
⮚For example, an application program running at a CPL = 3 can
set the RPL for a data segment selector to 0. With the RPL set to
0, only the CPL checks, not the RPL checks, will provide
protection against deliberate, direct attempts to violate privilege-
level security for the data segment.
⮚ To prevent these types of privilege-level-check violations, a
program or procedure can check access privileges whenever it
receives a data-segment selector from another procedure.
(ARPL-access privilege).
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 22
 Privilege Level check for DS
⮚Processor performs privilege check (CPL,RPL,DPL)
⮚To access operand from Data Segment, the segment selector
must be loaded into the data segment register (DS,ES,FS or GS) or SS
⮚Processor loads segment selector into segment register if the DPL
is numerically greater than or equal to both the CPL and RPL,
otherwise General Protection fault is generated and segment
2
register is not loaded
1
DPL >= Max(CPL and RPL)
3>=MAX (2 and 1) 3
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 23
 Privilege Level check for DS
Code Accessing from Data segment
DPL >= Max(CPL, RPL)

OR
DPL >= Max(CPL and RPL)

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 24

 Privilege Level check for DS:
Code Segment ------(Accessing)----🡪 Data Segment
Code Accessing Data
2 DPL >= Max(CPL, RPL)

DPL =3
1
CPL =2
RPL = 1

3
⮚To access operand from Data Segment, the segment selector must
be loaded into the data segment register (DS,ES,FS or GS) or SS

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 25

 Privilege Check
Code Segment ------(Accessing)----🡪 Data Segment
Code Accessing Data
DPL >= Max(CPL, RPL)
⮚ Code Segment ----(Accessing)---🡪 Conforming Code Segment [C=1]

CPL >= DPL

⮚ Code Segment ------(Accessing)----🡪 Non Conforming Code Segment

CPL = DPL
Achieved by checking conditions based on
RPL, DPL and CPL

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 26

Privilege Level Checking When Accessing Data Segments
Question: Can Code Segment A able to access DS E using E1
selector?
Quiz: Answer is in Able or Unable

Q1. CS- A ------to access DS E using E1 selector

Q1. Ans: CS –A able to access DS E using E1 selector

Q2. CS- B ----- to access DS E using E2 selector

Q2. Ans: CS- B able to access DS E using E2 selector

Q3. CS C is ------ to access DS E using E3 selector

Q3. Ans: CS C is unable to access DS E using E3 selector

Q4. CS D is ------ to access DS E using E3 selector
Q4.Ans: CS D is unable to access DS E using E3 selector

DPL >= Max(CPL and RPL)

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 27
 Data Segment : Privilege Access (Answer)
• CS – A able to access DS E using E1
selector as,
CPL of A and RPL of E1 = DPL E

• CS- B able to access DS E using

selector E2 as,
CPL of B and RPL of E2 < DPL of E

DPL >= Max(CPL,

RPL)

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 28

 Data Segment : Privilege Access (Answer)

• CS C is unable to access DS E using

selector E3 as,
CPL of CS C and RPL of E3 > DPL of DS E

DPL >= Max(CPL,

RPL)

• CS D is unable to access DS E using

selector E3 as
CPL of CS D < DPL of DS E

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 29

 Privilege Level check : Data Segment
⮚When CPL 0: • If max (CPL,RPL) <= DPL, Access allowed.
• Assume CPL=RPL
⮚ Data Segment at all PL are accessible
⮚When CPL 1: CPL Data segments
DPL >=(DPL)
accessed Max(CPL and RPL)
⮚ DS at PL 1 through 3 are accessible
0 0,1,2,3
1 1,2,3
⮚When CPL 2: 2 2,3
⮚ DS at PL 2 to 3 are accessible 3 3

RPL of segment selector can always

⮚When CPL 3: override the addressable domain of
⮚ DS at PL 3 is only accessible program
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 30
 Accessing Data in Code Segments
In some instances it may be desirable to access data structures that are contained in a
code segment.
1. Method 1: Load a data-segment register ⮚ Method 1: The same rules for accessing
data segments apply to method 1.
with a segment selector for a
nonconforming, readable code segment. DPL >= Max(CPL, RPL)
2. Method 2: Load a data-segment register ⮚ Method 2 is always valid because the
privilege level of a conforming code
with a segment selector for a conforming,
segment is effectively the same as the
readable, code segment.
CPL, regardless of its DPL.
3. Method 3: Use a code-segment override ⮚ Method 3 is always valid because the
prefix (CS) to read a readable, code DPL of the code segment selected by
segment whose selector is already loaded in the CS register is the same as the
the CS register. CPL.
• E.g.9/25/2024
MOV BL,CS:[ESI] Unit 3 MMA-CSE2PM02A 2024-25 S3 31
 Privilege Level Checking When Transferring
Program Control Between Code Segments
Program control transfers are carried out with the-----------------
⮚ JMP
⮚ CALL
⮚ RET (Return)
⮚ INT n
⮚ IRET (interrupt return) instructions (The IRET instruction is used at the end of an
interrupt service procedure to return execution to the interrupted program. )
⮚ The Exception and Interrupt mechanisms.

The NEAR forms of the JMP, CALL, and RET instructions transfer
program control within the current code segment, so privilege-level
checks are not performed.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 32
 Privilege Level Checking When Accessing Other Code Segments
⮚ Code segments can be either conforming or nonconforming.
⮚ A transfer of execution from code (e.g. CPL=3) into a more privileged conforming
segment(e.g. CPL=1) allows execution to continue at the current privilege level
(i.e. CPL=3).
⮚ A transfer of execution from code segment into a nonconforming segment at a
different privilege level results in a general-protection exception (#GP), unless a
call gate or task gate is used

• Non conforming code segment

• RPL is replaced by DPL after successful access • Conforming Code Segment
• The same field indicates CPL • RPL field status is retained
• DPL = CPL • The CPL >= DPL

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 33

 Privilege Level Checking When Transferring
Program Control Between Code Segments
A JMP or CALL instruction can reference another code segment in any
of four ways:
⮚The target operand contains the segment selector for the target code
segment.
⮚The target operand points to a call-gate descriptor, which contains the
segment selector for the target code segment.
⮚The target operand points to a TSS, which contains the segment selector
for the target code segment.
⮚The target operand points to a task gate, which points to a TSS, which
in turn contains the segment selector for the target code segment.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 34

 Code accessing Code (Non conforming code segments)
Code Segment ---(Accessing)--🡪 Non Conforming Code Segment [C=0]
Direct Calls or Jumps to Code Segments

Rule
DPL = CPL

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 35

 Code accessing Code (Non confirming code segments)
Running
Code Rule
Code Segment Register DPL = CPL
Code Segment A
CPL = 3
RPL = 3
X

Code Segment Register Code Segment B

Code Segment
RPL = 2 DPL = 2
CPL = 2

Code Segment
X One code segment can access another non
conforming code segment with different
Data Segment Register
CPL = 1 RPL = 1 privilege level only using a special descriptor
called “Call Gate” which is discussed later in
the unit.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 36
 Code accessing Code (Conforming Code Segments)
Code Segment ------(Accessing)----🡪 Conforming Code Segment [C=1]
⮚Can be called by a code with CPL >= DPL of destination code
segment
⮚Conforms to the privilege level of the caller code
⮚E.g. If PL 3 code transfers control to a conforming code segment
then conforming code runs at CPL=3.
⮚CPL does not change
⮚Allow sharing by codes with different privilege levels
⮚Application – math libraries

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 37

Example: Code accessing Code:
Conforming and Non Conforming Code Segment
Q: Can Code Segment A able to access CS
C using C1 selector?
Ans: Able
Code segment D is a conforming code
segment. Therefore, calling procedures
in both code segment A and B can
access code segment D (using either
segment selector D1 or D2,
respectively), because they both have
CPLs that are greater than or equal to
the DPL of the conforming code
segment.
For conforming code segments, the
Non confirming code segment DPL represents the numerically lowest
Confirming Code Segment
RPL is replaced by DPL after successful
access RPL field status is retained privilege level that a calling procedure
The same field indicates CPL CPL >= DPL may be at to successfully make a call
DPL = CPL to the code segment.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 38
 Code accessing Code (Conforming Code Segments:) Summary

⮚ Can be defined with different privilege levels.

⮚ Do not impart additional privileges.
⮚ Do not remove existing privileges.
⮚ Do not alter RPL bits in the Code segment register.
⮚ Can be shared by code at all privilege levels.
⮚ Application – math libraries, exception handlers
⮚ Can be called by a code with CPL >= DPL of destination code segment.
⮚ the processor generates a general-protection exception (#GP) only if the CPL is less
than the DPL.
⮚ The segment selector RPL for the destination code segment is not checked if the
segment is a conforming code segment.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 39
System
Descriptor
Types
if S=0

Call Gates

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 40

 Call Gate Descriptor

⮚ System descriptor
⮚ Do not define any memory space
⮚ Defines entry points in a more privileged
code to which control can be transferred
⮚ Only way to inter level transfer control
⮚ Must be invoked using CALL instruction
(therefore name is CALL Gate)

Target DPL <= Max(RPL, CPL) <= Gate DPL

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 41

Accessing Non Conforming Code Segment using Call Gates
Target DPL <= Max(RPL, CPL) <= Gate DPL

RPL

Gate DPL

Target DPL

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 42

 Code Segment ---(Accessing)--🡪 Non Conforming Code Segment
[C=0] using Call Gates
Provides controlled transfers of program control between different privilege levels
⮚ It specifies the code segment to be accessed.
⮚ It defines an entry point for a procedure in the specified code segment.
⮚ It specifies the privilege level required for a caller trying to access the
procedure.
⮚ If a stack switch occurs, it specifies the number of optional parameters to be
copied between stacks.
⮚ It defines the size of values to be pushed onto the target stack: 16-bit gates
force 16-bit pushes and 32-bit gates force 32-bit pushes.
⮚ It specifies whether the call-gate descriptor is valid.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 43

 Privilege Check Rules for using Call Gates
CALL Gate- DPL indicates numerically
highest privilege level that the currently
executing program can be and still able to
access the call gate.

Ex if DPL value in a call gate descriptor

is 1 then only programs running at a
CPL 0 or 1 can access the Call gate i.e.
CPL <= DPL(Call gate)
Target/
Target DPL <= Max(RPL, CPL) <= Gate DPL Target DPL <= Max(RPL, CPL) <= Gate DPL

Only calls to the more privileged code

segment are allowed.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 44

 Privilege Check Rules for using Call Gates: Example
1.Can Nonconforming Code
Segment E access Code
Segment A through call gate A
and Gate selector A? Justify.
2. Can Nonconforming Code
Segment E access Code
Segment B through call gate B
and Gate selector B1? Justify.

2. Can Code Segment A access

data from Code Segment D
through call gate a and Gate
selector A? Justify.
3. Can Code Segment B access
data from Code Segment D
through call gate a and Gate
selector B1? Justify.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 45

 Rules

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 46

 Stack Switching

⮚ Whenever a call gate is used to transfer program control to a more

privileged nonconforming code segment (that is, when the DPL of
the nonconforming destination code segment is less than the CPL),
the processor automatically switches to the stack for the destination
code segment’s privilege level.

⮚ This stack switching is carried out to prevent more privileged

procedures from crashing due to insufficient stack space. It also
prevents less privileged procedures from interfering (by accident or
intent) with more privileged procedures through a shared stack.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 47

 Rules to access other code segment
CPL Non Conforming Conforming Code Call Gate Code Segment
(calling program) Code Segment Segment Descriptor using Call Gate
CPL=DPL CPL>=DPL (called program) ( called
( called program) ( called program) program)

0 0 0 0,1,2,3 0
1 1 0,1 1,2,3 0,1
2 2 0,1,2 2,3 0,1,2
3 3 0,1,2,3 3 0,1,2,3

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 48

 How to apply rules?
⮚A program calls an external function ‘abc’
⮚Replaced by logical address seg selector:
⮚Offset 001B:0000H
⮚ 0000 0000 0001 1011
⮚Index = 3, TI=0, RPL=3
⮚GDT is accessed with entry number 3

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 49

 Possible segment descriptors at index 3
1. It is nonconforming segment with DPL=3; access
allowed
2. It is conforming code segment with DPL=2; Access
allowed but CPL=3 only; so no change in the accessible
segments
3. It is a Call Gate Descriptor with DPL=3; the selector for
code segment is accessed and DPL is checked if DPL of
code segment = 2; access is allowed, CPL changes to 2 but
care is taken that accessible segments are same as CPL=3

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 50

 Privilege Checking Prog. A cannot access
Prog. X since no call
gate available for A to
Prog. C can access access program at PL0
Prog. X since call
gate available for C to A
access program at PL0
B Prog. B can access
C
Prog. X since call
PL3 PL2 PL1 gate available for B to
PL0
Gate access program at PL0
for X
X

Gate
for X

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 51

 Privileged Instructions
Some instruction are protected from use by application program.
They can be executed with PL0
1. LGDT- load GDT Register 9. INVLPG- invalidate TLB entry
2. LLDT- Load LDT Register 10. HLT- halt Processor
3. LTR- load task register 11. RDMSR-read model specific register
4. LIDT- load IDT register
12. WRMSR- write model specific register
5. MOV (Control Registers) : MOV CRn, reg;
13. RDPMC-read performance monitoring
MOV reg, CRn.
counter
6. LMSW- load Machine Status Word (Lower
16 bits of CR0 register) 14. RDTSC-read time stamp counter
7. CLTS- clear task switch flag in CR0 15. MOV ( Debug registers) : MOV DRn, reg;
8. WBINVD-invalidate cache with write back MOV reg,DRn;
16. INVD- invalidate cache, without writeback
9/25/2024 52
Unit 3 MMA-CSE2PM02A 2024-25 S3
 Page Level Protection
• The paging mechanism distinguishes between two levels of
protection:
⮚ User which corresponds to level 3 of the segmentation based protection
⮚ supervisor which encompasses all of the other privilege levels (0, 1, 2).
• Programs executing at Level 0, 1 or 2 bypass the page protection,
although segmentation based protection is still enforced by the
hardware.
• The U/S and R/W bits are used to provide User/Supervisor and
Read/Write protection for individual pages or for all the pages
in a table

Unit 3 Microprocessor and Microcontroller_CET2004B

11/3/2023 53
2023-24 S3
 Page Level Protection

Unit 3 Microprocessor and Microcontroller_CET2004B

11/3/2023 54
2023-24 S3
 Timesharing
⮚Allows multiple users to
use the same computer.
⮚Provides economical use
of processing resources.
⮚Is invisible to the users.
⮚Can work for any number
of users.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 55

 Elements required to maintain Timesharing
⮚ When to change from one user to the
next?
⮚ When a user’s time slice expires,
computer must store the current state of
the program and restart the next user’s
program as it was left when its time slice
expired. context

⮚ To save the current state of program is

called context and changing to next
user’s program is called context switch. context switch

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 56

 A context switch

⮚ Is necessary to perform timesharing saves the state of

the current program.

⮚ Loads the state of the program allows any program to be

restarted at any time.

⮚The basic unit of multitasking is the task.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 57

 What is a Task?
⮚ A program or a group of program defined by OS as a task.
⮚ For Multiuser system, a task can be assigned to each user.
⮚ A task is a unit of work that a processor can dispatch,
execute, and suspend.
⮚ When operating in protected mode, all processor execution
takes place from within a task.
⮚ A task is invoked by an interrupt, exception, jump, or call.
⮚ Even simple systems must define at least one task.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 58

 Task Structure
TSS requires 104 bytes
(68 H) memory space.

TSS provides a storage place

for task state information

The segment selector for

the TSS must be loaded
into the Task Register TR
(using the LTR instruction).

TASK MANAGEMENT DATA STRUCTURES

1.Task State Segment (TSS)

2.Task State Segment Descriptor
3.Task Register (TR)
4.Task Gate Descriptor
5.NT flag in the EFLAGS register.
In multitasking systems, the TSS also provides a mechanism for linking tasks.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 59

 Task Structure

Question:
Question:
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 60
 Task Structure
⮚ A task is made up of two parts: a task execution space and a task-state
segment (TSS). TSS requires 104 bytes (68 H) memory space.
⮚ The task execution space consists of a code segment, a stack segment, and
one or more data segments.
⮚ The TSS specifies the segments that make up the task execution space
and provides a storage place for task state information.
⮚ In multitasking systems, the TSS also provides a mechanism for linking
tasks.
⮚ A task is identified by the segment selector for its TSS. When a task is
loaded into the processor for execution, the segment selector, base address,
limit, and segment descriptor attributes for the TSS are loaded into the
Task Register (TR).
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 61
 Static set (Green Colour)
TSS- Task State Segment (TSS requires 104 bytes (68 H) memory space)
⮚ It is that where processor reads but
does not change.
⮚ This set includes the fields that store: The
selector of the task's LDT.
⮚ The register (PDBR) that contains the base
address of the task's page directory (read only
when paging is enabled).
⮚ Pointers to the stacks for privilege levels 0-2.
⮚ The T-bit (debug trap bit) which causes the
processor to raise a debug exception when a
task switch occurs.
⮚ The I/O map base address
Dynamic set (Blue Colour)
⮚ where processor updates with each switch from the
task.
⮚ This set includes the fields that store: The general
registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
⮚ The segment registers (ES, CS, SS, DS, FS, GS).
⮚ The flags register (EFLAGS).
back link field ⮚ The instruction pointer (EIP).
26 Rows, each row=4 bytes ⮚ The selector of the TSS (back link field) of the previously
executing task (updated only when a return is expected).

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 62

 Task State (or context)
• The task’s current execution space, defined by the segment selectors in the
segment registers (CS, DS, SS, ES, FS, and GS).
• • The state of the general-purpose registers.
• • The state of the EFLAGS register.
• • The state of the EIP register.
• • The state of control register CR3.
• • The state of the Task Register (TR).
• • The state of the LDTR register.
• • The I/O map base address and I/O map (contained in the TSS).
• • Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS).
• • Link to previously executed task (contained in the TSS).

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 63

 Executing a Task
• Software or the Processor can dispatch a task for execution
in one of the following ways:
⮚A explicit (direct) call to a task with the CALL instruction.
⮚A explicit (direct) jump to a task with the JMP instruction.
⮚An implicit (indirect) call (by the processor) to an interrupt-
handler task.
⮚A return (initiated with an IRET instruction) when the NT flag
in the EFLAGS register is set.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 64

 Executing a Task
⮚ When a task is dispatched for execution, a task switch automatically
occurs between the currently running task and the dispatched task.
⮚ During a task switch, the execution environment of the currently
executing task (called the task’s state or context) is saved in its TSS
and execution of the task is suspended.
⮚ The context for the dispatched task is then loaded into the processor
and execution of that task begins with the instruction pointed to by the
newly loaded EIP register.
⮚ If the currently executing task (the calling task) called the task being
dispatched (the called task), the TSS segment selector for the calling task
is stored in the TSS of the called task to provide a link back to the
calling task.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 65

TASK MANAGEMENT DATA STRUCTURES
1. Task State Segment (TSS)
2. Task State Segment Descriptor
3. Task Register (TR)
4. Task Gate Descriptor
5. NT flag in the EFLAGS register.
In protected mode:
⮚TSS and TSS descriptor must be created for at least one
task.
⮚The segment selector for the TSS must be loaded into the
Task Register TR (using the LTR instruction).
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 66
 1. TSS- Task State Segment
⮚Each task must have a TSS associated with
it.
⮚TSS stores all the information that the
processor needs in order to manage a task.
⮚The current TSS is identified by a special
register the Task State Segment Register
(TR).
⮚This register contains a selector referring to
the task state segment descriptor that
defines the current TSS.
⮚The fields of a TSS are divided into two
main categories: Dynamic fields and Static
fields.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 67
 TSS
1. A dynamic set that the processor updates with each switch from the task.
This set includes the fields:
⮚ The General Purpose Registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
⮚ These are saved in the same order in which PUSHAD (Push All double General-Purpose
Registers:Pushes the contents of the general-purpose registers onto the stack) instruction saves
them.
⮚ The segment registers (ES, CS, SS, DS, FS, GS).
⮚ The flags register (EFLAGS).
⮚ The instruction pointer (EIP).
⮚ Previous task link field (back link field):
⮚ Contains the segment selector for the TSS of the previous task permits a task
switch back to the previous task to be initiated with an IRET instruction.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 68

 Static set
A static set that the processor reads but does not change. These fields are set up
when a task is created. The fields of this set are:

⮚The selector of the task's LDT.

⮚The CR3 register (PDBR): contains the base address of the task‘s page directory
(read only when paging is enabled).
⮚Pointers to the stacks for privilege levels 0-2.
⮚ These stack pointers consist of a logical address made up of the segment selector
for the stack segment (SS0, SS1, and SS2) and an offset into the stack (ESP0,
ESP1, and ESP2).
⮚Note that the values in these fields are static for a particular task; whereas, the SS
and ESP values will change if stack switching occurs within the task.
⮚The T-bit (debug trap bit) which causes the processor to raise a debug exception
when a task switch occurs.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 69
 Static set cont-
⮚ The I/O map base address
⮚ Contains a 16-bit offset from the base of the TSS to the I/O
permission bit map and interrupt redirection bitmap.

⮚ When present, these maps are stored in the TSS at higher

addresses.

⮚ The I/O map base address points to the beginning of the I/O
permission bit map and the end of the interrupt redirection bit map.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 70

 Two classes of TSS format
Static set Dynamic set
⮚ It is that where processor reads ⮚ where processor updates with each
but does not change. switch from the task.
⮚ This set includes the fields that store: ⮚ This set includes the fields that
The selector of the task's LDT. store: The general registers (EAX,
ECX, EDX, EBX, ESP, EBP, ESI,
⮚ The register (PDBR) that contains the
EDI).
base address of the task's page directory
⮚ The segment registers (ES, CS, SS,
(read only when paging is enabled).
DS, FS, GS).
⮚ Pointers to the stacks for privilege levels
⮚ The flags register (EFLAGS).
0-2.
⮚ The T-bit (debug trap bit) which causes ⮚ The instruction pointer (EIP).
the processor to raise a debug exception ⮚ The selector of the TSS (back link field)
when a task switch occurs. of the previously executing task
⮚ The I/O map base address (updated only when a return is
expected).
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 71
 B=0 Available (Non Busy Task )
B=1 Busy Task

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 72

 2. Task State Segment Descriptor

B=0 Non Busy Task (Available)

B=1 Busy Task

Fig. 2 :TSS Descriptor (32 bit)

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 73
 TSS Descriptor
⮚ The TSS, like all other segments, is defined by a segment
descriptor, it holds base address of TSS assigned to that task.
⮚ TSS descriptors may only be placed in the GDT; they cannot
be placed in an LDT or the IDT.
⮚ An attempt to identify a TSS with a selector that has TI=1
(indicating the current LDT) results in an exception.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 74

 TSS Descriptor
⮚The B-bit in the type field indicates whether the task is busy.
⮚A type code of 9 (1001 B) indicates a non-busy (Available) task;
⮚A type code of 11(1011 B) indicates a busy task.
⮚The processor uses the Busy bit to detect an attempt to call a task whose
execution has been interrupted.
⮚Tasks are not recursive.
⮚The BASE, LIMIT, and DPL fields and the G-bit and P-bit have
functions similar to their counterparts in data- segment descriptors.
⮚The Limit field must have a value equal to or greater than 103 (67H),
one byte less than the minimum size of a task state. An attempt to switch to
a task whose TSS descriptor has a limit less than 67H generates an
exception.
⮚ Max(CPL,RPL) <= TSS DPL
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 75
 How does Processor know which TSS to save the old task in?

⮚ In case of a Task switch, processor saves its complete context in a

TSS and load a new context from another TSS.
⮚ When a new task begins, Task Register is updated with a selector
to new task’s TSS.
⮚ Current context is saved in the TSS pointed to by Task Register.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 76

 3. TR: Task Register
⮚ It holds 16 bit selector pointing to TSS
descriptor (in GDT) of current task
being executed by processor.
⮚ The task register has both a "visible"
portion and an "invisible" portion.
⮚ The selector in the visible portion
selects a TSS descriptor in the GDT.
⮚ The processor uses the invisible portion
to cache the base and limit values from
the TSS descriptor.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 77

 Task Register cont-

Fig. 3 :Task Register

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 78
 Task Register cont-

• LTR (Load task register) :

⮚ Loads the visible portion of the task register with the operand, which must index
to a TSS descriptor in the GDT.
⮚ The LTR instruction also loads the invisible portion with information from the
TSS descriptor.
⮚ The LTR instruction is a privileged instruction; it may be executed only when
the CPL is 0.
⮚ The LTR instruction generally is used during system initialization to put an
initial value in the task register; afterwards, the contents of the TR register are
changed by events which cause a task switch.
• STR (Store task register):
⮚ Stores the visible portion of the task register in a general register or memory.
⮚ STR is not privileged.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 79
 Virtual memory to each task
• GDT- 8191 descriptors
• LDT- 8192 descriptors
• Each descriptor can define a segment up to 4GB
• Total memory = 4GB (8191+8192)
= 4GB x 16381
= 64 Tera Bytes

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 80

 4. Task Gate
⮚In Task switch, a program is deliberately putting itself
to sleep and awakening another.
⮚The new task receives no parameters from the old
task.
⮚Two tasks are totally separate.
⮚Task Switch can take place either through TSS
descriptor or through Task Gate.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 81

 5. Task Gate Descriptor

Fig. 5 :Task Gate Descriptor

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 82

How both a Task Gate in the LDT and a Task Gate in an IDT can identify the same task.

Task Gate
Descriptor

Task gate can reside

anywhere in GDT, LDT or
IDT.

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 83

 Task Gate Descriptor
⮚ A task gate descriptor provides an indirect, protected reference to a TSS. Figure 5
illustrates the format of a task gate descriptor.

⮚ The SELECTOR field of a task gate must refer to a TSS descriptor. The
value of the RPL in this selector is not used by the processor.

⮚ The DPL field of a task gate controls the right to use the descriptor to cause a task
switch.
⮚ A procedure may not select a task gate descriptor unless the maximum of the
selector's RPL and the CPL of the procedure is numerically less than or equal to
the DPL of the descriptor.
Max(CPL,RPL) <= Task Gate DPL
⮚ Task Gate can reside anywhere in GDT, LDT or IDT.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 84
 Task Switching
The Processor switches execution to another task in
any of Four cases:
1. The current task executes a JMP or CALL that refers to a TSS
descriptor.
2. The current task executes a JMP or CALL that refers to a Task Gate.
3. An interrupt or exception vectors to a task gate in the IDT.
4. The current task executes an IRET when the NT flag is set.

Question: Which four methods are used to invoke a task? Describe the steps involved in task
switching. What is the significance of NT bit and back link field?

9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 85

 A task switching operation involves these steps:
1. Checking that the current task is allowed to switch to
the designated task (New task).
2. Checking that the TSS descriptor of the new task is
marked present and has a valid limit.
3. Saving the state of the current task.
4. Loading the task register with the selector of the
incoming (New) task’s TSS descriptor
5. Loading the incoming (New) task’s state from its TSS
and continue execution.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 86
 6. NT : Nested Task
⮚ The previous task link field of
the TSS (sometimes called the
“back link”) and the NT flag in
the EFLAGS register are used to
return execution to the previous
task.
⮚ The NT flag indicates whether the
currently executing task is nested
within the execution of another
task.
⮚ The previous task link field of the
current task's TSS holds the TSS
selector for the higher-level task .
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 87
 IOPL Flag
• This two-bit field applies to Protected Mode.
⮚ IOPL indicates the numerically maximum CPL value permitted to
execute I/O instructions without generating an exception fault or
consulting the I/O Permission Bitmap.
⮚ Task switches can always alter the IOPL field, when the new flag image
is loaded from the incoming task's TSS.
⮚ I/O instructions can be unconditionally performed when CPL <= IOPL.
⮚ The I/O instructions are IN, OUT, INS (Input from Port to String),
OUTS (Output String to Port), REP.
⮚ When CPL > IOPL, and the current task is associated with a TSS, the I/O
Permission Bitmap (TSS) is consulted on whether I/O to the port is
allowed for that task.
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 88
9/25/2024 Unit 3 MMA-CSE2PM02A 2024-25 S3 89