Finfet Technology

FINFET
TECHNOLOGY
CONTENTS
• INTRODUCTION TO VLSI TECHNOLOGY
• MOORE’S LAW AND IT’S LIMITATIONS
• LIMITATIONS ON MOSFET TECHNOLOGY
• SHORT CHANNEL EFFECT IN MOSFET
• INTRODUCTION TO FINFET
• WHY WE NEED FINFET
• STRUCTURE OF FINFET
• FABRICATION PROCESS OF FINFET
• ADVANTAGES AND DISADVANTAGES OF FINFET
• APPLICATIONS OF FINFET
• CONCLUSION
INTRODUCTION TO VLSI
Very-large-scale integration (VLSI)
is the process of creating integrated
circuits by combining thousands of
transistors into a single chip.
VLSI began in the 1970s when

complex semiconductor
and communication technologies were
being developed.
3
MOSFET TECHNOLOGY
The growth of digital
technologies like the
microprocessor has provided the
motivation to advance MOSFET
technology faster than any other
type of silicon-based transistor.
A big advantage of
MOSFETs for digital
switching is that the oxide
layer between the gate and the
channel prevents DC current
from flowing through the gate,
further reducing power
consumption and giving a very
large input impedance
MOORE’S LAW
“”THE NUMBER OF TRANSISTORS INCORPORATED IN A CHIP

WILL APPROXIMATELY DOUBLE EVERY 24 MONTHS.“
—GORDON MOORE
LIMITATIONS ON MOSFET
TECHNOLOGY
• Short channel effects limiting
scaling into sub nanometer
regime.
• Oxide thickness cannot be

scaled down further, problems
of tunneling.
• performance and power

dissipation need to be
improved.
• Need to keep silicon

technology
as the base technology when
innovating future devices; cost
is an important factor
7
Power Consumption Problems
1.Not just a chip and package thermal
issue.
2.ICs use a few% of world’s electricity
today and
• Power per chip is growing.
• IC units in use also growing.
3.If power consumption is not reduced,
industry future growth is at risk.
Long channel Transistor(MOSFET)
GGaa
Ctegte Insulator
Source Drain
Energy Band Diagram

Vg
C OX
Ec
Ev Drain
SHORT CHANNEL EFFECTS IN MOSFET
 It is an effect whereby a MOSFET in which the

channel length is the same order of magnitude as the
depletion layer widths of source & drain junctions,
behaves differently from the other MOSFETs.
 As the channel length ‘l’ is reduced to increase both

the operation speed and the number of components per
chip, the so called SCE occurs.
SHORT CHANNEL-PROBLEMS
10-3 GGaa
m)
(A/
10-5 Ctegte Insulator

D
S
10-7 Smaller
Size Source Drain
Current, I
size
shrink Cd
Drain
-9
10
or
10-11
larger Vd
Gate 0.3
0.0 Voltage,
0.6 V
(V)
0.9
 MOSFET becomes “resistor” at very small L –- Drain

G
competes with Gate
S
to control the channel barrier.
Reducing EOT is Not Enough
Gate
Source Drain
Leakage Path
Gate cannot control the leakage current

paths that are far from the gate.
 In planar devices on-current is mostly carried

out in a top layer.
 Body current is a source of leakage when the
device is off.
One Way to Better Vt and S
The gate controls a thin body from
more than one side. Gate Length
Gate
Source
Source Drain
Gate
Drain
FinFET body is a  Fin Height
Fin Width
thin fin
Introduction
Double-gate FET (DGFET)
->Reduce Short Channel Effects (SCEs)

->Reduce Drain-Induced-Barrier-Lowering
->Improve Sub threshold Swing S
Medici-predicted DIBL and subthreshold swing versus

effective channel length for DG and bulk-silicon nFETs
Three Types of Double-gate FET
Quasi-CMOS structure
Relatively simple FAB
INTRODUCTION TO FINFET
 The term “FINFET” describes a non-planar, double
gate transistor built on an SOI substrate, based on the
single gate transistor design.
 The important characteristics of FINFET is that the

conducting channel is a thin Si “fin”, which forms the
body of the device.
 The thickness of the fin determines the effective

channel length of the device.
HISTORY OF FINFET
 FINFET is a transistor design first developed by
Chenming Hu and his colleagues at the University of
California at Berkeley, which tries to overcome the worst
types of SCE(Short Channel Effect).
 Originally, FINFET was developed for use on Silicon-

On-Insulator(SOI).
 SOI FINFET with thick oxide on top of fin are called

“Double-Gate” and those with thin oxide on top as well
as on sides are called “Triple-Gate” FINFETs
WHY WE NEED FINFET ?
Planar does’nt scale beyond gate length of 25nm
And also gate oxide does’nt scale.
If we assume we have a gate dielectric of thickness

zero, Then also we cannot control SEC’S.
For the double gate soi mosfet’s, The gates control the
energy barrier between source and drain effectively.
FINFET
WHAT DOES FINFET LOOK’S LIKE?
Effective channel width W = Tfin + 2×Hfin

Effective channel length Leff = Lgate + 2×Lext
GENERAL LAYOUT & MODE OF
OPERATION
 The basic electrical layout and
mode of operation of a FINFET does
not differ from a traditional FET.
 There is one source and one drain

contact as well as a gate to control the
current flow.
 In contrast to planar MOSFET, the

channel b/w source and drain is build
as 3D bar on top of the Si substrate
and are called fin.
“FINS”
 The fin is used to form the raised Gate Length
channel.
Source
As the channel is very thin the gate
has a great control over carriers within
it, but, when the device is switched.
Drain
The thickness of the fin (measured in
the direction from source to drain)
Fin Height
determines the effective length of the
Fin Width
device.
“FINS”
 The fin is used to form the raised channel.
 As the channel is very thin the gate has a great

control over carriers within it, but, when the
device is switched on, the shape limits the
current through it to a low level.
 The thickness of the fin (measured in the

direction from source to drain) determines the
effective length of the device.
Fabrication - Process Flow
“Easy in concept----Tough to build”
(a) SiN is deposited as a hard mask,

SiO2 cap is used to relieve the
stress.
(b) Si fin is patterned
(c) A thin sacrificial SiO2 is grown
(d) The sacrificial oxide is stripped

completely to remove etch damage
(e) Gate oxide is grown
(f) Poly-Si gate is formed

10 nm gate length, 12 nm fin width
ADVANTAGES OF FINFET
Higher technological maturity than planar DG
 Suppressed Short Channel Effect(SCE)
 Better in driving current
More compact
 Low cost
DISADVANTAGES OF FINFET
Reduced mobility for electrons
 Higher source and drain resistances
 Poor reliability
APPLICATIONS
Low power
design in digital
circuit, such as
RAM, because of
its low off-state
current.
Power amplifier
or other
application in
analog area which
requires good
linearity.
CONCLUSION
Double-gate FET can reduce Short Channel Effects and FinFET

is the leading DGFET.
Optimization design includes geometry, S-D fin-extension

doping, dielectric thickness scaling, threshold voltage control….
Fabrication of FinFET is compatible with CMOS process
10 nm gate length, 12 nm fin width device has been

fabricated and shows good performance

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FINFET

VLSI began in the 1970s when

“”THE NUMBER OF TRANSISTORS INCORPORATED IN A CHIP

• Oxide thickness cannot be

• performance and power

• Need to keep silicon

Energy Band Diagram

 It is an effect whereby a MOSFET in which the

 As the channel length ‘l’ is reduced to increase both

10-5 Ctegte Insulator

 MOSFET becomes “resistor” at very small L –- Drain

Gate cannot control the leakage current

 In planar devices on-current is mostly carried

->Reduce Short Channel Effects (SCEs)

Medici-predicted DIBL and subthreshold swing versus

 The important characteristics of FINFET is that the

 The thickness of the fin determines the effective

 Originally, FINFET was developed for use on Silicon-

 SOI FINFET with thick oxide on top of fin are called

And also gate oxide does’nt scale.

If we assume we have a gate dielectric of thickness

Effective channel width W = Tfin + 2×Hfin

 There is one source and one drain

 In contrast to planar MOSFET, the

 As the channel is very thin the gate has a great

 The thickness of the fin (measured in the

(a) SiN is deposited as a hard mask,

(b) Si fin is patterned

(c) A thin sacrificial SiO2 is grown

(d) The sacrificial oxide is stripped

(e) Gate oxide is grown

(f) Poly-Si gate is formed

Higher technological maturity than planar DG

 Suppressed Short Channel Effect(SCE)

 Better in driving current

Reduced mobility for electrons

 Higher source and drain resistances

Double-gate FET can reduce Short Channel Effects and FinFET

Optimization design includes geometry, S-D fin-extension

Fabrication of FinFET is compatible with CMOS process

10 nm gate length, 12 nm fin width device has been

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