ASIC Physical Design

Outline
• ASIC Design Flow
• Physical Design
— Introduction to Physical Design
— Physical Design Inputs
— Physical Design Flow
 Import Design & Partitioning
 Floor-planning & Power planning
 Placement & Placement Optimizations
 CTS & CTS Optimizations
 Routing & Routing Optimizations
 Physical Verification (DRC, LVS, ERC)
 DFM Checks
 Formal Verification (LEC)
 Parasitic Extraction (RC Extraction)
 Timing Analysis (STA),
 Power Analysis & IR Drop Analysis
 Tape-out
 ASIC Physical Design
ASIC Design Flow
Partitioning
System Specification
Floor Planning
ENTITY test is Architectural Design
port a: in bit;
end ENTITY RTL Design Placement
test; and Verification
Synthesize
Design the
F F F FF F
FFFFFF FFFFFF FFF CTS
FFF F F F F F F

Placement
Routing & Routing

PHYSICAL D
DRC
ERC LVS ESIGN
Signoff Parasitic Extraction

Mask Preparation Physical Verification

Fabrication Formal Verification

Packaging and
Testing Static Timing Analysis

Chip Power Analysis

IR-Drop Analysis

Link: ASIC Design Flow Diagram Courtesy: Wikipedia

Physical Design Introduction
• Structural Representation to Physical Implementation
i.e., Netlist to GDSII
• Stages
— Placement and Routing (PnR)
— Signoff
• Objectives
— Timing
— Congestion
— Area
— Power
• Possible Issues
— Timing Violations
— Congestion Issues
— Design Rule Violations
 ASIC Physical Design
Physical Design Inputs
• Netlist (.v or .vhd)
— Netlist contains — Netlist also consists of
 Std. Cell instance – Name & Drive  Ports of Standard Cells and Macros
Strength  Interconnection details
 Macros & Memories instances
• Constraints
— Types of Constraints — Synopsys Design Constraints
 Design Rule Constraints (SDC)
 Optimization Constraints — Timing Constraints
— Design Rules from the Fab.  Clock Definition (Time Period, Duty Cycle)
 Max. Cap./ Transition/Fanout  Timing Exceptions (False Paths,
 Clock Uncertainties Asynchronous Paths)
— Optimization Constraints from the — Non-Timing Constraints
designer  Operating conditions
 Timing Constraints/ Exceptions  Wire load models
 Delay Constraints (Latency, Input Delay,  System interface, Design rule constraints
Input Transition, Output Load and (DRVs - Max. Cap./ Transition/Fanout)
Output Transition)  Area constraints, Multi-voltage and Power
 Power and Area Constraints optimization constraints
 System interface  Logic assignments
 ASIC Physical Design
Physical Design Inputs
•Liberty Timing File (.lib or .db)
— Cell Logical View/ The Timing
Library
— Std. Cell lib, Macro lib, IO lib
— LIB contains
— Gate Delaytime
transition = function
and of input
output  Cell Type and Functionality
capacitance  Delay Models (WLD/ NLDM/ CCS)
•Library Exchange Format (LEF) Pin/ Cell Timings and design rules
— Cell Abstract View/ The Physical
Library

 PVT Conditions
— Std. Cell LEF  Power Details (Leakage and
Dynamic)
— Macro LEF
— IO LEF

— LEF contains
 Cell Name, Shape, Size, Orientation
& Class
 Port/Pin Name, Direction and Layout
Geometries
 Obstruction/ Blockages
 Antenna Diff. Area
 ASIC Physical Design
Physical Design Inputs
• Technology Related files
— Technology file — Interconnect Parasitic file
 Defines Units
Layers and Vias and
as Design
per theRules for
Technology  Used for layer parasitic extraction
 Name
Layers and
and Number
Vias conventions of  Contains
resistance Layer/
valuesVia
in capacitance
a Lookup Tableand
 Physical andVias
Electrical parameters of (LUT) format
 Layers
E.g. and  Also
for used
the to generate
extraction toolsparasitic formats
(e.g. nxtgrd,
Direction/Type/Pitch/Width/Offset/
Thickness/Resistance/Capacitance/ captbl)
Max. Metal Density/Antenna Rule/  Extraction
accurate tool formats are more
Blockages/Design Rules formats than interconnect parasitic
 .ict - Interconnect
(Cadence Format) Technology Format
 Manufacturing Grid definition .itf - Interconnect
 Site/Unit Tile definition

(Synopsys Format)Technology Format
 Technology fileLEF
hasfiles
to load before
 .ptf - Process
Graphics Technology File (Mentor
Format)
loading
the other
layer information since
for it holds
that
particular technology — Map file
Useful if is there is 2 different naming
convections
 .tech.lef (Cadence Format) InterconnectinParasitic
Technology
file file, LEF or
 .tf - technology file (Synopsys Format)
 ASIC Physical Design
Physical Design Inputs
• Power Specification File •Clock Tree Constraints/
— Power Modes & Power Domains Specification
— Tie Up supply & Tie Low supply • Root Pin Definition
— Power Nets & GND Nets • Insertion Delay (ID) and Skew Target
• Maximum Capacitance/ Transition/
• Optimization Directives Fanout (DRVs)
— Don’t use • Transition can be classified into Leaf
• Cells that are not supposed to Transition and Buffer Transition
optimize • No. of Buffer Levels (Tree depth) List
— Size only/ use only • of Buffers/ Inverters for CTS
• Upsizing/ Downsizing only with • List of Through pin, Preserved Pin,
this list of cells Exclude Pin
• NDRs can be defined in CTS Spec. for
• Design Exchange Formats the Clock Tree Routing
— List & locations of Components, Vias, • Macro Models
Pins, Nets, Special nets
— Die dimensions, Row definitions, • IO Information File
Placement and Bounding Box Data, — Pin/ Pad locations
Routing Grids, Power Grids, Pre-routes — Edge and order for IO Placement
— .def, .fp are the common formats — .tdf, .io are common formats
 ASIC Physical Design
Physical Design Flow

Import Design, Floor Planning, Pre-Placement,

Sanity Checks Partitioning
Power Planning Placement

Clock Tree
Routing Post-CTS Opt. Synthesis (CTS) Pre-CTS Opt.

Post-Routing Physical Formal Parasitic

Opt. Verification Verification Extraction

Static Timing
Tape-out IR-Drop Analysis Power Analysis Analysis
 ASIC Physical Design
Import Design
• Import Design
— The following input files information are loaded to the PnR tool
• Netlist (.v/ .vhd/ .edif)
• Physical Libraries (.lef)
• Timing Libraries (.lib)
• Technology Files
• Constraints (.sdc)
• IO Info. File (optional)
• Power Spec. File (optional)
• Optimization Directives (optional)
• Clock Tree Spec. File (optional at floorplan stage)
• DEF/ FP (optional if floorplan is not done)
— Core area is approximately calculated by the tool from the Netlist
— While Importing, first we have to load the LEF files and then LIB files
 ASIC Physical Design
Import Design
• Sanity Checks
— Sanity Checks mainly checks the quality of netlist in terms of timing
— It also consists of checking the issues related to Library files, Timing
Constraints, IOs and Optimization Directives
— Some of the Netlist Sanity Checks:
 Floating Pins
 Unconstrained Pins
 Un-driven i/p Ports
 Unloaded o/p Ports
 Pin direction mismatches
 Multiple drivers etc.
— Other possible issues include Unconnected/ Wrongly Connected Tie-
high/ Tie-low Pins and Power Pins (since Tie-up or Tie-down
connectivity always through Tie-Cells)
Partitioning
 An example of Partitioning:

 Partition a given netlist into smaller netlists such that:

• Interconnections between partitions is minimized.
• Delay due to partitioning is minimized
• Number of terminals is less than predetermined maximum value
• The area of each partition remains within the specified bounds
• The number of partitions are also remains within the specified bounds.
Partitioning:
 Partitioning at Different Levels
• System level
• Board Level
• Chip Level
Partitioning:
 Delay implications are different
• Intrachip: X
• Intraboard: 10X
• Interboard: 20X
Partitioning:
 Types of floorplan techniques
• Abutted floorplan: Channel less placement of blocks
• Non-abutted floorplan: Channel based placement of blocks
• Mix of both: Partially abutted with some channels
 ASIC Physical Design
Partitioning
• Styles of Implementation
— Flat
 Small to Medium ASIC
 Better Area Usage Since no reserve space around each sub-design for power/ground
— Hierarchical
 For very large design
 When sub-systems are design individually
 Possible only if a design hierarchy exist
 ASIC Physical Design
Partitioning
• The Hierarchical Partitioning is done prior to Floorplan
• Partition can be done based on
— Design Hierarchy
— Timing Criticality
— Functionality
— Clock Domain
— Design Files
— Block Size
• Partitioning Inputs and Outputs by Registers
• Minimize Cross-Partition- Boundary IO
• For Sub-block designs, the Partitioning is not required
• For Full Chip only we need to design with Partitioning
 ASIC Physical Design
Floorplanning
• Floor planning is the one of the critical & important step in the Physical Design
• Quality of Chip/Design implementation depends on how good is the Floorplan.
• A good floorplan can make implementation process (place, cts, route & timing closure)
cake walk.
• A bad floorplan can create all kinds of issues in the design (congestion, timing, noise,
IR, routing issues )
• A bad floorplan will blow up area, power & affects reliability, life of the IC and it can
increase the overall IC cost.
 ASIC Physical Design
Floorplanning
• Terminologies and Definitions
— Utilization
 Area of the core that is used by placed Standard Cells and Macros expressed in
percentage
— Manufacturing Grid
 The smallest geometry that semiconductor foundry can process or smallest
resolution of your technology process (e.g. 0.005)
 All drawn geometries during Physical Design must snap to this grid
 While Masking fab. use this as reference lines
— Standard Cell Site/ Standard Cell Placement Tile/ Unit Tile
 The minimum Width and Height a Cell that can occupy in the design
 The Standard Cell Site will have the same height as Standard Cells, but the width
will be as small as your smallest Filler Cell
 It’s one Vertical Routing Track and the Standard Cell Height
 All Standard Cells must be multiple of Unit Tile
— Standard Cell Rows
 Rows are actually the Standard Cell Sites abut side by side and then Standard Cells
are placed on these Rows
 Cells with the equal no. of Track definition will have same height
 ASIC Physical Design
Floorplanning
• Terminologies and Definitions
— Placement Grid
 Placement Grid is made up of Standard Cell Site
 Its always a multiple of Manufacturing Grid
 Placement Grid is made up of the Rows which are composed of Sites
— Routing Grid and Routing Track
 Horizontal and Vertical line drawn on the layout area which will guide for making
interconnections
 The Routing Grid is made up of the Routing Tracks
 Routing Tracks can be Grid-based, Gridless based or Subgrid-based
— Flight-line/ Fly-line
 Virtual connection between Macros and Macro or Macros and IOs
— Macro
 Any instances other than Standard Cell and is as loaded as black box to the
design is Macro
 Intellectual Property (IP) e.g. RAM, ROM, PLL, Analog Designs etc.
 Hard Macro: IP with Layout implemented
 Soft Macro: IP without Layout implemented (HDL)
 ASIC Physical Design
Floorplanning
• Steps in Floorplan
— Initialize with Chip & Core Aspect Ratio (AR)
— Initialize with Core Utilization
— Initialize Row Configuration & Cell Orientation
— Provide the Core to Pad/ IO spacing (Core to IO clearance)
— Pins/ Pads Placement
— Macro Placement by Fly-line Analysis
— Macro Placement requirements are also need to consider
— Blockage Management (Placement/ Routing)
 ASIC Physical Design
Floorplanning
• Initialization
— Row Configuration
 Slanting lines in the side of the cell rows denote the Cell Orientation

Most common because of better

space utilization

— Core to Pad/ IO spacing

 Core to IO clearance
 Used for Placing IOs and Power Ring
 ASIC Physical Design
Floorplanning
• Initialization
• Aspect Ratio defined as the ratio of height to width of a Chip/Block.
• Full chip Aspect Ratio can have a maximum value of 1.20
• Aspect Ratio decides the shape
 ASIC Physical Design
Floorplanning
• Initialization
• Core Utilization defines as area occupied by standard cells,
Macros and blockages.
• If core utilization is 0.7 means that 70% of area is available for
placement of cells, whereas 30% is left for routing.
 ASIC Physical Design
Floorplanning
• IO Placement
— Chip Level its IO Pads and Block Level its IO Pins
— Pin is a logical entity and is a property of a Port
— Port is a physical entity and a Port have only 1 Pin associated with it
— Netlist will have Pins and Layout will have Ports
— Unplaced Port is not represented in the Layout
— Different types of IOs
 Signal Pads/Pins
 Core Power Pads/Pins
 IO Power Pads/Pins
 Corner Pads (Doesn’t hold any logic, provides IO Pad Ring connectivity)
 Filler Pads (Fill the gaps between IO pads to get the Ring Connectivity)
— Physical-only pads that are not part of the input Gate level Netlist need
to be inserted prior to reading IO constraints
 ASIC Physical Design
Floorplanning
• IO Placement
— IO Pads enables the design to operate at different voltages with the
help of Level Shifters, Pre-Drivers (at Core Voltage) Post-Drivers (at IO
Voltage)
— No of Core Power Pads needed =

— There will be 1 Core GND Pad along with every Core Power Pad
— No. of IO Power Pads needed:

Thumb Rule: 1 pair of IO power pads for every 4 to 6 signal Pads

 ASIC Physical Design
Floorplanning
• Macro Placement
— Fly-line Analysis (For Connectivity information)
— Data-flow diagram
— Macro keep-out (For Uniform Standard Cell Region)
— Channel Calculation (Critical for Congestion and Timing)
— Avoid odd shaped area for Standard Cells
— Funnel shaped Macro Placements are preferred
— Fix the Macro locations, so that tool wont alter during Optimization
— Spacing between Macro:
 ASIC Physical Design
Floorplanning
• Macro Placement Tips
— Place macros around chip periphery, so that core area will be clustered
— Consider connections to fixed cells when placing Macros
— In advanced Technology Nodes Macro Orientation is fixed since the Poly
Orientation can’t vary, so there will be restrictions in Macro Orientation
— Reserve enough room around Macros for IO Routing
— Reduce open fields as much as possible
— Provide necessary Blockages around the Macro
 ASIC Physical Design
Floorplanning
 Blockages
 Placement Blockage & Routing Blockage Rectilinear
 Both of the Blockages can again be classified as- Macro
• Hard, Soft and Partial Blockages Without
 Hard Blockage Blockage
• Complete Standard Cell Blockage
 Soft Blockage
• Non-Buffering Blockage With
 Partial Blockage Blockage
• Partial Standard Cell Blockage and is used to avoid congestion
• We can Block Standard Cells as per the required percentage
value
 Keep-out/ Halo
• Halo is similar to Soft placement Blockage (Terminology in
Cadence EDI)
• Its basically a keep-out Macro margin Macro
• Halo respects Macro while other Blockages respect location
i.e., even if Macro is moved Halo also moves along with it.
Halo around Macro
Blockages Usage
 ASIC Physical Design
Floorplanning
• Issues arises due to bad Floorplan
— Congestion near Macro Pins/ Corners due to insufficient Placement
Blockage
— Std. Cell placement in narrow channels led to Congestion
— Macros of same partition which are placed far apart can cause Timing
Violation

Floorplan done with 1 Macro

 ASIC Physical Design
Power planning
• Power Plan
— To connect Power to the Chip by considering issues like EM and IR Drop
— Power Routing also called Pre-Routing
— Pre-Routing includes creating Power Ring, Stripes/Mesh/Grid, and
Standard Cell Power Rails
— Power Planning also includes Power Via insertion
— IO Rings are established through IO Cell abutment and through IO Filler
Cells
— Power Trunks are constructed between Core Power Ring and Power Pads
— Trunk is a piece of metal that connects IO Pad and Core Ring
— Technical information required for Power Planning:
 Total Dynamic Power info. will get from Compiler
 Technology File will provide Current Density (JMAX)
 LEF will prove the Metal Layer width
 Technology Library will provide Core Voltage
 ASIC Physical Design
Power planning
• Levels of Power Distribution
• Rings
— VDD and VSS Rings are formed around the Core and Macro
• Stripes
— Carries VDD and VSS around the chip
— Carries VDD and VSS from Rings across the chip
— Power Stripes are created in the Core Area to tap power from Core Rings to
the core area
• Rails (Special Route)
— Connect VDD and VSS to the standard cell
— Standard Cell Rails are created to tap power from Power Stripes to Std. Cell
Power/Ground Pins
• Power Vias
— Insert all Power Vias between Ring & Grid, Grid & Rail and Vertical Grid &
Horizontal Grid
• Trunks
— Connects Ring to Power Pad
 ASIC Physical Design
Power planning
• Power Plan: Calculations
 Total Dynamic Core Current =
𝐒𝐒𝐂𝐂𝐏𝐏𝐓𝐓𝐏𝐂𝐏𝐂𝐒𝐒𝐓𝐓𝐂
𝐌
𝐌𝐂𝐇𝐇𝐃𝐃𝐓𝐓𝐒𝐒𝐃𝐃𝐃
𝐓𝐃𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓
𝐂𝐂𝐑𝐑𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐕𝐂𝐕𝐂𝐒𝐒𝐓𝐓𝐂𝐂

 Pad to Core Trunk Width =

𝐓𝐓𝐒 𝐒𝐂𝐂𝐒 𝐒 𝐒 𝐒𝐑𝐑𝐂𝐂𝐂𝐂𝐒𝐒𝐓𝐓𝐂𝐌𝐌
𝐂
𝐇𝐇𝐃𝐃𝐓𝐓𝐒𝐒𝐃𝐃𝐃 𝐓𝐃𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓
𝐂𝐂𝐒 𝐒𝐇𝐇𝐑𝐒𝐑𝐒𝐂𝐂𝐩𝐑𝐩𝐑𝐂𝐂𝐌
𝐌𝐒𝐒𝐑𝐑𝐓𝐓𝐒𝐓 𝐒𝐓𝐒 𝐒𝐂𝐂𝐒 𝐒 𝐒 𝐒𝐑𝐑𝐂
𝐌𝐉𝐌
𝐂𝐉 𝐀𝐀
𝐌𝐌𝐉𝐌
𝐑
𝐌𝐉𝐑𝐂𝐂𝐒 𝐒𝐇𝐇𝐑𝐨
𝐑𝐨 𝐓
.𝐓
𝐍𝐓
𝐍

 Core Ring Width =

𝐓𝐓𝐒 𝐒𝐂𝐂𝐒 𝐒 𝐒 𝐒𝐑𝐑𝐂𝐂𝐂𝐂𝐒𝐒𝐓𝐓𝐂𝐌𝐌𝐂
𝐇𝐇𝐃𝐃𝐓𝐓𝐒𝐒𝐃𝐃𝐃
𝐓𝐃𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓𝐓
𝐂𝐂𝐌
𝐌𝐒 𝐒𝐑𝐑𝐓𝐓𝐒𝐓
𝐒𝐓𝐒 𝐒𝐂𝐂𝐒 𝐒 𝐒 𝐒𝐑𝐑𝐂
𝐌
𝐑𝐌
𝐂
𝐑𝐒𝐒𝐇𝐇𝐑𝐒
𝐑𝐒 𝐓 𝐓 𝐨𝐒
𝐨𝐒𝐂𝐂𝐃𝐃𝐓𝐓𝐋𝐓𝐋𝐓𝐓𝐓𝐓𝐓𝐂𝐂𝐌
𝐂
𝐌𝐂𝐓𝐓𝐓𝐨
𝐓𝐨 𝐓𝐉𝐓 𝐉 𝐀𝐀
𝐌𝐌𝐉𝐌
𝐑
𝐌𝐉

 Power Stripes Spacing =

𝐂𝐂𝐩𝐩𝐇𝐇𝐒𝐒𝐓𝐓𝐒𝐂
𝐒
)𝐂𝐓𝐓𝐓𝐨
𝐓𝐨 𝐓𝐓𝐓𝐓𝐓𝐓𝐒𝐒𝐇𝐌𝐇
𝐑
𝐖
𝐌𝐖
𝐑𝐂𝐂𝐩 𝐩𝐇𝐇𝐒 𝐒 𝐓 𝐓 𝐒𝐨
𝐒𝐓𝐨−𝐓
𝐓𝐓(𝐓
𝐓𝐍
𝐓
𝐍.𝐒𝐒𝐇𝐇
𝐂
𝐖𝐖𝐂𝐒𝐒𝐓𝐓𝐂𝐂
𝐑+𝐑𝟏𝐂
𝟏𝐂𝐩 𝐩𝐇𝐇𝐒 𝐒 𝐓 𝐓 𝐒𝐨
𝐒𝐨 𝐓
.𝐓
𝐍𝐓
𝐍

Courtesy: asic-soc.blogspot.in
 ASIC Physical Design
Power planning
• Sub-block Configuration
Grid Offset

Grid Steps
Core Boundary

Grid Spacing
Chip Boundary
Ring Width

Core Area
Ring Spacing
Rails

Horizontal
Core Ring Horizontal
Stripes Vertical Vertical
Core Ring
Stripes
 ASIC Physical Design
Power planning
• Full Chip Configuration

• Save Floorplan (.def / .fp)

 ASIC Physical Design
Pre-Placement
• Physical-Only Cells (Well Taps, End Caps)
— These libraryrails
and ground cells do not have signal connectivity and connect only to the power
— End
also Caps ensure
prevents DRCthat gaps dobynot
violations occur between
satisfying the requirements
Well tie-off Well and Implant Layers
for core and
rows
— Well Taps help to tie Substrate and N-wells to VDD and VSS levels and thus prevent
Latch-up
• Special Cells (Spare cells, Decap Cells)
— Spare Cells for ECO and Decaps for avoiding Instantaneous Voltage Drop (IVD)
— Place Decaps closer to Power Pads or any larger Drivers

• Cell Padding
— Cell Padding is done to reserve space for avoiding Routing Congestion
— Cell Padding adds Hard Constraints to Placement
— The Constraints are honored by Cell, Legalization, CTS, and Timing Optimization
 ASIC Physical Design
Pre-Placement Optimization
• Pre-Placement Optimization Goals
— Routability
— Performance (Timing)
— Power (with Cells)
• Optimizations before Placement
— Delay models must be removed (if any)
— Zero-RC (0-RC) Optimization
— Isolation Cell Insertion
— Multi Corner Multi Mode (MCMM) settings before Std. Cell Placement
• Zero-RC Optimization
— Optimizes the netlist without any delay models, thus provides an optimal
starting point for placement
— Timing during 0-RC Opt and that of during Synthesis has to be matched
— Else indicate problems in the Technology File, Timing Library, Constraint Files,
or overall design
— Logical restructuring and up/down size are optimizations at the 0-RC stage
• Take care of don’t use cells while doing optimization
 ASIC Physical Design
Placement
•Automated Standard Cell Placement for placing the Standard
Cells in Placement Tracks
• Placement Objectives
— Total wire length I/O
— Routability Placed Pads
— Performance Standard
— Power Cells
— Heat distribution
•Timing checks only with slow
corners at Placement stage
•Only Setup Time check, since
buffers are getting added during Macros
Clock Tree Synthesis
 ASIC Physical Design
Placement
• Placement Methods
— Timing Driven Placement
 To Refine placement based on congestion, timing and power
 To optimize large sets of path delays
 Net Based
— Congestion Driven Placement
 To distance standard cell instances from each other such that more routing
tracks are created between them
•Control the delay on signal path by imposing an upper bound
delay or weight to net
 ASIC Physical Design
Placement
• Placement Stages
— Global Placement
— Detail Placement
— Placement Legalization
— In-Place Optimizations
• Global/ Coarse Placement
— To get the approximate initial location Global/ Coarse Placement
— Cells are not legally placed and there
can be overlapping
• Detail/ Legal Placement
— To avoid cell overlapping
— Cells have legalized locations
— Legalize placement will place the cells
in their legal position with no overlap
Detail/ Legal Placement
 ASIC Physical Design
Placement
• Placement Legalization
— Placed Macros are legally oriented with Standard Cell Rows
• In-Place Optimizations
— Scan Chain Reordering
• After Placement, report Congestion, Utilization and Timing
•Tie off cell instances provide connectivity between the Tie- high
and Tie-low logical inputs pins of the Netlist instances to Power
and Ground
• Tie off cells are placed after the placement of Standard Cells
• After placement check the Cell Density
• Global Route (GR)
— Whole region is divided into an array of rectangular sub-regions each of which
may accommodate tens of routing tracks in each dimension called Global Cells
— Global Route is performed to estimate the inter-connect parasitics and Routing
Congestion Map
 ASIC Physical Design
Pre CTS Optimization/ Placement Opt.
• Cell Sizing
— Sized up/ down to meet optimizing for timing and area
— Up sizing will give timing advantage and Down sizing will give area advantage
• VT Swapping
— To optimize for leakage power (HVT, RVT/SVT, LVT)
• Cloning
— To reduce fanout
• Buffering
— Long nets are buffered or remove buffers to bring the timing advantage
• Re-Buffering
— To improve slews, reduce net capacitance and reduce fanout
• Logical Restructuring
— To optimize timing and area without changing the functionality of the design
— Breaking complex cells into simpler cells or vice versa
• Pin Swapping
 ASIC Physical Design
Pre CTS Optimization/ Placement Opt.
• Optimization Techniques
- Resizing - Cloning - Buffering
d 0.2
e 0.2 d 0.2
a d 0.2 a
b a b
? b fge 0.2 ? f 0.2
e
g
f 0.3 ? 0.2
h 0.2 h 0.2

a a d d
e 0.2
0.2
A C A
b b e
0.035 0.026 a f
b g a fg 0.2
B b B B h 0.2
0.1
h

- Redesign Fan-in Tree

Arr(a)=4 a
1 a e
b 1
1 Arr(e)=5
Arr(b)=3 b 1 e c
Arr(c)=1 c Arr(e)=6 1
1 Longest
SlowdownPath = 4 due to load
of buffer
Longest Path = 5
d
Arr(d)=0 d
 ASIC Physical Design
Pre CTS Optimization/ Placement Opt.
• Timing Optimization Techniques
- Decomposition

- Swap Commutative Pins

1 1
a 2
0 c
1
cb 5 1
1 3
1 b 1
1
a
2 0
2
 ASIC Physical Design
Pre CTS Optimization
• Set the Optimization Directives
— don’t_use, size_only
• Perform High Fanout Nets Synthesize (HFNS)
— High Fanout Nets are Synthesized before Clock Tree Synthesis
— HFNS is the Buffering of High Fanout Nets
— Usually High Fanout Nets may have Fanout of more
than 1000 Eg., Reset, Clear etc.
• Set CTS Routing Rules
— Shielding
— Non Default Rules (NDR)
• Set RC Delay Models
 ASIC Physical Design
Pre CTS Optimization
• Non-Default Rule (NDR)
— The user-defined Routing rules apart from the default Routing Rule
— Often used to “harden” the sensitive nets like Clock Nets
— NDRs make the Clock Routes less sensitive to CrossTalk or EM effects
— Double/ Triple Width for avoiding Electromigration
— Double/ Triple Spacing for avoiding Crosstalk
— NDRs will improve Insertion Delay
Default
Routing Rule Sig1
Clk
Sig2

Sig1
Double Spacing
NDR
on Route
Clock net Gnd
Clk Double Width
Ground
Shielding
Gnd
Sig2
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• The Clock Problem
— Clock skew
— Long clock insertion delay
— Skew across clocks
— Heavy clock net loading
— Clock is power hungry
— Clock to signal coupling effect (CrossTalk)
— Electromigration on clock net
•Clock Tree is a path from the Clock Source (Root) to Clock Sinks
(Leaf)
•Clock Tree Synthesis is the process of creating this Clock Path
from Clock Source to Clock Sinks
•All Clock pins of flip Flop are considered as Clock Sinks (Leaf);
where the Clock Tree Synthesis ends
 ASIC Physical Design
Clock Tree Synthesis (CTS)
Before CTS Clock Source

FF FF FF FF FF FF FF FF FF FF

After CTS Clock Source

FF FF FF FF FF FF FF FF FF FF
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• Main concerns for Clock Design
— Skew
 Most important concern for clock networks
 For increased clock frequency, skew may contribute over 10% of the system cycle
time
 Due to variations in trace length, metal width and height, coupling caps
 It can also be due to variations in local clock load, local power supply, local gate
length and threshold, local temperature
— Power
 Very important, as clock is a major
power consumer Clock
 It switches at every clock cycle
— Noise
 Clock is often a very strong aggressor
 May need shielding
— Delay
 Not really important
 But Slew Rate is important (sharp
transition)
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• Clock Skew: Spatial Clock Variation

Clock Skew Difference

in clock arrival time at
two
spatially distinct points

A A
Compressed timing
path
B

Skew
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• Clock Jitter: Temporal Clock Variation
Compressed timing path

Period A Period B
Clock Jitter
Difference in clock
period over time
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• CTS Pre-requisites
— Legally Placed and Optimized with acceptable Congestion
— Timing should be good
— No Design Rule Violations
— Power/Ground nets are pre-routed
— HFNS done
— Logical/Physical Library should have special Clock Cells
• CTS Objects
— The timer starts from every Clock Source and traces forward over Combinational Arcs
until it reaches the Clock Pin of a flop or another Clock Source
— All Pins/ Timing Arcs in the forward trace before a valid Leaf are considered to be in
the clock network
— Pin or Combinational Timing Arcs that trace to a non-clock pin are not part of Clock
Tree network (e.g. D pin of FF)
— Sequential elements are traced through if it is a source of the Generated Clock
— Clock tracing after the propagation of Case Analysis
— Clock tracing should be Mode aware
— Inverters are added in Clock Tree for better Duty Cycle
Limit the buffer/inverter list to just 3 or 4 buf/inv sizes
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• CTS Flow
— Check and fix Macro locations
— Read CTS SDC: Clock Tree begins at SDC defined clock pin and
ends at stop pin of the flop
— Generate CTS Specification file Example of CTS spec file AutoCTSRootPin
 Max. Skew SH1/I23/Z ExcludePin + XPU/CAM/C
MaxDelay 5ns
 Max. and Min. Insertion Delay MinDelay 0ns
 Max. Transition, Capacitance, Fanout Buffer buf1 buf2 inv1 inv2 del1
MaxSkew 500ps
 No. Buffer levels (Tree depth) MaxDepth 20
 Buffer/ Inverter list LeafPin + FPU/CORE/A rising END
 Clock Tree Routing Metal Layers
 Clock Tree Leaf Pin, Root Pin, Preserve
Pin, Through Pin and Exclude Pin
— Compile CTS using CTS Spec. file
— Place Clock Tree Cells
— Route Clock Tree (Optional and can be done during Signal net
routing also)
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• CTS Algorithms
— RC Tree Based CTS
— H Tree based Algorithm Clock Source

— X Tree based Algorithm

— Method of Mean and Median (MMM)
RC-
— Geometric Matching Algorithm (GMA) Tree
Clock Source
— Pi Configuration

H-
Tree
Clock
Source

GMA
Pi Configuration
Courtesy: usebackend.wordpress.com
Clock Source
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• Before CTS all Clock Pins are driven by a single Clock Source

FF FF FF FF FF FF
F F F F F F

FF FF FF FF FF FF
F F F F F F

Source clock Clock

sink pins
pin

FF FF FF FF FF FF
F F F F F F
Cloc
k

FF FF FF FF FF FF
F F F F F F

Courtesy: vlsi-basics.com
 ASIC Physical Design
Clock Tree Synthesis (CTS)
•After CTS the buffer tree is built to balance the loads and
minimize the skew
F FF FF F FF FF
F F

F F F F F F
F F F F F F

Clock
sink pins

Source clock pin Buffer Tree

F F F F F F
F F F F F F
Cloc
k

F F
F F F F F
F F F F F
 ASIC Physical Design
Clock Tree Synthesis (CTS)
•After CTS a “delay line” is added to meet the minimum Insertion
Delay (ID)
FF FF FF FF FF FF

Extra buffers
added for F
F F
F
F
F
F F
F
F
balancing
Minimum the F F

Insertion Delay

F F F F F F
F F F F F F

Cloc
k

F F F F F F
F F F F F F
 ASIC Physical Design
Clock Tree Synthesis (CTS)
• Analyze the Clock Tree
— Report Timing (both Setup and Hold)
— If timing not met then check clocks be grouped (balanced together)
— Report Insertion Delay & Skew and verify that the targets are achieved
— Report DRV targets (Fanout, Capacitance and Transition)
— Check the intended Leaf Cell (Clock Sinks) is reached
— Check the Clock Tree Exceptions are not in the Clock Tree
— Report the pre-existing cells, such as Clock Gating Cells
— Do Quality-of-Report (QoR)
— Check Clock Tree converges either with itself or with another Clock Tree
— Clock Tree has timing relationship with other Clock Trees for inter Clock
Skew balancing
— Check Design Rule Constraints
— Check Routing Constraints
— Report Power and Area
 ASIC Physical Design
Post CTS Optimization
• Post CTS Optimization
— Optimization with Useful Skew
— Optimization with Total Negative Slack (TNS)
— Fine Grid Spacing
— Post CTS Optimization Techniques
 Shielding
 Sizing
 Buffer re-location
 Level adjustment
— Optimize the design for Hold Time
 Hold Violations should be fixed first in Best Corner and then in Worst Corner
— Area Optimizations
 ASIC Physical Design
Routing
• Importance of Routing as Technology shrinks
— Device (Gate) delay decreases
— Interconnect resistance increases
— Vertical heights of interconnect
layers increase, in an attempt to
offset increasing interconnect
resistance
— Area component of interconnect
capacitance no longer dominates
— Lateral (sidewall) and fringing
components of capacitance start to
dominate the total capacitance of
the interconnect
— Interconnect capacitance dominates Multi-level Interconnection (MLI)
total Gate loading Technology Layer stacks
• Routing Objectives
— Skew requirements
— Open/Short circuit clean
— Routed paths must meet setup and hold timing margin
— DRVs max. Capacitance/ Transition must be under the limit
— Metal traces must meet foundry physical DRC requirements
— Layout geometries should meet Current Density specification
 ASIC Physical Design
Routing
• Routing Stages
— Trial/Global Routing
 Identifying
in a shortestroutable
distancepath for the nets driving/ driven pins
Does not consider DRC rules, which gives an overall view
 of routing and congested nets Assign layers to the nets
Identify
the androutable
specific assign net segments
window over
called Global Route Cell
(GRC)
Avoid
over congested areas and also long detours Avoid routing
blockages
 Avoid routingTree
Uses Steiner for pre-route
and Mazenets such as Rings/Stripes/Rails
algorithm






— Track Assignment
 Takes the Global Routed Layout and assigns each nets to the specific Tracks and
layer geometry
 It does not follow the physical DRC rules
 It will do the timing aware Track Assignment
 It helps in Via Minimization
 ASIC Physical Design
Routing
• Routing Stages
— Detail/Nano Routing
 Detailed routing follows up with the track
routed net segments and performs the
complete DRC aware and timing driven routing
 It is the final routing for the design built after
the CTS and the timing is freeze
 Filler Cells are adding before Detailed Routing
 Detail Routing is done after analyze the cause
for congestion in the design, add density screen
or change flooplan etc. Grid
Point
Trace

• Grid Based Routing

M1
— Metal traces (routes) are built along and
centered upon routing tracks on the grid points
— Various types of grids are Manufacturing Grid,
Routing Grid (Pitch) and Placement Grid
— Grid dimension should be multiple of
Manufacturing Grid M2
Pitch
Track
 ASIC Physical Design
Routing
• Routing Preferences
— Typically Routing only in “Manhattan” N/S E/W directions
E.g. layer 1 – N/S Layer 2 – E/W
Metal1
— Spacing checks with the adjacent layers VIA34
— Width checks for all layers Metal2
— Via dimension rules
— Slotting rules Metal3
— A segment
segment oncannot cross
the same another
wiring layer VIA23 Metal4
— Wire
othersegments
layers can cross wires on
— Power
layers, and Ground
mostly have
the top their own
layers Metal5

VIA12

• Layer Routing directions: Each metal layer has its

direction and are defined in a technology rule file own preferred routing
VIA45

— M1: Horizontal, M2: Vertical , M3: Horizontal, M4: Vertical and so on

• In some(Non-preferred
routing cases, we can avoid following preferred routing direction for smart
direction)
 ASIC Physical Design
Post Routing Optimization
• Signal Integrity (SI) Optimization by NDRs and Shielding for the
sensitive nets
• Types of Shielding for sensitive nets
— Same layer shielding
— Adjacent layer/ Coaxial shielding

Critical
net

Critical net Non-critical

nets

Non-critical nets Ground net

Ground net in Metal 4
Metal 3 Layer Metal 4 Layer Metal 5 Layer
Adjacent Layer/
Coaxial shielding
Same Layer shielding
 ASIC Physical Design
Post Routing Optimization
• Filler Cell insertion
— Filler Cells can be inserted before or after Detailed Routing
— If Fillers contain metal routing other than Pre-Routing then Fillers
should be inserted before Routing
— Width of the smallest Filler Cell is the Placement Grid Width
— Once Fillers are inserted then the placement is fixed and tool can’t
move Cells for further optimization
 ASIC Physical Design
Post Routing Optimization
• Metal Fill
— Filling up the empty metal tracks with metal shapes to met metal
density rules
— 2 types of Metal Fill
 Floating Metal Fill: Doesn’t completely shield the aggressor nets, so SI will be
prominent
 Grounded Metal Fill: Completely shields the aggressor nets, so less SI impact
 Grounded Metal Fill is complex as compared to Floating Metal Fill
— Metal Density Rule helps to avoid Over Etching/ Metal Erosion
• Spare Cells Tie-up/ Tie-down
— Tie Cells connects the Gate of Cells to VDD/ VSS so reduces ESD
— Tie-up Cells help in avoid Power Bounce
— Tie-down Cells help in avoid Ground Bounce
— Tie Cells are basically MOS in Diode-Connected configuration
 ASIC Physical Design
Physical Verification (DRC)
• Design Rule Check (DRC) is the process of checking physical layout data
against fabrication-specific rules specified by the foundry to ensure
successful fabrication
• Process specific design rules must be followed when drawing layouts to
avoid any manufacturing defects during the fabrication of an IC
• Process design rules are the minimum allowable drawing dimensions which
affects the X and Y dimensions of layout and not the depth/vertical
DRC Rule 130nm 90nm 65nm 45nm
dimensions
• As Technology
— Shrinks
Number of Design Rules are increasing
Width-
based
Spacing
1-2 2-3 3-5 7
— Complexity
Increasing of Routing
the number Rules is increasing
of objects
on involved
— Min-Area
Rule
— More Design Rules depending Width, Halo, Parallel Length
1 pitch 2 pitch 3 pitch 5 pitch
• Violating a design rule
Metal1 might result in a non-functional
Metal1 Cut
Number N/A
circuit
1-2
or4-5low Yield
5-6
(Via)
Dense EoL
N/A N/A M1/M2 All
(OPC) Layers
Min-step
(OPC) N/A 1 5 5

Before Fabrication After Fabrication After Fabrication

Spacing violation Width violation
 ASIC Physical Design
Physical Verification (DRC)
• Design
— Rule examples
Maximum Rules: Manufacturing of large continuous regions can lead to
— stress
Angles:cracks. Soonly
Usually ‘wide metal’ must
multiples of 45be ‘slotted’
degree are (holes)
allowed
— Grid:
error”All
is corner points
produced must lie on a minimal grid, otherwise an “off grid
— Minimum Spacing: The minimum spacing between objects on a single

layer Violations Cleared

Notch Spacing Violation

Notch Spacing Violation

Thin & Fat Spacing Violation

Min. Spacing Violation

 ASIC Physical Design
Physical Verification (DRC)
• Design
— Rule examples
Minimum Width: The min width rule specifies the minimum width of
— individual
Minimum shapes on aOverlap:
Enclosure/ single layer
Implies that the second layer is fully
— enclosed
Notch: by the first
Theincluding one
rule specifies the the
minimum spacing rule for objects on the
same
mergednet,
object defining minimum notch on a single-layer,
— Minimum Cut: the minimum number of cuts a via must have when it is

on a wide wire Violations Cleared

Minimum Width Violation

minimum Cut Violation

Minimum Enclosure Violation

 ASIC Physical Design
Physical Verification (LVS)
• Layout Versus Schematic (LVS) verifies the connectivity of a
Verilog Netlist and Layout Netlist (Extracted Netlist from GDS)
• Tool extracts circuit devices and interconnects from the layout
and saved as Layout Netlist (SPICE format)
• As LVS performs comparison between 2 Netlist, it does not
compare the functionalities of both the Netlist
• Input Requirements
— LVS Rule deck
— Verilog Netlist
— Physical layout database (GDS)
— Spice Netlist (Extracted by the tool from GDS)
• LVS checks examples
— Short Net Error, Open Net Error, Extract errors, Compare errors
 ASIC Physical Design
Physical Verification (LVS)
• Open Net Error

Same net is routed in two different metal layers but not connected

• Short Net Error

Same net with different pin names Two different nets shorting together
 ASIC Physical Design
Physical Verification (LVS)
• Extract Errors
— Parameter Mismatch
— Device parameters on schematic and layout are compared
— Example: Let us consider a transistor here, LVS checks are necessary
parameters like width, length, multiplication factor etc.
 ASIC Physical Design
Physical Verification (LVS)
• Compare Errors
— Malformed Devices
— Pin Errors
— Device Mismatch
— Net Mismatch
 ASIC Physical Design
Physical Verification (ERC)
• Electrical Rule Check (ERC) is used to analyze or confirm the
electrical connectivity of an IC design
• ERC checks are run to identify the following errors in layout
— To locate devices connected directly between Power and Ground
— To locate floating Devices, Substrates and Wells
— To locate devices which are shorted
— To locate devices with missing connections
• Well Tap connection error: The Well Taps should bias the Wells
as specified in the schematics

Courtesy: asicpd.blogspot.in
 ASIC Physical Design
Physical Verification (ERC)
• Well Tap Density Error: If there is no enough Taps for a
given area then this error is flagged
• Taps need to be placed regularly which biases the Well to
prevent Latch-up
e.g., In typical 90nm process the Well Tap Density Rule require Well-
taps to be placed every 50 microns
• Tools: Mentor Graphics Calibre, Synopsys Hercules, Cadence
Assura, Magma Quartz
 ASIC Physical Design
DFM Checks
• Antenna Check (Gate-Oxide Integrity check)
— Maximum net length restriction connected to Gate terminal
• Redundant Contacts/ Via
— Multiple Via improves both Yield and Timing by resistance paralleling
• Metal Filling
— Narrow Metal Layer separated from other Metal Layers may get high
density of etchant than closely spaced wires
— Over etched filling up empty tracks with metal shapes to meet Metal
Density Rules
• Metal Slotting
— Wide metal lines (Power Nets) expands significantly due to the high
temperature during fabrication leads to destruction of the isolation
and passivation layer that protect the wafer
— To avoid it put slots or holes in these metal layers at regular intervals
— Slotting also prevent the stress damage during wafer dicing and
packaging
 ASIC Physical Design
Formal Verification
• Formal Verification
— Verify the two representations of circuit design exhibits same behavior
— Checks the behavior of the Combinational Logics by checking the
Compare Points
— Targets implementation errors and not the design errors
— Power checks: checks Power Switches/ Retention Cells/ Isolation Cells/
Level Shifters and all power connectivity
— If any manual editing in the design then LEC has to be done at any
point of time
• Informal Verification
(Simulation)
• Formal Verification
—
Complete coverage
—
Effectively
simulation exhaustive
—
Cover all possible —
Incomplete coverage
sequences of inputs —
Limited amount of simulation
—
Check all corner cases —
Spot check
of input a limited number
sequences
—
No test vectors are needed —
Many corner cases not checked

— Designer provides test

vectors
 ASIC Physical Design
Formal Verification
• Types of Formal Verification
— Gate-level to Gate-level (Logical Equivalence Check after Routing)
• To ensure that some netlist post-processing did not change the functionality of the
circuit
•RTL to Gate-level (after Synthesis)
—
To verify that the netlist correctly implements the original RTL code
•RTL
Toto RTLthat
(before Synthesis)
—
• verify two RTL descriptions are logically identical
Logical Equivalence Check (LEC) will have two stages
—
— Constrains
Logical setup stage
Equivalence Check stage
• Tool will report equivalent/ non-equivalent/ abort/ not-checked
• Input Requirements
— Netlists (.v)
—
— Library (.lib (.sdc)
Constraints and .lef)
• Tools: Mentor Graphics FormalPro, Cadence Conformal, Synopsys Formality,
Magma Quartz Formal
 ASIC Physical Design
Parasitic Extraction
• Parasitic Extraction: Importance
— Shrinking process geometries
— New device structures
— An increasing number of metal layers at each new process node
— Much more closer nets at each new process node
— Increasing wire aspect ratio of height to width
— Increasing operating frequency
• Parasitic Capacitance can be reduced by using higher metals,
provide spacing, shielding, Avoid parallel routing
• At higher clock frequencies, RC interconnect modeling is no
longer adequate and inductance must be included in
interconnect modeling
• Reluctance (Inductance) effect becomes more and more
prominent as the resistance (both device and interconnect)
decreases and the operating frequency increases
 ASIC Physical Design
Parasitic Extraction
• Capacitance
C= εo W H/d
— Transistors
 Depends on area of transistor gate, physical of materials, thickness of insulator, diffusion
to substrate
— Poly to Substrate L
 Parallel plate and fringing d i H
— Capacitance between W
conductors
 Coupling Capacitance
 Area Capacitance
 Fringing Capacitance
 Crossover Capacitance
 ASIC Physical Design
Parasitic Extraction
• Coupling Capacitance/ Lateral Capacitance
— The capacitance between nets on the same Metal layer
— Dominant
technologyover interlayer capacitances with every new process
• Fringing Capacitance
— Capacitance
layers due tobetween
Sidewall nets of different Metal layers and other
Capacitance
• Parallel/Crossover Capacitance

— Capacitance
of 2 differentbetween nets
Metal layers
area area
• Area Capacitance
SUBSTRAT
E
— Capacitance between Metal layers and Substrate
• In modern
levels of processes,
metal is so the width
small that of interconnect
the Fringing wires at of
Capacitance lower
the
wire is larger than the Area Capacitance
 ASIC Physical Design
Parasitic Extraction
• Resistance
R = ρ L/H W
— Wire Resistivity
— Complex 3D geometry around Vias

• Inductance
— Self Inductance;
— Mutual Inductance,
— At high frequency Skin effect possibility
• Models used for Parasitic Extraction
— Lumped-C, Lumped-RC, Lumped-RLC
— Pi segment
— Pin-to-pin delays are modeled by RC delays
 ASIC Physical Design
Parasitic Extraction
• Sub-femto Farad accuracy required for extraction of designs at
advanced technology nodes
• STA tool uses extraction data at fast corner while calculating
hold and slow data while calculating setup to be pessimistic as
possible, so that your chip doesn't fail after it comes back
from the fab
• Common Extraction Formats: Standard Parasitic Format (SPF),
Reduced Standard Parasitic Format (RSPF), Detailed Standard
Parasitic Format (DSPF), Standard Parasitic Extraction Format
(SPEF)
• Tools: Synopsys Star-RCXT, Cadence QRC, Mentor Graphics
Calibre xRC
 ASIC Physical Design
Timing Analysis
• Static Timing Analysis: Methodical analysis of a digital circuit to
determine if the timing constraints imposed are met and to
check the design is working properly
• Static Timing Analysis Flow
— Read the inputs required
— Setting
(False/ up Constraints: IO Delay Constraints, DRVs, Timing Exceptions
Width Multi-Cycle paths), Recovery and Removal, Minimum Pulse
— Construct
Clock, CaseTiming Graph: Partition Clock Domain, Ideal/ Propagated
Analysis
—
— Propagation
Timing Report: End points with violations/ Paths enumeration
• Input Requirement
— Routed Netlist (.v)
— Libraries (.lib only)
— Constraints (.sdc)
—
— Delay Format
Parasitic Values(.sdf)
(.spef)
• Tools: Synopsys PrimeTime, Cadence ETS, Cadence Tempus
 ASIC Physical Design
Timing Analysis (SI)
• Signal Integrity (SI)
— SI refers to the quality of the signal transportation during the circuit
operation
— In deep sub-micron the delays associated with the logic elements far
outweighed delays associated with the interconnect
— SI effects like Crosstalk (both noise and timing), Voltage (IR) Drop,
Waveform Integrity and Electromigration have complex
interdependencies
— When the technology shrinks, the effect of coupling capacitance also
increases
— Crosstalk is the undesirable phenomenon, caused by the cross
coupling capacitance between metal wires in a chip
— Signal Integrity comes as an added feature of Timing Signoff tools
— Crosstalk effects can be analyzed by enabling the SI switch in tools
— If Crosstalk is enabled then the tool will by default do the timing in
On Chip Variation (OCV) mode
— Tool can read the .spef consists of coupling capacitance info.
 ASIC Physical Design
Power Analysis & IR Drop Analysis
• Power Analysis
— Static/ Leakage Power Analysis
— Dynamic Power Analysis
• IR Drop Analysis
— Static IR Drop Analysis
— Dynamic IR Drop Analysis
• Tools for Power and IR Drop Analysis
— Synopsys Prime Power
— Cadence EPS and Voltus
— Apache Redhawk
• Tape-out
— Final GDSII (Graphical Data Stream Information Interchange) or CIF
(Caltech Intermediate Format) to Foundry
— GDS contains Physical Layout information
Thank
You