L-4 Peripheral Interfac by Arpita Mam

PERIPHERAL
INTERFACING
Arpita howlader
Dept of Computer & Communication Engineering
Patuakhali Science and Technology University
CCE- 321 (Computer Peripheral and Interfacing) 1

Peripherals interfacing
• Interface is the path for communication between two components.
• Interfacing is of two types, memory interfacing and I/O interfacing.
• Microcontroller perform some operation on a data and gives the
output.
• Microcontrollers communicate with the outside via peripheral devices.
• Interfacing a microprocessor is to connect it with various peripherals to
perform various operations to obtain a desired output.
• Interfacing - transferring data between microcontrollers and
interfacing peripherals such as sensors, keypads, microprocessors,
analog to digital converters or ADC, LCD displays, motors, external
memories
• Memory Interfacing is used when the microprocessor needs to access
memory frequently for reading and writing data stored in the memory

Peripherals interfacing
• Transfer information between internal storage and external I/O devices
is known as I/O interface.
• The CPU is interfaced using special communication links by the
peripherals connected to any computer system.
• Peripherals connected to a computer need special communication links
for interfacing them with the central processing unit.
• Each I/O module interfaces with the system bus and controls one or more
peripheral devices.
• Why an I/O device or peripheral device is not directly connected to
the system bus?
– The data transfer rate of peripherals is often much slower than that of the
memory or processor.

Digital Communication
• Considered as the communication happening between two (or more)

devices in terms of bits.
• Transferring of data, either wirelessly or through wires, can be either one
bit at a time or the entire data (depending on the size of the processor
inside i.e., 8 bit, 16 bit etc.) at once.
• Classification
– Serial Communication
– Parallel Communication.
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CCE- 321 (Computer Peripheral and Interfacing)
• Parallel Communication
– Transferring of the bits in a parallel fashion at a time.
– despite using a single channel between sender and receiver, various links
are used and each bit of data is transmitted separately over all the
communication link.
– For connecting multiple lines between sender and receiver multiple
connecting unit are to be present between a pair of sender and receiver.
– Not suitable for long distance transmission, because connecting multiple
lines to large distances is very difficult and expensive.
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• Serial Communication
– Transferring of data bit by bit, sequentially.
– Communication needs only one line for the data transfer.
– highly suitable for long distance signal transmission as only a single
wire or bus is used
– It is slower.
– Hardware requirement is simple.
– E.g. RS-232C
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Serial Communication
• Serial communication reduce the cost of an IC package by reducing
the number of pins used for communication between different IC’s,
instead of using parallel communication.
• Modes of serial data transfer
i) Simplex mode
• Data travel in only one direction. E.g. from computer to printer
ii) Half duplex mode
• Data travel in both directions but not at the same time.
iii) Full duplex mode
• Data travel in both directions at the same time.
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• In Serial the data is sent sequentially and latched up at the receiving end thus
procuring the entire data from the data bus using USART/UART (Universal
Synchronous Asynchronous Receiver Transmitter) without any loss in
synchronization
• Types of serial data transfer
i) Synchronous Serial Communication
– Both transmitter and receiver are synchronized by same clock pulse.
– It is also called clock-oriented data transmission and use the Synchronous
method.
– Speed: >20 Kbps
– Always implemented with hardware.
Synchronous communication requires common timing signals and common
clock for synchronization. This means that as well as the data, the clock signals
must also be transmitted along. In synchronous method a block of data at a time
is transmitted.
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Synchronous Serial Communication
– Synchronous Transmission is efficient, reliable and is used for transferring a
large amount of data.
– Communication is performed is based on a synchronization signal added to
each bit from the sending side.
– Transmitter shifts data onto serial line using own clock and receiver extracts
data using the clock provided by transmitter
– Synchronization between the source and target is required so that the source
knows where the new byte begins since there is no space between the data.
– It provides real-time communication between connected devices. Chat
Rooms, Video Conferencing, telephonic conversations, as well as face to
face interactions, are some of the examples of Synchronous Transmission.
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ii) Asynchronous Serial Communication
– In Asynchronous Transmission data flows as 1 byte or a character at a time.
– A start bit is used to identify the beginning of each character and at least
one stop bit is used to identify end of data character
– Effectively, the sender and receiver are synchronized on a character by
character basis.
– Asynchronous serial data communication is widely used for character-oriented
transmissions, while block-oriented data transfers use the synchronous
method.
– each character is placed between start and stop bits. This is called framing.
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Asynchronous Serial Communication
– Start and Stop bits
• Each character is put between a start and stop bits, called framing. Data
such as ASCII characters are packed in between a start bit and stop bit.
• The start bit is always one bit, but the stop bit(s) can be one or two bits.
The start bit is always a 0 (low) and the stop bit(s) is 1 (high).
• The example below gives the framing of the ASCII character “A”, where,
binary 0100 0001, is framed in between the start bit and two stop bits.
Notice that the LSB is sent out first.
• Transmission begins with a start bit followed by D0, the LSB, and then the
rest of the bits until the MSB (D7), and finally, the 2 stop bits indicating
the end of character “A”.
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– The COM port connectors in our laptops and PCs are a typical example of serial
communication. Ethernet, I2C (inter-integrated circuit), SPI (Serial Peripheral
Interface) and UART/USART all follow serial interfacing.
– This has a full duplex communication as the wires for both the TX-RX
communication is different.
– Full duplex communication means that the transmission and reception can occur
simultaneously. Data transmission requires a start bit, an end bit and a parity bit.
• The start bit initiates the communication by informing the receiver.
• The end bit indicates the end of the communication. While the start bit is
compulsory, end bit is optional.
• The parity bit is for error detection
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– The COM port connectors in our laptops and PCs are a typical example of
serial communication. Ethernet, I2C (inter-integrated circuit), SPI (Serial
Peripheral Interface) and UART/USART all follow serial interfacing.
– The RS232 (Recommended Standard-232) comes under UART. This
requires two channels – one transmitter and one receiver. In addition to
it, it requires a common ground too.
– Data transmission requires a start bit, an end bit and a parity bit.
• The start bit initiates the communication by informing the receiver.
• The end bit indicates the end of the communication. While the start bit
is compulsory, end bit is optional.
• The parity bit is for error detection
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– The USART needs a common clock line but the RS232 being UART
does not require one.
– The data size varies from 5 to 9 bits. The requirement for RS232
communication is that the baud rate of both the transmitter and
receiver should be same.
– The UART, converts the signal into electrical pulse such that it can
be transmitted. The maximum distance for transmission with UART is
less than 50 feet.
– The Parallel port are now virtually non-existing because of the
universal serial bus (USB) being extensively used. Certain computer
buses though continue to use the parallel communication.
– The Conventional PCI (Peripheral Component Interconnect) is one of
the parallel bus. It uses a single synchronous clock bus.
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USART
• The USART (Universal Synchronous Asynchronous Receiver Transmitter)
module is a full duplex, serial I/O communication peripheral.
• It is packed in a 28 pin DIP (Dual In-line Package).
• It contains all shift registers, clock generators and data buffers needed for
serial communication.
• It can work in synchronous mode, or in asynchronous mode.
• The USART uses two I/O pins to transmit and receive serial data. Both
transmission and reception can occur at the same time i.e. ‘full duplex’
operation.
• To send a byte, the application writes the byte to the transmit buffer.
– The USART then sends the data, bit by bit in the requested format, adding
Stop, Start, and parity bits as needed.
• In a similar way, the USART stores received bytes in the receiver buffer.
– Then the USART can generate an interrupt to notify the processor to find
out if data has arrived.

8251A PCI (Programmable
Communication Interface)
• 8251 is a USART (Universal Synchronous Asynchronous Receiver
Transmitter) acts as a mediator between microprocessor and
peripheral for serial data communication.
• The 8251A is a programmable serial communication interface chip
designed for (Programmable peripheral designed )synchronous and
asynchronous serial data communication.
• packaged in a 28-pin DIP.
• Receives parallel data from the CPU & transmits serial data after
conversion.

8251A PCI (PIN Diagram)

• D0 – D7: Bi-directional, tri-state, 8-bit Data Bus. This pin allow transfer of bytes
between the CPU and the 8251A.
• RD (Read Control): Active low on this input allows the CPU to read data or status
bytes from 8251A.
• WR(Write Control): . This active- low on this input allows the CPU to write data
or command word to the 8251A.
• C/ D: (Control Word/Data): This input pin, together with RD and WR inputs,
informs the 8251A that the word on the data bus is either a data or control
word/status information. If this pin is 1, control / status is on the bus, otherwise
data is on the bus.
• CLK: This input is used to generate internal device timings and is normally
connected to clock generator output.
• RESET: A high on this input forces the 8251A into an idle state.
• CS : (Chip Select)When signal goes low, the 8251A is selected by the MPU for
communication.
CCE- 321 (Computer Peripheral

19
and Interfacing)
• T x D-(Transmit Data):-This is an output line for transmitting serial bits out .
• T x C-(Transmitter clock):-This input signal controls the rate at which the bits
are transmitted by the USART. In synchronous mode, the baud rate will be the
same as the frequency of T x C. In asynchronous mode, it is possible to select the
baud rate factor by mode instruction.
• T x RDY-transmitter Ready: This is the output signal. When it is high, it indicates

the buffer register is empty and USART is ready to accept a byte. It can be used
either to interrupt the MPU or to indicate the status. This signal is reset when a data
byte is loaded into the buffer.
• TxE-Transmitter Empty: This is an output signal. Logic 1 on this indicates the

output register is empty after transmitting all the characters. This signal is reset
when a byte is transferred from the buffer to the output register.

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and Interfacing)
• R x D-Receive Data: Bits are received serially on this line and converted into a
parallel byte in the receiver input register.
• R x C-Receiver clock: This is a clock signal that controls the rate at which bits are
received by the USART. In the asynchronous mode, the clock can be set to 1,16 or
64 times the baud.
• R x RDY-Receiver Ready: This is an output signal. It goes high when the USART
has a character in the buffer register and is ready to transfer into the MPU. This
line can be used either to indicate the status or to interrupt the MPU. When MPU
reads a data character, Rx RDY will be reset by the leading edge of RD signal.
• SYNDET (Sync Detect)/ BRKDET (Break Detect): This pin is used in

synchronous mode for detection of synchronous characters and may be used as either
input or output. In asynchronous mode this pin goes high if receiver line stays low
for more than 2 character times. It then indicates a break in the data stream.

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and Interfacing)
8251A Block Diagram:
• The functional block diagram of 8251A consists of five sections. They
are:
– Transmitter
– Receiver
– Data bus buffer
– Read/Write control logic
– Modem control.
• The functional block diagram is shown in fig:
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• Data Bus buffer :
– tri-state, bi-directional, 8-bit buffer is used to interface 8251 Block Diagram in
Microprocessor to the system data bus.
– D0-D7 : 8-bit data bus used to read or write status, command word or data
from or to the 8251A
• MODEM Control:
– This unit takes care of handshake signals for MODEM interface
– It provides control circuitry for the generation of RTS and DTR and the reception of CTS
and DSR.
– DSR (Data Set Ready) : Checks if the Data Set is ready when communicating with a
modem.
– DTR (Data Terminal Ready) : An active-low signal at this pin shows that the 8251 is
now ready to accept the data from the processor.
– RTS (Request to Send ) : Low signal indicates the modem that the receiver is ready to
receive a data byte from the modem.
– CTS (Clear to Send) : When 8251 receives a low signal at this pin then it clears all the
data present in the modem in order to allow further communication.
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• Read/Write control logic:
– The Read/Write Control logic interfaces the 8251A with CPU,
determines the functions of the 8251A according to the control word
written into its control register.
– It monitors the data flow. It controls the operation of the peripherals
depending upon the operation initiated by CPU
– This section has three registers and they are control register, status
register and data buffer.
– The chip select (CS) input is connected to an address decoder so the
device is enabled when addressed.
– The signals RD, WR, CS and C/D are used for read/write operations
with these three registers.
– when C/D high signal is present at this pin then control or status
register is addressed. While in case of low signal data register is
addressed.
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• Read/Write control logic:
– When the RESET is high, it forces 8251A into the idle mode.
– The CLK (clock input) is necessary for 8251A for communication with
CPU
– Control Register: 16-bit register for a control word consist of two
independent bytes namely mode word & command word.
• Mode word : Specifies the general characteristics of operation such as
baud rate, parity, number of bits etc.
• Command word : Enables the data transmission and reception.
– Status register:
• Checks the ready status of the peripheral.
• Status word in the status register provides the information concerning
register status and transmission errors.
– Data register:
• Used as an input and output port when the C/D is low .
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Mode Instruction
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Command Instruction
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• Transmitter section:
– The transmitter section accepts parallel data from CPU and converts
them into serial data.
– The transmitter section is double buffered, i.e., it has a buffer register
to hold an 8-bit parallel data and another register called output
register to convert the parallel data into serial bits.
– Whenever we want to transmit a character, that character must be
placed inside the transmitter buffer, which is to be shifted to output
register, from where it transmit the data bit by bit using TxD pin.
– TxD - Transmitted Data Output : Output signal to transmit the data to
peripherals
– TxC - Transmitter Clock Input : Input signal, controls the rate of
transmission.
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• Transmitter section:
– TxRDY - Transmitter Ready : Output signal, indicates the buffer
register is empty and the USART is ready to accept the next data byte.
– Tx E - Transmitter Empty : Output signal to indicate the output
register is empty and the USART is ready to accept the next data byte.
– When output register is empty, the data is transferred from buffer to
output register. Now the processor can again load another data in
buffer register.
– If buffer register is empty, then T x RDY goes high.
– If output register is empty then T x EMPTY goes high.
– The clock signal, T x C controls the rate at which the bits are
transmitted by the USART.
– The clock frequency can be 1, 16 or 64 times the baud rate.
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• Receiver Section:
– The receiver section accepts serial data and convert them into parallel data.
– The receiver section is double buffered, i.e., it has an input register to receive
serial data and convert to parallel, and a buffer register to hold the parallel
data.
– When the RxD line goes low, the control logic assumes it as a START bit,
waits for half a bit time and samples the line again.
– If the line is still low, then the input register accepts the following bits, forms a
character and loads it into buffer register at the rate determined by the receiver
clock.
– RxRDY - Receiver Ready Output: Output signal, goes high when the
USART has a character in the buffer register & is ready to transfer it to the
MPU.
– RxD - Receive Data Input : Bits are received serially on this line & converted
into a parallel byte in the receiver input register.
– RxC - Receiver Clock Input : Clock signal that controls the rate at which bits
are received by the USART.
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• Receiver Section:
– The CPU reads the parallel data from the buffer register.
– When the input register loads a parallel data to buffer register, the
R x RDY line goes high.
– The clock signal R x C controls the rate at which bits are received by
the USART.
– During asynchronous mode, the signal SYNDET/BRKDET will
indicate the break in the data transmission.
– During synchronous mode, the signal SYNDET/BRKDET will indicate
the reception of synchronous character.
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THANKS
END
INPUT / OUTPUT
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PERIPHERAL

CCE- 321 (Computer Peripheral and Interfacing) 1

CCE- 321 (Computer Peripheral and Interfacing) 2

CCE- 321 (Computer Peripheral and Interfacing) 3

• Considered as the communication happening between two (or more)

CCE- 321 (Computer Peripheral and Interfacing) 16

CCE- 321 (Computer Peripheral and Interfacing) 17

CCE- 321 (Computer Peripheral and Interfacing) 18

CCE- 321 (Computer Peripheral

• T x RDY-transmitter Ready: This is the output signal. When it is high, it indicates

• TxE-Transmitter Empty: This is an output signal. Logic 1 on this indicates the

CCE- 321 (Computer Peripheral

• SYNDET (Sync Detect)/ BRKDET (Break Detect): This pin is used in

CCE- 321 (Computer Peripheral

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