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    PIC 16f877a Memory Organization

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    Tarek Barhoum
    This document discusses memory organization, parallel ports, and clock cycles for the PIC16F877 microcontroller. It covers the program memory, data memory organization divided into banks, special function registers (SFRs), and how the parallel port can be used for both input and output. It also describes the four clock cycles (Q1, Q2, Q3, Q4) that make up one instruction cycle and how pipelining allows most instructions to execute in one cycle for efficient processing.

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    © All Rights Reserved
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    PIC 16f877a Memory Organization

    Uploaded by

    Tarek Barhoum
    372 views33 pages
    This document discusses memory organization, parallel ports, and clock cycles for the PIC16F877 microcontroller. It covers the program memory, data memory organization divided into banks, special function registers (SFRs), and how the parallel port can be used for both input and output. It also describes the four clock cycles (Q1, Q2, Q3, Q4) that make up one instruction cycle and how pipelining allows most instructions to execute in one cycle for efficient processing.

    Original Description:

    Introduction to Microcontrollers And Embedded Systems

    Original Title

    PIC 16f877A memory organization

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    © © All Rights Reserved

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    This document discusses memory organization, parallel ports, and clock cycles for the PIC16F877 microcontroller. It covers the program memory, data memory organization divided into banks, special function registers (SFRs), and how the parallel port can be used for both input and output. It also describes the four clock cycles (Q1, Q2, Q3, Q4) that make up one instruction cycle and how pipelining allows most instructions to execute in one cycle for efficient processing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    372 views33 pages

    PIC 16f877a Memory Organization

    Uploaded by

    Tarek Barhoum
    This document discusses memory organization, parallel ports, and clock cycles for the PIC16F877 microcontroller. It covers the program memory, data memory organization divided into banks, special function registers (SFRs), and how the parallel port can be used for both input and output. It also describes the four clock cycles (Q1, Q2, Q3, Q4) that make up one instruction cycle and how pipelining allows most instructions to execute in one cycle for efficient processing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 33

    Microcontrollers &

    Embedded Systems
    (MES)

    Lecture #4
    Memory Organization, Parallel Ports &
    Clock Cycles

    Instructor:
    Dr. Tarek Barhoum
    Agenda
    Memory of the PIC 16f877

    Parallel Input/Output

    Parallel Interface

    Connecting to the Parallel Port

    Clock and Instruction Cycles


    Memory organization of the PIC16F877 :
    Memory organization of the PIC16F877 :
    Program Memory
    Data Memory Organization
    Data Memory Organization
    Data Memory Organization
    Part of SFRs
    Part of bank 0
    Part of bank 1
    Part of bank 2
    W Register

    • W, the working register, is used by many instructions as the


    source of an operand. This is similar to accumulator in 8051.
    • It may also serve as the destination for the result of
    the instruction execution. It is an 8-bit register.
    Program Counter
    • Program Counter (PC) is 13 bit and capable of addressing an 8K word
    x 14 bit program memory space.
    • PC keeps track of the program execution by holding the address of
    the current instruction.
    • It is automatically incremented to the next instruction during the
    current instruction execution.
    FSR & INDF
    • FSR Register
    • (File Selection Register, address = 04H, 84H)
    is an 8-bit register used as data memory address pointer. This
    is used in indirect addressing mode.

    • INDF Register
    • (INDirect through FSR, address = 00H, 80H)
    INDF is not a physical register. Accessing INDF is actually
    access the location pointed to by FSR in indirect addressing
    mode.
    PCL & PCLATH

    • PCL Register
    • (Program Counter Low Byte, address =02H, 82H)
    PCL is actually the lower 8-bits of the 13-bit Program Counter. This is a both
    readable and writable register.

    • PCLATH Register
    • (Program Counter LATcH, address = 0AH, 8AH)
    PCLATH is a 8-bit register which can be used to decide the upper 5-bits of
    the PC. PCLATH is not the upper 5bits of the PC. PCLATH can be read from or
    written to without affecting the PC. The upper 3 bits of PCLATH remain zero
    and they serve no purpose. When PCL is written to, the lower 5bits of
    PCLATH are automatically loaded to the upper 5bits of the PC.
    Memory Map Registers

    • In order to start programming and build automated system,


    there is no need to study all the registers of the memory map,
    but only a few most important ones:

    • STATUS register – changes/moves from/between the


    banks.
    • PORT registers – assigns logic values (“0”/”1”) to the
    ports
    • TRIS registers – data direction register
    (input/output)
    STATUS Register
    • Is an 8-bit register that stores the status of the processor.
    • In most cases, this register is used to switch between the
    banks (Register Bank Select), but also has other capabilities.

    • IRP - Register Bank Select bit.


    • RP1:RP0: - Register Bank Select bits.
    • TO: Time-out bit Used in conjunction with PIC’s sleep mode
    • PD: Power-down bit
    • Z: Zero bit
    • DC: Digit carry/borrow bit
    • C: Carry/borrow bit
    Memory of the PIC16F877

    • Each one of them has a different role. Program Memory


    and Data Memory two memories that are needed to
    build a program, and Data EEPROM is used to save data
    after the microcontroller is turn off.
    PIC16F877A Program Memory

    • Is Flash Memory
    • Used for storing
    compiled code (user’s
    program)
    • Program Memory
    capacity is 8K x 14 bit

    Each location is 14 bits
    long
     Every instruction is
    coded as a 14 bit word
    • PC can address up to 8K
    addresses
    • Addresses H’000’
    and
    H’004’ are treated in a
    special way
    PIC16F877A Data Memory (RAM)

    • Memory storage for variables


    • Data Memory is also known as Register File and consists of
    two components.
    • General purpose register file (same as RAM).
    • Special purpose register file (similar to SFR in 8051).
    • Addresses range from 0 to 511 and partitioned into 4
    banks
     each bank extends up to 7Fh (128 bytes).
    • The user can only access a RAM byte in a set of 4 banks
    and
    only one bank at a time. The default bank is BANK0.
    • To access a register that is located in another bank, one
    should access it inside the program. There are special
    registers which can be accessed from any bank, such as
    STATUS register.
    The main idea – parallel
    input/output

    • Almost any embedded system needs to transfer digital data between


    its CPU and the outside world.
    • This transfer falls into a number of categories, which can be
    summarized as:

    • Direct user interface, including switches, keypads, light-emitting


    diodes (LEDs) and displays.
    • Input measurement information, from external sensors,
    possibly being acquired through an analog-to-digital converter.
    • Output control information, for example to motors or other
    actuators.
    • Bulk data transfer to or from other systems or subsystems,
    moving in serial or parallel form, for example sending serial data
    to an external memory.
    The technical challenge of parallel
    input/output

    • Our immediate challenge is how to provide the required


    interface between the microcontroller data and address buses
    and the outside world.
    • How can we grab the data we want from the bus,
    and transfer it to the outside world, via the parallel
    port?
    • Alternatively, how can we take external input data and
    introduce it onto the data bus, at the right time and place, so
    that it gets to the right place within the microcontroller? 4
    • Finally, given a port that can do these things, how can we
    make it really flexible, so that it can be used for input, or
    output, or a mixture of both, and can transfer a combination
    of data with possibly very different end uses?
    Building a parallel interface

    • Two bits of a possible digital output port


    Two bits of a possible digital input port
    Connecting to the Parallel Port
    Switches & LEDS
    Connecting to the Parallel Port
    Switches & LEDS
    Connecting to the Parallel Port
    Switches & LEDS
    Clock and Instruction Cycles

    • Clock from the oscillator enters a microcontroller via OSC1 pin where
    internal circuit of a microcontroller divides the clock into four even
    clocks Q1, Q2, Q3 and Q4 which do not overlap.
    • These four clocks make up one instruction cycle (also called
    machine cycle) during which one instruction is executed.
    Clock and Instruction Cycles..

    • Execution of instruction starts by calling an instruction that is


    next in
    string.
    • Instruction is called from program memory on every Q1
    and is written in Instruction Register (IR) on Q4.
    • Decoding and execution of instruction are done between the
    next Q1 and Q4 cycles. The following diagram shows the
    relationship between instruction cycle and clock of the
    oscillator (OSC1) as well as that of internal clocks Q1 – Q4.
    • Program Counter (PC) holds information about the address of
    the
    next instruction.
    Pipelining in PIC
    • There are 35 single word instructions. A two-stage pipeline
    overlaps fetch and execution of instructions. As a result, all
    instructions execute in a single cycle except for program branches.
    These take two cycles since the fetch instruction is “flushed” from
    the pipeline while the new instruction is being fetched and then
    executed.

    Figure3: Instruction Pipeline Flow


    Pipelining in PIC
    END

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