CHAPTER 11:

CPU STRUCTURE AND

FUNCTIONS
Addun, Calvin John D.
Rozelle, Jose
Villena, Sean Jared
 PROCESSOR ORGANIZATION (11.1)
To understand the organization of the CPU, let us consider the requirements placed on the CPU, the
things that it must do:

 Fetch instruction: The CPU reads an instruction from memory.

 Interpret instruction: The instruction is decoded to determine what action is required.
 Fetch data: The execution of an instruction may require reading data from memory or an I/O
module.
 Process data: The execution of an instruction may require performing some arithmetic or logical
operation on data.
 Write data: The results of an execution may require writing data to memory or an I/O module.

To do these things, it should be clear that the CPU needs to store some data temporarily. It must
remember the location of the last instruction so that it can know where to get the next instruction. It
needs to store instructions and data temporar­ily while an instruction is being executed. In other words,
the CPU needs a small internal memory.
 Figure a. The CPU with the System Bus

Figure a. is a simplified view of a CPU, indicating its connection to the rest of the system
via the system bus. You will recall (Lecture 1) that the major components of the CPU are
an arithmetic and logic unit (ALU) and a control unit (CU). The ALU does the actual
computation or processing of data. The con­trol unit controls the movement of data and
instructions into and out of the CPU and controls the operation of the ALU. In addition, the
figure shows a minimal internal memory, consisting of a set of storage locations, called
registers.
 Figure b. CPU Internal Structure
Figure b. is a slightly more detailed view of the CPU. The
data transfer and logic control paths are indicated,
including an element labeled internal CPU-bus. This
element is needed to transfer data between the various
registers and the ALU because the ALU in fact operates
only on data in the internal CPU mem­ory.
REGISTER ORGANIZATION (11.2)
The register in the processor performs two
roles:

 User-Visible Registers: enable the machine- or assembly language

programmer to minimize main-memory references by optimizing use of
registers.

 Control and Status Registers: used by the control unit to control the
operation of the CPU and by privileged, OS programs to control the
execution of programs.
USER-VISIBLE REGISTERS

Categories:
 General Purpose
 Data
 Address
 Condition Codes 
GENERAL PURPOSE

General Purpose Registers

 can be assigned to a variety of functions by the programmer.
 Mostly these registers contain the operand for any opcode.
 In some cases these are used for addressing purpose.
DATA REGISTERS

Data Register
- to hold data and cannot be employed in the calculation of an operand address.
ADDRESS REGISTERS

Address Register
- they may be devoted to a particular addressing mode
 
 Segment Pointers: a segment register holds the address of the base of the segment
 Index Registers: are used for indexed addressing and may be auto indexed.
 Stack Pointer: If there is user-visible stack addressing, then typically there is a dedicated
register that points to the top of the stack.
CONDITION CODES

Condition codes
- are bits set by the processor hardware as the result of operations.

 Condition codes are bits set by the processor hardware as the result of operation
CONTROL AND STATUS REGISTERS

Four Essential Registers:

 Program Counter (PC) – Contains the address of an instruction to be
fetched.
 Instruction Register (IR) – Contains the instruction mostly recently fetched.
 Memory Address Register (MAR) – Contains the address of a location in
memory.
 Memory Buffer Register (MBR) – Contains a word of data to be written to
memory or the word mostly recent read.
PROGRAM STATUS WORD

Program Status Word (PSW)

- also essential, common fields or flags contained

include:

 Sign - sign bit of last arithmetic op

 Zero - set when result of last arithmetic op is 0
 Carry - set if last op resulted in a carry into or borrow out of a high-order bit
 Equal - set if a logical compare result is equality
 Overflow - set when last arithmetic operation caused overflow
 Interrupt Enable/Disable - used to enable or disable interrupts

Supervisor - indicates if privileged ops can be used  

THE INSTRUCTION CYCLE (11.3)
INSTRUCTION CYCLE WITH INDIRECT SUB-CYCLE
 Fetch - read next instruction from memory into CPU .
 Execute - Interpret the opcode and perform the indicated
operation.
 Interrupt - if interrupts are enabled and one has occurred, save
the current process state and service the interrupt.

 The Indirect Cycle

 Think of as another instruction sub-cycle
 May require just another fetch (based upon last fetch)
 Might also require arithmetic, like indexing
 DATA FLOW

 Exact sequence depends on CPU design

 We can indicate sequence in general terms, assuming CPU
employs:
o a memory address register (MAR)
o a memory buffer register (MBR)
o a program counter (PC)
o an instruction register (IR)
1. FETCH CYCLE

 PC contains address of next instruction to be fetched

 This address is moved to MAR and placed on address bus
 Control unit requests a memory read
 Result is
 placed on data bus
 result copied to MBR
 then moved to IR
 Meanwhile, PC is incremented
2. INDIRECT CYCLE

 IR is examined.
 If indirect addressing, indirect cycle is performed.
 Right most N bits of MBR (the memory reference)
are transferred to MAR
 Control unit requests a memory read
 Result(address of operand) moved to MBR
 
 
 
3. EXECUTE CYCLE

 May take many forms

 Depends on instruction being executed
 May include
- Register transfers
- Memory read/write
- Input/Output
 ALU Operations
4. INTERRUPT CYCLE

 Simple & Predictable

 Current PC saved to allow resumption after
interrupt
 Content of PC copied to MBR
 Special memory location loaded to MAR
 MBR written to
 PC loaded with address of ISR
 Next instruction cycle can be fetched
 
INSTRUCTION PIPELINING (11.4)

Pipelining:
 Pipelining is the process of accumulating instruction from the processor
through a pipeline. It allows storing and executing instructions in an orderly
process. It is also known as pipeline processing.
 It is a technique where multiple instructions are overlapped during
execution. Pipeline is divided into stages and these stages are connected
with one another to form a pipe like structure. Instructions enter from one
end and exit from another end.
There are two types of pipeline:
1.) Arithmetic pipelines: are usually found in most of the
computers. They are used for floating point operations,
multiplication of fixed point numbers.
2.) Instruction Pipelines: In this a stream of instructions can be
executed by overlapping fetch, decode and execute phases of
an instruction cycle. This type of technique is used to increase
the throughput of the computer system.
ADVANTAGES AND DISADVANTAGES:

Advantages of Pipelining:

 The cycle time of the processor is reduced.

 It increases the throughput of the system
 It makes the system reliable.
 
Disadvantages of Pipelining:
 The design of pipelined processor is complex and costly to manufacture.
 The instruction latency is more.
INSTRUCTION CYCLE STATE DIAGRAM:
TWO STAGE INSTRUCTION PIPELINE:
WHAT IS INSTRUCTION PIPELINING?
 An instruction pipeline reads instruction from the memory while
previous instructions are being executed in other segments of the
pipeline. Thus we can execute multiple instructions simultaneously.
The pipeline will be more efficient if the instruction cycle is divided
into segments of equal duration. This type of technique is used to
increase the throughput of the computer system.
THE CONCEPT IS SIMILAR TO A MANUFACTURING ASSEMBLY
LINE
MANUFACTURING ASSEMBLY LINE:

 An assembly line is a manufacturing process (often called a progressive

assembly) in which parts (usually interchangeable parts) are added as the
semi-finished assembly moves from workstation to workstation where the
parts are added in sequence until the final assembly is produced.
 Products at various stages can be worked on simultaneously
 Also referred to as pipelining, because, as in a pipeline, new inputs
are accepted at
one end before previously accepted inputs appear as outputs at the
other end
CONSIDER SUBDIVIDING INSTRUCTION PROCESSING INTO
TWO STAGES:

 Fetch instruction
 Execute instruction
 During execution, there are times when main memory is not
being accessed.
 During this time, the next instruction could be fetched and
buffered (called instruction prefetch
or fetch overlap).
WHAT IS INSTRUCTION PREFETCH?
Prefetching is a technique used in microprocessors to speed up the execution of a program. It
occurs when a processor requests an instruction from main memory before it is actually needed.
Once the instruction comes back from memory, it is placed in a cache and accessed later.
Performance is likely to be best when instructions are prefetched in program order.
If the Fetch and Execute stages were of equal duration, the instruction cycle time would be
halved.
However, doubling of execution time is unlikely because:
 Execution time is generally longer than fetch time (it will also involve reading and
 storing operands, in addition to operation execution)
 A conditional branch makes the address of the next instruction to be fetched unknown
 (although we can minimize this problem by fetching the next sequential instruction anyway)
To gain further speedup, the pipeline must have more stages. Consider the following
decomposition of instruction processing: 

Pipeline Units
 FI (Fetch Instruction) fetch next expected instruction into buffer
 DI (decode Instruction) determine opcode & operand specifiers
 CO (Calculate Operands) calculate effective address of each operand, i.e., mode

• Displacement
• Register Indirect
• Indirect
• etc
 FO (Fetch Operands) fetch each operand from memory

 operands in Registers need not be fetched

 EI (Execute Instruction) perform operation & store result, if any, in the specified

 destination operand location

 WO (Write Operand) store the result in memory 
TIMING DIAGRAM, ASSUMING 6 STAGES OF FAIRLY EQUAL DURATION AND NO BRANCHING
Notes on the diagram:
 Each instruction is assumed to use all six stages
Not always true in reality
To simplify pipeline hardware, timing is set up assuming all 6 stages will be used
 
 It assumes that all stages can be performed in parallel
Not actually true, especially due to memory access conflicts.
Pipeline hardware must accommodate exclusive use of memory access lines,
so delays may occur.
 Often, the desired value will be in cache, or the FO or WO stage may be null,
so pipeline will not be slowed much of the time.
 If the six stages are not of equal duration, there will be some waiting involved for shorter
stages.

 The CO (Calculate Operands) stage may depend on the contents of a register that could be
altered by a previous instruction that is still in the pipeline
 
 It may appear that more stages will result in even more speedup
 There is some overhead in moving data from buffer to buffer, which increases with more stages
 The amount of control logic for dependencies, etc. for moving from stage to stage
Increases exponentially as stages are added
 Conditional branch instructions and interrupts can invalidate several instruction fetches
EFFECTS OF A CONDITIONAL BRANCH
INSTUCTION PIPELINE:
UNPREDICTABLE EVENTS
 Not all instructions go through all six stages
 Memory conflicts exist
 All stages do not execute simultaneously with the same execution time
 CO Stage may depend on the contents of a register that could have been altered by an
instruction that is still in the pipeline
 Interrupts occur - disrupt the ideal conditions
 Conditional branch instructions may invalidate multiple instruction fetches
 Instruction 3 is a conditional branch to Instruction 15
 Branch not taken is not determined until the end of time unit 7
 Pipeline must be flushed
 During time unit 8 instruction 15 enters the pipeline
 No instructions complete during time units 9 through 12
THE SIX STAGE OF INSTRUCTION PIPELINE:
 INTEL 80486 PIPELINING
Intel i486 (often called 486 or 80486) is a series of 32-bit Intel scalar CISC micro processors that
are part of the Intel x86 processor family. i486 is the successor to the processor Intel 80386,
processor micro 486 first time introduced in the 1989

 
From the assessment device software, the instruction set of the family i486 is very similar
to its predecessor, the Intel 80386, with some bit instructions extra.
USES A 5-STAGE PIPELINE
1. Fetch
 From cache or external memory
 Use one of the two prefetch buffers, each measuring 16 bytes
 Fill the buffer with new data as soon as the old data is finished using
 On average it can take 5 instructions for one operation
 Be independent of other stages so that the buffer can remain full

2. Decode stage 1
 Opcode information and memory tracking mode
 At most take the first 3 bytes of an instruction
 Delegate to Decode stage 2 to retrieve the remaining instructions
 
3. Decode stage 2
 Develop o- mode into control signal
 Calculations for complex addressing modes
 
4. Execute
 Operations on the ALU
 Access cache
 Perform an update to the register

5. Write back
 
 Updating many registers and flag
 Results are sent to the cache and the bus write interface is buffered