EEG CIRCUIT DESIGN

NSF Project

Electrode circuit
EEG sensing Interference

Micro-Power EEG Acquisition SoC[10]

Amplifier & Filter

Instrumentation amplier block diagram

Chopper stabilized LNA (a) core topology and (b) complete topology

Two-stage op-amp with embedded chopper-modulators used in CS-LNA

Equivalent circuit model for CS-LNA

EEG recordings in man

Examples of records and results of analysis made by Braintune (St. Petersbuurg) hardware/software.

EEG Probe System

Hardware Block Diagram
Lo1 Chan 1 Gain Gain Lo2 AM Mod

Sum
Chan 1 Ref DRL Gnd AM Mod

XFMR

To PC

Dual Channel Low Noise Amplifier Board

Dual Channel AM Modulator Board

Nyquist Theorem
The highest frequency which can

be accurately represented is onehalf of the sampling rate.

The sampling rate here is below

the Nyquist frequency, so the result of sampling is nothing like the input:aliasing.
For practical purposes the

sampling rate should be 10 higher than the highest frequency in the signal.

EEG is a difference in potential between two electrodes

If two electrodes are active, it is called bipolar

recording. If one electrode is silent, it is called monopolar recording. The reference sites: ear lobe, mastoid, nose.

Bipolar vs. monopolar recordings

Monopolar recording is used in research,

because it enables the researcher to localize the event of interest.

Bipolar recording is used in BF, because it

reduces shared artifacts. Electrodes should be placed on the sites with the strongest gradients of the potentials under training.

EMG and eye blink artifacts in EEG

These types of

artifacts can be detected by visual inspection. Eye blinks can be excluded from data analysis. EMG should be taken into account during

EEG recorded at Cz

EEG is a mixture of waves at different

frequencies and amplitudes.

EEG recorded at T5

At each time interval several sine-waves at

different frequencies may be present in the signal.

Quality control of EEG recording

1) EEG amplifies must be calibrated with daily

checks 2) acquisition parameters must be checked daily and keep the same 3) the same procedures must be employed in all individuals 4) all artifacts must be eliminated or taken into account prior to spectral analysis.

EMG Artifact
EMG artifact starts as low as 12 Hz and ranges

to 300 Hz. Most of the spectrum lies between 30-150 Hz. Sites F3, F4, T3, T4, P3, P4 can pick up EMG the massester and temporalis muscles. Posterior electrodes can pick up EMG from occipitalis, trapezius and supraspinal muscles. To avoid this type of artifact one can relax or position the head properly or change slightly the position of electrode. Fz, Cz, Pz can give a relatively pure EEG signal.

EKG artifact
ECG artifacts occur from the electrodes that pick

up activity from underlying pulsating blood vessels in the scalp. EKG artifact gets more prevalent with aging.

The noise from the standard AC electrical line current

This noise can be diminished by the proper

grounding of the equipment (both computer and amplifies). It could be also eliminated by a so called notch filter which selectively removes 50 (60 for the US) Hz activity from the signal. This noise could be attenuated by obtaining good contact of electrodes with the scalp. The electrode impedance less than 10 kOhms is desirable.

EEG recording in man

Eyes opened condition. Examples of different waves.

Reviewing EEG
EEG is characterized by: 1) voltage 2) frequency (is used for BF) 3) spatial location (is used for BF) 4) inter-hemispheric symmetries 5) reactivity (reaction to state change) 6) character of waveform occurrence (random,

serial, continuous) 6) morphology of transient events

Reviewing EEG: voltage

Amplitude is the voltage in microvolts measured

from the peak of the wave to the trough of the wave. Varies from 10 mcV to 100 mcV with average around 20-50 mcV.

Reviewing EEG: frequency

Spectrums reflect the amount of energy in a

certain frequency range of EEG. Term monorhythmic means that a particular portion of EEG shows a rhythmic component in a singular frequency. Term polyrhythmic means that several rhythmic frequencies are present in EEG. The presence of large-amplitude delta-activity may indicate infarct or other lesion.

Reviewing EEG: frequency

Slow (0-4 Hz) and high (more 20 Hz) frequency bands

of EEG may pick up artifacts, such as eye movements and muscle activity, and therefore should be evaluated with caution. Despite the use of artifact rejection algorithms, the failure to accurately distinguish true physiological rhythmicity from the artifacts is a serious shortcoming of current software systems and requires the expert assessment.

Reviewing EEG: transient events

A transient is an isolated form or feature that stands

out from the background activity. It is called a spike if it has the duration less than 70 msec. It is called a sharp wave if it has the duration between 70 and 200 msec. The presence of large amplitude spikes and waves may indicate the presence of epilepsy.

Maps of EEG spectrums in standards bands

Eyes opened

condition.

EEG recording in man

Eyes closed condition. Enhancement of alpha waves.

Maps of EEG spectrums

Eyes closed

condition

EEG spectrums
Three conditions (EC, R, M)

are compared to Eyes Opened condition. Two peaks (in theta and alpha band) with different scalp distribution are observed. Reading and math produce big (but different) changes in alpha band and small changes in theta and beta bands. Note that alpha activities are different for all four conditions both in distribution and

EEG spectrums in individual bands

Regular theta -

idling rhythm Irregular theta working activity Reading and math produce alpha rhythms that are different in frequency and location.

EEG as a sequence of microstates

EEG consists of series of

short-lasting quasistationary epochs corresponding to what Lehmann et al. (1987) have called brain functional micro-states. EEG reflects the changes in the state of neuronal networks rather than specific aspects of information processing.

Normal distribution
When many independent

random factors act in an additive manner to create variability, data will follow a bell-shaped distribution called the Gaussian distribution. This distribution is also called a Normal distribution.
Although no data follows

that mathematical ideal, many kinds of data follow a distribution that is approximately Gaussian

Dysfunction as a deviation from normal distribution

If we measure some

parameter in the population with some brain dysfunction, then this parameter must has a different, not Gaussian distribution. There are statistical tests that measure this difference.

Bimodal distribution in ADHD?

Clinicians who diagnose this disorder have been criticized for

merely taking a percentage of the normal population who have the most evidence of inattention and continuous activity and labeling them as having a disease. In fact, it is unclear whether the signs of ADHD represent a bimodal distribution in the population or one end of a continuum of characteristics. This is not unique to ADHD as other medical diagnoses, such as essential hypertension and hyperlipidemia, are continuous in the general population, yet the utility of diagnosis and treatment have been proven. Nevertheless, related problems of diagnosis include differentiating this entity from other behavioral problems and determining the appropriate boundary between the normal population and those with ADHD.

Life span normative EEG database (LNDB)

There are at least four eyes-closed LNDB:
1) E. Roy John et al. (1977) 2) Frank Duffy et al. (1994) 3) Robert Thatcher et al. (1987) 4) Barry Sterman et al. (199?)

Three goals of LNDB

1) to assess the neurological basis for the

patients complains (the issue of organicity) 2) to identify the weakness of electrophysiological organization of the brain (the issue of neurotherapy design) 3) to evaluate the efficacy of treatment ( the issue of treatment evaluation) Thatcher, 1999

Active and passive conditions for NDB

1) Eyes opened and eyes closed conditions are

often used in NDB, because of simplicity and relative uniformity of recording conditions. 2) Active tasks depend of many uncontrolled factors, such as intensity of stimuli, the subjects involvement, the distance from stimuli, etc. There are no standards for active conditions.

What is an EEG?
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EEG stands for electroencephalogram EEG signals are created by measuring the difference in electrical currents across neuron membranes Electrodes attached to the body pick up these signals There can be a only a few electrodes or many attached to the head

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EEG signals
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Many naturally occurring signals in the human body effect EEG signals Frequency Analysis helps to separate the different signals

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Types of EEG signals

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EEG signals have been classified into 4 categories: Delta 0.3 to 4 Hz

u Dreamless sleep

Theta Alpha Beta

4 to 8 Hz 8 to 13 Hz above 13 Hz

u Associated with thoughts which produce dreams

u Result of unfocused thoughts u Result of interactions with environment
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Electrode placement
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Electrode placement can effect signals received

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Related Research
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Creating a Brain Computer Interface (BCI) has been a goal for researchers since computers were first introduced BCIs could help patients with motor disabilities use computers or mobility platforms What is necessary: Amplification Filtering Classification Control

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Related Research (cont.)

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Large programs researching BCIs: Wadsworth Center in Albany Graz University of Technology in Austria Problems facing the programs: Data transfer rate Efficiency Differences between test subjects Learning curve for new users

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Design Block Diagram

Adrian Smith, Daniel Shinn,Ken Grove,

Project ECE 4006 - Group N1

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Amplifier Board
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Built in previous semester Based on Thomas Colluras design, founder of Brainmaster Two stage amplifier

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7805 voltage regulator power supply Can use 9V battery or 6V-35V DC power supply

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Amplifier Schematic

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Amplifier Design
Stage 1 Gain of 50 Common Mode Rejection Ratio Provides noise reduction and signal centering Stage 2 Gain of 390 Capacitors stabilize power supply

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Amplifier Parts List

Resistors:
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Capacitors:
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(1) 10K 1/4W 5%

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(2) 1K 1/4W 5%
(3) 130K 1/4W 5% (2) 200K 1/4W 5% (2) 10M 1/4W 5%
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(1) 0.47uF 400V polypropylene (P474J) (3) 0.1uF 400V polypropylene (P104J) (2) 0.001uF 400V polypropylene (P103J) (1) 10uF 6.3VDC Tantalum

l
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(2) 200K 1/4W 5%

(1) 51K 1/4W 5%
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Integrated Circuits:
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(3) OP-90 amplifiers (1) 620AN amplifier (1) LM7805C voltage regulator

Other:
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(1) Set of 3 conductor signal leads

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Analog-Digital Converter
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Current board is a Keithley DAS-1701ST Installed in borrowed computer Must be moved but face PCI interface problem

Keithley KPCI-1307 card is the proposed solution

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Keithley KPCI-1307
l l l l l l l

100k samples/sec 16 single ended or 8 differential inputs AutoZero capability filters out drift 32 digital I/O

3 clock/timer
drivers included VHDL program or DriverLINX software options Price : $680
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VHDL Implementation
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Download code to Flex10k20 chip on Altera board Board receives signals from the KPCI-1307 and controls mechanical devices

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DriverLINX Implementation
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Create DLLs for data acquisition and signal routing Interface can be programmed in C C++ Visual Basic Active X

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Overview of Completed Objectives

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EEG Amplifier Order parts Assembly Testing Data Acquisition Board Order board Installation of board Installation of drivers and software

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EEG Amplifier (Parts)

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Resistors: (1) 10K 1/4W 5% (2) 1K 1/4W 5% (3) 130K 1/4W 5% (2) 200K 1/4W 5% (2) 10M 1/4W 5% (2) 200K 1/4W 5% (1) 51K 1/4W 5%

Capacitors: (1) 0.47uF polypropylene (P474J) [$1.62] (3) 0.1uF polypropylene (P104J) [$0.74]

(2) 0.001uF polypropylene (P103J) [$0.45]

(1) 10uF 6.3VDC Tantalum [$0.52]
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Integrated Circuits: (3) OP-90 amplifiers [$2.35] (DIP package was not available when placing orders so SOIC package was substituted with the use of an 8-pin SOIC to DIP adapter. Price reflects cost of DIP package, as this should be

ordered in future semesters.)

(1) 620AN amplifier [$5.92] (1) LM7805C voltage regulator [$0.43]
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Other: (1) Set of 3 conductor signal leads [$14.40] (3) Disposable electrodes for each testing session [$0.24]

(1) Pre-holed circuit board [$8.49]

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Data Acquisition Board - Installation

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KPCI-3107 16 analog single-ended or 8 analog differential. 32 digital outputs PCI interface CAB-1284CC-2 STP-36

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KPCI-3107 (DriverLINX software)

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Real-time data acquisition (with test panels) Analog/Digital I/O programming uses C++, VB, and Active X Real-time Triggering via driver
allows user to specify trigger voltage and action to take after device is triggered.

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Final Testing Waveforms

AIO Test Panel with Sine Wave input to Channel A

The test panel allowed for verification that the acquisition board was functioning correctly

Eyebrow and eye blinks were recorded and graphed using the A/D board.

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Final Testing Waveforms

T wo Ey e b r o w R a i se s
1 0. 8 0. 6 0. 4 0. 2 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2

T wo B l i n k s

0. 5 0. 4 0. 3 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2

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Board at End of Semester A/D Board

A/D board connected to Computer

Amplifier connected to A/D board with electrodes

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Ideas for Continuing the Project

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Build a low-noise case for STP-36 break-out boards. Calibrate gain for the EEG Amp input signal into an analog differential input channel. Research and learn how to use programming knowledge into a DriverLINX program. Program driver for KPCI-3107 board to output needed digital signal.

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Block diagram of the system

Brain Computer Interface Signal Processing Preprocessing
Feature Extraction by FD (CEM)

Classification (Detection)

Signal Acquisition

Application Interface

Feedback

EEG Signal Acquisition Module

Where to place the electrodes?
NASION

The electrodes are placed according to the

international standard 10-20 system.

FP1 F7 F3 FZ CZ F4 GND GND P3 T5 O1 O2 PZ P4 T6 REF FP2 F8

The electrode position of 16 channels placed as shown in Fig. of frontal area (F3 and F4), central area (C3, Cz and C4), parietal area(P3, Pz and P4)
T4

T3

C3

C4

The grounding electrode and referencing electrode are placed at forehead and right ear lobe respectively.
EEG signal are digitized at 1024 samples/sec, resolution 16bit/sample. Signal were analog bandpass filtered between 1.5 and 100 Hz.

FPGA Architeture

FPGA-

Field-programmable gate-array

Designers Choice

Digital designer has various options

integrated circuits) components

SSI (small scale integrated circuits) or MSI (medium scale

Difficulties arises as design size increases Interconnections grow with complexity resulting in a prolonged testing phase

Simple programmable logic devices

PALs (programmable array logic) PLAs (programmable logic array) Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designs Implementation of larger designs leads to same difficulty as that of discrete components

Designers Choice
Quest

for high capacity; Two choices available

MPGA (Masked Programmable Logic Devices)

Customized during fabrication Low volume expensive Prolonged time-to-market and high financial risk

FPGA (Field Programmable Logic Devices)

Customized by end user Implements multi-level logic function Fast time to market and low risk

FPGA A Quick Look

Two dimensional array of customizable logic block placed in an interconnect array Like PLDs programmable at users site Like MPGAs, implements thousands of gates of logic in a single device

Employs logic and interconnect structure capable of implementing multi-level logic Scalable in proportion with logic removing many of the size limitations of PLD derived two level architecture

FPGAs offer the benefit of both MPGAs and PLDs!

FPGA A Detailed Look

Based on the principle of functional completeness FPGA: Functionally complete elements (Logic Blocks) placed in an interconnect framework Interconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocks Circuits are partitioned to logic block size, mapped and routed

A Fictitious FPGA Architecture

(With Multiplexer As Functionally Complete Cell)

Basic

building block

Design Steps Involved in Designing With FPGAs

Understand and define design requirements Design description Behavioural simulation (Source code interpretation) Synthesis Functional or Gate level simulation Implementation Fitting Place and Route Timing or Post layout simulation Programming, Test and Debug

Field Programmability

Field programmability is achieved through switches (Transistors controlled by memory elements or fuses) Switches control the following aspects

Interconnection among wire segments Configuration of logic blocks

Distributed memory elements controlling the switches and configuration of logic blocks are together called Configuration Memory

Technology of Programmable Elements

Vary from vendor to vendor. All share the common property: Configurable in one of the two positions ON or OFF Can be classified into three categories:

SRAM based Fuse based EPROM/EEPROM/Flash based

Desired properties:
Minimum area consumption Low on resistance; High off resistance Low parasitic capacitance to the attached wire Reliability in volume production

Comparison: FPGA benefits vs ASICs:

- Design time: - Cost: - Volume:

Product FPGA vs ASIC

9 month design cycle vs 2-3 years No $3-5 M upfront (NRE) design cost. No $100-500K mask-set cost High initial ASIC cost recovered only in very high volume products

Due to Moores law, many ASIC market requirements now met by FPGAs
- Eg. Virtex II Pro has 4 processors, 10 Mb memory, IO

Resulting Market Shift: Dramatic decline in number of ASIC design starts:

- 11,000 in 97 - 1,500 in 02

FPGAs as a % of Logic market:

- Increase from 10 to 22% in past 3-4 years

FPGAs (or programmable logic) is the fastest growing segment of the semiconductor industry!!

FPGA/ASIC Crossover Changes

Cost FPGA Cost Advantage FPGA FPGA Cost Advantage Cost Advantage ASIC Cost ASICAdvantage Cost Advantage Production Volume

Taxonomy of FPGAs
FPGA

SRAM Programmed

Antifuse Programmed channeled

EPROM Programmed Array

Island

Cellular

Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control System

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, APRIL 2010

FPGA-Based

low-cost eld-programmable gate-array (FPGA)-based braincomputer interface (BCI) multi-media control system
Low cost Small size Flexible Real-time control

Use their brainwave to communicate with or control multimedia devices

Customized stimulation panel

a light-emitting diode stimulation panel instead of cathode ray tube or liquidcrystal display

stronger steady-state visual evoked potential (SSVEP)

SSVEP-based BCI multimedia control system

Brainwave-acquisition circuit

SSVEP acquisition

System Schema

Block diagram

Simulation panel

Implement and results

Implement and results

Implement and results

A CAPACITIVELY COUPLED SENSOR READOUT CIRCUIT [5]

Contact-less Capacitively coupled sensor Without any need for gel Electronic readout circuit

CIRCUIT DESIGN

CIRCUIT DESIGN
A. B. C. D. E.

Capacitive Sensor Instrumentation Amplier Notch FiltersSecond Amplication Stage PCB Layout

CIRCUIT DESIGN

DESIGN OF AN ELECTRONIC DEVICE FOR BCI [4]

Describes the single electronic stage for the conditioning of the analog acquired signal.

CIRCUIT DESIGN

Power supply Acquisition and signal conditioning Processing and transmission of digital data to PC.

CIRCIUT DESIGN

Input Guarding Configuration

EEG Machine
By The All-American Boys Featuring SloMo
Motaz Alturayef Shawn Arni Adam Bierman Jon Ohman

Goals and Perspective

Goals:
Design an EEG (Electroencephalography) machine to promote the generation of user selected brainwave frequencies Accesible Frequency ranges (Theta, Alpha, Beta) Using Audio and Video Feedback to synchronize brain

Block Diagram Description

PC/FOURIER WAVEFORM MONITOR

ELECTRODE INPUTS RAM CPU FLASH USER INPUTS AUDIO/VIDEO OUTPUTS

Physiology and Input Design

Electrode Input 1 Preamplifier Amplifier Low-Pass Filter High-Pass Filter

Summer/ Averager

A/D Converter

High-Pass Filter

Processor

Electrode Input 2

Preamplifier

Amplifier

Low-Pass Filter

Physiology of Neurofeedback
Brain waves divided into distinct frequency bands:
Delta: 0-3 Hz, Associated with slow wave sleep Theta: 4-7 Hz, Associated with drowsiness or arousal Alpha: 8-13 Hz, Associated with relaxed concentration or contentment Beta: 14-30 Hz, Associated with intense concentration, high levels of thought activity

Physiology Continued
Synchronization of Brain waves is possible
External stimuli used to synchronize brain wave frequencies
Our project will use both audio and video stimuli to synchronize waves

Can be used to train an individual to put themselves in desired state

Electrode Input Design

Five electrode two channel EEG headband for signal monitoring
Design compiled from multiple schematics Using active electrodes
Powered either with lithium batteries or hard line to main board

Small voltage values require ultra low noise devices

Amplification, Filtering, and A/D

Done at main board Amplifier strengthens microvolt signals to usable levels Signal passes through low-pass and high pass filters to remove DC components and higher frequency noise and brain waves
Possibly sent through band-pass filters as well

Digitized using low noise A/D converter

Design Aspects
Low signal levels require very low noise devices Battery powering could introduce too much signal noise unless properly shielded Two channels sufficient to measure frequency content
Differential voltage measurements Fifth electrode along scalp midline to create unbiased ground

Risks
Too much noise in system
Will distort signal and render it useless Can use commercial electrodes, conductive paste Filters should assist in removing noise, also use shielding techniques for battery and twisted pairs for wires

Two channels insufficient for measurement

Possible to build more channels

Filters drop off too shallowly to isolate bands

Only a problem if band-pass filtering is employed (Additional Feature)

Flash Memory and System Outputs

Physiological Effects of Outputs

Alter brain frequency through external stimulus
Auditory stimulus is most effective Produce a stimulating frequency equal to that of the desired brain frequency state
Binaural beats: Auditory processing artifacts, the perception of which arises in the brain independent of physical stimuli

Visual stimulus is another common option

A screen or monitor flashes an image at the rate of the desired brain frequency state

Memory Options
Two types
RAM (Volitile) ROM (Non-Volitile)
SD Card Flash
Easy to load

Board Mounted Flash

More permanent

Spansion Memory
8 MBIT Storage 3.0V Supply No Bus Contention Memory controller in Altera FPGA
Controller allows access to program and read data from memory Controller will also transfer data to audio/video controller for output

Output Flow

Risks
Not enough room in Flash for both audio and video signals
Can revert to SD Card where more space is available

High risk of epileptic seizures with a flashing monitor

Warning must be presented Auditory signal can be used exclusively

 PC : (Matlab or LabView)
Analyze the brainwave for frequency content and find the dominant frequency. Two Approaches of doing this: 1. Signal as a whole and do Power Spectral Density (PSD) analysis. 2.Divide the signal into 4 frequency bands then do PSD.
Risks
Not being able to debug the code with real brainwave signals. Synchronising the PC output with the whole system.

Processor Flow Diagram

Altera DE2 Development Board

I/O needs Readily available 32-bit Nios II embedded processor & SOPC Builder configuration & integration Quartus II - Scalable environment

DE2 Risks
Risks
Too much reliance on built-in features Input data usable? (ADC conversion) Potential usage of development boards many options may spread team too thin

Alternate choice MSP430

Processor Testing
Input Signals
User Input on LEDs Verify Electrode/ADC sample and store, as audio output Check DF result and store using 7-segment displays/LEDs Show difference between UI and DF on LED/7 segment

Processor Testing
Output Signal
Stored Electrode/ADC signal to PC, output as audio on PC

Wait State
Between samples illuminate LED

Budget
PCBs (3) 100 DAQ 150 Electrode Tips & Wires 50 Serial Cable 10 Serial Port & Controller 20 A2D Port & Controller 25 Onboard Memory 10 Audio Port, Controller & Headphones 70 Video Port, Controller & Monitor 300 SD Card, Card Slot & Controller 80 FPGA 100 USB Blaster Controller 40 Power 20 Misc 50 Total $ 1,025

Topics[9]
Exp. design and ERPs SPM for EEG-MEG 2D interpolation 1st level analysis 2nd level analysis Time as another dimension Time-frequency analysis Conclusion

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Popular approaches to M/EEG Data

Event-Related Potentials (ERP) & Event-Related Fields (ERF) ERP/F Quantification Approaches
Peaks, latency, area-under-curve

Spectral Analysis (a.k.a. time-frequency)

Connectivity

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What is the ERP/ERF?

-Def: the average (across trials/subjects) potential/field at the scalp relative to some specific event in time

Stimulus/Event Onset

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What is the ERP/ERF?

-Def: the average (across trials/subjects) potential at the scalp relative to some specific event in time

Averaging

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What is the ERP/ERF?

-Def: the average (across trials/subjects) potential at the scalp relative to some specific event in time

Reflects reliable changes in potential that are strongly timelocked to stimulus onset (i.e. are synchronous over trials)

Non-time-locked activity is lost to averaging

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Interpreting ERP/ERF Waveforms

ERP/ERF waveforms are often interpreted in terms of their constituent components Component (def) - Scalp-recorded electrical activity that is generated by a given patch of cortex engaged in a specific computational operation

sensor

+ + +

119

Chin-Teng Lin Che-Jui Chang Shao-Hang Hung Chih-Feng Chao

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 4, AUGUST 2010

Drowsy level detection

Safe car driving to alert tired drivers real-time drowsiness monitoring can prevent trafc accidents effectively

A preamplier, A band-pass lter An analog-to-digital converter (ADC) Designed to amplify and lter the EEG signal

The gain of the EEG amplier and acquisition unit was set to about 5040 times with the frequency band of 0.1100 Hz.

Design of a Compact Amplifier

[11]

DESIGN CONSIDERATIONS
A. Effects of Interference B. Amplifier requirements

System design

System design
A. Amplifier design B. Filter Stages C. Driven right leg circuit D. Power Supply design E. Construction of the system

Design on Sampling Circuit [12]

A sampling circuit of EEG signal based on

AT89C2051 single-chip is designed

signal condition, signal acquisition serial communication interface

BASIC CHARACTERISTICS OF EEG

SAMPLING CIRCUIT
A. Signal Condition

Circuit

Ciucuit

Performances
1) Amplifier gain is variable with 5000, 10000,

20000, or 30000.
2) Common mode rejection ratio is 102dB. 3) Pass-band frequency is with 0.12Hz-35.4Hz. 4) Input impedance is 113M.

References
[1] http://en.wikipedia.org/wiki/EEG [2] Design of a Compact Amplifier and Signal Conditioning Module for Wireless EEG Monitoring, Ashwin K. Whitchurch Member, IEEE, Jose K. Abraham [3] Novel Hydrogel-Based Preparation-Free EEG Electrode, Nicolas Alexander Alba, Robert J. Sclabassi, Mingui Sun, IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 18, NO. 4, AUGUST 2010 [4] Design Of An Electronic Device For Brain Computer Interface Applications, . Palumbo,P. Vizza,P. Veltri, MeMeA 2009 - International Workshop on Medical Measurements and Applications [5] Design and Evaluation of a Capacitively Coupled Sensor Readout Circuit, toward Contact-less ECG and EEG, Daniel Sard, Andrzej Cichockiand Atila Alvandpour, 2010 IEEE [6] Design of Portable Multi-Channel EEG Signal Acquisition System , Lin ZHU, Haifeng CHEN, Xu ZHANG, IEEE

References
[7] Design and Implementation of a Wireless Multi-Channel EEG Recording, R. Dilmaghani, M. Ghavami, K. Cumar, A Dualeh, S. Gomes Da Sousa, R. Salleh Mohd, CSNDSP 2010 [8] Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control System, Kuo-Kai Shyu, Member, IEEE, Po-Lei Lee, Ming-Huan Lee, Student Member, IEEE, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, APRIL 2010 [9] Joseph Brooks (ICN)Maria Joao (FIL) Methods for Dummies 2007Wellcome Department For Neuroimaging [10] A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System, Naveen Verma, Ali Shoeb, Jose Bohorquez, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 [11]Design of a Compact Amplifier and Signal Conditioning Module for Wireless EEG Monitoring, Ashwin K. Whitchurch (a), Member, IEEE, Jose K.Abraham (a), Senior Member, IEEE, Meghana A. Lonkar , 2007 IEEE Region 5 Technical Conference, April 20-21, Fayetteville, AR [12]Design on Sampling Circuit of EEG Signal Based on AT89C2051 Single-chip, Xiao-dong Zhang,Zhen-hai Zhang, 2009 Fourth International Conference on Innovative Computing, Information and Control