Unit 2 : Microcontroller and Processor architecture and Interfacing

Electronics and Communication Engineering Geethanjali College of Engineering and Technology

Cheeryal (V), Keesara (M), RR Dt. AP 501301 Email: [email protected]
Rev 1(5/1/2013)

Prepared by : Prof. K S Rao, E C E Dept

Topics:

8051 Architecture Input/Output ports and circuits External Memory Counters and Timers PIC Controllers Interfacing processor (8051, PIC) Memory interfacing I/O Devices Memory controller and Memory arbitration Schemes
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8051 Architecture
8051 features:
Processor: It is a 8bit microcontroller, with Harvard architecture, CISC system, with 1 MHz to 12 MHz clock. 11.0592 MHz clock is used to get proper baud rate speed for serial communication. Processor instruction cycle time is : 12 clock pulses ( 1 uSec for 12 MHz clock) Memory: Onchip 128 Bytes RAM and 4KB ROM exists. External Max. 64KB RAM and 64KB ROM can be connected. Registers: 16 bit PC, 16 bit DPTR ( as two registers of DPL and DPH of each 8 bit), SP (8 bit) are the various pointers. During reset, PC & DPTR will be zero, SP is loaded with 07h. A (Accumulator) and B Registers are the Math registers. ALU processes data using these two. It has 8 GPRs ( R0 to R7) in each bank. Four banks (Bank 0 to Bank 3) are available. Various SFRs (Special Function Registers) like TCON, TMOD, SCON, PCON, IE, IP. Other features: Interrupts: Two external interrupts and 3 internal interrupts are available. Two level priority (Using IP SFR) can be set. Interrupt vector addresses are 0003h, 000Bh, 0013h, 001Bh, 0023h. Interrupt masking can be done using IE SFR. Serial port: It has one serial port & can be used in 4 modes of operation (SBUF, SCON & PCON). Timers/counters: It has Two 16 bits timer/counters (T0, T1). 4 modes of operation using SFRs TCON and TMOD. I/O ports: It has four I/O ports (P0, P1, P2 & P3). Instruction set: Byte manipulation instructions, bit manipulation instructions are available. Floating point processor, Cache, Memory management unit, atomic operations unit, ADC, DAC facilities are not available in 8051.

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8051 Architecture

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8051 Architecture (Block diagram)

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Input/Output ports and circuits

There are Four I/O ports in the 8051. The circuit diagrams are given in the next slide. Port 0 is used for I/O, Ext Memory Address (Lower byte) and External memory data. Port 1 is used for I/O only. Port 2 is used for I/O, Ext Memory Address (Higher byte). Port 3 is used for I/O and various other purposes like Rx & Tx for serial port, INT0, INT1 for giving external Interrupts, Timer 0 and Timer 1 inputs for counting, write strobe & read strobe for external RAM. Latches are provided for each I/O port, to store the data for sending out. Port 0 has no internal pull up registers, where as port 1, port 2 and port 3 are having. Port 0 is called fully bidirectional port where as Port 1, Port 2 and Port 3 are called as Quasi bidirectional ports. In Port 0, if both the output FETs are OFF, the bit is treated as Input. If Top FET is ON, the bit is output as 1. If bottom FET is ON, the bit is output as 0. In port 1, 2 & 3, if the FET is ON the bit is output as 0. If the FET is OFF and this circuit is connected as output to other circuit, it is output as 1, through the pull-up. If the circuit is connected as input, then it is input with additional load of the pull-up for the external circuit.

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Input/Output ports and circuits

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External Memory
Memory : 128 Bytes internal RAM and 4 K internal ROM is available. ROM: If EA=0, Only external ROM is used. Internal 4K ROM is not considered. If EA=1, the first 4K ROM as internal and the balance 60K ROM as external, is considered. PSEN signal is used to read external ROM. RAM: Both internal and External RAM can be used, based on type of instruction (MOV or MOVX). RD, WR signals are used for reading / writing data into the external RAM. Connections: As P0 (Port 0) is used for sending lower byte address and the same port is also used for reading / writing data, an external latch is required to store the address using ALE signal. P2 (Port 2) is used for higher byte address. RD and WR signals are used for reading and writing pulses into the external RAM. The external memory connection diagram is given in the slide 10.

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External Memory
Internal memory allotment 128 bytes internal RAM is divided as *32 bytes used as GPRs in 4 banks (R0 to R7) *16 bytes used as 128 bit Addressable flags *balance 80 bytes as scratch pad ( General purpose)

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External Memory (Connection block diagram)

8051

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Counters and Timers

There are two 16 bit timer/counters in 8051. These can be used as timer if the count pulses to the counter are from the internal clock. It works as counter if the count pulses are from the external pulses. There are 4 modes of operation of the timer/counter. TMOD and TCON SFRs are used for the operation of the Timer/counters. TCON Register: Bit 7: TF1 Timer 1 overflow flag-sets when T1 overflows, clears when processor runs its ISR Bit 6: TR1 Timer 1 run control bit if set, T1 to count & if cleared, T1 to stop counting Bit 5: TF0 Timer 0 overflow flag. Sets when T0 overflows, clears when processor runs its ISR Bit 4: TR0 Timer 0 run control bit if set, T0 to count & if cleared, T0 to stop counting Bit 3: IE1 Sets with the falling edge of the INT1 input. Cleared when processor runs its ISR Bit 2: IT1 If set, INT1 triggers IE1 with falling edge, otherwise, low level signal triggers. Bit 1: IE0 - Sets with the falling edge of the INT0 input. Cleared when processor runs its ISR Bit 0: IT0 - If set, INT0 triggers IE0 with falling edge, otherwise, low level signal triggers. Bit 7 to Bit 4 are related to timer/counters. Bit 3 to Bit 0 are related to External interrupts. . TCON Register ISR=Interrupt service routine

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Counters and Timers

TMOD Register: Bit 7: Gate Timer 1 enables the count only when INT1 is high. I.e the count is enabled or disabled based on the external input. Bit 6: C/T If this bit is 0, it acts as a Timer. Otherwise, it acts as a Counter. Bit 5: M1 M1 and M0 are mode selection bits. 00 -> Mode 0, 01 -> Mode 1, 10 -> Mode 2 & Bit 4: M0 11 -> Mode 3 Bit 7 to 4 are timer/counter 1. Bit 3: Gate Bit 2: C/T Bit 1: M1 These are timer/counter 0 with the same above functions. Bit 0: M0 TMOD Register

Basic operation: The diagram for the operation of the timer/counter is given in the next slide. @ C/T bit of TMOD is used to select the count pulses as internal or external. # if the gate bit in TMOD is 1, then the output of OR gate $ is 1 only if INT is 1. Otherwise, $ is 0 and disables the count. If # is 0, the $ is 1 irrespective of INT input.

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Counters and Timers

i.e. if Gate bit is selected, the count will happen whenever the INT is 1. This will happen only when the * bit is 1 i.e. run control bit in TCON is selected. If this bit is not selected, there is no counting at all. The four modes of operation of the timer/counters is detailed in the next slide. $

* #

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Counters and Timers

Mode 0: As 13 bit timer/counter

Mode 1: As 16 bit timer/counter Mode 2; As 8 bit timer/counter with auto reload the preset value.

Mode 3: As 8 bit two counters and another 16 bit counter with out interrupt facility.

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PIC Controllers
PIC: Peripheral Interface controller Manufacturer: Microchip Technology Family: PIC16, PIC18,PIC24, PIC32 etc.

Note: Pl see the PIC18F458 data sheet for more details

PIC18F458 architecture: Processor: High performance RISC CPU with Harvard architecture ( Total 77 instruction set) Clock: DC to 40 MHz ( Execution speed: 10MIPS) Operating voltage: 2.0 V to 5.5 V Width: 16 bit wide instructions and 8 bit wide data Program memory: 32K Bytes Flash. Max Addressing capacity: 2 M Bytes Data memory: 1536 Bytes RAM and 256 Bytes EEPROM. Max. Addressing capacity: 4K Bytes IO Ports: A (6 lines), B,C, D, E(3 lines) ADC: 10 bit, with 5 channels input mux. ADC conversion available during sleep, using an internal RC oscillator. For DAC, PWM: 1 can be used. I/o Interfaces: I2C, SPI, USART, CAN 2.0B Timers: 8 bit-1No., 16bit 3Nos. Priority levels for interrupt: available Package: 40 pin DIP / 44 pin TQFP. Development tool : MP Lab IDE Both socket and software are upwardly compatible to the PIC 16 family. WDT: works based on internal RC Oscillator.

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PIC Controllers
External Clock circuit:
Crystal C1 and C2 are capacitors.

Registers in PIC 18
There are many registers in PIC18. Some of them are: Configuration Registers: oscillator selection, brownout register, Watch dog enable registers. I/O port related registers: PortA, PortB, PortC, PortD, PortE, LAT A, LAT B, LAT C, LAT D, LAT E, TRIS A, TRIS B, TRIS C, TRIS D, TRIS E. SFRs: T0CON, T1CON, T2CON, T3CON, INTCON, PIR1, PIE1, IPR1, and so on.

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PIC Controllers

Block Diagram

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PIC Controllers

SPI

I2C

CCPs : Capture compare Pulse width modules. SPI: Serial peripheral Interface Peripheral modules of a PIC controller I2C : Inter-Integrated Circuit CAN: Control Area Network USB: Universal Serial bus

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PIC Controllers
Pin diagram:

Most of the pins are used for multiple purposes.

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PIC Controllers
Operation of I/O ports:
If FETs P and N are OFF, OFF, then port line is Data IN. are ON, OFF, then port line is Data out 1. are OFF, On, then port line is Data out 0. Each port has 3 registers. For Port A, these are Port A, LATA & TRISA. Port A register is used for reading data. LAT A register is Data Latch and is for writing data. TRIS A register is Tristate register which sets the port either as input or as output. These registers are loaded as FF during MCLR, and hence, all ports are configured as input ports. Circuit varies for each port, based on the application of the port. Circuit for Port A is given here.

PORT A Block diagram.

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PIC Controllers
Operation of Timers: There are 4 timer counters in PIC18F458 controller. Timer 0 : TMR0 ( 8bit / 16 bit Timer counter); Timer 1 : TMR1 (16 bit timer counter) Timer 2 : TMR2 (8 bit timer counter); Timer 3 : TMR3 (16 bit timer counter) TCON register is used to configure timers. T0CON is for T0 and so on. The details of T0CON are as follows:

TOPS: Timer prescalar selector: 3 bits: 000 -> 1:2 (Fosc/4/2) 001 -> 1:4 (Fosc/4/4) and so on. 111 -> 1:256 (Fosc/4/256) Bit 3 : PSA : 1-> use Prescalar. 0 -> Do not use prescalar Bit 4 : T0SE: Timer source edge selection 1->raising edge, 0 -> falling edge to count Bit 5 : T0CS: Timer clock source select bit: 1->External, 0 -> Internal Bit 6 : T08BIT: TMR0 8bit / 16 bit counter 1-> 16 bit, 0->8 bit timer counter. Bit 7 : TMR0ON: 1-> Enable timer, 0 -> Stop timer.

TMR0IF (Timer 0 Interrupt flag) bit is set in INTCON register, when Timer 0 overflows.

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Interfacing processor (8051, PIC)

Interfacing Examples: P3 SI Rx P1-0 INT0 Using I/O ports, the interconnection details between the Microcontroller and the device are given below. With Keyboard Data from t2 onwards Acknowledge t1 Interrupt t0 Data at to Chip select at t1 Write at t2 INT0 Data Chip select Start command Channels address bits KB

controller
controller

P1/P2

P1-0 P3-WR
P3 INT0

DAC

With DAC

controller

P1/P0
P2-0 P2-1 P2-2

ADC

With ADC

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Memory controller
It is a circuit which manages of data going to & from the memory. It can be a separate chip or integrated with the die of micro processor. This is also called as MCC (Memory chip controller).
Ex.: Intel North Bridge a separate IC DEC Compaqs Alpha, AMDs Athlons 64, opetron, IBMs Power 5; Sun micro systems Ultra sparc, Intels core i7 have integrated memory controllers.

Purpose :

Memory controllers contain the logic necessary to read and write to DRAM, and to "refresh" the DRAM by sending current through the entire device. Without constant refreshes, DRAM will lose the data written to it as the capacitors leak their charge within a fraction of a second (not less than 64 milliseconds according to JEDEC standards).
Reading and writing to DRAM is performed by selecting the row and column addresses of the DRAM as the inputs to the multiplexer circuit, where the de-multiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation. Bus width is the number of parallel lines available to communicate with the memory cell. Memory controllers' bus widths range from 8 bit in earlier systems, to 512-bit in more complicated systems and video cards (typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 128 bit memory device

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Memory controller and Memory arbitration Schemes

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Memory Arbitration schemes

High speed interfaces Large amount of data to be transferred with in the applications in Dual port memory. Main processor can write and create graphics in the memory and video graphics hardware can fetch information from the same memory. Arbitration required for Dual port memory using MRDY signal. Software waits. Both software and graphics can work simultaneously using cycle steeling. Bank switched memory: shared access. Two modules M=1 and M=0 if one bank is under use by CPU, another bank will be used by graphics. Computer Bus address and data Graphic bus Address and data

Ref: Embedded micro computer systems by Jonathan w valvano Page 579

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