QUT Digital Repository:

http://eprints.qut.edu.au/
Nami, Ali Reza and Zare, Firuz and Ledwich, Gerard F. and Ghosh, Arindam and
Blaabjerg, Frede (2007) A new configuration for multilevel converters with diode
clamped topology . In Proceedings 8th International Power Engineering
Conference (IPEC 2007), pages pp. 661-665, Singapore.

Copyright 2007 IEEE
Personal use of this material is permitted. However, permission to
reprint/republish this material for advertising or promotional purposes or for
creating new collective works for resale or redistribution to servers or lists, or to
reuse any copyrighted component of this work in other works must be obtained
from the IEEE.

AbstractDue to the increased use of renewable energy and
power electronic applications, more multilevel converters (MLC)
are developed. A Neutral Point Clamped (NPC) inverter is one of
the most used multilevel topologies for wind turbine (WT) and
photovoltaic (PV) applications. One of the most crucial points in
this type of converter is dc-voltage control. In this paper, a novel
multi output dc-dc converter connected to a diode clamped
topology is presented. This converter, for a given duty cycles, is
able to regulate the capacitor voltage to provide an appropriate
input voltage for NPC regardless of load changes which can avoid
neutral point balancing problem in such converters. In addition,
the presented topology is suitable for renewable energy systems
to boost the low rectified output-voltage. In order to verify the
proposed topology, steady state analysis, modelling and
simulations are carried out.


,QGH[ 7HUPV-Multilevel inverter, diode clamped inverter,
neutral point voltage, dc-dc converter, multi-output converter.

I. INTRODUCTION
INCE wind turbine (WT) and photovoltaic (PV) systems
have been addressed by many researches, the need of
direct connection of these systems to a high and medium
voltage grids forces modification of the multilevel topologies.
Among them, (NPC) is the most common type of converter
which is widely used in WT and PV applications. Fig. 1 shows
a basic configuration of a three-level NPC topology. The most
crucial issue in NPC is the neutral point voltage balancing and
it has been studied by several authors [1-3].
Multi output dc-dc converters are such eIIicient and
economical devices which are used instead oI several separate
single output converters to make up a multi output power
supply |4|. Recently, several types oI multi output dc-dc
converters such as switched-capacitor, LLC resonant
topology, cross regulation and parallel regulation techniques
which are widely use in telecommunication, computers and
industrial Iields, are addressed in |5-8| respectively.
This paper proposes a novel dc-dc converter with series
capacitors in order to generate two diIIerent voltage levels Ior
NPC inverter. It can also be applied Ior more voltage levels.


The authors are with School oI Engineering Systems, Queensland University
oI Technology, Australia (e-mail: namiaqut.edu.au).
* ProI. Blaabjerg is with Aalborg University in Denmark.

Fig.1. A circuit conIiguration oI a traditional three-level NPC.
This converter basically operates as a boost or buck
converter based on duty cycles oI the switches in each
subinterval oI the switching period. In this converter, by
controlling the duty cycles oI the switches in each subinterval,
the output voltage can be controlled to provide the appropriate
input dc-voltage Ior the NPC. This can avoid the capacitors
voltage unbalancing in the diode clamped topology. Moreover,
by applying the presented topology in renewable energy
systems, low rectiIied output-voltage can be boosted to a
desired level.
In order to veriIy a Ieasibility oI this topology and its
application, steady state and dynamic analysis have been
carried out. Finally simulation results are compared with the
theoretical analysis both Ior the steady state and transient
modes.
II. BASIC OF CIRCUIT
A. basic configuration and circuit diagram
A basic conIiguration and circuit diagram oI the novel dc-
dc converter with two output-voltages is shown in Fig. 2 (a).
This circuit includes three switches which are named S
m
, S
1

and S
2
and two capacitors C
1
and C
2
with diIIerent loads R
1
and
R
2
. In the subinterval zero, S
m
is turned on and the inductor can
be magnetized by the current Ilowing through it. In the next
two subintervals, S
m
remains oII and the two switches, S
1
and
S
2
work in a complimentary Iashion to charge the capacitors.
When S
1
is on and S
2
is oII, the inductor current can charge
both C
1
and C
2
to produce v
1
and v
2
, respectively. On the other
hand, when S
1
is oII and S
2
is on in the last subinterval, C
1
is
being discharged through R
1
as reverse current Ilow is
prohibited by the diode, while C
2
is being charged by the
inductor current. Consequently the output voltage level can be
controlled by adjusting the duty cycle oI each switch.
A New ConIiguration Ior Multilevel Converters
With Diode Clamped Topology
A.Nami, F.Zare, SMIEEE, G.Ledwich, SMIEEE, A.Ghosh, FIEEE, F.Blaabferg
*
, FIEEE

S
661
978-981-05-9423-7 c 2007 RPS


(a)

(b)
Fig.2. A circuit diagram (a) with switch S1 (b) with diode D1.

Corresponding to circuit operation, it is possible to replace
the top switch S
1
by a diode, as shown in Fig. 2 (b). During the
second subinterval, the diode can direct the inductor current to
both the capacitors. However when S
2
is on in the last
subinterval, the diode obstruct the charging current through C
1

because the voltage across the diode will be negative. Thus the
switch S
2
conducts to direct the inductor current to C
2
.
Fig.3 shows the proposed dc-dc converter connected to a
three-level NPC which provides multi output voltages Ior the
converter. As described in the previous section, by controlling
the proposed dc-dc converter, the input dc-voltage oI inverter
can be regulated to v
1
and v
2
. The Iollowing sub-section
discusses the operation oI the dc-dc converter in steady state.


Fig.3: an application oI the multi output dc-dc converter topology Ior a three-
level NPC

B. Steadv State analvsis
With respect to Fig. 2 (b), diIIerent operation modes oI the
circuit are described as Iollows:
During the subinterval zero, S
m
is on and S
2
is oII. Fig.4
illustrates the equivalent circuit. The inductor is magnetized
by the input current and the capacitors are discharged through
the loads. Fig. 5 shows the capacitors currents and the inductor
voltage waveIorms.


Fig.4.Equivalent circuit in Iirst subinterval.

Fig.5.Capacitor currents and inductor voltage in Iirst subinterval.

During the subinterval one, S
m
and S
2
are switched oII.
Fig.6 shows the equivalent circuit. As shown in Fig. 6 and Fig.
7, the capacitors are being charged by the inductor current.

Fig.6.Equivalent circuit in second subinterval.

Fig.7.Capacitor currents and inductor voltage in second subinterval.

In subinterval two, S
m
is oII and S
2
is on. Fig. 8 shows the
equivalent circuit. As illustrated in Fig. 9, C
2
is being charged
by the inductor current and C
1
is discharging through R
1
.
662 The 8
th
International Power Engineering Conference (IPEC 2007)


Fig.8.Equivalent circuit in third subinterval.

Fig.9.Capacitor currents and inductor voltage in third subinterval.

In the steady state, the average capacitor current over one
switching cycle is equal to zero, thus
0 ) (
2
1
1
1
1
1
1
1
= + T D
R
J
T D
R
J
i T D
R
J
m
(1)
0 ) ( ) (
2
2
2
1
2
2
2
2
= + + T D
R
J
i T D
R
J
i T D
R
J
m
(2)
In above equations, T is deIined as a switching period and D
m,
D
1,
D
2
are duty cycles Ior subinterval zero, one and two,
respectively.
The average inductor voltage over one switching cycle is
equal to zero and as a result:
0 ) ( ) (
2 2 1 2 1
= + T D J J T D J J J T D J
dc dc m dc
(3)
Also
1
2 1
= + + D D D
m
(4)
By solving these three equations we have
2
1
2
2 1
2
1
1
) ( nD D D n
J nD
J
dc
+ +
=
(5)
1
1
2 1
2
) (
J
D
D D n
J
+
=
(6)
Where nR
2
/R
1
, the Iollowing relation holds Ior the inductor
current,
2 1
2
2
1 1
2
2
) (
R R J
R J R J
I
dc
+
=
(7)
As it can be seen, the output voltages in the steady-state are
related to J
dc
, D
1
, D
2
and R
2
to R
1
ratio.

C. Modelling of the circuit based on averaging method
To construct a small-signal ac model at the quiescent
operation (I, J
1
, J
2
), we can assume a small perturbation at the
operating point. Thus, the input variables are deIined as Iollow
) ( ` ) ( ) (
`
) ( , ) (
`
) (
2 2 2 1 1 1
t v J t v and t d D t d t d D t d
g g g
+ = + = + =

And the output variables are given by
) (
`
) ( ) ( ` ) ( , ) ( ` ) (
2 2 2 1 1 1
t i I t i and t v J t v t v J t v + = + = + =

Where each variable consists oI two parameters, a dc value
and a small perturbation signal. Thus, the above equations
associated with the inductor voltage and the capacitors
currents at diIIerent subintervals can be rewritten Ior this
situation. In the subinterval zero (Fig. 2), we have the
Iollowing equations:
T
g l
t v
dt
t di
L t v ) (
) (
) ( = =
(8)
1
1
1
1
) (
) (
) (
1
R
t v
dt
t dv
C t i
T
C
= =
(9)
2
2
2
2
) (
) (
) (
2
R
t v
dt
t dv
C t i
T
C
= =
(10)
Likewise Irom the subinterval one (Fig. 4) the equations are:
T T
T
g l
t v t v t v
dt
t di
L t v ) ( ) ( ) (
) (
) (
2 1
= =
(11)
1
1
1
1
) (
) (
) (
) (
1
R
t v
t i
dt
t dv
C t i
T
T
C
= =
(12)
2
2
2
2
) (
) (
) (
) (
2
R
t v
t i
dt
t dv
C t i
T
T
C
= =
(13)
Also Ior the subinterval three (Fig. 6), we have:
T
T
g l
t v t v
dt
t di
L t v ) ( ) (
) (
) (
2
= =
(14)
1
1
1
1
) (
) (
) (
1
R
t v
dt
t dv
C t i
T
C
= =
(15)
2
2
2
2
) (
) (
) (
) (
2
R
t v
t i
dt
t dv
C t i
T
T
C
= =
(16)
From (8 to 16), the average amounts oI inductor voltage and
capacitors currents over one switching cycle are computed as
Iollows:
[ ]
[ ]
T T
g
T T T
g
T
g m
T
t v t v t d
t v t v t v t d
t v t d
dt
t i d
L
) ( ) ( ) (
) ( ) ( ) ( ) (
) ( ) (
) (
2 2
2 1 1
+
+
=
(17)
1
1
2
1
1
1
1
1 1
1
) (
) (
) (
) ( ) (
) (
) (
) (
R
t v
t d
R
t v
t i t d
R
t v
t d
dt
t v d
C
T T
T
T
m
T

+
=
(18)

+
=
2
2
2
2
2
1
2
2 2
2
) (
) ( ) (
) (
) ( ) (
) (
) (
) (
R
t v
t i t d
R
t v
t i t d
R
t v
t d
dt
t v d
C
T
T
T
T
T
m
T
(19)
As the sum oI the duty cycles equals one, we have
1 ) ( ) ( ) (
2 1
= + + t d t d t d
m
(20)
Consequently, by substitution oI (14-16) in (17-19), the small-
signal equations can be extracted as below:
) (
`
) (
`
) ( ) ( ` ) ( ) ( ` ) ( `
) (
`
2 2 1 2 1 2 2 1 1 1
t d J t d J J t v D D t v D t v
dt
t i d
L
g
+ + =
(21)
The 8
th
International Power Engineering Conference (IPEC 2007) 663

) (
`
) (
`
) ( ` ) ( `
1 1
1
1 1
1
t d I t i D
R
t v
dt
t v d
C + + =
(22)
) (
`
) (
`
) (
`
) (
) ( ` ) ( `
2 1 2 1
2
2 2
2
t d I t d I t i D D
R
t v
dt
t v d
C + + + + =
(23)
Considering these equations and choosing the capacitors
voltages and the inductor current as the state vector variables,
where v
g
(t) and d(t) are the inputs oI small-signal ac model
oI the system, the ac circuit model can be deIined as shown in
Fig.10.


Fig.10: Small-signal ac equivalent circuit model oI a multi-output
converter
III. SIMULATION RESULT
The objective oI this section is to veriIy the proposed
topology by comparing the theoretical results Ior the steady-
state and modelling with the simulation results at diIIerent
conditions and operation modes. As presented in the Iinal
equations, in the steady state the output voltages can be
controlled by the duty cycles oI the switches and the load
impedance. In order to consider the eIIect oI the load on the
output voltages, simulations have been perIormed Ior three
diIIerent load conditions (n
1
1, n
2
1.5 and n
3
0.67) where
nR
1
/R
2
. The simulation results are shown in Fig. 11 to Fig. 13
Ior a wide range oI variables. These simulation results show
that the output voltage can be controlled by suitable duty
cycles regardless oI changes in the load. Another advantage oI
this topology is that the dc-dc converter can be either a boost
or a buck boost converter.

Fig.11.Variation oI V
1
and V
2
in terms oI D
1
and D
2
Ior n11


Fig.11.Variation oI V
1
and V
2
in terms oI D
1
and D
2
Ior n21.5


Fig.11.Variation oI V
1
and V
2
in terms oI D
1
and D
2
Ior n30.67

Fig.12 represents the output voltages in simulations Ior
three diIIerent load conditions in the steady state, where
T0.0001s, R
1
R
2
10O, D
1
and D
2
are 0.2. The simulation
results conIirm the theoretical analysis and the equations Ior
the steady state operation.
In order to veriIy the small-signal ac model, two diIIerent
simulations have been carried out in SIMULINK based on the
averaging model and the circuit diagram shown in Fig. 13 with
ideal components and same capacitors and inductor values.
The simulation results are shown in Fig. 13 and the only error
between these models are associated with the high Irequency
part oI the signal which is not considered in the averaging
techniques. For this case study, the load parameters chosen are
R
1
10O, R
2
10O, D
1
and D
2
are 0.2.
664 The 8
th
International Power Engineering Conference (IPEC 2007)


(a) (b) (c)
Fig.12.Output voltages Ior three load conditions (a) R1R2, (b) R21.5R1, (c) R11.5R2.



(a) (b) (c)
Fig.13. waveIorms Ior small-signal ac model and switching circuit model (a) v1(t), (b)v2(t), (c)i(t).


IV. CONCLUSION
In this paper, a new topology Ior a multi output dc-dc
converter is presented in order to supply input voltages Ior a
diode-clamp multilevel inverter. Using this circuit, the input
voltages oI the NPC can be adjusted to a desired voltage level
by the dc-dc converter thereby solving the main problem
associated with balancing the capacitors voltages in the NPC
topology. Furthermore, since the dc output voltage oI PV or
wind turbine systems are not very high, this topology is a
suitable candidate Ior these systems as it can boost the input
voltage Ior a transIormer less grid connection based on the
multilevel topology. To veriIy the operation oI this topology,
both steady-state and small-signal ac model have been
compared through simulation.

V. REFERENCES
|1| A.Bendre, G.Venkataramanan, D.Rosene and V.Srinivasan, Modelling and
design oI a neutral-point voltage regulator Ior a three-level diode clamped
inverter using multiple-carrier modulation, IEEE Transactions on Industrial
Electronics, pp. 718-726,Vol.53, June 2006.
|2| N.Celanovic, D.Boroyevich, 'A Comprehensive study oI neutral-point
voltage balancing Problem in three-level neutral-point clamped voltage source
PWM inverters, IEEE Transactions on Power Electronics, pp.242-249,
Vol.15, 2000.
|3| J.Pou, R.Pindado, D.Boroyevich, P.Rodriguez, 'Evaluation oI the low-
Irequency neutral point voltage oscillations in the three-level inverter, IEEE
IECON`2003, pp.21792184, Vol.3, November 2003.
|4| X.Yunxiang and G.Jiuchao, 'Study on the voltage stability oI multi-output
Converters, IEEE IPEMC`2004, pp. 482-486, Vol. 2, August 2004.
|5| I.Harada, N.hara, F.Ueno and I.Oota, 'Multi-output SC type DC-DC
Converter using a Ilexible capacitor ring operation, 'IEEE INTELEC`99, June
1999.
|6|Y.Gu,L.Hang,H.Chen,Zh.Lu,Zh.Qian and J.Li, 'A simple structure oI LLC
resonant DC-DC converter Ior multi-output application, IEEE APEC`2005,
pp. 1485-1490, Vol.3, March 2005.
|7| K N Bateson and D C Hamill, 'Cross-regulation in two related multi-
output resonant DC to DC converters, IEEE Power Electronics and Variable-
Speed Drives, pp. 262-267, October1994.
|8|A.Ferreres,J.A.Carrasco,E.Sanchis,J.M.Espi and E.Maset, 'Application oI
a novel parallel regulation technique in two output Iorward converter, IEEE
PESC`99, pp. 914-919, Vol.2, July 1999.
|9| J.Rodriguez, J.S.Lai and F.Zh.Peng, 'Multilevel inverters: A survey oI
topologies, control, and applications IEEE Transactions on Industrial
Electronics, Vol.49, August 2002.
The 8
th
International Power Engineering Conference (IPEC 2007) 665