CPLD-Oriented Design Projects for the First Course in Digital Systems

David J. Ahlgren Department of Engineering Trinity College Hartford, CT 06106

Abstract - This paper reports on enhanced educational outcomes that have been achieved at Trinity College by introducing complex programmable logic devices (CPLDs) and the hardware description language VHDL in the first course in digital design. Using Alteras Max + Plus II package and concurrent engineering practices, a team of eight students implemented a fully operational four-bit tiny CPU as a three-week final design project. Such successes demonstrate that modern CAD tools and use of CPLD's encourage creativity and system-level thinking in the first course.These basic outcomes are realized primarily through a sequence of introductory laboratory design projects. Based on the standard LSTTL family, these projects have included traffic light controllers, adders and subtractors, and minicommunication networks. Design has been facilitated by the use of a a user-friendly schematic-capture and simulation program, B^2Logic, that runs on Macintosh and PC machines. (B^2Logic is available from Beige Bag Software, Ann Arbor, MI.) Students use B^2Logic to enter and verify their LSTTL-based designs before constructing them thereby reducing hardware debugging time significantly. Still, the scope of student designs is limited by breadboard space and wiring complexity. The basic educational outcomes listed above have been augmented by the following enhanced outcomes: completion of a large, team-based design project that requires use of hierarchical design and concurrent engineering methods; experience in the use of an advanced CAD toolset; working knowledge of a useful subset of the standard hardware description language, VHDL. Underlying the enhanced outcomes is the belief that tackling problems large enough to require teamwork develops new skills that will prove useful in advanced courses, senior design projects (e.g. in digital signal processing and robotics), and on the job. Moreover, successful large projects would instill pride and be seen as exciting and contemporary.

Introduction
This paper focuses on educational outcomes that have been achieved by introducing complex programmable logic devices (CPLD's) in the introductory digital design course at Trinity College. It describes the pedagogical approaches and CAD tools used to engage students in large-scale projects that require teamwork and concurrent engineering methods. The paper introduces the CPU221/97 design, a working four-bit "tiny" processor that was developed by a team of eight students during a three-week period in Fall, 1997. This introductory course, ENGR 221L, is taken primarily by sophomores pursuing concentrations in electrical or computer engineering. It also attracts computer science majors. ENGR 221L has three one-hour lectures and a three-hour laboratory session each week. The basic outcomes expected of students are: a working knowledge of logic gates, flip-flops, synchronous sequential networks, and memory elements and their implementation in a standard logic family (LSTTL, primarily); the ability to design digital circuitry using standard methods (e.g., K-maps, state transition diagrams); the ability to use CAD tools for schematic capture and simulation; the ability to build and debug hardware circuits; familiarity with programmable logic devices (e.g. GAL22V10) and an associated hardware description language (ABEL or CUPL); the ability to complete a term project working closely with other students; the ability to write clear and complete documentation.

Pedagogical Approach
The keys to achieving the enhanced outcomes were twofold. First, the teaching of VHDL was integrated throughout the course. Whenever logic gates, MSI components, flip-flops, counters, and registers were introduced in class, students were given VHDL descriptions of them. These examples provided a basic knowledge of language structure and syntax and introduced a VHDL subset sufficient to develop CPLDbased designs. (This subset consists of the VHDL constructs: ENTITY, ARCHITECTURE, SIGNAL, TYPE, PORT, PROCESS, IF-THEN-ELSE, CASE..WHEN, WHEN...ELSE conditional assignment structure, and EVENT.) Second, the laboratory provided a smooth

transition between designing with standard logic circuits and CPLD's. This transition was eased by the CAD toolset used in ENGR 221L: Altera's Max + Plus II. The first four lab projects, which were carried out using LSTTL chips, took students through the basics of applying standard synthesis methods for combinational logic (K-Maps), using Beige Bag Software's B^Logic, and wiring and debugging circuits on a breadboard. The fifth lab design--a 4-bit adder/subtractor--was built first using LSTTL chips. In the next week's lab, students entered the same design with the Max + Plus II graphic editor using LSTTL equivalent cells from the Altera library. They added a BCDto-seven segment decoder developed in VHDL, connected the modules together using the Max + Plus II graphic editor, simulated the overall system, programmed the design into a single Altera EPM5032 device, and tested the programmed chip. In the next lab, students improved a skeletal design for an arithmetic logic unit (ALU) by increasing the word size and adding new logical operations. This exercise paved the way for the CPU221/97 final design project. From these VHDL exercises, students gained appreciation for the productivity increase that results from the use of VHDL and CPLD's. As a result, Max + Plus II and VHDL became the preferred design tools for the rest of the semester.

control element in a programmable system. Students were given a tutorial handout that included the following: 1) block diagram of the previous year's processor showing CPU sub-systems and their interconnections (ALU, addressing logic, bi-directional data bus interface, control unit including control logic and finite-state machine); 2) timing diagram showing the two-phase system clock, control unit states, and the timing of internal register transfers and data path multiplexer select signals; 3) programming model showing CPU registers (accumulator A, temporary register B, address register MAR, program counter PC, status register SR, and index register X); 4) initial instruction set and op-code list (Table I below) (Students were encouraged to revise this set.); 5) planning matrix where students recorded, for each machine instruction, the necessary register transfers at each microinstruction cycle of the CPU; and 6) program examples (e.g., subtraction program, and array summation program). (Assignment handouts are available from the author.) The planning matrix was the key instructional tool for this project. By completing it, students developed a full understanding of the state transitions and data transfers necessary to execute each machine instruction. From the matrix, they were able to develop a Boolean expression for every data path select signal and register transfer enable signal in the CPU.

Final Design Projects

With the background provided by these exercises, students were able to tackle their final design projects using Max + Plus II and Altera CPLD's. Handed out four weeks before the end of the term, the assignment included project suggestions, but it encouraged students to develop their own ideas. Students had worked in pairs throughout the term, a pattern that they were expected to continue. To attack final design projects, pairs could be combined to form larger teams. A one-page project prospectus was due on November 24, and the final project report was due on December 17. In addition to the CPU design, suggested projects included a vending machine, digital stopwatch, calculator, shutter speed tester, and serial ASCII interface. Of the twelve enrolled students, eight teamed up to work on the CPU, one worked on the calculator, and three teamed up to design a digital stopwatch. The CPU project implicitly led students to achieve the enhanced outcomes. Similar projects had been completed by ENGR 221L students each year since 1994. The problem required the development of a four-bit processor and associated EEPROM and RAM circuitry. Specific project goals included: 1) to introduce the stored program concept; 2) to introduce memory interfacing; 3) to introduce the concept of address and (bi-directional) data busses; and 4) to illustrate the application of a finite state machine as the

Results
In previous years, teams divided the CPU into sub-systems and assigned design and verification of a sub-system to each pair of students. In 1997, students organized themselves instead by job category, as follows: 1) team leader (one student); 2) programming and hardware design (three Instruction Load A immediate Load A direct Load A indexed Add immediate Add indexed NAND indexed Store A direct Store A indexed NAND immediate Unused Load X immediate Load X direct Store X direct Update X Immediate Branch uncondl Branch if zero Mnemonic LDAI LDAD LDAX ADDI ADDX NANDX STAD STAX NANDI * LDXI LDXD STXD UDXI BRA BEQ Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Table I: Initial Instruction Set

students); 3) memory system, wiring, and writing (three students); 4) librarian, chief simulator, and programmer (one student). The team made the following improvements to the initial design: expansion of the address bus from 7 bits to 8 bits, allowing the processor to access 256 locations--128 in ROM and 128 in RAM; deletion of the STAX instruction in the initial design and addition of op-codes OUTI and OUTX; design of a tone generator interfaced via a new CPU register sk and controlled by OUTI and OUTX. The tone generator is a table-driven presettable downcounter that divides a 30kHz external clock to yield a twooctave musical scale. Each element of this tiny computer, including CPU, external ROM and RAM, and sound generator, was verified using Max + Plus II. Then, the modules were integrated using the graphic editor, and full verification was carried out at the system level. After this step, the CPU221/97 design was programmed into an Altera MAX9320 84-pin CPLD. The design required 272 logic cells of the 320 available on the chip, the equivalent of approximately 5000 logic gates. The first programmed chip executed programs correctly. The wiring group created a bank of LED's that displayed data and address bus activity, register contents, and machine states. By running the CPU at a slow clock rate, the team could observe register transfers and state changes during the execution of each machine instruction. They programmed a second Altera CPLD (type MAX7064) as a buffer to drive the LED monitors. The MAX9320 and MAX7064 devices, both contained in 84-pin PLCC packages, were interfaced to a standard breadboard using convenient PLCC-to-DIP adapters, producing a clean circuit layout. (These adapters are available from Technological Arts, Toronto.) To demonstrate their system, the programmers developed code, in CPU221/97s machine language, to play "Mary Had a Little Lamb" and "Jingle Bells", the latter just in time for the holidays.

approach, complete, and document large projects that require teamwork and concurrent engineering approaches, in short time frames. For example, it would be impractical for sophomores to build, in the space of three weeks, the CPU221/97 processor from standard SSI and MSI components. Modern CAD tools and CPLD's encourage system-level thinking in the first course by enabling the completion of such large projects. The tools also encourage creativity; for example, ENGR 221L students were able quickly to design and implement a tone generator for CPU221/97 using VHDL. The success of this project and earlier CPU design projects in ENGR 221L has been a source of pride for students and has motivated the further study of digital electronics. The design experience provided in ENGR 221L has served as a springboard for independent study and senior design projects, especially in the application of digital design to robotics and DSP hardware development. Almost all students who have taken ENGR 221L go on to take a more advanced course in digital electronics, and several students have applied what they have learned about VHDL and CPLDs in ENGR 221L to their senior design projects.

Appendix: Getting Started

Altera CPLD technology and development tools are available from the Altera University Program, which can be contacted via the e-mail address [email protected] o r on the Web at http://www.altera.com. Altera donates software and CPLD chips to schools that offer courses in digital systems. There are no charges to the school for software support and maintenance. Altera is eager to receive course materials and student papers that may be shared with other University Program schools. Enrollment in the University Program is straightforward and may be accomplished through the Web site. Altera provides to member schools multiple copies of Max + Plus II software and documentation for PC's or workstations, support for hardware description languages (VHDL and AHDL) and interfaces to other EDA tools. (AHDL is the Altera Hardware Description Language.) In addition, participating schools receive the University Program Design Laboratory Package, which contains Max + Plus II Student Edition software and device programming hardware. Max + Plus II runs on appropriately-configured PCs equipped with Windows 95 or NT 3.51 or higher and on HP, Sun SPARC, and IBM RISC 6000 UNIX machines. Altera provides clear documentation about Max + Plus II installation and operation [1] and very readable manuals on VHDL and AHDL [2], [3]. Reference [2] includes a number of excellent VHDL templates that have helped ENGR221L students to understand language syntax and structure. In addition, the texts [4]-[7] have proved to

Conclusion
All ENGR 221L students achieved the basic outcomes of the course listed earlier in the paper. In addition, they developed a working knowledge of CPLD-based design and the use of VHDL as a means for describing and synthesizing digital systems. This success was made possible by the CAD tools, which enabled team-based design by supporting concurrent engineering of sub-systems and the hierarchical integration of these modules. An advantage of incorporating CPLD's in the introductory course is that students can

be helpful references for both teacher and students, and they are recommended by the author.

References
[1] Getting Started With Max+Plus II, San Jose, Altera Corporation, 1997. [2] Max+Plus II VHDL, San Jose, Altera Corporation, 1997. [3] Max+Plus II AHDL, San Jose, Altera Corporation, 1997. [4] K. Skahill,VHDL for Programmable Logic, Boston, Addison Wesley, 1996. [5] Z. Salcic, VHDL and FPLDs in Digital Systems Design, Prototyping, and Customization, Kluwer, 1997. [6] F. Scarpino, VHDL and AHDL, Prentice-Hall, 1998. [7] P. Ashenden, The Designers Guide to VHDL, San Francisco, Morgan-Kaufman, 1996.

Acknowledgements The author thanks the Altera University Program for its generous support. The author also acknowledges the hard work of the CPU221/97 design team: Amir Tamrakar, Sheldon Provost, Michael Kornhauser, Michael Lock, Nick Allen, Steve Baker, Patrick Hannon, and Brian Jackson