VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Belgaum, Karnataka-590 014

DIGITAL DESIGN AND COMPUTER ORGANIZATION

Subject Code: BCS302
(As per Visvesvaraya Technological University Syllabus)

B.E- 3rd Semester , Information Science and Engineering

Prepared and Reviewed By

Prof. Sushma.T.M. Prof. Chaitra.B.

Assistant Professor Assistant Professor

Approved By:
Dr. Kala Venugopal
Head of Department Information Science and Engineering

ACHARYA INSTITUTE OF TECHNOLOGY

(Affiliated to VTU, Belgaum, Approved by AICTE, New Delhi and Govt. of Karnataka),
Acharya Dr. Sarvepalli Radhakrishnan Road, Bangalore-560107.
Ph: 91-080-28396011, 23723466, 28376431
URL: www.acharya.ac.in
2023-24
 Table of contents

Vision, Mission, Motto of Institute I

Vision, Mission of Department II
Laboratory Objectives III
Program Specific Outcomes (PSOs) III
Program outcomes (POs) IV
Course outcomes (COs) VI
 MOTTO

"Nurturing Aspirations Supporting Growth" VISION “Acharya Institute of

Technology, committed to the cause of sustainable value-based education in all
disciplines, envisions itself as a global fountainhead of innovative human enterprise,
with inspirational initiatives for Academic Excellence”.

VISION OF THE INSTITUTE

Acharya Institute of Technology, committed to the cause of value-based education

in all disciplines, envisions itself as fountainhead of innovative humanenterprise,
with inspirational initiatives for Academic Excellence.

MISSION OF INSTITUTE

“Acharya Institute of Technology strives to provide excellent academic ambiance to

the students for achieving global standards of technical education, foster intellectual
and personal development, meaningful research and ethical service to sustainable
societal needs.”
 VISION OF THE DEPARTMENT

“To be centre of Academic and Research excellence in the field of Information

Technology inculcating value based education for the development of quality
Human Resource”

MISSION OF THE DEPARTMENT

“Equip students with fundamental concepts, practical knowledge and professional

ethics through dedicated faculty for higher studies and professional career in
various Scientific, Engineering and Technological streams leading to proficiency
in the field of Information Technology”
 DIGITAL DESIGN AND COMPUTER ORGANIZATION
[As per National Education Policy (NEP) scheme - Effective from the academic year 2021-22]

Semester III CIE Marks 50

Course Code BCS302 Exam Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 Total Marks 100
Total Hours of Pedagogy 40 hours Theory + 20 Exam Hours 03
Hours of Practicals

LABORATORY OBJECTIVES

Course Objective:
● To understand the working of simulide simulator.

 To understand the syntax of Verilog HDL and Modelsim simulator.

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various
course outcomes.

1. Chalk and Talk

2. Live Demo with experiments
3. Power point presentation

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: Able to apply knowledge of information management and communication systems to provide secured
solutions for real time engineering applications.
PSO2: Apply best software engineering practices, modern tools and technologies to deliver quality products.
 PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to provide
valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.
 COURSE OUTCOMES

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:

CO 6: Design combinational logic circuit using simulide simulator.

CO 7: Demonstrate the working of Verilog HDL for combinational and sequential logic circuit using
Modelsim simulator.

Course Outcomes-Program Outcomes mapping

Program Outcomes Program Specific

COs Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
3
CO-6 1
3
CO-7 1
 Rubrics for assessing student’s performance in Laboratory courses

The internals marks of lab for 2022 scheme is 15 Marks for Continuous Evaluation and 10 Marks for Lab Internals.
Continuous Evaluation for 2022 scheme:

Sl Parameters Mark 5 4 3 0
No
1. Writing Program/Logic 5 The student is The student is The student has The student is
(present able to write able to write the written not attempted
week’s/previous the program program with incomplete to write
week’s) without any minor logical program with program.
logical and error major logical
syntactical and syntactical
error and error
proper
indentation is
followed.
2. Implementation in the 5 Student is able Student is able Student is The student
target language with to execute, to execute the executed the has not
different inputs debug, and test program, but program executed the
the program for fails to debug, partially(fails to program.
all possible and test the meet desired
inputs/test program for all output)
cases. possible
inputs/test
cases.
Parameters 3 3 2 1 0
3. Record 3 Student Student submits Student fails to The student
submits the the record on submit the does not
record on time time but not record on time . submit the
and, neatly documented record.
documented properly with all
with all possible
possible input/output
input/output samples.
samples.
Parameters 2 2 1.5 1 0
4. Viva 2 Student Student answers Student Student fails
answers for for atleast 60% answers for to answer any
atleast 80% of of questions atleast 40% of question
questions questions
5. Internal Assessment 10
PRACTICAL COMPONENT OF IPCC :

Sl.NO Experiments

Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
1
using basic gates.

2 Design a 4 bit full adder and sub tractor and simulate the same using basic gates.

3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioral model.

Design Verilog HDL to implement Binary Adder-Sub tractor – Half and Full Adder, Half and Full
4
Sub tractor.

5 Design Verilog HDL to implement Decimal adder.

6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.

7 Design Verilog program to implement types of De-Multiplexer.

8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

LAB PROGRAMS
1. Given a 4-variable logic expression, simplify it using appropriate technique
and simulate the same using basic gates.

F(A,B,C,D) = ∑m(0,2,4,5,6,7,8,10,11,12,14,15)

A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1`
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
Simplified expression if F(A,B,C,D) = D’ + A’B + AC

KMAP :
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

F
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

2. Design a 4 bit full adder and subtractor and simulate the same using basic
gates
 Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

3. Design Verilog HDL to implement simple circuits using Structural,

Data flow and Behavioral model.
INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Structural :

module cktand(output Y, input A, B);

and(Y, A, B);
endmodule

Dataflow :

module andgate(output Y, input A, B);

assign Y = A & B;
endmodule

Behavioral :

module andgate(Y,A,B);
input A,B;
output Y;
reg Y;
always @ (A or B)
begin
if(A ==1 && B == 1)
Y = 1;
else
Y = 0;
end
endmodule
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and

Full Adder, Half and Full Subtractor.

Half Adder:

module half_adder(input a,b, output sum, cout );

assign sum = a ^ b ;
assign cout = a & b;
endmodule

INPUT OUTPUT
COU
A B SUM
T
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half subtractor:

module half_sub(input a,b, output br,dif);

assign dif = a ^ b;
assign br = ~a & b;
endmodule

INPUT OUTPUT
A B DIFF BC
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

Full adder:
module full_adder(input a,b,c,output sum,cout);
assign sum = (a ^ b ^ c );
assign cout = (a & b ) | (b & c) | (a & c);
endmodule

INPUT OUTPUT
C COU
A B SUM
T
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Full subtractor :

module full_sub(input a,b,c,output br,dif);

assign dif = (a ^ b ^ c );
assign br = (~a & b ) | (b & c) | (~a & c);
endmodule

INPUT OUTPUT
A B C DIFF BR
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

5. Design Verilog HDL to implement Decimal adder

module bcdadder(a,b,carry_in,sum,carry);
input [3:0]a,b;
input carry_in;
output[3:0]sum;
output carry;
reg[4:0]sum_temp;
reg[3:0]sum;
reg carry;
always @ (a,b,carry_in)
begin
sum_temp = a+b+carry_in;
if(sum_temp > 9)
begin
sum_temp = sum_temp + 6;
carry = 1;
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

6. Design Verilog program to implement Different types of multiplexer like

2:1, 4:1 and 8:1.

2:1 MUX :
module mux2to1(D0, D1, S, Y);
output Y;
input D0, D1, S;
assign Y=(D0 & ~S) | (D1 & S);
or
assign Y=(S)? D1:D0;
endmodule

INPUT OUTPUT
S Y
0 D0
1 D1

4:1 MUX :

module mux4to1(output Y, input D0, D1, D2, D3, S0, S1);

assign Y = (D0 & ~S0 & ~S1) | (D1 & ~S0 & S1) | (D2 & S0 & ~S1) |
(D3 & S0 & S1);
endmodule

INPUT OUTPUT
S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

8:1 MUX :

module mux8to1(output Y, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1,
S2);

assign Y = (D0 & ~S0 & ~S1 & ~S2) | (D1 & ~S0 & ~S1 & S2) | (D2 &
~S0 & S1 & ~S2) | (D3 & ~S0 & S1 & S2) | (D4 & S0 & ~S1 & ~S2) | (D5
& S0 & ~S1 & S2) | (D6 & S0 & S1 & ~S2) | (D7 & S0 & S1 & S2);

endmodule

INPUT OUTPUT
S0 S1 S2 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

7. Design Verilog program to implement types of De-Multiplexer

1:8 DEMUX :

module demux1to8(d,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input s,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = (d & ~s0 & ~s1 & ~s2),
d1=(d & ~s0 & ~s1 & s2),
d2=(d & ~s0 & s1 & ~s2),
d3=(d & ~s0 & s1 & s2),
d4=(d & s0 & ~s1 & ~s2),
d5=(d & s0 & ~s1 & s2),
d6=(d & s0 & s1 & ~s2),
d7=(d & s0 & s1 & s2);
endmodule

INPUT OUTPUT
s0 s1 s2 d0 d1 d2 d3 d4 d5 d6 d7
0 0 0 d 0 0 0 0 0 0 0
0 0 1 0 d 0 0 0 0 0 0
0 1 0 0 0 d 0 0 0 0 0
0 1 1 0 0 0 d 0 0 0 0
1 0 0 0 0 0 0 d 0 0 0
1 0 1 0 0 0 0 0 d 0 0
1 1 0 0 0 0 0 0 0 d 0
1 1 1 0 0 0 0 0 0 0 d
 Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

1:4 demux :

module demux1to4(d,s0,s1,d0,d1,d2,d3);
input d,s0,s1;
output d0,d1,d2,d3;
assign d0 = (d & ~s0 & ~s1),
d1 = (d & ~s0 & s1),
d2 = (d & s0 & ~s1),
d3 = (d & s0 &s1);
endmodule

INPUT OUTPUT
s0 s1 d0 d1 d2 d3
0 0 d 0 0 0
0 1 0 d 0 0
1 0 0 0 d 0
1 1 0 0 0 d

1:2 demux :

module demux1to2(d,s,d0,d1);
input d,s;
output d0,d1;
assign d0 = (d & ~s),
d1 = (d & s);
endmodule

INPUT OUTPUT
s d0 d1
0 d O
1 0 d
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

8. Design Verilog program for implementing various types of Flip-Flops such

as SR, JK and D

D Flip flop(POSITIVE EDGE TRIGRRED FLIP FLOP) :

module dff(D,CLK,Q);
input D, CLK;
output Q;
reg Q;
always @(posedge CLK)
begin
Q <= D;
end
endmodule

INPUT OUTPUT
COMMENTS
CLK D Q
↑ D D Q=D
NO
X D Q
CHANGE
Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

SR FLIPFLOP :

module SR_flipflop ( input clk, rst_n, input s,r,output reg q,output q_bar )
always@(posedge clk) begin
if(!rst_n) q <= 0;
else begin
case({s,r})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
endcase
end
end
assign q_bar = ~q;
endmodule

INPUT OUTPUT
COMMENTS
clk s r q
↑ 0 0 Q NO CHANGE
↑ 0 1 0 RESET
↑ 1 0 1 SET
↑ 1 1 x FORBIDDEN
 Digital Design & Computer Organization Dept. of ISE, AcIT, Bangalore

JK FLIP-FLOP (POSITIVE EDGE TRIGGERED FLIP-FLOP) :

module JK_flipflop (input clk, rst_n,input j,k,output reg q, output q_bar);

always@(posedge clk) begin
if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
endcase
end
end
assign q_bar = ~q;
endmodule

INPUT OUTPUT
COMMENTS
clk j k q
↑ 0 0 Q NO CNANGE
↑ 0 1 0 0
↑ 1 0 1 1
↑ 1 1 q’ TOGGLE