Ra4m2 Group Datasheet

Datasheet
RA4M2 Group R01DS0367EJ0130

Rev.1.30
Renesas Microcontrollers Jul 28, 2023
Leading-performance 100 MHz Arm Cortex-M33 core, up to 512 KB code flash memory with background operation, 8 KB
Data flash memory, and 128 KB SRAM with Parity/ECC. High-integration with USB 2.0 Full-Speed, SDHI, Quad SPI, and
advanced analog. Integrated Secure Crypto Engine with cryptography accelerators, key management support, tamper
detection and power analysis resistance in concert with Arm TrustZone for integrated secure element functionality.
Features
■ Arm® Cortex®-M33 Core ● Independent Watchdog Timer (IWDT)
● Armv8-M architecture with the main extension ■ Human Machine Interface (HMI)
● Maximum operating frequency: 100 MHz
● Arm Memory Protection Unit (Arm MPU) ● Capacitive Touch Sensing Unit (CTSU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions ■ Multiple Clock Sources
– Non-secure MPU (MPU_NS): 8 regions ● Main clock oscillator (MOSC) (8 to 24 MHz)
● SysTick timer ● Sub-clock oscillator (SOSC) (32.768 kHz)
– Embeds two Systick timers: Secure and Non-secure instance ● High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
– Driven by LOCO or system clock ● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● CoreSight™ ETM-M33 ● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● IWDT-dedicated on-chip oscillator (15 kHz)
■ Memory ● Clock trim function for HOCO/MOCO/LOCO
● PLL/PLL2
● Up to 512-KB code flash memory ● Clock out support
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 128-KB SRAM
■ General-Purpose I/O Ports
■ Connectivity ● 5-V tolerance, open drain, input pull-up, switchable driving ability
● Serial Communications Interface (SCI) × 6
– Asynchronous interfaces
■ Operating Voltage
– 8-bit clock synchronous interface ● VCC: 2.7 to 3.6 V
– Smart card interface
– Simple IIC ■ Operating Temperature and Packages
– Simple SPI ● Ta = -40℃ to +105℃
– Manchester coding (SCI3, SCI4) – 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
● I2C bus interface (IIC) × 2 – 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
● Serial Peripheral Interface (SPI) – 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)
● Quad Serial Peripheral Interface (QSPI) – 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
● USB 2.0 Full-Speed Module (USBFS)
● Control Area Network module (CAN)
● SD/MMC Host Interface (SDHI)
● Serial Sound Interface Enhanced (SSIE)
■ Analog
● 12-bit A/D Converter (ADC12)
● 12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 4
● Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption

● Secure Crypto Engine 9
– Symmetric algorithms: AES
– Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
● Arm® TrustZone®
– Up to three regions for the code flash
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecyle management
● Pin function
– Up to three tamper pins
– Secure pin multiplexing
■ System and Power Management

● Low power modes
● Battery backup function (VBATT)
● Realtime Clock (RTC) with calendar and VBATT support
● Event Link Controller (ELC)
● Data Transfer Controller (DTC)
● DMA Controller (DMAC) × 8
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings
● Watchdog Timer (WDT)
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RA4M2 Datasheet 1. Overview
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 100 MHz with the following
features:
● Up to 512 KB code flash memory
● 128 KB SRAM
● Quad Serial Peripheral Interface (QSPI)
● USBFS, SD/MMC Host Interface
● Capacitive Touch Sensing Unit (CTSU)
● Analog peripherals
● Security and safety features
1.1 Function Outline

Table 1.1 Arm core
Feature Functional description
Arm Cortex-M33 core ● Maximum operating frequency: up to 100 MHz

● Arm Cortex-M33 core:
– Armv8-M architecture with security extension
– Revision: r0p4-00rel0
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
● CoreSight™ ETM-M33
Table 1.2 Memory

Code flash memory Maximum 512 KB of code flash memory.

Data flash memory 8 KB of data flash memory.
Option-setting memory The option-setting memory determines the state of the MCU after a reset.
SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3 System (1 of 2)

Operating modes Two operating modes:

● Single-chip mode
● SCI/USB boot mode
Resets The MCU provides 13 resets.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
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Table 1.3 System (2 of 2)

Clocks ● Main clock oscillator (MOSC)

● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator
● PLL/PLL2
● Clock out support
Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
Measurement Circuit (CAC) measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range. When measurement
is complete or the number of pulses within the time generated by the measurement reference
clock is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)
modules. The ICU also controls non-maskable interrupts.
Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered area
includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.
Register write protection The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
Memory Protection Unit (MPU) The MCU has one Memory Protection Unit (MPU).
Table 1.4 Event link

Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5 Direct memory access

Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
DMA Controller (DMAC) The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data
without intervention from the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.
Table 1.6 External bus interface

External bus ● QSPI area (EQBIU): Connected to the QSPI (external device interface)
Table 1.7 Timers (1 of 2)

General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 4 channels. PWM waveforms can be generated by controlling the up-counter, down-
counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG) The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
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Table 1.7 Timers (2 of 2)

Low Power Asynchronous General The Low Power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
Purpose Timer (AGT) for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
Realtime Clock (RTC) For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and
retains the information as a serial value. Binary count mode can be used for calendars other
than the Gregorian (Western) calendar.
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.8 Communication interfaces (1 of 2)

Serial Communications Interface (SCI) The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous
serial interfaces:
● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
● 8-bit clock synchronous interface
● Simple IIC (master-only)
● Simple SPI
● Smart card interface
● Manchester interface
● Extended Serial interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0, 3, 4, 9) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.
I2C bus interface (IIC) The I2C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset
of the NXP I2C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) has 1 channel. The SPI provides high-speed full-duplex
synchronous serial communications with multiple processors and peripheral devices.
Control Area Network (CAN) The Controller Area Network (CAN) module uses a message-based protocol to receive and
transmit data between multiple slaves and masters in electromagnetically noisy applications. The
module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32
mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN
module requires an additional external CAN transceiver.
USB 2.0 Full-Speed module (USBFS) The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has
buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned
any endpoint number based on the peripheral devices used for communication or based on your
system.
Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM
(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has
an SPI-compatible interface.
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Table 1.8 Communication interfaces (2 of 2)

Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting I2S/Monaural/TDM audio data over a serial bus. The SSIE
supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master
receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage
FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data
reception and transmission.
SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with the
SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit,
and 4-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device access.
This interface also provides backward compatibility and supports high-speed SDR transfer
modes.
Table 1.9 Analog

12-bit A/D Converter (ADC12) A 12-bit successive approximation A/D converter (ADC12) is provided. Analog input channels
are selectable up to 22. The temperature sensor output and an internal reference voltage are
selectable for conversion.
12-bit D/A Converter (DAC12) A 12-bit D/A converter (DAC12) is provided.
Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.
Table 1.10 Human machine interfaces

Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch
sensor. Changes in the electrostatic capacitance are determined by software that enables the
CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the
touch sensor is usually enclosed with an electrical conductor so that a finger does not come into
direct contact with the electrode.
Table 1.11 Data processing

Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit
calculator order of CRC calculation results can be switched for LSB-first or MSB-first communication.
Additionally, various CRC-generation polynomials are available.
Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.
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Table 1.12 I/O ports

Programmable I/O ports ● I/O ports for the 100-pin LQFP

– I/O pins: 77
– Input pins: 1
– Pull-up resistors: 78
– N-ch open-drain outputs: 77
– 5-V tolerance: 14
● I/O ports for the 64-pin LQFP
– I/O pins: 43
– Input pins: 1
● I/O ports for the 48-pin LQFP, 48-pin QFN
– I/O pins: 29
– Input pins: 1
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1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Memory Bus Arm Cortex-M33 System
512 KB code flash MPU DSP FPU POR/LVD Clocks
MOSC/SOSC
8 KB data flash
IDAU
Reset
(H/M/L) OCO
128 KB SRAM
MPU
1 KB Standby Mode control PLL/PLL2
SRAM
NVIC
Power control CAC
DMA System timer

ICU Battery backup
DTC
Test and DBG interface
Register write
DMAC × 8 protection
Timers Communication interfaces Human machine interfaces
GPT32 x 4 SCI × 6 QSPI CTSU

GPT16 x 4
IIC × 2 SDHI
AGT × 6
SPI CAN
RTC
SSIE USBFS
WDT/IWDT
Event link Data processing Analog

ELC CRC ADC12 TSN
Security DOC DAC12 × 2
SCE9
Note: Not available on all parts.
Figure 1.1 Block diagram
1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.13 shows a
list of products.
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R7FA4M2AD3C FP #AA 0
Production identification code
Terminal material (Pb-free)
A: Sn (Tin) only
C: Others
Packing
A: Tray
B: Tray (Full carton)
H: Tape and reel
Package type
FL: LQFP 48 pins
FM: LQFP 64 pins
FP: LQFP 100 pins
NE: QFN 48 pins
Quality Grade
Operating temperature
3: -40°C to 105°C
Code flash memory size

B: 256 KB
C: 384 KB
D: 512 KB
Feature set
Group name
Series name
RA family
Flash memory
Renesas microcontroller
Note: Check the order screen for each product on the Renesas website for valid symbols after the #.
Figure 1.2 Part numbering scheme
Table 1.13 Product list (1 of 2)

Data Operating
Product part number Package code Code flash flash SRAM temperature
R7FA4M2AD3CFP PLQP0100KB-B 512 KB 8 KB 128 KB -40 to +105°C

R7FA4M2AD3CFM PLQP0064KB-C
R7FA4M2AD3CFL PLQP0048KB-B
R7FA4M2AD3CNE PWQN0048KC-A
R7FA4M2AC3CFP PLQP0100KB-B 384 KB 8 KB 128 KB -40 to +105°C
R7FA4M2AC3CFM PLQP0064KB-C
R7FA4M2AC3CFL PLQP0048KB-B
R7FA4M2AC3CNE PWQN0048KC-A
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Table 1.13 Product list (2 of 2)

Data Operating
Product part number Package code Code flash flash SRAM temperature
R7FA4M2AB3CFP PLQP0100KB-B 256 KB 8 KB 128 KB -40 to +105°C

R7FA4M2AB3CFM PLQP0064KB-C
R7FA4M2AB3CFL PLQP0048KB-B
R7FA4M2AB3CNE PWQN0048KC-A
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1.4 Function Comparison

Table 1.14 Function Comparison (1 of 2)
R7FA4M2AD3CFP R7FA4M2AD3CFM R7FA4M2AD3CFL R7FA4M2AD3CNE
R7FA4M2AC3CFP R7FA4M2AC3CFM R7FA4M2AC3CFL R7FA4M2AC3CNE
Parts number R7FA4M2AB3CFP R7FA4M2AB3CFM R7FA4M2AB3CFL R7FA4M2AB3CNE
Pin count 100 64 48 48

Package LQFP QFN
Code flash memory 512KB
384KB
256KB
Data flash memory 8 KB
SRAM 128 KB
Parity 64 KB
ECC 64 KB
Standby SRAM 1 KB
DMA DTC Yes
DMAC 8
System CPU clock 100 MHz (max.)
CPU clock sources MOSC, SOSC, HOCO, MOCO, LOCO, PLL
CAC Yes
WDT/IWDT Yes
Backup register 128 B
Communication SCI 6
IIC 2 1
SPI 1
CAN 1
USBFS Yes
QSPI Yes
SSIE Yes No
SDHI/MMC Yes No
Timers GPT32*1 4
GPT16*1 4
AGT*1 6
RTC Yes
Analog ADC12 Unit 0: 13 Unit 0: 9 Unit 0: 7
DAC12 2
TSN Yes
HMI CTSU 12 7 4
Data processing CRC Yes
DOC Yes
Event control ELC Yes
Security SCE9, TrustZone, and Lifecycle management
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Table 1.14 Function Comparison (2 of 2)

R7FA4M2AD3CFP R7FA4M2AD3CFM R7FA4M2AD3CFL R7FA4M2AD3CNE
R7FA4M2AC3CFP R7FA4M2AC3CFM R7FA4M2AC3CFL R7FA4M2AC3CNE
Parts number R7FA4M2AB3CFP R7FA4M2AB3CFM R7FA4M2AB3CFL R7FA4M2AB3CNE
I/O ports I/O pins 77 43 29

Input pins 1 1 1
Pull-up resistors 78 44 30
N-ch open-drain 77 43 29
outputs
5-V tolerance 14 9 4
Note 1. Available pins depend on the Pin count, about details see section 1.7. Pin Lists.
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1.5 Pin Functions

Table 1.15 Pin functions (1 of 4)
Function Signal I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. The capacitor should be
placed close to the pin.
VCL I/O Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VBATT Input Battery Backup power pin
VSS Input Ground pin. Connect it to the system power supply (0 V).
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT Output
CLKOUT Output Clock output pin
Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC CACREF Input Measurement reference clock input pin
On-chip emulator TMS Input On-chip emulator or boundary scan pins
TDI Input
TCK Input
TDO Output
TCLK Output Output clock for synchronization with the trace data
TDATA0 to TDATA3 Output Trace data output
SWO Output Serial wire trace output pin
SWDIO I/O Serial wire debug data input/output pin
SWCLK Input Serial wire clock pin
Interrupt NMI Input Non-maskable interrupt request pin
IRQn Input Maskable interrupt request pins
IRQn-DS Input Maskable interrupt request pins that can also be used in Deep
Software Standby mode
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GPT GTETRGA, GTETRGB, Input External trigger input pins

GTETRGC, GTETRGD
GTIOCnA, GTIOCnB I/O Input capture, output compare, or PWM output pins
GTIU Input Hall sensor input pin U
GTIV Input Hall sensor input pin V
GTIW Input Hall sensor input pin W
GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase)
GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase)
AGT AGTEEn Input External event input enable signals
AGTIOn I/O External event input and pulse output pins
AGTOn Output Pulse output pins
AGTOAn Output Output compare match A output pins
AGTOBn Output Output compare match B output pins
RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock
RTCICn Input Time capture event input pins
SCI SCKn I/O Input/output pins for the clock (clock synchronous mode)
RXDn Input Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn Output Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn I/O Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), active-
low.
CTSn Input Input for the start of transmission.
SCLn I/O Input/output pins for the IIC clock (simple IIC mode)
SDAn I/O Input/output pins for the IIC data (simple IIC mode)
SCKn I/O Input/output pins for the clock (simple SPI mode)
MISOn I/O Input/output pins for slave transmission of data (simple SPI mode)
MOSIn I/O Input/output pins for master transmission of data (simple SPI mode)
RXDXn Input Input pins for received data (Extended Serial Mode)
TXDXn Output Output pins for transmitted data (Extended Serial Mode)
SIOXn I/O Input/output pins for received or transmitted data (Extended Serial
Mode)
SSn Input Chip-select input pins (simple SPI mode), active-low
IIC SCLn I/O Input/output pins for the clock
SDAn I/O Input/output pins for data
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SPI RSPCKA I/O Clock input/output pin

MOSIA I/O Input or output pins for data output from the master
MISOA I/O Input or output pins for data output from the slave
SSLA0 I/O Input or output pin for slave selection
SSLA1 to SSLA3 Output Output pins for slave selection
CAN CRXn Input Receive data
CTXn Output Transmit data
USBFS VCC_USB Input Power supply pin
VSS_USB Input Ground pin
USB_DP I/O D+ pin of the USB on-chip transceiver. Connect this pin to the D+
pin of the USB bus.
USB_DM I/O D- pin of the USB on-chip transceiver. Connect this pin to the D- pin
of the USB bus.
USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the
USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
USB_EXICEN Output Low-power control signal for external power supply (OTG) chip
USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA, Input Connect the external overcurrent detection signals to these pins.
USB_OVRCURB Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_OVRCURA-DS Input Overcurrent pins for USBFS that can also be used in Deep Software
Standby mode.
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_ID Input Connect the MicroAB connector ID input signal to this pin during
operation in OTG mode
QSPI QSPCLK Output QSPI clock output pin
QSSL Output QSPI slave output pin
QIO0 to QIO3 I/O Data0 to Data3
SSIE SSIBCK0 I/O SSIE serial bit clock pins
SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins
SSITXD0 Output Serial data output pin
SSIRXD0 Input Serial data input pin
AUDIO_CLK Input External clock pin for audio (input oversampling clock)
SDHI/MMC SD0CLK Output SD/MMC clock output pins
SD0CMD I/O Command output pin and response input signal pins
SD0DAT0 to SD0DAT3 I/O SD/MMC data bus pins
SD0CD Input SD/MMC card detection pins
SD0WP Input SD/MMC write-protect signals
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Analog power supply AVCC0 Input Analog voltage supply pin. This is used as the analog power supply
for the respective modules. Supply this pin with the same voltage as
the VCC pin.
AVSS0 Input Analog ground pin. This is used as the analog ground for the
respective modules. Supply this pin with the same voltage as the
VSS pin.
VREFH Input Analog reference voltage supply pin for the D/A Converter. Connect
this pin to AVCC0 when not using the D/A Converter.
VREFL Input Analog reference ground pin for the D/A Converter. Connect this pin
to AVSS0 when not using the D/A Converter.
VREFH0 Input Analog reference voltage supply pin for the ADC12. Connect this pin
to AVCC0 when not using the ADC12.
VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12.
ADC12 ANmn Input Input pins for the analog signals to be processed by the A/D
converter.
(m: ADC unit number, n: pin number)
ADTRGm Input Input pins for the external trigger signals that start the A/D
conversion, active-low.
DAC12 DAn Output Output pins for the analog signals processed by the D/A converter.
CTSU TSn Input Capacitive touch detection pins (touch pins)
TSCAP I/O Secondary power supply pin for the touch driver
I/O ports Pmn I/O General-purpose input/output pins
(m: port number, n: pin number)
P200 Input General-purpose input pin
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Jul 28, 2023
1.6 Pin Assignments

The following figures show the pin assignments from the top view.
P108/TMS/SWDIO
P109/TDO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602
P603
P610
P609
P608
P115
P114
P113
P112
P111
VCC
VSS
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75
P500 76 50 P300/TCK/SWCLK
P501 77 49 P301
P502 78 48 P302
P503 79 47 P303
P504 80 46 VCC
P505 81 45 VSS
VCC 82 44 P304
VSS 83 43 P305
P015 84 42 P306
P014 85 41 P307
P013 86 40 P200
VREFH 87 39 P201/MD
AVCC0 88 38 RES
AVSS0/VREFL 89 37 P208
VREFL0 90 36 P209
VREFH0 91 35 P210
P008 92 34 P211
P007 93 33 P214
P006 94 32 P205
P005 95 31 P206
P004 96 30 P207
P003 97 29 VCC_USB
P002 98 28 USB_DP
P001 99 27 USB_DM
P000 100 26 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
VCL
VSS
VCC
P400
P401
P402
P403
P404
P405
P406
P708
P415
P414
P413
P412
P410
P409
P408
P407
XCIN
P411
XCOUT
VBATT
P213/XTAL
P212/EXTAL
Figure 1.3 Pin assignment for LQFP 100-pin

P108/TMS/SWDIO
P109/TDO/SWO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107
P113
P112
P111
VCC
VSS
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
VCC 50 31 P301
VSS 51 30 P302
P015 52 29 P303
P014 53 28 P304
P013 54 27 P200
VREFH 55 26 P201/MD
AVCC0 56 25 RES
VREFL0 58 23 P205
VREFH0 59 22 P206
P004 60 21 P207
P003 61 20 VCC_USB
P002 62 19 USB_DP
P001 63 18 USB_DM
P000 64 17 VSS_USB
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
VCL
VSS
VCC
P400
P401
P402
P410
P409
P408
P407
XCIN
P411
XCOUT
VBATT
P213/XTAL
P212/EXTAL
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Jul 28, 2023
P108/TMS/SWDIO
P109/TDO/SWO
P110/TDI
P100
P101
P102
P103
P104
P112
P111
VCC
VSS
35
34
33
32
31
30
29
28
27
26
25
36
P015 38 23 P301
P014 39 22 P302
P013 40 21 P200
VREFH 41 20 P201/MD
AVCC0 42 19 RES
VREFL0 44 17 P207
VREFH0 45 16 VCC_USB
P002 46 15 USB_DP
P001 47 14 USB_DM
P000 48 13 VSS_USB
10
11
12
1
2
3
4
5
6
7
8
9
VCL
VSS
VCC
P402
P409
P408
P407
XCIN
XCOUT
VBATT
P213/XTAL
P212/EXTAL

P108/TMS/SWDIO
P109/TDO/SWO
P110/TDI
P100
P101
P102
P103
P104
P112
P111
VCC
VSS
36
35
34
33
32
31
30
29
28
27
26
25
P500 37 Exposed die pad 24 P300/TCK/SWCLK

P015 38 23 P301
P014 39 22 P302
P013 40 21 P200
VREFH 41 20 P201/MD
AVCC0 42 19 RES
VREFL0 44 17 P207
VREFH0 45 16 VCC_USB
P002 46 15 USB_DP
P001 47 14 USB_DM
P000 48 13 VSS_USB
10
12
11
1
2
3
4
5
6
7
8
9
VCL
VSS
VCC
P402
P409
P408
P407
XCIN
XCOUT
VBATT
P213/XTAL
P212/EXTAL
Note: Exposed die pad is recommended to connect to VSS.
Figure 1.6 Pin assignment for QFN 48-pin
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Jul 28, 2023
1.7 Pin Lists

Table 1.16 Pin list (1 of 3)
LQFP100
LQFP64
LQFP48,
Power, System,
QFN48
Clock, Debug, I/O

CAC ports Ex. Interrupt SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC GPT/AGT/RTC ADC12/DAC12 CTSU
1 1 — — P400 IRQ0 SCK4/SCL0_A/AUDIO_CLK GTIOC6A/AGTIO1 — —
2 2 — — P401 IRQ5-DS CTS4_RTS4/SS4/SDA0_A/CTX0 GTETRGA/GTIOC6B — —
3 3 1 CACREF P402 IRQ4-DS CTS4/CRX0/AUDIO_CLK AGTIO0/AGTIO1/AGTIO2/AGTIO3/ — —

RTCIC0
4 — — — P403 IRQ14-DS SSIBCK0_A GTIOC3A/AGTIO0/AGTIO1/AGTIO2/ — —

AGTIO3/RTCIC1
5 — — — P404 IRQ15-DS SSILRCK0/SSIFS0_A GTIOC3B/AGTIO0/AGTIO1/AGTIO2/ — —

AGTIO3/RTCIC2
6 — — — P405 — SSITXD0_A GTIOC1A — —
7 — — — P406 — SSIRXD0_A GTIOC1B/AGTO5 — —
8 4 2 VBATT — — — — — —
9 5 3 VCL — — — — — —
10 6 4 XCIN — — — — — —
11 7 5 XCOUT — — — — — —
12 8 6 VSS — — — — — —
13 9 7 XTAL P213 IRQ2 TXD1/MOSI1/SDA1/TXDX1/SIOX1 GTETRGC/GTIOC0A/AGTEE2 — —
14 10 8 EXTAL P212 IRQ3 RXD1/MISO1/SCL1/RXDX1 GTETRGD/GTIOC0B/AGTEE1 — —
15 11 9 VCC — — — — — —
16 — — CACREF P708 IRQ11 RXD1/MISO1/SCL1/RXDX1/AUDIO_CLK — — TS12
17 — — — P415 IRQ8 USB_VBUSEN/SD0CD GTIOC0A/AGTIO4 — TS11
18 — — — P414 IRQ9 CTS0/SD0WP GTIOC0B/AGTIO5 — TS10
19 — — — P413 — CTS0_RTS0/SS0/SD0CLK_A GTOUUP/AGTEE3 — TS09
20 — — — P412 — SCK0/CTS3/SD0CMD_A GTOULO/AGTEE1 — TS08
21 12 — — P411 IRQ4 TXD0/MOSI0/SDA0/CTS3_RTS3/SS3/SD0DAT0_A GTOVUP/AGTOA1 — TS07
22 13 — — P410 IRQ5 RXD0/MISO0/SCL0/SCK3/SD0DAT1_A GTOVLO/AGTOB1 — TS06
23 14 10 — P409 IRQ6 TXD3/MOSI3/SDA3/USB_EXICEN GTOWUP/AGTOA2 — TS05
24 15 11 — P408 IRQ7 CTS4/RXD3/MISO3/SCL3/SCL0_B/USB_ID GTOWLO/GTIOC6B/AGTOB2 — TS04
25 16 12 — P407 — CTS4_RTS4/SS4/SDA0_B/USB_VBUS GTIOC6A/AGTIO0/RTCOUT ADTRG0 TS03
26 17 13 VSS_USB — — — — — —
27 18 14 USB_DM — — — — — —
28 19 15 USB_DP — — — — — —
29 20 16 VCC_USB — — — — — —
30 21 17 — P207 — TXD4/MOSI4/SDA4/QSSL — — TSCAP
31 22 18 — P206 IRQ0-DS RXD4/MISO4/SCL4/CTS9/SDA1_B/USB_VBUSEN/ GTIU — TS02

SD0DAT2_A
32 23 — CLKOUT P205 IRQ1-DS TXD4/MOSI4/SDA4/CTS9_RTS9/SS9/SCL1_B/ GTIV/GTIOC4A/AGTO1 — TS01

USB_OVRCURA-DS/SD0DAT3_A
33 — — TCLK P214 — QSPCLK/SD0CLK_B GTIU/AGTO5 — —
34 — — TDATA0 P211 — QIO0/SD0CMD_B GTIV/AGTOA5 — —
35 — — TDATA1 P210 — QIO1/SD0CD GTIW/AGTOB5 — —
36 — — TDATA2 P209 — QIO2/SD0WP GTOVUP/AGTEE5 — —
37 24 — TDATA3 P208 — QIO3/SD0DAT0_B GTOVLO — —
38 25 19 RES — — — — — —
39 26 20 MD P201 — — — — —
40 27 21 — P200 NMI — — — —
41 — — — P307 — QIO0 GTOUUP/AGTEE4 — —
42 — — — P306 — QSSL GTOULO/AGTOA2 — —
43 — — — P305 IRQ8 QSPCLK GTOWUP/AGTOB2 — —
44 28 — — P304 IRQ9 — GTOWLO/GTIOC7A/AGTEE2 — —
45 — — VSS — — — — — —
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Jul 28, 2023

LQFP100
LQFP64
LQFP48,
Power, System,
QFN48
Clock, Debug, I/O

46 — — VCC — — — — — —
47 29 — — P303 — CTS9 GTIOC7B — —
48 30 22 — P302 IRQ5 TXD2/MOSI2/SDA2/TXDX2/SIOX2/SSLA3 GTOUUP/GTIOC4A — —
49 31 23 — P301 IRQ6 RXD2/MISO2/SCL2/RXDX2/CTS9_RTS9/SS9/SSLA2 GTOULO/GTIOC4B/AGTIO0 — —
50 32 24 TCK/SWCLK P300 — SSLA1 GTOUUP/GTIOC0A — —
51 33 25 TMS/SWDIO P108 — CTS9_RTS9/SS9/SSLA0 GTOULO/GTIOC0B/AGTOA3 — —
52 34 26 TDO/SWO/CLKOUT P109 — TXD9/MOSI9/SDA9/MOSIA GTOVUP/GTIOC1A/AGTOB3 — —
53 35 27 TDI P110 IRQ3 CTS2_RTS2/SS2/RXD9/MISO9/SCL9/MISOA GTOVLO/GTIOC1B/AGTEE3 — —
54 36 28 — P111 IRQ4 SCK2/SCK9/RSPCKA GTIOC3A/AGTOA5 — —
55 37 29 — P112 — TXD2/MOSI2/SDA2/TXDX2/SIOX2/SCK1/SSLA0/QSSL/ GTIOC3B/AGTOB5 — —

SSIBCK0_B
56 38 — — P113 — RXD2/MISO2/SCL2/RXDX2/SSILRCK0/SSIFS0_B GTIOC2A/AGTEE5 — —
57 — — — P114 — CTS9/SSIRXD0_B GTIOC2B/AGTIO5 — —
58 — — — P115 — SSITXD0_B GTIOC4A — —
59 — — — P608 — — GTIOC4B — —
60 — — — P609 — — GTIOC5A/AGTO5 — —
61 — — — P610 — — GTIOC5B/AGTO4 — —
62 39 30 VCC — — — — — —
63 40 31 VSS — — — — — —
64 — — — P603 — CTS9_RTS9/SS9 GTIOC7A/AGTIO4 — —
65 — — — P602 — TXD9/MOSI9/SDA9 GTIOC7B/AGTO3 — —
66 — — — P601 — RXD9/MISO9/SCL9 GTIOC6A/AGTEE3 — —
67 — — CACREF/CLKOUT P600 — SCK9 GTIOC6B/AGTIO3 — —
68 41 — — P107 — — AGTOA0 — —
69 42 — — P106 — — AGTOB0 — —
70 43 — — P105 IRQ0 — GTETRGA/GTIOC1A/AGTO2 — —
71 44 32 — P104 IRQ1 QIO2 GTETRGB/GTIOC1B/AGTEE2 — —
72 45 33 — P103 — CTS0_RTS0/SS0/CTX0/QIO3 GTOWUP/GTIOC2A/AGTIO2 — —
73 46 34 — P102 — SCK0/CRX0/QIO0 GTOWLO/GTIOC2B/AGTO0 ADTRG0 —
74 47 35 — P101 IRQ1 TXD0/MOSI0/SDA0/CTS1_RTS1/SS1/QIO1 GTETRGB/GTIOC5A/AGTEE0 — —
75 48 36 — P100 IRQ2 RXD0/MISO0/SCL0/SCK1/QSPCLK GTETRGA/GTIOC5B/AGTIO0 — —
76 49 37 CACREF P500 — USB_VBUSEN/QSPCLK GTIU/AGTOA0 AN016 —
77 — — — P501 IRQ11 USB_OVRCURA/QSSL GTIV/AGTOB0 — —
78 — — — P502 IRQ12 USB_OVRCURB/QIO0 GTIW/AGTOA2 — —
79 — — — P503 — USB_EXICEN/QIO1 GTETRGC/AGTOB2 — —
80 — — — P504 — USB_ID/QIO2 GTETRGD/AGTOA3 — —
81 — — — P505 IRQ14 QIO3 AGTOB3 — —
82 50 — VCC — — — — — —
83 51 — VSS — — — — — —
84 52 38 — P015 IRQ13 — — AN013/DA1 —
85 53 39 — P014 — — — AN012/DA0 —
86 54 40 — P013 — — — AN011 —
87 55 41 VREFH — — — — — —
88 56 42 AVCC0 — — — — — —
89 57 43 AVSS0/VREFL — — — — — —
90 58 44 VREFL0 — — — — — —
91 59 45 VREFH0 — — — — — —
92 — — — P008 IRQ12-DS — — AN008 —
93 — — — P007 — — — AN007 —
94 — — — P006 IRQ11-DS — — AN006 —
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Jul 28, 2023

LQFP100
LQFP64
LQFP48,
Power, System,
QFN48
Clock, Debug, I/O

95 — — — P005 IRQ10-DS — — AN005 —
96 60 — — P004 IRQ9-DS — — AN004 —
97 61 — — P003 — — — AN003 —
98 62 46 — P002 IRQ8-DS — — AN002 —
99 63 47 — P001 IRQ7-DS — — AN001 —
100 64 48 — P000 IRQ6-DS — — AN000 —
Note: Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.
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Jul 28, 2023
RA4M2 Datasheet 2. Electrical Characteristics
2. Electrical Characteristics
Supported peripheral functions and pins differ from one product name to another.
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
● VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V
● 2.7 ≤ VREFH0/VREFH ≤ AVCC0
● VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V
● Ta = Topr
Figure 2.1 shows the timing conditions.
For example, P100
VOH = VCC × 0.7, VOL = VCC × 0.3

VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1 Input or output timing measurement conditions

The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.
2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings
Parameter Symbol Value Unit
Power supply voltage VCC, VCC_USB*2 –0.3 to +4.0 V
VBATT power supply voltage VBATT –0.3 to +4.0 V
Input voltage (except for 5 V-tolerant ports*1) Vin –0.3 to VCC + 0.3 V
Input voltage (5 V-tolerant ports*1) Vin –0.3 to + VCC + 4.0 (max. 5.8) V
Reference power supply voltage VREFH/VREFH0 –0.3 to VCC + 0.3 V

Analog power supply voltage AVCC0*2 –0.3 to +4.0 V
Analog input voltage VAN –0.3 to AVCC0 + 0.3 V
Operating temperature*3 *4 Topr –40 to +105 °C
Storage temperature Tstg –55 to +125 °C
Note 1. Ports P205, P206, P400, P401, P407 to P415, and P708 are 5 V tolerant.
Note 2. Connect AVCC0 and VCC_USB to VCC.
Note 3. See section 2.2.1. Tj/Ta Definition.
Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
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Jul 28, 2023
Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
Table 2.2 Recommended operating conditions

Parameter Symbol Value Min Typ Max Unit
Power supply voltages VCC When USB is not used 2.7 — 3.6 V
When USB is used 3.0 — 3.6 V
VSS — 0 — V
USB power supply voltages VCC_USB — VCC — V
VSS_USB — 0 — V
VBATT power supply voltage VBATT 1.65*2 — 3.6 V
Analog power supply voltages AVCC0*1 — VCC — V
AVSS0 — 0 — V
Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0,
AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/
VREFL0 pins to VSS, respectively.
Note 2. Low CL crystal cannot be used below VBATT = 1.8V.
2.2 DC Characteristics
2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter Symbol Typ Max Unit Test conditions
Permissible junction temperature Tj — 125 °C High-speed mode

Low-speed mode
Subosc-speed mode
Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL +
ICCmax × VCC.
2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL (1 of 2)
Parameter Symbol Min Typ Max Unit
Input voltage Peripheral EXTAL (external clock input), SPI (except RSPCK) VIH VCC × — — V
(except for function pin 0.8
Schmitt trigger
input pins) VIL — — VCC × 0.2
IIC (SMBus) VIH 2.1 — VCC + 3.6

(max 5.8)
VIL — — 0.8
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Jul 28, 2023
Table 2.4 I/O VIH, VIL (2 of 2)

Schmitt trigger Peripheral IIC (except for SMBus) VIH VCC × — VCC + 3.6 V
input voltage function pin 0.7 (max 5.8)
VIL — — VCC × 0.3
ΔVT VCC × — —
0.05
5 V-tolerant ports*1 *5 VIH VCC × — VCC + 3.6

0.8 (max 5.8)
VIL — — VCC × 0.2
ΔVT VCC × — —
0.05
RTCIC0, When using the When VBATT VIH VBATT × — VBATT + 0.3
RTCIC1, Battery Backup power supply is 0.8
RTCIC2 Function selected
VIL — — VBATT × 0.2
ΔVT VBATT × — —
0.05
When VCC VIH VCC × — Higher
power supply is 0.8 voltage
selected either
VCC + 0.3 V
or
VBATT + 0.3
V
VIL — — VCC × 0.2
ΔVT VCC × — —
0.05
When not using the Battery Backup VIH VCC × — VCC + 0.3
Function 0.8
VIL — — VCC × 0.2
ΔVT VCC × — —
0.05
Other input pins*2 VIH VCC × — —

0.8
VIL — — VCC × 0.2
ΔVT VCC × — —
0.05
Ports 5 V-tolerant ports*3 *5 VIH VCC × — VCC + 3.6 V
0.8 (max 5.8)
VIL — — VCC × 0.2
Other input pins*4 VIH VCC × — —

0.8
VIL — — VCC × 0.2
Note 1. RES and peripheral function pins associated with Ports P205, P206, P400, P401, P407 to P415, and P708（total 15 pins).
Note 2. All input pins except for the peripheral function pins already described in the table.
Note 3. Ports P205, P206, P400, P401, P407 to P415, and P708（total 14 pins).
Note 4. All input pins except for the ports already described in the table.
Note 5. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.
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2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL
Permissible output current (average value per Ports P000 to P008, P013 to P015, — IOH — — –2.0 mA
pin) P201
IOL — — 2.0 mA
Ports P205, P206, P407 to P415, P708 Low drive*1 IOH — — –2.0 mA
(total 12 pins)
IOL — — 2.0 mA
Middle drive*2 IOH — — –4.0 mA
IOL — — 4.0 mA
High drive*3 IOH — — –20 mA
IOL — — 20 mA
Other output pins*4 Low drive*1 IOH — — –2.0 mA
IOL — — 2.0 mA
IOL — — 4.0 mA
IOL — — 16 mA
Permissible output current (max value per pin) Ports P000 to P008, P013 to P015, — IOH — — –4.0 mA
P201
IOL — — 4.0 mA
Ports P205, P206, P407 to P415, P708 Low drive*1 IOH — — –4.0 mA
(total 12 pins)
IOL — — 4.0 mA
IOL — — 8.0 mA
IOL — — 40 mA
Other output pins*4 Low drive*1 IOH — — –4.0 mA
IOL — — 4.0 mA
IOL — — 8.0 mA
IOL — — 32 mA
Permissible output current (maxvalue of total Maximum of all output pins ΣIOH (max) — — –80 mA
of all pins)
ΣIOL (max) — — 80 mA
Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
Note 4. Except for P200, which is an input port.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table.
The average output current indicates the average value of current measured during 100 µs.
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2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL, and other characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Output voltage IIC VOL — — 0.4 V IOL = 3.0 mA
VOL — — 0.6 IOL = 6.0 mA
IIC*1 VOL — — 0.4 IOL = 15.0 mA (ICFER.FMPE = 1)
VOL — 0.4 — IOL = 20.0 mA (ICFER.FMPE = 1)
Ports P205, P206, P407 to VOH VCC – 1.0 — — IOH = –20 mA

P415, P708 (total 12 pins)*2 VCC = 3.3 V
VOL — — 1.0 IOL = 20 mA
VCC = 3.3 V
Other output pins VOH VCC – 0.5 — — IOH = –1.0 mA
VOL — — 0.5 IOL = 1.0 mA
Input leakage current RES |Iin| — — 5.0 µA Vin = 0 V

Vin = 5.5 V
Port P200 — — 1.0 Vin = 0 V

Vin = VCC
Three-state leakage current 5 V-tolerant ports |ITSI| — — 5.0 µA Vin = 0 V

(off state) Vin = 5.5 V
Other ports (except for port — — 1.0 Vin = 0 V

P200) Vin = VCC
Input pull-up MOS current Ports P0 to P7 Ip –300 — –10 µA VCC = 2.7 to 3.6 V
Vin = 0 V
Input capacitance Ports P014, P015 Cin — — 16 pF Vbias = 0 V

Vamp = 20 mV
USB_DP and USB_DM — — 12 f = 1 MHz
Ports P400, P401 — — 10 Ta = 25°C
Other input pins — — 8

Note 1. SCL0_A, SDA0_A (total 2 pins).
Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.
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2.2.5 Operating and Standby Current

Table 2.7 Operating and standby current (1 of 2)
Supply High-speed Maximum*2 *13 ICC*3 — — 65 mA ICLK = 100

current*1 mode MHz
CoreMark®*5 *6 *12 *14 — 8.1 — PCLKA = 100
MHz
Normal mode All peripheral clocks enabled, — 15.4 —
PCLKB = 50
while (1) code executing from
MHz
flash*4 *12 PCLKC = 50
All peripheral clocks disabled, — 6.1 — MHz
while (1) code executing from PCLKD = 100
MHz
flash*5 *6 *12 *14
FCLK = 50 MHz
Sleep mode*5 *14 — 4.4*6 25*7
*12 *13
Increase Data flash P/E — 6 —

during BGO
operation Code flash P/E — 8 —
Low-speed mode*5 *10 — 0.8 — ICLK = 1 MHz
Subosc-speed mode*5 *11 — 0.7 — ICLK = 32.768

kHz
Software Standby mode SNZCR.RXDREQEN = 1 — — 14 —
SNZCR.RXDREQEN = 0 — 0.7 — —
Deep Power supplied to Standby SRAM and USB — 16 96 µA —
Software resume detecting unit
Standby
mode Power not Power-on reset circuit low power — 12 27 —
supplied to function disabled
SRAM or USB
resume Power-on reset circuit low power — 5 17 —
detecting unit function enabled
Increase when When the low-speed on-chip — 4.4 — —

the RTC and oscillator (LOCO) is in use
AGT are
operating When a crystal oscillator for low — 1.0 — —
clock loads is in use
When a crystal oscillator for — 1.6 — —
standard clock loads is in use
RTC operating while VCC is off (with the When a crystal — 0.6 — VBATT = 1.8 V,
battery backup function, only the RTC and oscillator for low VCC = 0 V
sub-clock oscillator operate) clock loads is in use
— 1.2 — VBATT = 3.3 V,
VCC = 0 V
When a crystal — 1.1 — VBATT = 1.8 V,
oscillator for VCC = 0 V
standard clock
loads is in use — 1.8 — VBATT = 3.3 V,
VCC = 0 V
Inrush current on returning from Deep Inrush current*8 IRUSH — 160 — mA
Energy of inrush ERUSH — 1.0 — µC
current*8
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Jul 28, 2023
Table 2.7 Operating and standby current (2 of 2)

Analog During 12-bit A/D conversion AICC — 0.8 1.1 mA —

power
supply Temperature sensor — 0.1 0.2 mA —
current During D/A conversion (per unit) Without AMP output — 0.1 0.2 mA —
With AMP output — 0.6 1.1 mA —
Waiting for A/D, D/A conversion (all units) — 0.5 1.0 mA —
ADC12, DAC12 in standby modes (all units)*9 — 0.4 4.0 µA —
Reference During 12-bit A/D conversion (unit 0) AIREFH0 — 70 120 µA —

power
supply Waiting for 12-bit A/D conversion (unit 0) — 0.07 0.5 µA —
current ADC12 in standby modes (unit 0) — 0.07 0.5 µA —
(VREFH0)
Reference During D/A conversion (per unit) Without AMP output AIREFH — 0.1 0.4 mA —
power
supply With AMP ouput — 0.1 0.4 mA —
current Waiting for D/A (all units) conversion — 0.07 0.8 µA —
(VREFH)
USB Low speed USB ICCUSBLS — 3.5 6.5 mA VCC_USB
operating
current Full speed USB ICCUSBFS — 4.0 10.0 mA VCC_USB
LDO operating current (1 unit)*15 ICCLDO — 0.18 — mA —
PLL2-LDO operating current ICCPLL2LDO — 0.21 — mA —
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows.
ICC Max. = 0.53 × f + 12 (max. operation in high-speed mode)
ICC Typ. = 0.05 × f + 1.85 (normal operation in high-speed mode, all peripheral clocks disabled)
ICC Typ. = 0.12 × f + 0.69 (low-speed mode)
ICC Max. = 0.13 × f + 12 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.563 MHz).
Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).
Note 8. Reference value
Note 9. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and
MSTPCRD.MSTPD20 (12-bit D/A converter module stop bit) are in the module-stop state.
Note 10. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).
Note 11. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.
Note 12. PLL output frequency = 100MHz.
Note 13. PLL output frequency = 200MHz.
Note 14. PLL2-LDO disabled.
Note 15. n = 0, 1
Table 2.8 Coremark and normal mode current

Parameter Symbol Typ Unit Test conditions
Supply Current*1 Coremark*2 *3 *4 ICC 81 µA/MHz ICLK = 100MHz

PCLKA
Normal mode All peripheral 60 = PCLKB
clocks disabled, = PCLKC
cache on, while = PCLKD
(1) code = FCLK
executing from = 1.56 MHz
flash*2 *3 *4
All peripheral 118
clocks disabled,
cache off, while
(1) code
executing from
flash*2 *3 *4
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Jul 28, 2023
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Under development Preliminary document
Note 3. PLL output frequency = 100MHz.Specifications in this document are tentative and subject to change
Note 4. PLL2-LDO disabled.
Under
RA4M2 development
Series Preliminary document 59. Electrical Characteristics
Specifications in this document are tentative and subject to change
RA4M2 Series 59. Electrical Characteristics
100.0
100.0
10.0
ICC (mA)
10.0
ICC (mA)
1.0
1.0
0.1
-40 -20 0 20 40 60 80 100
0.1 Ta (℃)
-40 -20 0 20 40 60 80 100
Ta (℃) during product evaluation.
Average value of the tested middle samples
Average value of the tested upper-limit samples during product evaluation.
Average value of the tested middle samples during product evaluation.
Figure 47.2 Temperature dependency in Software Standby mode (reference data)
1000
1000
100
ICC (uA)
100
ICC (uA)
10
10
1
-40 -20 0 20 40 60 80 100
1 Ta (℃)
-40 -20 0 20 40 60 80 100
Average value of the tested middle Ta (℃) during product evaluation.
samples
Average value of the tested middle samples during product evaluation.
Figure 47.3 Temperature dependency
Average value in Deep
of the tested Software
upper-limit Standby
samples duringmode,
productpower supplied to standby
evaluation.
SRAM and USB resume detecting unit (reference data)
Figure 47.3 Temperature dependency in Deep Software Standby mode, power supplied to standby
Figure 2.3 SRAM and
Temperature USB resume detecting
dependency in Deepunit (reference
Software data)
Standby mode, power supplied to standby SRAM
and USB resume detecting unit (reference data)
RA4M2 Target Spec Page 9 of 2123

xx xx, 2019
RA4M2 Target Spec Page 9 of 2123
xx xx, 2019
R01DS0367EJ0130 Rev.1.30 Page 28 of 93

Jul 28, 2023
RA4M2 Datasheet Under development Preliminary document 2. Electrical Characteristics
Specifications in this document are tentative and subject to change
Under development Preliminary document

100 Specifications in this document are tentative and subject to change
100
ICC (uA)
10
ICC (uA)
10
1
-40 -20 0 20 40 60 80 100
Ta (℃)
1 Average value of the tested middle samples during product evaluation.

-40 -20 0 20 40 60 80 100
Ta (℃)
Figure 47.4 Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
Figure 2.4 USB resume
Temperature Averageunit,
detecting
dependency value of the tested
in power-on
Deep middle
reset
Software samples
circuit low during
Standby power product evaluation.
function
mode, disabled
power not (reference
supplieddata)
to SRAM or
USB resume detecting unit,
Average valuepower-on
of the tested reset circuit
upper-limit low
samples power
during function
product disabled (reference
evaluation.
data) Figure 47.4 Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
100
USB resume detecting unit, power-on reset circuit low power function disabled (reference data)
100
ICC (uA)
10
ICC (uA)
10
1
-40 -20 0 20 40 60 80 100
Ta (℃)
1 Average value of the tested middle samples during product evaluation.

-40 -20 0 20 40 60 80 100
Ta (℃)
Averageunit,
USB resume detecting valuepower-on
of the tested middle
reset samples
circuit low during
powerproduct evaluation.
function enabled (reference data)
Figure 2.5 Temperature dependency
USB resume in power-on
detecting unit, Deep Software Standby
reset circuit mode,
low power power
function not(reference
enabled supplieddata)
to SRAM or
USB resume detecting unit, power-on reset circuit low power function enabled (reference data)
2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.9 Rise and fall gradient characteristics
RA4M2 Starget Spec Page 10 of 2123
xx xx, 2019 Test
Parameter Symbol Min Typ Max Unit conditions
VCC rising gradient RA4M2 Starget

Voltage monitorSpec
0 reset disabled at startup SrVCC 0.0084 — Page
20 10 ms/V
of 2123 —
xx xx, 2019
Voltage monitor 0 reset enabled at startup 0.0084 — — —
SCI/USB boot mode*1 0.0084 — 20 —
VCC falling gradient*2 SfVCC 0.0084 — — ms/V —
Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.
Note 2. This applies when VBATT is used.
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Table 2.10 Rising and falling gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7
V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Allowable ripple fr (VCC) — — 10 kHz Figure 2.6

frequency Vr (VCC) ≤ VCC × 0.2
— — 1 MHz Figure 2.6

Vr (VCC) ≤ VCC × 0.08
— — 10 MHz Figure 2.6

Vr (VCC) ≤ VCC × 0.06
Allowable voltage dt/dVCC 1.0 — — ms/V When VCC change

change rising and exceeds VCC ±10%
falling gradient
1 / fr(VCC)
VCC Vr(VCC)
Figure 2.6 Ripple waveform
2.2.7 Thermal Characteristics

Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”.
Tj is calculated by either of the following equations.
● Tj = Ta + θja × Total power consumption
● Tj = Tt + Ψjt × Total power consumption
– Tj : Junction Temperature (°C)
– Ta : Ambient Temperature (°C)
– Tt : Top Center Case Temperature (°C)
– θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W)
– Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
● Total power consumption = Voltage × (Leakage current + Dynamic current)
● Leakage current of IO = Σ (IOL × VOL) /Voltage + Σ (|IOH| × |VCC – VOH|) /Voltage
● Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage
– Cin: Input capacitance
– Cload: Output capacitance
Regarding θja and Ψjt, refer to Table 2.11.
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Table 2.11 Thermal Resistance

Parameter Package Symbol Value*1 Unit Test conditions
Thermal 48-pin QFN (PWQN0048KC-A) θja 23.9 °C/W JESD 51-2 and 51-7
Resistance compliant
48-pin LQFP (PLQP0048KB-B) 62.1
64-pin LQFP (PLQP0064KB-C) 54.6
48-pin QFN (PWQN0048KC-A) Ψjt 0.28 °C/W JESD 51-2 and 51-7
compliant
64-pin LQFP (PLQP0064KB-C) 1.90
Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the
board. For details, refer to the JEDEC standards.
2.2.7.1 Calculation guide of ICCmax

Table 2.12 shows the power consumption of each unit.
Table 2.12 Power consumption of each unit (1 of 2)
Dynamic current/ MCU Frequency Current Current*1
Leakage current Domain Category Item [MHz] [uA/MHz] [mA]
Leakage current Analog LDO and Leak*2 Ta = 75 °C*3 — — 7.82
Ta = 85 °C*3 — — 9.13
Ta = 95 °C*3 — — 11.08
Ta = 105 °C*3 — — 14.33
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Table 2.12 Power consumption of each unit (2 of 2)

Dynamic current/ MCU Frequency Current Current*1
Leakage current Domain Category Item [MHz] [uA/MHz] [mA]
Dynamic current CPU Operation with Coremark 100 55.556 5.56

Flash and SRAM
Peripheral Unit Timer GPT16 (4ch)*4 100 3.575 0.36
GPT32 (4ch)*4 100 4.230 0.42
POEG (4 Groups) 50 1.361 0.07
AGT (6ch)*4 50 9.228 0.46
RTC 50 4.277 0.21

WDT 50 0.764 0.04
IWDT 50 0.339 0.02
Communication USBFS 50 9.385 0.47
interfaces
SCI (6ch)*4 100 18.715 1.87
IIC (2ch)*4 50 3.367 0.16
CAN 50 1.898 0.09

SPI 100 3.024 0.30
QSPI 100 2.051 0.21
SSIE 50 3.208 0.16
SDHI 50 6.341 0.32
Analog ADC12 100 2.287 0.23
DAC12 (2ch)*4 100 0.869 0.09
TSN 50 0.166 0.01

Human machine CTSU 50 0.605 0.03
interfaces
Event link ELC 50 0.865 0.04
Security SCE9 100 218.100 21.81
Data processing CRC 100 0.600 0.06
DOC 100 0.388 0.04
System CAC 50 0.844 0.04
DMA DMAC 100 4.479 0.45
DTC 100 4.274 0.43
Note 1. The values are guaranteed by design.
Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current.
It is selected according to the temperature of Ta.
Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current.
Note 4. To determine the current consumption per channel, group or unit, divide Current [mA] by the number of channels, groups or units.
Table 2.13 shows the outline of operation for each unit.
Table 2.13 Outline of operation for each unit (1 of 2)
Peripheral Outline of operation
GPT Operating modes is set to saw-wave PWM mode.

GPT is operating with PCLKD.
POEG Only clear module stop bit.
AGT AGT is operating with PCLKB.
RTC RTC is operating with LOCO.
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Table 2.13 Outline of operation for each unit (2 of 2)

Peripheral Outline of operation
WDT WDT is operating with PCLKB.

IWDT IWDT is operating with IWDTCLK.
USBFS Transfer types is set to bulk transfer.
USBFS is operating using Full-speed transfer (12 Mbps).
SCI SCI is transmitting data in clock synchronous mode.
IIC Communication format is set to I2C-bus format.
IIC is transmitting data in master mode.
CAN CAN is transmitting and receiving data in self-test mode 1.
SPI SPI mode is set to SPI operation (4-wire method).
SPI master/slave mode is set to master mode.
SPI is transmitting 8-bit width data.
QSPI QSPI is issuing Fast Read Quad I/O Instruction.
SSIE Communication mode is set to Master.
System word length is set to 32 bits.
Data word length is set to 20 bits.
SSIE is transmitting data using I2S format.
SDHI Transfer bus mode is set to 4-bit wide bus mode.
SDHI is issuing CMD24 (single-block write).
ADC12 Resolution is set to 12-bit accuracy.
Data registers is set to A/D-converted value addition mode.
ADC12 is converting the analog input in continuous scan mode.
DAC12 DAC12 is outputting the conversion result while updating the value of data register.
TSN TSN is operating.
CTSU CTSU is operating in self-capacitance single scan mode.
ELC Only clear module stop bit.
SCE9 SCE9 is executing built-in self test.
CRC CRC is generating CRC code using 32-bit CRC32-C polynomial.
DOC DOC is operating in data addition mode.
CAC Measurement target clocks is set to PCLKB.
Measurement reference clocks is set to PCLKB.
CAC is measuring the clock frequency accuracy.
DMAC Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DMAC is transferring data from SRAM0 to SRAM0.
DTC Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DTC is transferring data from SRAM0 to SRAM0.
2.2.7.2 Example of Tj calculation

Assumption :
● Package 100-pin LQFP : θja = 55.1 °C/W
● Ta = 100 °C
● ICCmax = 40 mA
● VCC = 3.5 V (VCC = AVCC = VCC_USB)
● IOH = 1 mA, VOH = VCC – 0.5 V, 12 Outputs
● IOL = 20 mA, VOL = 1.0 V, 8 Outputs
● IOL = 1 mA, VOL = 0.5 V, 12 Outputs
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Jul 28, 2023
● Cin = 8 pF, 16 pins, Input frequency = 10 MHz

● Cload = 30 pF, 16 pins, Output frequency = 10 MHz
Leakage current of IO = Σ (VOL × IOL) / Voltage + Σ ((VCC - VOH) × IOH) / Voltage
= (20 mA × 1 V) × 8 / 3.5 V + (1 mA × 0.5 V) × 12 / 3.5 V + ((VCC - (VCC - 0.5 V)) × 1 mA) × 12 / 3.5 V
= 45.7 mA + 1.71 mA + 1.71 mA
= 49.1 mA
Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage
= ((8 pF × 16) × 10 MHz + (30 pF × 16) × 10 MHz) × 3.5 V

= 21.3 mA
Total power consumption = Voltage × (Leakage current + Dynamic current)

= (40 mA × 3.5 V) + (49.1 mA + 21.3 mA) × 3.5 V
= 386 mW (0.386 W)
Tj = Ta + θja × Total power consumption

= 100 °C + 55.1 °C/W × 0.386W
= 121.3 °C
2.3 AC Characteristics
2.3.1 Frequency
Table 2.14 Operation frequency value in high-speed mode
Operation frequency System clock (ICLK) f — — 100 MHz

Peripheral module clock (PCLKA) — — 100
Peripheral module clock (PCLKB) — — 50
Peripheral module clock (PCLKC) —*2 — 50
Peripheral module clock (PCLKD) — — 100

Flash interface clock (FCLK) —*1 — 50
Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.
Table 2.15 Operation frequency value in low-speed mode

Operation frequency System clock (ICLK) f — — 1 MHz

Peripheral module clock (PCLKA) — — 1
Peripheral module clock (PCLKB) — — 1
Peripheral module clock (PCLKC) *2 —*2 — 1
Peripheral module clock (PCLKD) — — 1
Flash interface clock (FCLK)*1 — — 1
Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.
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Jul 28, 2023
Table 2.16 Operation frequency value in Subosc-speed mode

Operation frequency System clock (ICLK) f 29.4 — 36.1 kHz

Peripheral module clock (PCLKA) — — 36.1
Peripheral module clock (PCLKB) — — 36.1
Peripheral module clock (PCLKC) *2 — — 36.1
Peripheral module clock (PCLKD) — — 36.1
Flash interface clock (FCLK)*1 29.4 — 36.1
Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.

Note 2. The ADC12 cannot be used.
2.3.2 Clock Timing

Table 2.17 Clock timing except for sub-clock oscillator (1 of 2)
EXTAL external clock input cycle time tEXcyc 41.66 — — ns Figure 2.7
EXTAL external clock input high pulse width tEXH 15.83 — — ns
EXTAL external clock input low pulse width tEXL 15.83 — — ns
EXTAL external clock rise time tEXr — — 5.0 ns
EXTAL external clock fall time tEXf — — 5.0 ns
Main clock oscillator frequency fMAIN 8 — 24 MHz —
Main clock oscillation stabilization wait time (crystal)*1 tMAINOSCWT — — —*1 ms Figure 2.8
LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz —
LOCO clock oscillation stabilization wait time tLOCOWT — — 60.4 µs Figure 2.9
ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz —
MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz —
MOCO clock oscillation stabilization wait time tMOCOWT — — 15.0 µs —
HOCO clock oscillator oscillation Without FLL fHOCO16 15.78 16 16.22 MHz –20 ≤ Ta ≤ 105°C
frequency
fHOCO18 17.75 18 18.25
fHOCO20 19.72 20 20.28
fHOCO16 15.71 16 16.29 –40 ≤ Ta ≤ –20°C
fHOCO18 17.68 18 18.32
fHOCO20 19.64 20 20.36
With FLL fHOCO16 15.960 16 16.040 –40 ≤ Ta ≤ 105°C

Sub-clock frequency accuracy
fHOCO18 17.955 18 18.045 is ±50 ppm.
fHOCO20 19.950 20 20.050
HOCO clock oscillation stabilization wait time*2 tHOCOWT — — 64.7 µs —
HOCO period jitter — — ±85 — ps —

FLL stabilization wait time tFLLWT — — 1.8 ms —
PLL clock frequency fPLL 100 — 200 MHz —
PLL2 clock frequency fPLL2 120 — 240 MHz —
PLL/PLL2 clock oscillation stabilization wait time tPLLWT — — 174.9 µs Figure 2.10
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Table 2.17 Clock timing except for sub-clock oscillator (2 of 2)

PLL/PLL2 period jitter fPLL, fPLL2 ≥ 120MHz — — ±100 — ps —
fPLL, fPLL2 < 120MHz — — ±120 — ps —
PLL/PLL2 long term jitter — — ±300 — ps Term: 1µs, 10µs

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that
it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed
operation.
Table 2.18 Clock timing for the sub-clock oscillator

Sub-clock frequency fSUB — 32.768 — kHz —
Sub-clock oscillation stabilization wait time tSUBOSCWT — — —*1 s Figure 2.11
Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the
sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended.
tXcyc
tXH tXL
EXTAL external clock input VCC × 0.5
tXr tXf
Figure 2.7 EXTAL external clock input timing
MOSCCR.MOSTP
Main clock oscillator output
tMAINOSCWT
Main clock
Figure 2.8 Main clock oscillation start timing
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LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.9 LOCO clock oscillation start timing
PLLCR.PLLSTP
PLL2CR.PLL2STP
PLL/PLL2 circuit output
tPLLWT
OSCSF.PLLSF
OSCSF.PLL2SF
PLL/PLL2 clock
Figure 2.10 PLL/PLL2 clock oscillation start timing
SOSCCR.SOSTP
Sub-clock oscillator output
tSUBOSCWT
Sub-clock
Figure 2.11 Sub-clock oscillation start timing
2.3.3 Reset Timing

Table 2.19 Reset timing (1 of 2)
RES pulse width Power-on tRESWP 0.7 — — ms Figure 2.12
Deep Software Standby mode tRESWD 0.6 — — ms Figure 2.13
Software Standby mode, Subosc-speed tRESWS 0.3 — — ms

mode
All other tRESW 200 — — µs
Wait time after RES cancellation tRESWT — 37.3 41.2 µs Figure 2.12
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Table 2.19 Reset timing (2 of 2)

Wait time after internal reset cancellation tRESW2 — 324 397.7 µs —

(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error
reset, bus master MPU error reset, TrustZone error reset)
VCC VCCmin
RES
tRESWP
Internal reset signal
(low is valid)
tRESWT
Figure 2.12 RES pin input timing under the condition that VCC exceeds VPOR voltage threshold
tRESWD, tRESWS, tRESW
RES

(low is valid)
tRESWT
Figure 2.13 Reset input timing
2.3.4 Wakeup Timing

Table 2.20 Timing of recovery from low power modes (1 of 2)
Recovery time from Crystal resonator System clock source is tSBYMC*13 — 2.1 2.4 ms Figure 2.14
Software Standby connected to main clock main clock oscillator*2 The division ratio of all
mode*1 oscillator oscillators is 1.
System clock source is tSBYPC*13 — 2.2 2.6 ms
PLL with main clock
oscillator*3
External clock input to System clock source is tSBYEX*13 — 45 125 μs
main clock oscillator main clock oscillator*4
System clock source is tSBYPE*13 — 170 255 μs
PLL with main clock
oscillator*5
System clock source is sub-clock oscillator*6 *11 tSBYSC*13 — 0.7 0.8 ms
System clock source is LOCO*7 *11 tSBYLO*13 — 0.7 0.9 ms
System clock source is HOCO clock oscillator*8 tSBYHO*13 — 55 130 µs
System clock source is PLL with HOCO*9 tSBYPH*13 — 175 265 µs
System clock source is MOCO clock oscillator*10 tSBYMO*13 — 35 65 µs
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Table 2.20 Timing of recovery from low power modes (2 of 2)

Recovery time from DPSBYCR.DEEPCUT[1] = 0 and tDSBY — 0.38 0.54 ms Figure 2.15
Deep Software DPSWCR.WTSTS[5:0] = 0x0E
Standby mode
DPSBYCR.DEEPCUT[1] = 1 and tDSBY — 0.55 0.73 ms
DPSWCR.WTSTS[5:0] = 0x19
Wait time after cancellation of Deep Software Standby mode tDSBYWT 56 — 57 tcyc
Recovery time from High-speed mode when system clock source is tSNZ — 35*12 70*12 μs Figure 2.16
Software Standby HOCO (20 MHz)
mode to Snooze
mode High-speed mode when system clock source is tSNZ — 11*12 14*12 μs
MOCO (8 MHz)
Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators -
tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC
module stop))
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the
greatest value of the internal clock division setting is 1.
Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest
value of the internal clock division setting is 4.
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and
the greatest value of the internal clock division setting is 1.
Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest
value of the internal clock division setting is 4.
Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.
Note 7. The LOCO frequency is 32.768 kHz and the greatest value of the internal clock division setting is 1.
Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.
Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.
Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.
Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs
(maximum).
Note 13. The recovery time can be calculated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the following
value and equation. For n, the greatest value is selected from among the internal clock division settings.
Wakeup time TYP MAX Unit

tSBYOSCWT tSBYSEQ tSBYOSCWT tSBYSEQ
tSBYMC (MSTS[7:0]*32 + 3) / 35 + 18 / fICLK + 4n / fMAIN (MSTS[7:0]*32 + 14 / 62 + 18 / fICLK + 4n / fMAIN µs

0.262 0.236
tSBYPC (MSTS[7:0]*32 + 34) / 35 + 18 / fICLK + 4n / fPLL (MSTS[7:0]*32 + 45) / 62 + 18 / fICLK + 4n / fPLL µs
0.262 0.236
tSBYEX 10 35 + 18 / fICLK + 4n / fEXMAIN 62 62 + 18 / fICLK + 4n / fEXMAIN µs
tSBYPE 135 35 + 18 / fICLK + 4n / fPLL 192 62 + 18 / fICLK + 4n / fPLL µs
tSBYSC 0 35 + 18 / fICLK + 4n / fSUB 0 62 + 18 / fICLK + 4n / fSUB µs
tSBYLO 0 35 + 18 / fICLK + 4n / fLOCO 0 62 + 18 / fICLK + 4n / fLOCO µs
tSBYHO 20 35 + 18 / fICLK + 4n / fHOCO 67 62 + 18 / fICLK + 4n / fHOCO µs
tSBYPH 140 35 + 18 / fICLK + 4n / fPLL 202 62 + 18 / fICLK + 4n / fPLL µs
tSBYMO 0 35 + 18 / fICLK + 4n / fMOCO 0 62 + 18 / fICLK + 4n / fMOCO µs
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Oscillator
(system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock)
ICLK
IRQ
tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock)
tSBYOSCWT
ICLK
IRQ
tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.14 Software Standby mode cancellation timing
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Oscillator
IRQ
Deep Software Standby

reset
(low is valid)
Internal reset
(low is valid)
Deep Software Standby mode

tDSBY
tDSBYWT
Reset exception handling start
Figure 2.15 Deep Software Standby mode cancellation timing
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode Snooze mode

tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.16 Recovery timing from Software Standby mode to Snooze mode
2.3.5 NMI and IRQ Noise Filter

Table 2.21 NMI and IRQ noise filter
NMI pulse tNMIW 200 — — ns NMI digital filter tPcyc × 2 ≤ 200 ns

width disabled
tPcyc × 2*1 — — tPcyc × 2 > 200 ns
200 — — NMI digital filter tNMICK × 3 ≤ 200 ns

enabled
tNMICK × 3.5*2 — — tNMICK × 3 > 200 ns
IRQ pulse tIRQW 200 — — ns IRQ digital filter tPcyc × 2 ≤ 200 ns

width disabled
tPcyc × 2*1 — — tPcyc × 2 > 200 ns
200 — — IRQ digital filter tIRQCK × 3 ≤ 200 ns

enabled
tIRQCK × 3.5*3 — — tIRQCK × 3 > 200 ns
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Note: 200 ns minimum in Software Standby mode.

Note: If the clock source is switched, add 4 clock cycles of the switched source.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.
NMI
tNMIW
Figure 2.17 NMI interrupt input timing
IRQ
tIRQW
Figure 2.18 IRQ interrupt input timing
2.3.6 I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing
Table 2.22 I/O ports, POEG, GPT, AGT, and ADC12 trigger timing
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions
I/O ports Input data pulse width tPRW 1.5 — tPcyc Figure 2.19
POEG POEG input trigger pulse width tPOEW 3 — tPcyc Figure 2.20
GPT Input capture pulse width Single edge tGTICW 1.5 — tPDcyc Figure 2.21
Dual edge 2.5 —
GTIOCxY output skew Middle drive buffer tGTISK*1 — 4 ns Figure 2.22
(x = 0 to 3, Y = A or B)
High drive buffer — 4
GTIOCxY output skew Middle drive buffer — 4
(x = 4 to 7, Y = A or B)
GTIOCxY output skew Middle drive buffer — 6
(x = 0 to 7, Y = A or B)
OPS output skew tGTOSK — 5 ns Figure 2.23
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
AGT AGTIO, AGTEE input cycle tACYC*2 100 — ns Figure 2.24
AGTIO, AGTEE input high width, low width tACKWH, tACKWL 40 — ns
AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 — ns
ADC12 ADC12 trigger input pulse width tTRGW 1.5 — tPcyc Figure 2.25
Note: tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.
Note 2. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
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When switching the source clock: tPcyc × 6 < tACYC should be satisfied.
Port
tPRW
Figure 2.19 I/O ports input timing
POEG input trigger
tPOEW
Figure 2.20 POEG input trigger timing
Input capture
tGTICW
Figure 2.21 GPT input capture timing
PCLKD
Output delay
GPT output
tGTISK
Figure 2.22 GPT output delay skew
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PCLKD
Output delay
GPT output
tGTOSK
Figure 2.23 GPT output delay skew for OPS
tACYC
tACKWL tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.24 AGT input/output timing
ADTRG0
tTRGW
Figure 2.25 ADC12 trigger input timing
2.3.7 CAC Timing

Table 2.23 CAC timing
CAC CACREF input pulse tPBcyc ≤ tcac*1 tCACREF 4.5 × tcac + 3 × tPBcyc — — ns —
width
tPBcyc > tcac*1 5 × tcac + 6.5 × tPBcyc — — ns
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Note: tPBcyc: PCLKB cycle.

Note 1. tcac: CAC count clock source cycle.
2.3.8 SCI Timing

Table 2.24 SCI timing (1)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
SCI Input clock cycle Asynchronous tScyc 4 — tPcyc Figure 2.26

Clock synchronous 6 —
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr — 5 ns
Input clock fall time tSCKf — 5 ns
Output clock cycle Asynchronous tScyc 6 (other than SCI1, — tPcyc

SCI2)
8 (SCI1, SCI2)
Clock synchronous 4 —
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time tSCKr — 5 ns
Output clock fall time tSCKf — 5 ns
Transmit data delay Clock synchronous master mode (internal tTXD — 5 ns Figure 2.27
clock)
Clock synchronous slave mode (external tTXD — 25 ns
clock)
Receive data setup time Clock synchronous master mode (internal tRXS 15 — ns
clock)
Clock synchronous slave mode (external tRXS 5 — ns
clock)
Receive data hold time Clock synchronous tRXH 5 — ns
Note: tPcyc: PCLKA cycle.
tSCKW tSCKr tSCKf
SCKn
tScyc
Note: n = 0 to 4, 9
Figure 2.26 SCK clock input/output timing
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SCKn
tTXD
TXDn
tRXS tRXH
RXDn
Note: n = 0 to 4, 9
Figure 2.27 SCI input/output timing in clock synchronous mode

Simple SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.28
SCK clock cycle input (slave) 6 65536
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise and fall time tSPCKr, tSPCKf — 5 ns
Data input setup time master tSU 15 — ns Figure 2.29 to Figure

2.32
slave 5 — ns
Data input hold time tH 5 — ns
SS input setup time tLEAD 1 — tSPcyc
SS input hold time tLAG 1 — tSPcyc
Data output delay master tOD — 5 ns

slave — 25 ns
Data output hold time tOH -5 — ns
Data rise and fall time tDr, tDf — 5 ns
SS input rise and fall time tSSLr, tSSLf — 5 ns
Slave access time tSA — 3 × tPcyc + 25 ns Figure 2.32
Slave output release time tREL — 3 × tPcyc + 25 ns
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tSPCKWH tSPCKr tSPCKf
VOH VOH VOH VOH

SCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc
VIH VIH VIH VIH

SCKn
slave select input VIL VIL VIL
tSPCKWL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note: n = 0 to 4, 9
Figure 2.28 SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU tH
MISOn
MSB IN DATA LSB IN MSB IN
input
tDr, tDf tOH tOD
MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output
Note: n = 0 to 4, 9
Figure 2.29 SCI simple SPI mode timing for master when CKPH = 1
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SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU tH
MISOn
input
tOH tOD tDr, tDf
MOSIn
output
Note: n = 0 to 4, 9
Figure 2.30 SCI simple SPI mode timing for master when CKPH = 0
tTD
SSn
input
tLEAD tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA tOH tOD tREL
MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output
tSU tH tDr, tDf
MOSIn
input
Note: n = 0 to 4, 9
Figure 2.31 SCI simple SPI mode timing for slave when CKPH = 1
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Jul 28, 2023
tTD
SSn
input
tLEAD tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA tOH tOD tREL
MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output
tSU tH tDr, tDf
MOSIn
input
Note: n = 0 to 4, 9
Figure 2.32 SCI simple SPI mode timing for slave when CKPH = 0

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Simple IIC SDA input rise time tSr — 1000 ns Figure 2.33
(Standard mode)
SDA input fall time tSf — 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 250 — ns
Data input hold time tSDAH 0 — ns
SCL, SDA capacitive load Cb*1 — 400 pF
Simple IIC SDA input rise time tSr — 300 ns Figure 2.33
(Fast mode)
SDA input fall time tSf — 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 100 — ns
Note: tIICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.
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VIH
SDAn
VIL
tSr tSf
tSP
SCLn
P*1 S*1 Sr*1 P*1
tSDAH tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note: n = 0 to 4, 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.33 SCI simple IIC mode timing
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2.3.9 SPI Timing

Table 2.27 SPI timing
SPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc Figure 2.34
Slave 4 4096
RSPCK clock high Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / — ns
pulse width 2–3
Slave 0.4 0.6 tSPcyc
RSPCK clock low Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / — ns

pulse width 2–3
Slave 0.4 0.6 tSPcyc
RSPCK clock rise and Master tSPCKr, tSPCKf — 5 ns

fall time
Slave — 1 µs
Data input setup time Master tSU 4 — ns Figure 2.35 to Figure
2.40
Slave 5 —
Data input hold time Master tHF 0 — ns
(PCLKA
division ratio
set to 1/2)
Master tH tPcyc —
(PCLKA
division ratio
set to a value
other than
1/2)
Slave tH 20 —
SSL setup time Master tLEAD N × tSPcyc - 10*1 N × tSPcyc + ns

100*1
Slave 4 × tPcyc — ns
SSL hold time Master tLAG N × tSPcyc - 10*2 N × tSPcyc + ns

100*2
Slave 4 × tPcyc — ns
Data output delay Master tOD1 — 6.3 ns
tOD2 — 6.3
Slave tOD — 20
Data output hold time Master tOH 0 — ns

Slave 0 —
Successive Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 ns
transmission delay × tPcyc
Slave 4 × tPcyc
MOSI and MISO rise Output tDr, tDf — 5 ns

and fall time
Input — 1 µs
SSL rise and fall time Output tSSLr, tSSLf — 5 ns
Input — 1 µs
Slave access time tSA — 25 ns Figure 2.39 and
Figure 2.40
Slave output release time tREL — 25
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Jul 28, 2023
Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. N is set to an integer from 1 to 8 by the SPCKD register.
Note 2. N is set to an integer from 1 to 8 by the SSLND register.
VOH VOH VOH VOH

RSPCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc
VIH VIH VIH VIH

RSPCKn
slave select input VIL VIL VIL
tSPCKWL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note: n=A
Figure 2.34 SPI clock timing
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU tH
MISOn
input
tDr, tDf tOH tOD2
MOSIn
output
tOD1
Note: n=A
Figure 2.35 SPI timing for master when CPHA = 0
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SPI tTD
SSLn0 to
SSLn3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU tHF tHF
MISOn MSB IN DATA LSB IN MSB IN

input
tDr, tDf tOH tOD2
MOSIn MSB OUT DATA LSB OUT IDLE MSB OUT

output
tOD1
Note: n=A
Figure 2.36 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU tH
MISOn
input
tOH tOD2 tDr, tDf
MOSIn
output
Note: n=A
Figure 2.37 SPI timing for master when CPHA = 1
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Jul 28, 2023
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU tHF tH
MISOn
input
tOH tOD2 tDr, tDf
MOSIn
output
Note: n=A
Figure 2.38 SPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2
tTD
SSLn0
input
tLEAD tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA tOH tOD tREL
MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output
tSU tH tDr, tDf
MOSIn
input
Note: n=A
Figure 2.39 SPI timing for slave when CPHA = 0
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tTD
SSLn0
input
tLEAD tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA tOH tOD tREL
MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output
tSU tH tDr, tDf
MOSIn
input
Note: n=A
Figure 2.40 SPI timing for slave when CPHA = 1
2.3.10 QSPI Timing

Table 2.28 QSPI timing
QSPI QSPCK clock cycle tQScyc 2 48 tPcyc Figure 2.41
QSPCK clock high pulse tQSWH tQScyc × 0.4 — ns

width
QSPCK clock low pulse tQSWL tQScyc × 0.4 — ns
width
Data input setup time tSu 10 — ns Figure 2.42
Data input hold time tIH 0 — ns
QSSL setup time tLEAD (N + 0.5) × tQscyc - 5*1 (N + 0.5) × tQscyc + ns

100*1
QSSL hold time tLAG (N + 0.5) × tQscyc - 5*2 (N + 0.5) × tQscyc + ns
100*2
Data output delay tOD — 4 ns
Data output hold time tOH –3.3 — ns
Successive transmission tTD 1 16 tQScyc

delay
Note 1. N is set to 0 or 1 in SFMSLD.
Note 2. N is set to 0 or 1 in SFMSHD.
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tQSWH tQSWL
QSPCLK output
tQScyc
Figure 2.41 QSPI clock timing
tTD
QSSL
output
tLEAD tLAG
QSPCLK
output
tSU tH
QIO0-3
MSB IN DATA LSB IN
input
tOH tOD
QIO0-3
MSB OUT DATA LSB OUT IDLE
output
Figure 2.42 Transmit and receive timing
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2.3.11 IIC Timing

Table 2.29 IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Test
Parameter Symbol Min Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 — ns Figure 2.43
(Standard mode,
SMBus) SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns
ICFER.FMPE = 0
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns
SCL, SDA rise time tSr — 1000 ns
SCL, SDA fall time tSf — 300 ns
SCL, SDA input spike pulse tSP 0 1 (4) × tIICcyc ns

removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 — ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc + — ns
wakeup function is enabled 300
START condition input hold time tSTAH tIICcyc + 300 — ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + 300 — ns
when wakeup function is enabled
Repeated START condition input tSTAS 1000 — ns
setup time
STOP condition input setup time tSTOS 1000 — ns
Data input setup time tSDAS tIICcyc + 50 — ns
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Table 2.29 IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
Test
Parameter Symbol Min Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 600 — ns Figure 2.43
(Fast mode)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns
SCL, SDA rise time tSr 20 × (external pullup 300 ns

voltage/5.5V)*1
SCL, SDA fall time tSf 20 × (external pullup 300 ns
voltage/5.5V)*1
removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc + — ns
wakeup function is enabled 300
START condition input hold time tSTAH tIICcyc + 300 — ns
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + 300 — ns
when wakeup function is enabled
Repeated START condition input tSTAS 300 — ns
setup time
STOP condition input setup time tSTOS 300 — ns
Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note: Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. Only supported for SCL0_A and SDA0_A.
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Table 2.30 IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + — ns Figure 2.43
(Fast-mode+) 240
ICFER.FMPE = 1
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 — ns
SCL, SDA rise time tSr — 120 ns
SCL, SDA fall time tSf 20 × (external 120 ns

pullup voltage/
5.5V)
removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × — ns
wakeup function is enabled tPcyc + 120
Start condition input hold time tSTAH tIICcyc + 120 — ns

START condition input hold time tSTAH 1 (5) × tIICcyc + — ns
when wakeup function is enabled tPcyc + 120
Restart condition input setup time tSTAS 120 — ns
Stop condition input setup time tSTOS 120 — ns
Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note: Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
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VIH
SDAn
VIL
tBUF
tSCLH
tSTAH tSTAS tSP tSTOS
SCLn
P*1 S*1 Sr*1 P*1

tSCLL
tSf tSr tSDAS
tSCL
tSDAH
Note: n = 0, 1
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.43 I2C bus interface input/output timing
2.3.12 SSIE Timing

Table 2.31 SSIE timing
(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the
Target specification
Parameter Symbol Min. Max. Unit Comments
SSIBCK0 Cycle Master tO 80 — ns Figure 2.44
Slave tI 80 — ns
High level/ low Master tHC/tLC 0.35 — tO

level
Slave 0.35 — tI
Rising time/ Master tRC/tFC — 0.15 tO / tI

falling time
Slave — 0.15 tO / tI
SSILRCK0/ Input set up Master tSR 12 — ns Figure 2.46,

SSIFS0, time Figure 2.47
SSITXD0, Slave 12 — ns
SSIRXD0 Input hold time Master tHR 8 — ns
Slave 15 — ns
Output delay Master tDTR -10 5 ns
time
Slave 0 20 ns Figure 2.46,
Figure 2.47
Output delay Slave tDTRW — 20 ns Figure 2.48*1
time from
SSILRCK0/
SSIFS0 change
GTIOC2A, Cycle tEXcyc 20 — ns Figure 2.45
AUDIO_CLK
High level/ low level tEXL/tEXH 0.4 0.6 tEXcyc
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Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 pin.
tHC tRC tFC
SSIBCK0 tLC
tO, tI
Figure 2.44 SSIE clock input/output timing
tEXcyc
tEXH tEXL
GTIOC2A,
AUDIO_CLK 1/2 VCC
(input)
tEXf tEXr
Figure 2.45 Clock input timing
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0 (input)
tSR tHR
SSILRCK0/SSIFS0 (output),
SSITXD0 (output)
tDTR
Figure 2.46 SSIE data transmit and receive timing when SSICR.BCKP = 0
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SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0 (input)
tSR tHR
SSILRCK0/SSIFS0 (output),
SSITXD0 (output)
tDTR
Figure 2.47 SSIE data transmit and receive timing when SSICR.BCKP = 1
SSILRCK0/SSIFS0 (input)
SSITXD0 (output)
tDTRW
MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.
Figure 2.48 SSIE data output delay after SSILRCK0/SSIFS0 change
2.3.13 SD/MMC Host Interface Timing (m = 0 to 3)

Table 2.32 SD/MMC Host Interface signal timing
Clock duty ratio is 50%.
SD0CLK clock cycle TSDCYC 20 — ns Figure 2.49
SD0CLK clock high pulse width TSDWH 6.5 — ns
SD0CLK clock low pulse width TSDWL 6.5 — ns
SD0CLK clock rise time TSDLH — 3 ns
SD0CLK clock fall time TSDHL — 3 ns
SD0CMD/SD0DATm output data delay TSDODLY –7 4 ns
SD0CMD/SD0DATm input data setup TSDIS 4.5 — ns
SD0CMD/SD0DATm input data hold TSDIH 1.5 — ns
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Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC
Host interface, the AC portion of the electrical characteristics is measured for each group.
TSDCYC
TSDWL TSDWH
SDnCLK
(output) TSDLH
TSDHL TSDODLY(max) TSDODLY(min)
SDnCMD/SDnDATm
(output)
TSDIS TSDIH
SDnCMD/SDnDATm
(input)
n = 0, m = 0 to 3
Figure 2.49 SD/MMC Host Interface signal timing
2.4 USB Characteristics
2.4.1 USBFS Timing

Table 2.33 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —
Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |
Differential common-mode range VCM 0.8 — 2.5 V —
Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA
Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.50
Rise time tLR 75 — 300 ns
Fall time tLF 75 — 300 ns
Rise/fall time ratio tLR / tLF 80 — 125 % tLR/ tLF
Pull-up and USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —

pull-down resistance in host controller mode
characteristics
USB_DP, VCRS 90% 90%

USB_DM 10% 10%
tLR tLF
Figure 2.50 USB_DP and USB_DM output timing in low-speed mode
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Observation
point
USB_DP
200 pF to
600 pF 3.6 V
27 
1.5 K
USB_DM
200 pF to
600 pF
Figure 2.51 Test circuit in low-speed mode
Table 2.34 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —
Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |
Differential common-mode range VCM 0.8 — 2.5 V —
Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA
Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.52
Rise time tLR 4 — 20 ns
Fall time tLF 4 — 20 ns
Rise/fall time ratio tLR / tLF 90 — 111.11 % tFR/ tFF
Output resistance ZDRV 28 — 44 Ω USBFS: Rs = 27 Ω included
Pull-up and DM pull-up resistance in device controller Rpu 0.900 — 1.575 kΩ During idle state
pull-down mode
characteristics 1.425 — 3.090 kΩ During transmission and
reception
USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —
resistance in host controller mode
USB_DP, VCRS 90% 90%

USB_DM 10% 10%
tFR tFF
Figure 2.52 USB_DP and USB_DM output timing in full-speed mode
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Observation
point
USB_DP
50 pF
27 
USB_DM
50 pF
Figure 2.53 Test circuit in full-speed mode
Table 2.35 USBFS characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Battery Charging D+ sink current IDP_SINK 25 — 175 µA —

Specification
D- sink current IDM_SINK 25 — 175 µA —
DCD source current IDP_SRC 7 — 13 µA —
Data detection voltage VDAT_REF 0.25 — 0.4 V —
D+ source voltage VDP_SRC 0.5 — 0.7 V Output current = 250 µA
D- source voltage VDM_SRC 0.5 — 0.7 V Output current = 250 µA
2.5 ADC12 Characteristics

Table 2.36 A/D conversion characteristics for unit 0 (1 of 2)
Conditions: PCLKC = 1 to 50 MHz
Parameter Min Typ Max Unit Test conditions
Frequency 1 — 50 MHz —
Analog input capacitance — — 30 pF —
Quantization error — ±0.5 — LSB —
Resolution — — 12 Bits —
High-precision high-speed Conversion time*1 Permissible signal 0.52 (0.26)*2 — — μs Sampling in 13
channels (operation at PCLKC = source impedance states
(AN000 to AN002) 50 MHz) Max. = 1 kΩ
Max. = 400 Ω 0.40 (0.14)*2 — — μs Sampling in 7
states
VCC = AVCC0 =
3.0 to 3.6 V
3.0 V ≤ VREFH0 ≤
AVCC0
Offset error — ±1.0 ±2.5 LSB —
Full-scale error — ±1.0 ±2.5 LSB —
Absolute accuracy — ±2.0 ±4.5 LSB —
DNL differential nonlinearity error — ±0.5 ±1.5 LSB —
INL integral nonlinearity error — ±1.0 ±2.5 LSB —
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Table 2.36 A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 50 MHz
High-precision normal-speed Conversion time*1 Permissible signal 0.92 (0.66)*2 — — μs Sampling in 33

channels (Operation at PCLKC = source impedance states
(AN003 to AN008, AN011 to 50 MHz) Max. = 1 kΩ
AN013)
Normal-precision normal-speed Conversion time*1 Permissible signal 0.92 (0.66)*2 — — μs Sampling in 33
channels (AN016) (Operation at PCLKC = source impedance states
50 MHz) Max. = 1 kΩ

Note: These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0, VREFL0, and 12-bit A/D converter input voltage are stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Table 2.37 A/D internal reference voltage characteristics

A/D internal reference voltage 1.13 1.18 1.23 V —

Sampling time 4.15 — — µs —
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0xFFF
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic
Ideal A/D conversion

characteristic Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D

conversion characteristic
Absolute accuracy
0x000 Offset error

0 Analog input voltage VREFH0
(full-scale)
Figure 2.54 Illustration of ADC12 characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the
analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D
conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical
A/D conversion characteristics.
Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.
Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
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Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.6 DAC12 Characteristics

Table 2.38 D/A conversion characteristics
Resolution — — 12 Bits —
Without output amplifier
Absolute accuracy — — ±24 LSB Resistive load 2 MΩ
INL — ±2.0 ±8.0 LSB Resistive load 2 MΩ
DNL — ±1.0 ±2.0 LSB —
Output impedance — 8.5 — kΩ —
Conversion time — — 3 µs Resistive load 2 MΩ, Capacitive load 20 pF
Output voltage range 0 — VREFH V —
With output amplifier
INL — ±2.0 ±4.0 LSB —
DNL — ±1.0 ±2.0 LSB —
Conversion time — — 4.0 µs —
Resistive load 5 — — kΩ —
Capacitive load — — 50 pF —
Output voltage range 0.2 — VREFH – 0.2 V —
2.7 TSN Characteristics

Table 2.39 TSN characteristics
Relative accuracy — — ± 1.0 — °C —

Temperature slope — — 4.0 — mV/°C —
Output voltage (at 25 °C) — — 1.24 — V —
Temperature sensor start time tSTART — — 30 µs —
Sampling time — 4.15 — — µs —
2.8 OSC Stop Detect Characteristics

Table 2.40 Oscillation stop detection circuit characteristics
Detection time tdr — — 1 ms Figure 2.55
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Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 2.55 Oscillation stop detection timing
2.9 POR and LVD Characteristics

Table 2.41 Power-on reset circuit and voltage detection circuit characteristics (1)
Un
Parameter Symbol Min Typ Max it Test conditions
Voltage detection Power-on reset DPSBYCR.DEEPCUT[1:0] = 00b or VPOR 2.5 2.6 2.7 V Figure 2.56
level (POR) 01b.
DPSBYCR.DEEPCUT[1:0] = 11b. 1.8 2.25 2.7
Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.57
Vdet0_2 2.77 2.87 2.97
Vdet0_3 2.70 2.80 2.90
Vdet1_2 2.82 2.92 3.02
Vdet1_3 2.75 2.85 2.95
Vdet2_2 2.82 2.92 3.02
Vdet2_3 2.75 2.85 2.95
Internal reset time Power-on reset time tPOR — 4.5 — ms Figure 2.56
LVD0 reset time tLVD0 — 0.51 — Figure 2.57
Minimum VCC down time*1 tVOFF 200 — — µs Figure 2.56,

Figure 2.57
Response delay tdet — — 200 µs Figure 2.57 to
Figure 2.59
LVD operation stabilization time (after LVD is enabled) td(E-A) — — 10 µs Figure 2.58,
Figure 2.59
Hysteresis width (LVD1 and LVD2) VLVH — 70 — m
V
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for POR and LVD.
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tVOFF
VPOR
VCC

(active-low)
tdet tPOR tdet tdet tPOR
Figure 2.56 Power-on reset timing
tVOFF
VCC Vdet0 VLVH

(active-low)
tdet tdet tLVD0
Figure 2.57 Voltage detection circuit timing (Vdet0)
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tVOFF
VCC Vdet1 VLVH
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
(active-low)
When LVD1CR0.RN = 0
tdet tdet tLVD1
When LVD1CR0.RN = 1
tLVD1
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tVOFF
VCC Vdet2 VLVH
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
(active-low)
When LVD2CR0.RN = 0
tdet tdet tLVD2
When LVD2CR0.RN = 1
tLVD2
2.10 VBATT Characteristics

Table 2.42 Battery backup function characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.65 to 3.6 V*1
Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.60
Lower-limit VBATT voltage for power supply VBATTSW 2.70 — — V

switching caused by VCC voltage drop
VCC-off period for starting power supply tVOFFBATT 200 — — µs
switching
VBATT low voltage detection level Vbattldet 1.8 1.9 2.0 V Figure 2.61
Minimum VBATT down time tBATTOFF 200 — — µs
Response delay tBATTdet — — 200 µs
VBATT monitor operation stabilization time td(E-A) — — 20 µs

(after VBATTMNSELR.VBATTMNSEL is
changed to 1)
VBATT current increase (when IVBATTSEL — 140 350 nA
VBATTMNSELR.VBATTMNSEL is 1 compared
to the case that VBATTMNSELR.VBATTMNSEL
is 0)
Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage
level for switching to battery backup (VDETBATT).
Note 1. Low CL crystal cannot be used below VBATT = 1.8 V.
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tVOFFBATT
VDETBATT
VCC
VBATT VBATTSW
Backup power
VCC supply VBATT supply VCC supply
area
Figure 2.60 Battery backup function characteristics
tBATTOFF
Vbattldet
VBATT
td(E-A)
VBATTMON
tBATTdet tBATTdet
VBATTMNSEL
Figure 2.61 Battery backup function characteristics
2.11 CTSU Characteristics

Table 2.43 CTSU characteristics
External capacitance connected to TSCAP pin Ctscap 9 10 11 nF —
TS pin capacitive load Cbase — — 50 pF —
Permissible output high current ΣIoH — — -40 mA When the mutual capacitance
method is applied
2.12 Flash Memory Characteristics
2.12.1 Code Flash Memory Characteristics

Table 2.44 Code flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz
Test
Parameter Symbol Min Typ*6 Max Min Typ*6 Max Unit conditions
Programming time 128-byte tP128 — 0.75 13.2 — 0.34 6.0 ms

NPEC ≤ 100 times
8-KB tP8K — 49 176 — 22 80 ms
32-KB tP32K — 194 704 — 88 320 ms
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Table 2.44 Code flash memory characteristics (2 of 2)

Test
Programming time 128-byte tP128 — 0.91 15.8 — 0.41 7.2 ms

NPEC > 100 times
8-KB tP8K — 60 212 — 27 96 ms
32-KB tP32K — 234 848 — 106 384 ms
Erasure time 8-KB tE8K — 78 216 — 43 120 ms

NPEC ≤ 100 times
32-KB tE32K — 283 864 — 157 480 ms
Erasure time 8-KB tE8K — 94 260 — 52 144 ms

NPEC > 100 times
32-KB tE32K — 341 1040 — 189 576 ms
Reprogramming/erasure cycle*4 NPEC 10000*1 — — 10000*1 — — Times
Suspend delay during programming tSPD — — 264 — — 120 µs
Programming resume time tPRT — — 110 — — 50 µs
First suspend delay during erasure in suspend tSESD1 — — 216 — — 120 µs

priority mode
Second suspend delay during erasure in suspend tSESD2 — — 1.7 — — 1.7 ms
priority mode
Suspend delay during erasure in erasure priority tSEED — — 1.7 — — 1.7 ms
mode
First erasing resume time during erasure in suspend tREST1 — — 1.7 — — 1.7 ms
priority mode*5
Second erasing resume time during erasure in tREST2 — — 144 — — 80 µs
suspend priority mode
Erasing resume time during erasure in erasure tREET — — 144 — — 80 µs
priority mode
Forced stop command tFD — — 32 — — 20 µs
Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3V and room temperature.
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• Suspension during programming
FACI command Program Suspend Resume
tSPD
FSTATR.FRDY Ready Not Ready Ready
tPRT
Programming pulse Programming Programming
• Suspension during erasure in suspend priority mode
FACI command Erase Suspend Resume Suspend Resume
tSESD1 tSESD2
FSTATR.FRDY Ready Not Ready Ready Not Ready Ready Not Ready
tREST1
tREST2
Erasure pulse Erasing Erasing Erasing
• Suspension during erasure in erasure priority mode
FACI command Erase Suspend Resume
tSEED
FSTATR.FRDY Ready Not Ready Ready Not Ready
tREET
Erasure pulse Erasing Erasing
• Forced Stop
FACI command Forced Stop
tFD
FSTATR.FRDY Not Ready Ready
Figure 2.62 Suspension and forced stop timing for flash memory programming and erasure
2.12.2 Data Flash Memory Characteristics

Table 2.45 Data flash memory characteristics (1 of 2)
Test
Programming time 4-byte tDP4 — 0.36 3.8 — 0.16 1.7 ms
8-byte tDP8 — 0.38 4.0 — 0.17 1.8
16-byte tDP16 — 0.42 4.5 — 0.19 2.0
Erasure time 64-byte tDE64 — 3.1 18 — 1.7 10 ms
128-byte tDE128 — 4.7 27 — 2.6 15
256-byte tDE256 — 8.9 50 — 4.9 28
Blank check time 4-byte tDBC4 — — 84 — — 30 µs
Reprogramming/erasure cycle*1 NDPEC 125000*2 — — 125000*2 — — —
Suspend delay during programming 4-byte tDSPD — — 264 — — 120 µs

8-byte — — 264 — — 120
16-byte — — 264 — — 120
Programming resume time tDPRT — — 110 — — 50 µs
First suspend delay during erasure in 64-byte tDSESD1 — — 216 — — 120 µs

128-byte — — 216 — — 120
256-byte — — 216 — — 120
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Table 2.45 Data flash memory characteristics (2 of 2)

Test
Second suspend delay during erasure in 64-byte tDSESD2 — — 300 — — 300 µs

128-byte — — 390 — — 390
256-byte — — 570 — — 570
Suspend delay during erasing in erasure 64-byte tDSEED — — 300 — — 300 µs
priority mode
128-byte — — 390 — — 390
256-byte — — 570 — — 570
First erasing resume time during erasure in suspend tDREST1 — — 300 — — 300 µs
priority mode*5
Second erasing resume time during erasure in tDREST2 — — 126 — — 70 µs
Erasing resume time during erasure in erasure tDREET — — 126 — — 70 µs
priority mode
Forced stop command tFD — — 32 — — 20 µs
Data hold time*3 tDRP 10*3 *4 — — 10*3 *4 — — Year
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.
the minimum value.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3 V and room temperature.
2.12.3 Option Setting Memory Characteristics

Table 2.46 Option setting memory characteristics
Conditions: Program: FCLK = 4 to 50 MHz
Parameter Symbol Min Typ*4 Max Min Typ*4 Max Unit Test conditions
Programming time tOP — 83 309 — 45 162 ms

NOPC ≤ 100 times
Programming time tOP — 100 371 — 55 195 ms

NOPC > 100 times
Reprogramming cycle NOPC 20000*1 — — 20000*1 — — Times
Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years
the minimum value.
Note 4. The reference value at VCC = 3.3 V and room temperature.
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2.13 Boundary Scan

Table 2.47 Boundary scan characteristics
TCK clock cycle time tTCKcyc 100 — — ns Figure 2.63
TCK clock high pulse width tTCKH 45 — — ns
TCK clock low pulse width tTCKL 45 — — ns
TCK clock rise time tTCKr — — 5 ns
TCK clock fall time tTCKf — — 5 ns
TMS setup time tTMSS 20 — — ns Figure 2.64
TMS hold time tTMSH 20 — — ns
TDI setup time tTDIS 20 — — ns
TDI hold time tTDIH 20 — — ns
TDO data delay tTDOD — — 40 ns
Boundary scan circuit startup time*1 TBSSTUP tRESWP — — — Figure 2.65
Note 1. Boundary scan does not function until the power-on reset becomes negative.
tTCKcyc
tTCKH
TCK tTCKf
tTCKr
tTCKL
Figure 2.63 Boundary scan TCK timing
TCK
tTMSS tTMSH
TMS
tTDIS tTDIH
TDI
tTDOD
TDO
Figure 2.64 Boundary scan input/output timing
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VCC
RES
tBSSTUP Boundary scan

(= tRESWP) execute
Figure 2.65 Boundary scan circuit startup timing
2.14 Joint Test Action Group (JTAG)

Table 2.48 JTAG
TCK clock cycle time tTCKcyc 40 — — ns Figure 2.66
TCK clock high pulse width tTCKH 15 — — ns
TCK clock low pulse width tTCKL 15 — — ns
TCK clock rise time tTCKr — — 5 ns
TCK clock fall time tTCKf — — 5 ns
TMS setup time tTMSS 8 — — ns Figure 2.67
TMS hold time tTMSH 8 — — ns
TDI setup time tTDIS 8 — — ns
TDI hold time tTDIH 8 — — ns
TDO data delay time tTDOD — — 20 ns
tTCKcyc
tTCKH
TCK tTCKf
tTCKr
tTCKL
Figure 2.66 JTAG TCK timing
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TCK
tTMSS tTMSH
TMS
tTDIS tTDIH
TDI
tTDOD
TDO
Figure 2.67 JTAG input/output timing
2.15 Serial Wire Debug (SWD)

Table 2.49 SWD
SWCLK clock cycle time tSWCKcyc 40 — — ns Figure 2.68
SWCLK clock high pulse width tSWCKH 15 — — ns
SWCLK clock low pulse width tSWCKL 15 — — ns
SWCLK clock rise time tSWCKr — — 5 ns
SWCLK clock fall time tSWCKf — — 5 ns
SWDIO setup time tSWDS 8 — — ns Figure 2.69
SWDIO hold time tSWDH 8 — — ns
SWDIO data delay time tSWDD 2 — 28 ns
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tSWCKcyc
tSWCKH
SWCLK
tSWCKL
Figure 2.68 SWD SWCLK timing
SWCLK
tSWDS tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.69 SWD input/output timing
2.16 Embedded Trace Macro Interface (ETM)

Table 2.50 ETM (1 of 2)
Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
TCLK clock cycle time tTCLKcyc 40 — — ns Figure 2.70
TCLK clock high pulse width tTCLKH 17 — — ns
TCLK clock low pulse width tTCLKL 17 — — ns
TCLK clock rise time tTCLKr — — 3 ns
TCLK clock fall time tTCLKf — — 3 ns
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Table 2.50 ETM (2 of 2)

Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
TDATA[3:0] output setup time tTRDS 3.5 — — ns Figure 2.71
TDATA[3:0] output hold time tTRDH 2.5 — — ns
tTCLKcyc
tTCLKH
TCLK tTCLKf
tTCLKr
tTCLKL
Figure 2.70 ETM TCLK timing
TCLK
tTRDS tTRDH tTRDS tTRDH
TDATA[3:0]
Figure 2.71 ETM output timing
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RA4M2 Datasheet Appendix 1. Port States in Each Processing Mode
Appendix 1. Port States in Each Processing Mode

After Deep Software Standby
mode is canceled (return to
startup mode)
Deep Software
Function Pin function Reset Software Standby mode Standby mode IOKEEP = 0 IOKEEP = 1*1
Mode MD Pull-up Keep-O Keep Hi-Z Keep
JTAG TCK/TMS/TDI Pull-up Keep-O Keep Hi-Z Keep
TDO output Keep-O Keep TDO output Keep
IRQ IRQx Hi-Z Keep-O*2 Keep Hi-Z Keep
IRQx-DS Hi-Z Keep-O*2 Keep*3 Hi-Z Keep
AGT AGTIOn Hi-Z Keep-O*2 Keep Hi-Z Keep
AGTIOn (n=1,3) Hi-Z Keep-O*2 Keep*3 Hi-Z Keep
SCI RXD0 Hi-Z Keep-O*2 Keep Hi-Z Keep
IIC SCLn/SDAn Hi-Z Keep-O*2 Keep Hi-Z Keep
USBFS USB_OVRCURx Hi-Z Keep-O*2 Keep Hi-Z Keep
USB_OVRCURx-DS/ Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

USB_VBUS
USB_DP/USB_DM Hi-Z Keep-O*4 Keep*3 Hi-Z Keep
RTC RTCICx Hi-Z Keep-O*2 Keep*3 Hi-Z Keep
RTCOUT Hi-Z [RTCOUT selected] RTCOUT output Keep Hi-Z Keep
CLKOUT CLKOUT Hi-Z [CLKOUT selected] CLKOUT output Keep Hi-Z Keep
DAC DAn Hi-Z [DAn output (DAOE = 1)] D/A output retained Keep Hi-Z Keep
Others — Hi-Z Keep-O Keep Hi-Z Keep
Note: H: High-level
L: Low-level
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins go to high-impedance.
Keep: Pin states are retained during periods in Software Standby mode.
Note 1. Retains the I/O port state until the DPSBYCR.IOKEEP bit is cleared to 0.
Note 2. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Note 3. Input is enabled if the pin is specified as the Deep Software Standby canceling source.
Note 4. Input is enabled while the pin is used as an input pin.
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RA4M2 Datasheet Appendix 2. Package Dimensions
Appendix 2. Package Dimensions

Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6
HD
Unit: mm
*1 D
75 51
76 50
HE
E
*2
100
26
1 25 NOTE 4
Index area NOTE)
NOTE 3 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
F
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
S
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters

y S Symbol
*3 Min Nom Max
e bp
M
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2  1.4 
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
0.25
A   1.7
A2
A
A1 0.05  0.15

bp 0.15 0.20 0.27

A1
c 0.09  0.20
Lp
 0 3.5 8
L1
e  0.5 
Detail F
x   0.08
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.1 LQFP 100-pin
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P-LFQFP64-10x10-0.50 PLQP0064KB-C — 0.3
Unit: mm
HD
*1 D
48 33
49 32
*2 E
HE
64
17
1 16 NOTE 4
Index area
NOTE 3
F NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
S 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
y S
*3
bp Reference Dimensions in millimeters
e
M Symbol
Min Nom Max
D 9.9 10.0 10.1
E 9.9 10.0 10.1
A2  1.4 
HD 11.8 12.0 12.2
HE 11.8 12.0 12.2
0.25
A   1.7
A2
A
A1 0.05  0.15

bp 0.15 0.20 0.27

A1
c 0.09  0.20
Lp  0 3.5 8
L1
e  0.5 
Detail F
x   0.08
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 
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P-LFQFP48-7x7-0.50 PLQP0048KB-B — 0.2
HD
Unit: mm
*1 D
36 25
37 24
HE
E
*2
48
13
1 12 NOTE 4
Index area NOTE)
NOTE 3 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
F
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
S
Reference Dimensions in millimeters
Symbol
Min Nom Max
D 6.9 7.0 7.1
y S *3
e bp E 6.9 7.0 7.1
M
A2  1.4 
HD 8.8 9.0 9.2
HE 8.8 9.0 9.2
A   1.7
0.25
A1 0.05  0.15
A2
A
bp 0.17 0.20 0.27


c 0.09  0.20
A1
 0 3.5 8
Lp
L1 e  0.5 
x   0.08
Detail F
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 
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JEITA Package code RENESAS code MASS(TYP.)[g]
P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g
2X
aaa C
36 25
37 24
INDEX AREA
(D/2 X E/2)
48 13
2X
aaa C
1 12
B E A
ccc C
C
SEATING PLANE
A (A3) A1
e b(48X) bbb C A B
48X
ddd C
eee C Dimension in Millimeters
Reference
Symbol
E2 fff C A B Min. Nom. Max.
1 12 A －－ 0.80
EXPOSED A1 0.00 0.02 0.05
fff C A B 48 13 DIE PAD
A3 0.203 REF.
b 0.20 0.25 0.30
D 7.00 BSC
E 7.00 BSC
D2 e 0.50 BSC
L 0.30 0.40 0.50
K 0.20 －－
D2 5.25 5.30 5.35
24 E2 5.25 5.30 5.35
37
aaa 0.15
36 25
bbb 0.10
L(48X) K(48X)
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Figure 2.4 QFN 48-pin
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RA4M2 Datasheet Appendix 3. I/O Registers
Appendix 3. I/O Registers

This appendix describes I/O register address and access cycles by function.
3.1 Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual. Table 3.1 shows the name, description,
and the base address of each peripheral.
Table 3.1 Peripheral base address (1 of 2)
Name Description Base address
RMPU Renesas Memory Protection Unit 0x4000_0000

TZF TrustZone Filter 0x4000_0E00
SRAM SRAM Control 0x4000_2000
BUS BUS Control 0x4000_3000
DMAC0 Direct memory access controller 0 0x4000_5000
DMAC3 Direct memory access controller 3 0x4000_50C0
DMAC7 Direct memory access controller 7 0x4000_51C0
DMA DMAC Module Activation 0x4000_5200
DTC Data Transfer Controller 0x4000_5400
ICU Interrupt Controller 0x4000_6000
CPSCU CPU System Security Control Unit 0x4000_8000
DBG Debug Function 0x400_1B000
FCACHE Flash Cache 0x400_1C100
SYSC System Control 0x4001_E000
PORT0 Port 0 Control Registers 0x4008_0000
PORT5 Port 5 Control Registers 0x4008_00A0
PORT6 Port 6 Control Registers 0x4008_00C0
PORT7 Port 7 Control Registers 0x4008_00E0
PFS Pmn Pin Function Control Register 0x4008_0800
ELC Event Link Controller 0x4008_2000
RTC Realtime Clock 0x4008_3000
IWDT Independent Watchdog Timer 0x4008_3200
WDT Watchdog Timer 0x4008_3400
CAC Clock Frequency Accuracy Measurement Circuit 0x4008_3600
MSTP Module Stop Control A, B, C, D 0x4008_4000
POEG Port Output Enable Module for GPT 0x4008_A000
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Table 3.1 Peripheral base address (2 of 2)

Name Description Base address
USBFS USB 2.0 FS Module 0x4009_0000

SDHI0 SD Host Interface 0 0x4009_2000
SSIE0 Serial Sound Interface Enhanced (SSIE) 0x4009_D000
IIC0 Inter-Integrated Circuit 0 0x4009_F000
IIC0WU Inter-Integrated Circuit 0 Wake-up Unit 0x4009_F014
IIC1 Inter-Integrated Circuit 1 0x4009_F100
CAN0 CAN0 Module 0x400A_8000
CTSU Capacitive Touch Sensing Unit 0x400D_0000
PSCU Peripheral Security Control Unit 0x400E_0000
AGT0 Low Power Asynchronous General purpose Timer 0 0x400E_8000
TSN Temperature Sensor 0x400F_3000
CRC CRC Calculator 0x4010_8000
DOC Data Operation Circuit 0x4010_9000
SCI0 Serial Communication Interface 0 0x4011_8000
SPI0 Serial Peripheral Interface 0 0x4011_A000
SCE9 Secure Cryptographic Engine 0x4016_1000
GPT320 General PWM 32-Bit Timer 0 0x4016_9000
GPT_OPS Output Phase Switching Controller 0x4016_9A00
ADC120 12bit A/D Converter 0 0x4017_0000
DAC12 12-bit D/A converter 0x4017_1000
FLAD Data Flash 0x407F_C000
FACI Flash Application Command Interface 0x407F_E000
QSPI Quad-SPI 0x6400_0000
Note: Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
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3.2 Access Cycles

This section provides access cycle information for the I/O registers described in this manual.
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.
Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus masters such as DTC or DMAC.
Table 3.2 Access cycles (1 of 3)

Number of access cycles
Address ICLK = PCLK ICLK > PCLK*1

Cycle
Peripherals From To Read Write Read Write Unit Related function
RMPU, TZF, 0x4000_0000 0x4000_6FFF 2 2 2 2 ICLK Renesas Memory

SRAM, BUS, Protection Unit,
DMACn, DMA, TrustZone Filter,
DTC, ICU SRAM Control, BUS
Control, Direct
memory access
controller n, DMAC
Module Activation,
DTC Control Register,
Interrupt Controller
CPSCU, DBG, 0x4000_8000 0x4001_CFFF 4 3 4 3 ICLK CPU System Security

FCACHE Control Unit, Debug
Function, Flash Cache
SYSC 0x4001_E000 0x4001_E3FF 5 4 5 4 ICLK System Control
SYSC 0x4001_E400 0x4001_E5FF 9 8 5 to 8 5 to 8 PCLKB System Control
PORTn, PFS 0x4008_0000 0x4008_0FFF 5 4 2 to 5 2 to 4 PCLKB Port n Control

Registers, Pmn Pin
Function Control
Register
ELC, RTC, IWDT, 0x4008_2000 0x4008_3FFF 5 4 3 to 5 2 to 4 PCLKB Event Link Controller,

WDT, CAC Realtime Clock,
Independent
Watchdog Timer,
Watchdog Timer,
Clock Frequency
Accuracy
Measurement Circuit
MSTP 0x4008_4000 0x4008_4FFF 5 4 2 to 5 2 to 4 PCLKB Module Stop Control
POEG 0x4008_A000 0x4008_AFFF 5 4 3 to 5 2 to 4 PCLKB Port Output Enable

Module for GPT
USBFS 0x4009_0000 0x4009_03FF 6 5 3 to 6 3 to 5 PCLKB USB 2.0 FS Module
USBFS 0x4009_0400 0x4009_04FF 4 3 1 to 4 1 to 3 PCLKB USB 2.0 FS Module
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Address ICLK = PCLK ICLK > PCLK*1

Cycle
SDHI0, SSIE0, 0x4009_2000 0x4009_FFFF 5 4 2 to 5 2 to 4 PCLKB SD Host Interface 0,

IICn, IIC0WU Serial Sound Interface
Enhanced, Inter-
Integrated Circuit n,
Inter-Integrated Circuit
0 Wake-up Unit
CANn 0x400A_8000 0x400A_9FFF 5 4 2 to 5 2 to 4 PCLKB CANn Module
CTSU 0x400D_0000 0x400D_FFFF 4 3 1 to 4 1 to 3 PCLKB Capacitive Touch

Sensing Unit
PSCU 0x400E_0000 0x400E_0FFF 5 4 2 to 5 2 to 4 PCLKB Peripheral Security

Control Unit
AGTn 0x400E_8000 0x400E_8FFF 7 4 5 to 7 2 to 4 PCLKB Low Power

Asynchronous
General purpose
Timer n
TSN 0x400F_3000 0x400F_3FFF 5 4 2 to 5 2 to 4 PCLKB Temperature Sensor
CRC, DOC 0x4010_8000 0x4010_9FFF 5 4 2 to 5 2 to 4 PCLKA CRC Calculator, Data

Operation Circuit
SCIn 0x4011_8000 0x4011_8FFF 5*2 4*2 2 to 5*2 2 to 4*2 PCLKA Serial Communication
Interface n
SPIn 0x4011_A000 0x4011_AFFF 5*3 4*3 2 to 5*3 2 to 4*3 PCLKA Serial Peripheral
Interface n
SCE9 0x4016_1000 0x4016_1FFF 6 4 3 to 6 2 to 4 PCLKA Secure Cryptographic

Engine
GPT32n, GPT16n, 0x4016_9000 0x4016_9FFF 7 4 4 to 7 2 to 4 PCLKA General PWM 32-Bit

GPT_OPS Timer n, General
PWM 16-Bit Timer n,
Output Phase
Switching Controller
ADC12n, DAC12 0x4017_0000 0x4017_2FFF 5 4 2 to 5 2 to 4 PCLKA 12bit A/D Converter n,

12-bit D/A converter
QSPI 0x6400_0000 0x6400_000F 5 14 to *4 2 to 5 14 to *4 PCLKA Quad-SPI
QSPI 0x6400_0010 0x6400_0013 25 to *4 6 to *4 25 to *4 5 to *4 PCLKA Quad-SPI
QSPI 0x6400_0014 0x6400_0037 5 14 to *4 2 to 5 14 to *4 PCLKA Quad-SPI
QSPI 0x6400_0804 0x6400_0807 4 3 1 to 4 1 to 3 PCLKA Quad-SPI

Address ICLK = FCLK ICLK > FCLK*1

Cycle
FLAD, FACI 0x407F_C000 0x407F_EFFF 3 3 2 to 3 2 to 3 FCLK Data Flash, Flash

Application Command
Interface
Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the
maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in
Table 3.2.
Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table 3.2.
Note 4. The access cycles depend on the QSPI bus cycles.
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RA4M2 Datasheet Revision History
Revision History
Revision 1.00 — Aug 28, 2020
First edition, issued
Revision 1.10 — Jan 27, 2021

1. Overview:
● Added note to Figure 1.1 Block diagram.
● Changed pin name in Table 1.15 Pin functions.
2. Electrical Characteristics:
● Added information about supported functions and pins.
● Changed LDO to LDOn in Table 2.7 Operating and standby current.
● added Note 15 to PLL2-LDO operating current in Table 2.7 Operating and standby current.
● Removed ADTRG1 in Figure 2.25 ADC12 trigger input timing.
Revision 1.20 — May 31, 2023

1. Overview:
● Fixed 1.1 Function Outline.
● Fixed 1.3 Part Numbering.
● Fixed 1.5 Pin Functions.
● Fixed 1.6 Pin Assignments.
● Fixed 2.2.1 Tj/Ta Definition.
● Fixed Table 2.7 Operating and standby current.
Appendix 3. I/O Registers:
● Fixed Table 3.2 Access cycles.
Revision 1.30 — Jul 28, 2023

1. Overview:
● Fixed Figure 1.2 Part numbering scheme.
● Fixed Table 2.6 I/O VOH, VOL, and other characteristics.
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General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
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Ra4m2 Group Datasheet

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RA4M2 Group R01DS0367EJ0130

■ Security and Encryption

■ System and Power Management

R01DS0367EJ0130 Rev.1.30 Page 1 of 93

1.1 Function Outline

Arm Cortex-M33 core ● Maximum operating frequency: up to 100 MHz

Table 1.2 Memory

Code flash memory Maximum 512 KB of code flash memory.

Table 1.3 System (1 of 2)

Operating modes Two operating modes:

R01DS0367EJ0130 Rev.1.30 Page 2 of 93

Table 1.3 System (2 of 2)

Clocks ● Main clock oscillator (MOSC)

Table 1.4 Event link

Table 1.5 Direct memory access

Table 1.6 External bus interface

Table 1.7 Timers (1 of 2)

R01DS0367EJ0130 Rev.1.30 Page 3 of 93

Table 1.7 Timers (2 of 2)

Table 1.8 Communication interfaces (1 of 2)

R01DS0367EJ0130 Rev.1.30 Page 4 of 93

Table 1.8 Communication interfaces (2 of 2)

Table 1.9 Analog

Table 1.10 Human machine interfaces

Table 1.11 Data processing

R01DS0367EJ0130 Rev.1.30 Page 5 of 93

Table 1.12 I/O ports

Programmable I/O ports ● I/O ports for the 100-pin LQFP

R01DS0367EJ0130 Rev.1.30 Page 6 of 93

1.2 Block Diagram

Memory Bus Arm Cortex-M33 System

512 KB code flash MPU DSP FPU POR/LVD Clocks

DMA System timer

Timers Communication interfaces Human machine interfaces

GPT32 x 4 SCI × 6 QSPI CTSU

Event link Data processing Analog

Security DOC DAC12 × 2

Note: Not available on all parts.

Figure 1.1 Block diagram

1.3 Part Numbering

R01DS0367EJ0130 Rev.1.30 Page 7 of 93

Code flash memory size

Figure 1.2 Part numbering scheme

Table 1.13 Product list (1 of 2)

R7FA4M2AD3CFP PLQP0100KB-B 512 KB 8 KB 128 KB -40 to +105°C

R01DS0367EJ0130 Rev.1.30 Page 8 of 93

Table 1.13 Product list (2 of 2)

R7FA4M2AB3CFP PLQP0100KB-B 256 KB 8 KB 128 KB -40 to +105°C

R01DS0367EJ0130 Rev.1.30 Page 9 of 93

1.4 Function Comparison

Pin count 100 64 48 48

R01DS0367EJ0130 Rev.1.30 Page 10 of 93

Table 1.14 Function Comparison (2 of 2)

I/O ports I/O pins 77 43 29

R01DS0367EJ0130 Rev.1.30 Page 11 of 93

1.5 Pin Functions

R01DS0367EJ0130 Rev.1.30 Page 12 of 93

Table 1.15 Pin functions (2 of 4)