Scribd Logo
Upload

Welcome to Scribd!

  • 5 views

    Tong Hop

    Uploaded by

    22119064

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Tong Hop

    Uploaded by

    22119064
    5 views12 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    5 views12 pages

    Tong Hop

    Uploaded by

    22119064

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 12

    1.

    Đếm 0-59 hiển thị trên led 7 đoạn


     Thiết kế logic

     Mô tả phần cứng
    module counterchuc
    #(parameter M=50000)
    ( input clki, rs,
    output wire [3:0] q);
    wire [3:0] r_next;
    reg [3:0] r_reg ;
    always @(posedge clki,posedge rs)
    if (rs)
    r_reg <=0;
    else
    r_reg <= r_next;
    assign r_next = r_reg+1;
    assign q = r_reg;
    endmodule

    module counterdv
    #(parameter M=50000)
    ( input clki, rs,
    output wire [3:0] q);
    wire [3:0] r_next;
    reg [3:0] r_reg ;
    always @(posedge clki,posedge rs)
    if (rs)
    r_reg <=0;
    else
    r_reg <= r_next;
    assign r_next = r_reg+1;
    assign q = r_reg;
    endmodule

    module led7doandv( input wire [3:0]S,


    output reg [6:0]Y
    );
    always @(*) begin
    case(S)
    4'd0 : Y = 7'b0111111;
    4'd1 : Y = 7'b0000110;
    4'd2 : Y = 7'b1011011;
    4'd3 : Y = 7'b1001111;
    4'd4 : Y = 7'b1100110;
    4'd5 : Y = 7'b1101101;
    4'd6 : Y = 7'b1111101;
    4'd7 : Y = 7'b0000111;
    4'd8 : Y = 7'b1111111;
    4'd9 : Y = 7'b1101111;
    default : Y = 4'b0000;
    endcase

    end
    endmodule

    module led7doanchuc(
    input wire [3:0]S,
    output reg [6:0]Y
    );
    always @(*) begin
    case(S)
    4'd0 : Y = 7'b0111111;
    4'd1 : Y = 7'b0000110;
    4'd2 : Y = 7'b1011011;
    4'd3 : Y = 7'b1001111;
    4'd4 : Y = 7'b1100110;
    4'd5 : Y = 7'b1101101;
    4'd6 : Y = 7'b1111101;
    4'd7 : Y = 7'b0000111;
    4'd8 : Y = 7'b1111111;
    4'd9 : Y = 7'b1101111;
    default : Y = 4'b0000;
    endcase
    end
    endmodule

     Test bench
    module test;

    // Inputs
    reg ck;
    reg rs;

    // Outputs
    wire [6:0] a;
    wire [6:0] b;

    // Instantiate the Unit Under Test (UUT)


    dem0_59 uut (
    .ck(ck),
    .rs(rs),
    .a(a),
    .b(b)
    );

    initial begin
    // Initialize Inputs
    ck = 0;
    rs = 0;

    // Wait 100 ns for global reset to finish


    #10;
    rs=1;
    #10;
    rs=0;

    // Add stimulus here

    end
    always begin
    #10;
    ck = ~ck;
    end

    endmodule

     Mô phỏng
    2. Hiển thị đồng hồ số (giờ-phút-giây)
     Thiết kế logic
     Mô tả phần cứng

    module clockDiv
    #(parameter M=50000)
    (
    input clki,
    output clko);
    wire [30:0] r_next;
    reg [30:0] r_reg ;
    initial r_reg =0;
    always @(posedge clki)
    r_reg <=r_next;
    assign r_next =(r_reg==M)?0:r_reg+1;
    assign clko = (r_reg<=M/2)?0:1 ;
    endmodule

    module Counter(
    input wire clk,rs,
    output wire [7:0] q
    );
    wire [7:0] r_next ;
    reg [7:0] r_reg;
    initial r_reg =0 ;
    always @(posedge clk,posedge rs)
    if(rs)
    r_reg<=0;
    else
    r_reg <= r_next;
    assign r_next =(r_reg==8'b00111011)?0 :r_reg + 1 ;
    assign q=r_reg;
    endmodule

    module add(in,out);
    input [3:0] in;
    output [3:0] out;
    reg [3:0] out;
    always @ (in)
    case (in)
    4'b0000: out <= 4'b0000;
    4'b0001: out <= 4'b0001;
    4'b0010: out <= 4'b0010;
    4'b0011: out <= 4'b0011;
    4'b0100: out <= 4'b0100;
    4'b0101: out <= 4'b1000;
    4'b0110: out <= 4'b1001;
    4'b0111: out <= 4'b1010;
    4'b1000: out <= 4'b1011;
    4'b1001: out <= 4'b1100;
    default: out <= 4'b0000;
    endcase
    endmodule
    module HexBcd(
    input [7:0] hex,
    output wire [3:0] ones,
    output wire [3:0] tens
    );
    wire [3:0] c1,c2,c3,c4,c5,c6,c7;
    wire [3:0] d1,d2,d3,d4,d5,d6,d7;
    assign d1 = {1'b0,hex[7:5]};
    assign d2 = {c1[2:0],hex[4]};
    assign d3 = {c2[2:0],hex[3]};
    assign d4 = {c3[2:0],hex[2]};
    assign d5 = {c4[2:0],hex[1]};
    assign d6 = {1'b0,c1[3],c2[3],c3[3]};
    assign d7 = {c6[2:0],c4[3]};
    add t1(d1,c1);
    add1 t2(d2,c2);
    add1 t3(d3,c3);
    add1 t4(d4,c4);
    add1 t5(d5,c5);
    add1 t6(d6,c6);
    add1 t7(d7,c7);
    assign ones = {c5[2:0],hex[0]};
    assign tens = {c7[2:0],c5[3]};
    assign hundreds = {c6[3],c7[3]};
    endmodule

    module chinh(input clk,rs,


    output [3:0] ones1,tens1,
    output [3:0] ones2,tens2,
    output [3:0] ones3,tens3

    );
    wire cko;
    wire [7:0] q1,q2,q3;
    wire xung1,xung2,xung3,rst;
    clockDiv clock (clk, clko) ;
    Counter counter1 (clko,rst,q1 ) ;
    Counter counter2 (xung1,rst,q2 ) ;
    Counter counter3 (xung2,rst,q3 ) ;
    nor (xung1,q1[0],q1[1],q1[2],q1[3],q1[4],q1[5],q1[6],q1[7]);//0
    nor (xung2,q2[0],q2[1],q2[2],q2[3],q2[4],q2[5],q2[6],q2[7]);//0
    and(xung3,q3[4],q3[3]);
    or(rst,rs,xung3);

    HexBcd hex_bcd1 (q1,ones1,tens1);


    HexBcd hex_bcd2 (q2,ones2,tens2);
    HexBcd hex_bcd3 (q3,ones3,tens3);

    endmodule

     Test bench
    module thu1;

    // Inputs
    reg clk;
    reg rs;

    // Outputs
    wire [3:0] ones1;
    wire [3:0] tens1;
    wire [3:0] ones2;
    wire [3:0] tens2;
    wire [3:0] ones3;
    wire [3:0] tens3;

    // Instantiate the Unit Under Test (UUT)


    chinh uut (
    .clk(clk),
    .rs(rs),
    .ones1(ones1),
    .tens1(tens1),
    .ones2(ones2),
    .tens2(tens2),
    .ones3(ones3),
    .tens3(tens3)
    );

    initial begin
    // Initialize Inputs
    clk = 0;
    rs = 0;

    // Wait 100 ns for global reset to finish

    #10;
    rs=1;
    #10;
    rs=0;

    // Add stimulus here

    end

    always begin
    #10;
    clk=~clk;
    end

    endmodule
     Mô phỏng

    You might also like