V32G410x Datasheet

V32G410x
Datasheet
Contents V32G410x Datasheet
Contents
1 Introduction ............................................................................................... 12
2 Description ................................................................................................. 13
2.1 Device overview ................................................................................ 13
2.2 Overview .......................................................................................... 14
2.2.1 ARM® Cortex®-M4F with FPU core and DSP instruction set ........ 14
2.2.2 Memory protection unit (MPU) ................................................. 15
2.2.3 Flash memory ....................................................................... 16
2.2.4 Cyclic redundancy check (CRC) calculation unit ......................... 16
2.2.5 Embedded SRAM ................................................................... 16
2.2.6 Nested vectored interrupt controller (NVIC) .............................. 16
2.2.7 External interrupt/event controller (EXTI) ................................. 17
2.2.8 Clocks and startup ................................................................. 17
2.2.9 Boot modes........................................................................... 18
2.2.10 Power supply schemes............................................................ 19
2.2.11 Power supply supervisor ......................................................... 19
2.2.12 Voltage regulator ................................................................... 19
2.2.13 Low-power modes .................................................................. 19
2.2.14 Direct Memory Access Controller (DMA) .................................... 20
2.2.15 Real-time clock (RTC) and backup registers .............................. 20
2.2.16 Timers and watchdogs (TMR/WDG) .......................................... 21
2.2.17 Inter-integrated-circuit interface (I2C) ..................................... 23
2.2.18 Universal synchronous/asynchronous receiver transmitters (USART)

23
2.2.19 Serial peripheral interface (SPI) ............................................... 24
2.2.20 Inter-integrated sound interface (I2S) ...................................... 25
2.2.21 Controller area network (CAN)................................................. 25
2.2.22 General-purpose inputs/outputs (GPIO) .................................... 25
2.2.23 Remap capability ................................................................... 25
2.2.24 Analog to digital converter (ADC) ............................................. 25
2.2.25 Temperature sensor ............................................................... 26
2.2.26 Serial wire JTAG debug port (SWJ-DP)...................................... 26
Vango Technologies, Inc. 2 / 84

3 Pinouts and pin descriptions ...................................................................... 27
4 Memory mapping ........................................................................................ 44
5 Electrical characteristics............................................................................. 45
5.1 Parameter conditions ......................................................................... 45
5.1.1 Minimum and maximum values ............................................... 45
5.1.2 Typical values ....................................................................... 45
5.1.3 Typical curves ....................................................................... 45
5.1.4 Loading capacitor................................................................... 45
5.1.5 Pin input voltage .................................................................... 46
5.1.6 Power supply scheme ............................................................. 46
5.1.7 Current consumption measurement.......................................... 47
5.2 Absolute maximum ratings ................................................................. 48
5.3 Operating conditions .......................................................................... 49
5.3.1 General operating conditions ................................................... 49
5.3.2 Operating conditions at power-up/ power-down ......................... 49
5.3.3 Embedded reset and power control block characteristics ............. 49
5.3.4 Embedded reference voltage ................................................... 51
5.3.5 Supply current characteristics.................................................. 52
5.3.6 External clock source characteristics ........................................ 58
5.3.7 Internal clock source characteristics ......................................... 62
5.3.8 Wakeup time from low-power mode ......................................... 63
5.3.9 PLL characteristics ................................................................. 64
5.3.10 Memory characteristics ........................................................... 64
5.3.11 I/O port characteristics ........................................................... 65
5.3.12 NRST pin characteristics ......................................................... 66
5.3.13 TMR timer characteristics ........................................................ 67
5.3.14 Communications interfaces ..................................................... 67
5.3.15 12-bit ADC characteristics ....................................................... 74
5.3.16 Temperature sensor characteristics .......................................... 75
5.4 ESD electricial character ..................................................................... 76
6 stroage ....................................................................................................... 77
6.1 Hmidity sensitivity ............................................................................. 77
6.2 Storage conditions ............................................................................. 77

7 Reflow soldering process............................................................................ 78
8 Package information................................................................................... 79
8.1 LQFP100 14 x 14 mm package information ........................................... 79
8.2 LQFP64 10x10mm package information ................................................ 81
8.3 QFN48 7 x 7 mm package information.................................................. 82
8.4 Thermal characteristics ...................................................................... 83

List of Tables V32G410x Datasheet
List of Tables
Table1. Document Version History ............................................................................ 9
Table2. V32G410x series device function and configuration ................................... 13
Table3. The bootloader pin configurations .............................................................. 18
Table4. Timer feature comparison .......................................................................... 21
Table5. USART/UART feature comparison............................................................... 24
Table6. V32G410x series pin definitions ................................................................. 30
Table7. Voltage characteristics ............................................................................... 48
Table8. Current characteristics ............................................................................... 48
Table9. Thermal characteristics .............................................................................. 48
Table10. General operating conditions...................................................................... 49
Table11. Operating conditions at power-up / power-down ....................................... 49
Table12. Embedded reset and power control block characteristics ........................... 50
Table13. Embedded internal reference voltage ......................................................... 51
Table14. Typical Current Consumption in Operating Modes ...................................... 52
Table15. Typical Current Consumption in Sleep Mode ............................................... 53
Table16. Maximum Current Consumption in Operating Mode .................................... 54
Table17. Maximum Current Consumption in Sleep Mode ........................................... 55
Table18. Typical and Maximum Current Consumption in Shutdown and Standby

Modes ......................................................................................................... 55
Table19. Comparison of typical current consumption in standby mode with

temperature at different VDD ..................................................................... 56
Table20. Current Consumption of Built-in Peripherals .............................................. 57
Table21. High-speed external user clock characteristics........................................... 58
Table22. Low-speed external user clock characteristics ........................................... 59
Table23. HSE 4-25 MHz oscillator characteristics(1)(2) ............................................... 61
Table24. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) .................................... 61
Table25. HSI oscillator characteristics(1) .................................................................. 62

List of Tables V32G410x Datasheet
Table26. LSI oscillator characteristics(1) ................................................................... 63
Table27. Low-power mode wakeup timings .............................................................. 64
Table28. PLL characteristics ..................................................................................... 64
Table29. Internal Flash memory characteristics ....................................................... 64
Table30. Internal Flash memory endurance and data retention ................................ 65
Table31. I/O static characteristics............................................................................ 65
Table32. NRST pin characteristics ............................................................................. 66
Table33. TMRx(1) characteristics ............................................................................... 67
Table34. I2C characteristics ..................................................................................... 68
Table35. SCL frequency (fPCLK1 = 36 MHz, VDD = 3.3 V)(1)(2)...................................... 69
Table36. SPI characteristics ..................................................................................... 70
Table37. I2S characteristics ..................................................................................... 72
Table38. ADC Characteristics .................................................................................... 74
Table39. Temperature sensor characteristics ........................................................... 75
Table40. ESD electricial parameter ........................................................................... 76
Table41. MSL summary ............................................................................................. 77
Table42. Bagged storage conditions ......................................................................... 77
Table43. Reflow profile conditions ............................................................................ 78
Table44. Package thermal characteristics ................................................................. 83

List of Figures V32G410x Datasheet
List of Figure
Figure1. V32G410x block diagram............................................................................ 14
Figure2. Clock tree ................................................................................................... 17
Figure3. V32G410CGU7 QFN48 pinout ...................................................................... 27
Figure4. V32G410RGT7 LQFP64 pinout .................................................................... 28
Figure5. V32G410VUT7/ V32G410VGT7 LQFP100 pinout ......................................... 29
Figure6. Memory map............................................................................................... 44
Figure7. Pin loading conditions ................................................................................ 45
Figure8. Pin input voltage ........................................................................................ 46
Figure9. Power supply scheme ................................................................................. 46
Figure10. Power on reset/power down reset waveform ............................................ 51
Figure11. Typical Current Consumption in Shutdown Mode vs. Temperature at

Different VDD ............................................................................................. 56
Figure12. High-speed external clock source AC timing diagram ................................. 59
Figure13. Low-speed external clock source AC timing diagram .................................. 60
Figure14. Typical application with an 8 MHz crystal ................................................... 61
Figure15. Typical application with a 32.768 KHz crystal............................................. 62
Figure16. HSI oscillator frequency accuracy vs. Temperature .................................... 63
Figure17. Recommended NRST pin protection............................................................ 67
Figure18. I2C bus AC waveforms and measurement circuit(1) .................................... 68
Figure19. SPI timing diagram - slave mode and CPHA = 0 ......................................... 70
Figure20. SPI timing diagram - slave mode and CPHA = 1(1) ...................................... 71
(1)
Figure21. SPI timing diagram - master mode ......................................................... 71
Figure22. I2S slave timing diagram (Philips protocol)(1) ............................................ 72
Figure23. I2S master timing diagram (Philips protocol)(1) ......................................... 73
Figure24. VSENSE vs. temperature ................................................................................ 76
Figure25. A typical lead-free reflow mode .................................................................. 78
Figure26. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline ....... 79

List of Figures V32G410x Datasheet
Figure27. LQFP64 10x10mm 64 pin low-profile quad flat package outline ................. 81
Figure28. QFN48 – 7 x 7 mm 48 pin low-profile quad flat package outline ................. 82

Revision History V32G410x Datasheet
Revision History
Table1. Document Version History

Date Revision Description
2022.08.19 V1.2 Initial Version;
Add V32G410VGT7, and delete

2022.10.28 V1.3
V32G410CGUB,V32G410CGTB,V32G410RGT7
2023.01.09 V1.4 Delete V32G410LUT7
2023.02.17 V1.5 Add V32G410RGT7
Delete GPIO open drain output and input pull-up
mode
2023.04.23 V1.6 I2C Delete Slave Mode
I2S Delete Slave and Data Extension Mode

Remove LSE Stable signal

Feature V32G410x Datasheet
ARM®-based 32-bit Cortex®-M4F MCU + FPU, with 4096 Kbyte

Internal Flash Memory, 17 Timers, 2 ADCs, 16 Communication
Interfaces
Feature
⚫ Core: ARM®32-bit Cortex®-M4F CPU with FPU
– 200 MHz maximum frequency, with a Memory Protection Unit (MPU), single
cycle multiplication and hardware division
– Floating Point Unit (FPU), DSP instructions
⚫ Memory
– Up to 4096 Kbytes of Flash instruction/data memory
– SPIM interface: Extra interfacing up to 16 Mbytes of external SPI Flash
– Up to 1536 Kbytes of SRAM
⚫ Clock, Reset, and Power Management
– 2.6 V ~ 3.6 V application supply and I/Os
– POR/ PDR, and programmable voltage detector (PVD)
– 4 to 25 MHz crystal oscillator
– Internal 48 MHz factory-trimmed RC (accuracy 1% at TA=25 °C, 2.5 % at
TA=-40 to +105 °C)
– Internal 40 KHz RC oscillator
– 32 KHz oscillator with calibration
⚫ Low Power Consumption
– Sleep, Stop, and Standby modes
– 4 WKUP pins, which can wake up the standby mode
⚫ 2 12-bit A/D converters, 0.5 μs converting time (Up to 16 channels)
– Conversion range: 0 V to 3.6 V
– Triple sample and hold capability
– Temparature sensor
⚫ DMA: 14 channel DMA controller
– Peripherals supported: timers, ADC, I2S, SPI, I2C, and USART
⚫ Debug Mode
– Serial Wire Debug (SWD) and JTAG interface
⚫ Up to 86 Fast I/O Interfaces
– 86 multifunctional and bidirectional I/Os, up to 79 GPIOs mappable to 16
external interrupt vectors and almost 5 V-tolerant
– All fast I/Os, control registers accessable with fAHB speed
⚫ Up to 17 Timers
– Up to 8 x 16-bit timers + 2 x 32-bit timers; each with 4 input capture/
output comparison/PWM or pulse counter and quadrature (incremental)
encoder input.

Feature V32G410x Datasheet
– Up to 2 x 16-bit motor control PWM advanced timers with dead-time

generator and emergency stop
– 2 x Watchdog timers (independent and window)
– SysTick timer: 24-bit downcounter
– 2 x 16-bit basic timers
⚫ Up to 16 Communication Interfaces
– Up to 3 x I2C interfaces (SMBus/ PMBus)
– Up to 8 x USARTs (ISO7816 interface, LIN, IrDA capability, and modem
control)
– Up to 4 x SPIs (36 Mbit/s), all with I2S interface multiplexed
– CAN interface (2.0A and 2.0B)
⚫ CRC Calculation Unit
⚫ Packaging
– QFN48 7x7 mm (V32G410CGU7)
– LQFP64 10x10 mm (V32G410RGT7)
– LQFP100 14x14 mm (V32G410VUT7)
– LQFP100 14x14 mm (V32G410VGT7)

Introduction V32G410x Datasheet
1 Introduction
This article gives the function information of the V32G410x series products.
The introduction of the V32G410x series must be read together with the V32G410x
series product manual and the V32G410x series reference manual. About internal
flash storage Information about programming, erasing and protection of the device
can also be obtained in the V32G410x series reference manual. For information
about the Cortex®-M4 core, please refer to The Cortex-M4 technical reference
manual can be downloaded from the ARM website: http://infocenter.arm.com

Description V32G410x Datasheet
2 Description
The V32G410x incorporates the high-performance ARM® Cortex®-M4F 32-bit RISC

core operating at 200MHZ. The Cortex®-M4F core features a Floating point unit
(FPU) single precision which supports all ARM single-precision data processing
instructions and data type. It also implements a full set of DSP instructions and a
memory protection unit (MPU) which enhances application security.
The V32G410x incorporates high-speed embedded memories (up to 4096 Kbytes of

Flash memory, up to 1536 Kbytes of SRAM), the extensive external SPI Flash (up to
16 Mbytes addressing capability), and enhanced I/Os and peripherals connected to
two APB buses.
The V32G410x offers two 12-bit ADCs, eight general-purpose 16-bit timers plus two
general- purpose 32-bit timers, and up to two PWM timers for motor control, as well
as standard and advanced communication interfaces, up to three I2Cs, four SPIs (all
multiplexed as I2S), eight USART/UART and a CAN.
The V32G410x operates in the -40 to +105 °C temperature range, from a 2.6 to 3.6
V power supply. A comprehensive set of power-saving mode allows the design of
low-power application.
2.1 Device overview
The V32G410x offers devices in four different package types: from 48 pins and 100
pins. The description below gives an overview of the complete range of peripherals
proposed in different devices.
Table2. V32G410x series device function and configuration

V32G41 V32G41 V32G41 V32G41
Part Number
0VGT7 0CGU7 0RGT7 0VUT7
CPU frequency (MHz) 200
Flash (Kbytes) 1024 1024 1024 4096
(1)
SRAM (Kbytes) 1536 1536 1536 1536
SPIM 0 0 0 0
Advanced-control 2
32-bit general-purpose 2
16-bit general-purpose 8
Basic 2
Timers
SysTick 1
IWDG 1
WWDG 1
RTC 1

I2C 3 1 3 3
SPI_I2S 4 3 4/4 4
Comm.
USART+UART 4+4 2+3 4+4 4+4
CAN 1 1 1 1
12-bit ADC 2
Analog
numbers/channels 16 10 16 16
GPIOs 80 41 51 80
Operating temperatures -40 to +105 °C
LQFP100 QFN48 LQFP64 LQFP100
Packages 14 x 14 7x7 10x10 14 x 14
mm mm mm mm
In 1536KB mode, the flash memory capacity with zero wait state is disabled;
In 1408KB mode, the flash memory capacity with zero wait state is limited to 128K bytes;
In 896KB mode, the flash memory capacity with zero wait state is limited to 640K bytes.
2.2 Overview
The ARM Cortex®-M4F with FPU processor is the latest generation of ARM
processors for embedded systems. It was developed to provide a low-cost platform
that meets the needs of MCU implementation, with a reduced pin count and low-
power consumption, while delivering outstanding computational performance and an
advanced response to interrupts.
2.2.1 ARM® Cortex®-M4F with FPU core and DSP instruction set
The ARM Cortex®-M4F with FPU 32-bit RISC processor features exceptional code
efficiency, delivering the high-performance expected from an ARM core in the
memory size usually associated with 8- and 16-bit devices. The processor supports a
set of DSP instructions which allow efficient signal processing and complex algorithm
execution. Its single precision FPU (floating point unit) speeds up software
development by using meta language development tools, while avoiding saturation.
With its embedded ARM core, the V32G410x is compatible with all ARM tools and
software.
Figure 1 shows the general block diagram of the V32G410x.
Cortex®-M4F with FPU is binary compatible with Cortex®-M3.
Figure1. V32G410x block diagram

HSE 4~25MHz
HSI 48MHz
PLL
SWJTAG
FCLK Max. 200MHz
ARM HCLK
Cortex-M4 RCC PCLK1
(Freq. Max. 200MHz) PCLK2
NVIC Flash @VDD

Flash
Controller POR/PDR
AHB Bus Matrix (Freq. Max. 200MHz)

PVD
DMA1 SRAM LDO 1.1V
SRAM
7 Channel Controller
GPIOA
DMA2
7 Channel GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
APB1 APB2
Bridge Bridge
@VDD
GPTM2 AFIO
PWR
GPTM3 EXTI
IWDG
GPTM4 TM1
LSI 40KHz
GPTM5 TM8
GPTM12 @VDD SPI1/I2S1
GPTM13 RTC USART1
GPTM14 BKP USART6

APB2 Bus (Freq. Max. 100MHz)
APB1 Bus (Freq. Max. 100MHz)
SPI2/I2S2 LSE 32KHz GPTM9
SPI3/I2S3 GPTM10
SPI4/I2S4 GPTM11
BSCTM6
USART2
BSCTM7
USART3
WWDG
UART4
UART5 UART7
I2C1 UART8
I2C2 Temper
ature
I2C3 ADCIF1 Sensor
ADC1
CAN1 ADCIF2 ADC2
@VDDA
2.2.2 Memory protection unit (MPU)
The memory protection unit (MPU) is used to manage the CPU accesses to memory
to prevent one task to accidentally corrupt the memory or resources used by any
other active task. This memory area is organized into up to 8 protected areas that
can in turn be divided up into 8 subareas. The protection area sizes are between 32
bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code
has to be protected against the misbehavior of other tasks. It is usually managed by
an RTOS (real-time operating system). If a program accesses a memory location
that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
2.2.3 Flash memory
Up to 4096 Kbytes of embedded Flash is available for storing programs and data.
The V32G410x provides extra interface called SPIM (SPI memory), which interfaces
the external SPI Flash memory storing programs and data. With maximum 16
Mbytes addressing capability, SPIM can be used as an extensive Flash memory Bank
2.
2.2.4 Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a
32-bit data word and a fixed generator polynomial among other applications, CRC-
based techniques are used to verify data transmission or storage integrity. In the
scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash
memory integrity. The CRC calculation unit helps compute a signature of the
software during runtime, to be compared with a reference signature generated at
link time and stored at a given memory location.
2.2.5 Embedded SRAM
Up to 1536 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed

with 0 wait states.
2.2.6 Nested vectored interrupt controller (NVIC)
The V32G410x embed a nested vectored interrupt controller able to manage 16

priority levels and handle up to 79 maskable interrupt channels plus the 16 interrupt
lines of the Cortex®-M4 with FPU.
⚫ Closely coupled NVIC gives low-latency interrupt processing

⚫ Interrupt entry vector table address passed directly to the core
⚫ Closely coupled NVIC core interface
⚫ Allows early processing of interrupts
⚫ Processing of late arriving higher priority interrupts
⚫ Support for tail-chaining

⚫ Processor state automatically saved

⚫ Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal
interrupt latency.
2.2.7 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to

generate interrupt/event requests. Each line can be independently configured to
select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The
EXTI can detect an external line with a pulse width shorter than the Internal APB2
clock period. Up to 86 GPIOs can be connected to the 16 external interrupt lines.
2.2.8 Clocks and startup
System clock selection is performed on startup, however the internal RC 48 MHz

oscillator (HSI) through a divided-by-6 divider (8 MHz) is selected as default CPU
clock on reset. An external 4 to 25 MHz clock (HSE) can be selected, in which case it
is monitored for failure. If failure is detected, the system automatically switches back
to the internal RC oscillator. A software interrupt is generated. Similarly, full interrupt
management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Multiple prescalers allow the configuration of the AHB and the APB (APB1 and APB2)
frequency. The maximum frequency of the AHB domain is 200MHZ. The maximum
allowed frequency of the APB domains are 100 MHz See Figure 2 for details on the
clock tree.
Figure2. Clock tree

HIS_DIV_EN
HSI
HSI RC
48M
/6
I2SCLK[1,2,3,4]
HSISYSCTRL
/2 SYSCLKSEL Peripheral c lock enable
PLL PLLCLK Ma x. 200MHz

AHB
200M+ DIV FCLK
SYSCLK
Peripheral c lock enable
AHB、Memory、DMA
PLLSRC CFD
/8 Systick clock
OSC_OUT
HSE H SE Ma x. 100MH z
APB1
4~25M DIV PCLK1
OSC_IN HSE Peripheral c lock enable
DIV
PLLHSEPSC /8
PWR_PCLK
/128
If( APB1 prescaler = Ma x. 200MH z
OSC32_IN 1) x 1
LSE else x 2 TMRx[2~7,12~14]
32.768K LSE
RTCCLK Peripheral c lock enable
OSC32_OUT
Max. 100MH z
APB2 PCLK2
RTCSEL DIV
LSI RC Peripheral c lock enable
IWDGCLK
40K LSI
If( APB2 prescaler Ma x. 200MH z

=1) x 1
else x 2 TMRx[1,8~11]
/2 PLLCLK ADC
DIV
ADCCLK
/4 PLLCLK Peripheral c lock enable
CLKOUT HSI
CLKOUT HSE
DIV
LSI
LSE Legend:
SYSCLK HSE = High-speed external clock signal
HIS = High-speed internal clock signal
ADCCLK LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
2.2.9 Boot modes
At startup, boot pins are used to select one of three boot options:
⚫ Boot from user Flash. By default, boot from Flash memory bank 1 is selected.
User can choose to boot from Flash memory bank 2 by setting a bit in the option
bytes.
⚫ Boot from system memory
⚫ Boot from embedded SRAM
The bootloader is stored in system memory. The flash memory can be

reprogrammed via USART1 or USART2. Table3 provides the the bootloader pin
configurations.
Table3. The bootloader pin configurations

Interface Pin
PA9: USART1_TX
USART1
PA10: USART1_RX
PA2: USART2_TX (remapped)
USART2
PA3: USART2_RX (remapped)

2.2.10 Power supply schemes
⚫ VDD = 2.6～3.6 V: external power supply for I/Os, RCL, XOL and the internal
regulator provided externally through VDD pins.
⚫ VDDA = 2.6～3.6 V: external analog power supplies for ADC\RCH\Tempersensor.
VDDA and VSSA must be connected to VDD and VSS, respectively.
For more detail on how to connect power pins, refer to Figure9.
2.2.11 Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR)

circuitry. It is always active, and ensures proper operation starting from/down to 2.6
V. The device remains in reset mode when V DD is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that

monitors the VDD power supply and compares it to the VPVD threshold. An interrupt
can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by
software. Refer to Table 13 for the characteristic values of VPOR/PDR and VPVD.
2.2.12 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power
down.
⚫ Main mode (MR) is used in the nominal regulation mode (Run) and in the Stop
mode
⚫ Low-power mode (LPR) can be used in the Stop mode
⚫ Power down mode is used in Standby mode: the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption
of the regulator (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
2.2.13 Low-power modes
The V32G410x supports three low-power modes to achieve the best compromise
between low- power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.1 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator is put in normal
mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.1 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the
Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm occurs.
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or
Standby mode.
2.2.14 Direct Memory Access Controller (DMA)
The flexible 14-channel general-purpose DMAs (7 channels for DMA1 and 7 channels
for DMA2) are able to manage memory-to-memory, peripheral-to-memory, and
memory-to-peripheral transfers. The two DMA controllers support circular buffer
management, removing the need for user code intervention when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for
software trigger on each channel. Configuration is made by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose,
basic, and advanced-control timers TMRx, I2S, and ADC.
2.2.15 Real-time clock (RTC) and backup registers
The RTC and the backup registers are supplied with VDD. The backup registers are
sixty- four 16-bit registers used to store 128 bytes of user application data. They are
not reset by a system or power reset, and they are not reset when the device wakes
up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be
used with suitable software to provide a clock calendar function, and provides an

alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external

crystal, resonator or oscillator, the internal low- power RC oscillator, or the high-
speed external clock divided by 128. The internal low-speed RC has a typical
frequency of 40 kHz. The RTC can be calibrated using a divied-by-64 output of
TAMPER pin to compensate for any natural quartz deviation. The RTC features a 32-
bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.2.16 Timers and watchdogs (TMR/WDG)
The V32G410x devices include up to 2 advanced-control timers, up to 10 general-

purpose timers, 2 basic timers, 2 watchdog timers, and a SysTick timer.
The table below compares the features of the advanced-control, general-purpose,

and basic timers.
Table4. Timer feature comparison

Timer
resolution
Counter
Counter type
factor
Prescaler
generation
DMA request
channels
compare
Capture/
ary outputs
Complement
TMR1, Up, down, Any integer between
16-bit Yes 4 Yes
TMR8 up/down 1 and 65536
32-bit Yes 4 No
16-bit Yes 4 No
TMR9, Any integer between
16-bit Up No 2 No
TMR12 1 and 65536
TMR10,
16-bit Up No 1 No
TMR13, 1 and 65536
TMR14
16-bit Up Yes 0 No
TMR7 1 and 65536
Advanced-control timers (TMR1 and TMR8)
The two advanced-control timers (TMR1 and TMR8) can each be seen a three-phase
PWM multiplexed on 6 channels. They have complementary PWM outputs with

programmable inserted dead-times. They can also be seen as a complete general-
purpose timer. The 4 independent channels can be used for:

⚫ Input capture
⚫ Output compare
⚫ PWM generation (edge or center-aligned modes)
⚫ One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TMRx timer.
If configured as the 16-bit PWM generator, it has full modulation capability (0-
100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM
outputs disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TMR timers which have
the same architecture. The advanced-control timer can therefore work together with
the TMR timers via the link feature for synchronization or event chaining.
General-purpose timers (TMRx)
There are 10 synchronizable general-purpose timers embedded in the V32G410x.
⚫ TMR2, TMR3, TMR4, and TMR5
The V32G410x has 4 full- featured general-purpose timers: TMR2, TMR3, TMR4, and
TMR5. The TMR2 and TMR5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TMR3 and TMR4 timers are based on a 16-bit
auto-reload up/down counter and a 16-bit prescaler. They all feature four
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input capture/output compare/PWMs.
The TMR2, TMR3, TMR4, and TMR5 general-purpose timers can work together, or
with the other general-purpose timers and the advanced-control timers via the link
feature for synchronization or event chaining. In debug mode, their counter can be
frozen. Any of these general-purpose timers can be used to generate PWM outputs.
The TMR2, TMR3, TMR4, and TMR5 are capable of handling quadrature (incremental)
encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
⚫ TMR9 and TMR12
TMR9 and TMR12 are based on a 16-bit auto-reload up-counter, a 16-bit prescaler,
and two independent channels for input capture/output compare, PWM, or one-pulse
mode output. They can be synchronized with the TMR2, TMR3, TMR4, and TMR5 full-
featured general-purpose timers. They can also be used as simple time bases.
⚫ TMR10, TMR11, TMR13, and TMR14
These timers are based on a 16-bit auto-reload up-counter, a 16-bit prescaler, and
one independent channels for input capture/output compare, PWM, or one-pulse
mode output.
They can be synchronized with the TMR2, TMR3, TMR4, and TMR5 full-featured

general-purpose timers. They can also be used as simple time bases.
Basic timers (TMR6 and TMR7)
These two timers can be used as a generic 16-bit time base.
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. It

is clocked from an independent 40 kHz internal RC and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free running
timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
Window watchdog (WWDG)
The window watchdog is based on a 7-bit down-counter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It
is clocked from the main clock. It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a
standard down counter. It features:
⚫ A 24-bit down counter

⚫ Auto-reload capability
⚫ Mask-able system interrupt generation when the counter reaches 0
⚫ Programmable clock source
2.2.17 Inter-integrated-circuit interface (I2C)
Up to 3 I2C bus interfaces can operate master mode. They can support standard and
fast modes.
They support 7/10-bit addressing. A hardware CRC generation/verification is

included.
They can be served by DMA and they support SMBus 2.0/PMBus.
2.2.18 Universal synchronous/asynchronous receiver transmitters

(USART)
The V32G410x embeds 4 universal synchronous/asynchronous receiver transmitters

(USART1, USART2, USART3, and USART6) and 4 universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These eight interfaces provide asynchronous communication, IrDA SIR ENDEC

support, multiprocessor communication mode, single-wire half-duplex

communication mode, and have LIN Master/Slave capability.
These eight interfaces are able to communicate at speeds of up to 5.625 Mbit/s.
USART1, USART2, and USART3 provide hardware management of the CTS and RTS
signals. USART1, USART2, USART3, and USART6 also provide Smart Card mode
(ISO7816 compliant) and SPI-like communication capability. All interfaces can be
served by the DMA controller.
Table5. USART/UART feature comparison

USART/UA USAR USAR USAR UART UART USAR UART UART
RT name T1 T2 T3 4 5 T6 7 8
Hardware Yes Yes Yes - - - - -
flow control
for modem
Continuous Yes Yes Yes Yes Yes Yes Yes Yes
communicat
ion using
DMA
Multiprocess Yes Yes Yes Yes Yes Yes Yes Yes
or
communicat
ion
Synchronou Yes Yes Yes - - Yes - -
s mode
Smartcard Yes Yes Yes - - Yes - -
mode
Single-wire Yes Yes Yes Yes Yes Yes Yes Yes
half-duplex
communicat
ion
IrDA SIR Yes Yes Yes Yes Yes Yes Yes Yes
ENDEC
block
LIN mode Yes Yes Yes Yes Yes Yes Yes Yes
2.2.19 Serial peripheral interface (SPI)
Up to four SPIs are able to communicate up to 36 Mbits/s in slave and master modes
in full- duplex and simplex communication modes. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware
CRC generation/verification supports basic SD Card/MMC/SDHC modes.
All SPIs can be served by the DMA controller.

2.2.20 Inter-integrated sound interface (I2S)
Four standard I2S interfaces (multiplexed with SPI) are available, that can be
operated in master mode in half-duplex mode. These interfaces can be configured to
operate with 16/32 bit resolution, as input or output channels. Audio sampling
frequencies from 8 kHz up to 192 kHz are supported. The master clock can be
output to the external CODEC at 256 times the sampling frequency.
2.2.21 Controller area network (CAN)
Two CANs are compliant with specifications 2.0A and B with a bit rate up to 1 Mbit/s.
It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive
FIFOs with 3 stages and 14 scalable filter banks.
2.2.22 General-purpose inputs/outputs (GPIO)
Each of the GPIO pins can be configured by software as output (push-pull), as input
(with pull-down or without pull-up or pull-down), or as peripheral alternate function.
Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs
are high current-capable.
The I/Os alternate function configuration can be locked, if needed, in order to avoid
spurious writing to the I/Os registers by following a specific sequence.
2.2.23 Remap capability
This feature allows the use of a maximum number of peripherals in a given

application. Indeed, alternate functions are available not only on the default pins but
also on other specific pins onto which they are remappable. This has the advantage
of making board design and port usage much more flexible.
For details refer to Table 6; it shows the list of remappable alternate functions and
the pins onto which they can be remapped. See the V32G410x reference manual for
software considerations.
2.2.24 Analog to digital converter (ADC)
Two 12-bit analog-to-digital converters are embedded into V32G410x devices and
they share up to 16 external channels, performing conversions in single-shot or scan
modes. In scan mode, automatic conversion is performed on a selected group of
analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage

of one, some or all selected channels. An interrupt is generated when the converted
voltage is outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control

timers can be internally connected to the ADC start trigger and injection trigger,
respectively, to allow the application to synchronize A/D conversion and timers.
2.2.25 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with
temperature. The conversion range is between 2.6 V ≤ VDDA ≤ 3.6 V. The
temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
2.2.26 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire
debug port that enables either a serial wire debug or a JTAG probe to be connected
to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and
SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP
and SW-DP.

Pinouts and pin descriptions V32G410x Datasheet
3 Pinouts and pin descriptions
Figure3. V32G410CGU7 QFN48 pinout
PB13
PA12
PB14
PB15
PA11
PA10
PD8
PD9
PC7
PC6
PA8
PA9
26
33
34
30
28
35
32
31
29
27
36
25
PA13 37 PB12
PA14 38 VDD_2
PA15 39 PE8
PB3 40 PE7
PB4 41 PB2
PB5 42 GND PB1
PB6 43 PB0
PB7 44 PA7
BOOT0 45 PA6
PB8 46 PA5
PB9 47 PA4
PE0 48 PA3
10
11
12
3
4
6
7
1
2
8
9
PA2
PA0/WKUP1
OSC_IN
PA1/WKUP2
VDD_1
PE6
PE4
PE5
VDDA
PE2
OSC_OUT
NRST

Figure4. V32G410RGT7 LQFP64 pinout
VDD_2
VSS_2
PB15
PB14
PB13
PB12
PA13
PA12
PA11
PA10
PC9
PC8
PC7
PC6
PA9
PA8
48
47
46
45
40
39
38
37
33
44
43
42
41
36
35
34
PA14 49 32 VDD_1
PA15 50 31 VSS_1
PC10 51 30 PB11
PC11 52 29 PB10
PC12 53 28 PB2
PD2 54 27 PB1
PB3 55 26 PB0
PB4 56 25 PC5
PB5 57 24 PC4
PB6 58 23 PA7
PB7
BOOT0
59
60
LQFP-64 22 PA6
21 PA5
PB8 61 20 PA4
PB9 62 19 VDD_4
VSS_3 63 18 VSS_4
VDD_3 64 17 PA3
10
11
16
12
13
14
15
1
2
3
8
9
4
5
6
7
OSC_IN
VDDA
NC
PC0
PC1
PC2
PC3
PA0
PA1
PA2
OSC_OUT
VSSA
NRST
PC15
PC13
PC14

Figure5. V32G410VUT7/ V32G410VGT7 LQFP100 pinout
VDD_2
VSS_2
PD14
PD13
PD11
PD10
PD15
PD12
PA13
PA12
PA10
PA11
PB15
PB13
PB12
PB14
PD8
PD9
PA9
PA8
PC9
PC7
PC6
PC8
NC
75
72
71
68
67
63
59
58
55
54
51
74
73
70
69
66
65
64
62
61
60
57
56
53
52
PA14 76 50 VDD_1
PA15 77 49 VSS_1
PC10 78 48 PB11
PC11 79 47 PB10
PC12 80 46 PE15
PD0 81 45 PE14
PD1 82 44 PE13
PD2 83 43 PE12
PD3 84 42 PE11
PD4 85 41 PE10
PD5 86 40 PE9
PD6 87 39 PE8
PD7 88 38 PE7
PB3 89 37 PB2
PB4 90 36 PB1
PB5
PB6
91
92 LQFP-100 35
34
PB0
PC5
PB7 93 33 PC4/WKUP4
BOOT0 94 32 PA7
PB8 95 31 PA6
PB9 96 30 PA5
PE0 97 29 PA4
PE1 98 28 VDD_4
VSS_3 99 27 VSS_4
VDD_3 100 26 PA3
10
13
14
18
22
23
11
12
15
16
17
19
20
21
24
25
1
2
5
6
9
3
4
7
8 PC14/OSC32_IN
OSC_IN
VSSA
PE3
PE4
PE6
VSS_5
VDD_5
PC1
PC2
VREF+
PA1/WKUP2
PA2
PE2
PE5
PC0/WKUP3
PC3
NC
VREF-
PA0/WKUP1
NRST
VDDA
OSC_OUT
PC15/OSC32_OUT
PC13/TAMPER-RTC

The following table is the pin definition of V32G410x series. The multiplexing functions are arranged in order of priority. The
basic principle is that the analog signal is higher than the digital signal, and the output digital signal is higher than the input
digital signal.
Table6. V32G410x series pin definitions

Pin number Alternate functions（4）
V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever
（2）
function（3） Default Remap Default Remap
1 - - - NC not connected
SPI4_SCK(7)/
2 1 2 - PE2 I/O FT PE2 -
I2S4_CK(7)
3 2 - - PE3 I/O FT PE3 - -
(7)
SPI4_NSS /
4 3 3 - PE4 I/O FT PE4 -
I2S4_WS(7)
5 4 4 - PE5 I/O FT PE5 SPI4_MISO(7) TMR9_CH1
(7)
SPI4_MOSI /
6 5 5 - PE6 I/O FT PE6 TMR9_CH2
I2S4_SD(7)
8 6 - 1 NC not connected
TAMPER-
9 7 - 2 I/O FT PC13（6） TAMPER-RTC -
RTC/PC13（5）
OSC32_IN/
10 8 - 3 I/O FT PC14(6) OSC32_IN -
PC14(5)

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
function Default Remap Default Remap
OSC32_OUT/
11 9 - 4 I/O FT PC15 OSC32_OUT -
PC15(5)
13 10 - - VSS_5 S - VSS_5 - -
14 11 - - VDD_5 S - VDD_5 - -
15 12 6 5 OSC_IN I/O TC OSC_IN - -
16 13 7 6 OSC_OUT I/O TC OSC_OUT - -
17 14 8 7 NRST I/O - NRST - -
ADC1/2_IN10/
19 15 - 8 PC0/WKUP3 I/O FTa PC0 -
WKUP3
20 16 - 9 PC1 I/O FTa PC1 ADC1/2_IN11 -
21 - - NC not connected
22 17 - 10 PC2 I/O FTa PC2 ADC1/2_IN12 UART8_TX
23 18 - 11 PC3 I/O FTa PC3 ADC1/2_IN13 UART8_RX
24 19 - 12 VSSA S - VSSA - -
26 20 - - VREF- S - VREF- - -
27 21 - - VREF+ S - VREF+ - -
28 22 9 13 VDDA S - VDDA - -

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
ADC1/2_IN0/
WKUP1/
USART2_CTS(7)/
29 23 10 14 PA0/WKUP1 I/O FT PA0 TMR2_CH1(7) / UART4_TX
(7)
TMR2_ETR /
TMR5_CH1/
TMR8_ETR
ADC1/2_IN1/
WKUP2/
30 24 11 15 PA1/WKUP2 I/O FTa PA1 USART2_RTS(7)/ UART4_RX
(7)
TMR2_CH2 /
TMR5_CH2
ADC1/2_IN2/
USART2_TX(7)/
31 25 12 16 PA2 I/O FTa PA2 TMR2_CH3(7)/ -
TMR5_CH3/
TMR9_CH1(7)
33 - - SPIM_IO0 I/O FT SPIM_IO0 PF2 -
ADC1/2_IN3/
34 26 13 17 PA3 I/O FTa PA3 I2S2_MCK
USART2_RX(7)/
V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
TMR2_CH4(7)/
TMR5_CH4/
TMR9_CH2(7)
35 27 18 VSS_4 S - VSS_4 - -
36 28 19 VDD_4 S - VDD_4 - -
37 - - SPIM_SCK O FT SPIM_SCK PF4 -
ADC1/2_IN4/
USART6_TX/
USART2_CK(7)/
38 29 14 20 PA4 I/O FTa PA4 SPI3_NSS/
SPI1_NSS(7)/
I2S3_WS
I2S1_WS(7)
ADC1/2_IN5/
39 30 15 21 PA5 I/O FTa PA5 SPI1_SCK(7)/ USART6_RX
(7)
I2S1_CK
ADC1/2_IN6/
SPI1_MISO(7)/
I2S2_MCK/
40 31 16 22 PA6 I/O FTa PA6 TMR3_CH1(7)/
TMR1_BKIN
TMR8_BKIN/
TMR13_CH1
42 32 17 23 PA7 I/O FTa PA7 ADC1/2_IN7/ TMR1_CH1N

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
SPI1_MOSI(7)/
I2S1_SD(7)/
TMR3_CH2(7)/
TMR8_CH1N/
TMR14_CH1
ADC1/2_IN14/
43 33 24 PC4/ WKUP4 I/O FTa PC4 -
WKUP4
44 34 25 PC5 I/O FTa PC5 ADC1/2_IN15
ADC1/2_IN8/
I2S1_MCK(7)/
45 35 18 26 PB0 I/O FTa PB0 TMR1_CH2N
TMR3_CH3(7)/
TMR8_CH2N
ADC1_IN9/
47 36 19 27 PB1 I/O FTa PB1 TMR3_CH4(7)/ TMR1_CH3N
TMR8_CH3N
48 37 20 28 PB2 I/O FT PB2 / BOOT1 - -
(7)
49 38 21 - PE7 I/O FT PE7 UART7_RX TMR1_ETR
(7)
50 39 22 - PE8 I/O FT PE8 UART7_TX TMR1_CH1N
51 40 - PE9 I/O FT PE9 TMR1_CH1

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
53 41 - PE10 I/O FT PE10 TMR1_CH2N
SPI4_SCK/
54 42 - PE11 I/O FT PE11 I2S4_CK/
TMR1_CH2
SPI4_NSS/
55 43 - PE12 I/O FT PE12 I2S4_WS/
TMR1_CH3N
SPI4_MISO/
57 44 - PE13 I/O FT PE13
TMR1_CH3
SPI4_MOSI/
58 45 - PE14 I/O FT PE14 I2S4_SD/
TMR1_CH4
59 46 - PE15 I/O FT PE15 TMR1_BKIN
(7)
USART3_TX / I2S3_MCK/
60 47 29 PB10 I/O FT PB10
I2C2_SCL TMR2_CH3
(7)
USART3_RX /
61 48 30 PB11 I/O FT PB11 TMR2_CH4
I2C2_SDA
62 49 31 VSS_1 S - VSS_1 - -

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
63 50 1 32 VDD_1 S - VDD_1 - -
USART3_CK(7)/
I2C2_SMBA/
66 51 24 33 PB12 I/O FT PB12 SPI2_NSS / -
I2S2_WS/
TMR1_BKIN(7)
USART3_CTS(7)/
SPI2_SCK/
67 52 25 34 PB13 I/O FT PB13 -
I2S2_CK/
TMR1_CH1N(7)
USART3_RTS(7)/
SPI2_MISO/
68 53 26 35 PB14 I/O FT PB14 -
TMR1_CH2N(7)/
TMR12_CH1
SPI2_MOSI/
70 54 27 36 PB15 I/O FT PB15 I2S2_SD/ -
(7)
TMR1_CH3N /

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
TMR12_CH2
71 55 28 - PD8 I/O FT PD8 - USART3_TX
72 56 29 - PD9 I/O FT PD9 - USART3_RX
74 57 - PD10 I/O FT PD10 - USART3_CK
75 58 - PD11 I/O FT PD11 - USART3_CTS
USART3_RTS/
76 59 - PD12 I/O FT PD12 -
TMR4_CH1
77 60 - PD13 I/O FT PD13 - TMR4_CH2
79 61 - PD14 I/O FT PD14 - TMR4_CH3
80 62 - PD15 I/O FT PD15 - TMR4_CH4
(7)
USART6_TX /
81 63 30 37 PC6 I/O FT PC6 I2S2_MCK(7)/ TMR3_CH1
TMR8_CH1
USART6_RX(7)/
82 64 31 38 PC7 I/O FT PC7 I2S3_MCK(7)/ TMR3_CH2
TMR8_CH2
USART6_CK/
83 65 39 PC8 I/O FT PC8 TMR3_CH3
I2S4_MCK(7)/

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
TMR8_CH3
I2C3_SDA(7)/
85 66 40 PC9 I/O FT PC9 TMR3_CH4
TMR8_CH4
CLKOUT/
USART1_CK/
86 67 32 41 PA8 I/O FT PA8 -
I2C3_SCL/
TMR1_CH1(7)
USART1_TX(7)/
87 68 33 42 PA9 I/O FT PA9 I2C3_SMBA/ -
(7)
TMR1_CH2
USART1_RX(7) /
89 69 34 43 PA10 I/O FT PA10 I2S4_MCK
TMR1_CH3(7)
USART1_CTS/
90 70 35 44 PA11 I/O FT PA11 CAN1_RX(7)/ -
(7)
TMR1_CH4
USART1_RTS/
91 71 36 45 PA12 I/O FT PA12 CAN1_TX(7)/ -
(7)
TMR1_ETR

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
92 72 37 46 PA13 I/O FT JTMS-SWDIO - PA13

93 73 - NC not connected
94 74 47 VSS_2 S - VSS_2 - -
95 75 23 48 VDD_2 S - VDD_2 - -
98 76 38 49 PA14 I/O FT JTCK-SWCLK - PA14
PA15/
SPI1_NSS/
SPI3_NSS(7)/
99 77 39 50 PA15 I/O FT JTDI I2S1_WS/
I2S3_WS(7)
TMR2_CH1/
TMR2_ETR
USART3_TX/
100 78 51 PC10 I/O FT PC10 UART4_TX(7) SPI3_SCK/
I2S3_CK
USART3_RX/
101 79 52 PC11 I/O FT PC11 UART4_RX(7)
SPI3_MISO
USART3_CK/
103 80 53 PC12 I/O FT PC12 UART5_TX(7)
SPI3_MOSI/

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
I2S3_SD
104 81 - PD0 I/O FT PD0 CAN1_RX
105 82 - PD1 I/O FT PD1 CAN1_TX
(7)
UART5_RX /
106 83 54 PD2 I/O FT PD2
TMR3_ETR
108 84 - PD3 I/O FT PD3 - USART2_CTS
109 85 - PD4 I/O FT PD4 - USART2_RTS
110 86 - PD5 I/O FT PD5 - USART2_TX
112 87 - PD6 I/O FT PD6 - USART2_RX
113 88 - PD7 I/O FT PD7 - USART2_CK
PB3/
UART7_RX/
SPI3_SCK(7)/
114 89 40 55 PB3 I/O FT JTDO SPI1_SCK/
I2S3_CK(7)
I2S1_CK/
TMR2_CH2
PB4/
115 90 41 56 PB4 I/O FT NJTRST SPI3_MISO(7) SPI1_MISO/
I2C3_SDA/

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
UART7_TX/
TMR3_CH1
116 - - SPIM_NSS O FT SPIM_NSS PF5 -
(7)
SPI3_MOSI / SPI1_MOSI/
(7)
117 91 42 57 PB5 I/O FT PB5 I2S3_SD / I2S1_SD/
(7)
I2C1_SMBA TMR3_CH2
USART1_TX/
I2C1_SCL(7)/ I2S1_MCK/
118 92 43 58 PB6 I/O FT PB6 (7)
TMR4_CH1 SPI4_NSS/
I2S4_WS
USART1_RX/
I2C1_SDA(7)/
119 93 44 59 PB7 I/O FT PB7 SPI4_SCK/
TMR4_CH2(7)
I2S4_CK
121 94 45 60 BOOT0 I - BOOT0 - -
UART5_RX/
(7)
TMR4_CH3 / SPI4_MISO/
122 95 46 61 PB8 I/O FT PB8
TMR10_CH1 I2C1_SCL/
CAN1_RX
(7)
123 96 47 62 PB9 I/O FT PB9 TMR4_CH4 / UART5_TX/

V32G410RGT7
V32G410x
V32G410VGT7
V32G410VUT7
V32G410CGU7
IO
Type Main
Pin name （1）
lever （3）
（2）
TMR11_CH1 SPI4_MOSI/
I2S4_SD/
I2C1_SDA/
CAN1_TX
(7)
UART8_RX /
125 97 48 - PE0 I/O FT PE0 -
TMR4_ETR
126 98 - PE1 I/O FT PE1 UART8_TX(7) -
127 99 63 VSS_3 S - VSS_3 - -
128 100 64 VDD_3 S - VDD_3 - -
I = input, O = output, S = supply.
FT = general 5 V-tolerant I/O, FTa = 5 V-tolerant I/O with analog functionalities. FTa pin is 5 V- tolerant when configured as input floating,
input pull-up, or input pull-down mode. However, it cannot be 5 V-tolerant when configured as analog mode. Meanwhile, its input level
should not higher than VDD + 0.3 V.
Function availability depends on the chosen device.
If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a
time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
PC13, PC14, and PC15 only sink a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the normal
sourcing/sinking strength should be used with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive
an LED).
Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because

these registers are not reset by the main reset). For details on how to manage these IOs, refer to the backup domain and BKP register
description sections in the V32G410x reference manual.
This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to
the Alternate function I/O and debug configuration section in the V32G410x reference manual.

Memory mapping V32G410x Datasheet
4 Memory mapping
Figure6. Memory map
0x1FFF_FFFF
Reserved
0x1FFF_F840
0x1FFF_F83F
0xFFFF_FFFF
Option Bytes
0x1FFF_F800
Reserved
0x1FFF_F7FF
Reserved
0x1FFF_ F000 0xE010_0000
0x1FFF_EFFF 0xE00F_FFFF Cortex-M4 Internal
System memory
0x1FFF_7000 0xE000_0000 Peripherals
0x1FFF_6FFF 0xDFFF_FFFF
Reserved Reserved
0x0980_0000 0x6000_0000
0x097F_FFFF 0x5FFF_FFFF
External SPI Flash Peripherals
memory 0x4000_0000
0x0880_0000 0x3FFF_FFFF
0x087F_FFFF Reserved
Reserved 0x2018_0000
0x2017_FFFF
0x0840_0000
0x083F_FFFF SRAM
Flash memory 0x2000_0000
0x1FFF_FFFF
0x0800_0000
0x07FF_FFFF Aliased to Flash or
Aliased to Flash or system memory or
system memory SRAM according to
according to BOOT BOOT pins
pins configuration configuration
0x0000_0000 0x0000_0000

Electrical characteristics V32G410x Datasheet
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the
worst conditions of ambient temperature, supply voltage and frequencies by tests in
production with an ambient temperature at TA = 25 °C and TA = TA max.
Data based on characterization results, design simulation and/or technology

characteristics are indicated in the table footnotes and are not tested in production.
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They
are given only as design guidelines and are not tested.
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and
are not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure7.
Figure7. Pin loading conditions

5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure8.
Figure8. Pin input voltage
5.1.6 Power supply scheme
Figure9. Power supply scheme

RTC
logic(LSE,RTC,W
akeup logic
Backup
register)
OUT
Level shift
IO
GPIOs Logic
IN
Kernel
logic(CPU,digi
LSI tal & memory)
HSE
VDD
VDD
1/2/...5
Voltage
regulator
5 × 100 nF
+ 1 × 4.7 μF
VSS
1/2/...5
PLL
VDD
VDDA
100 nF
+ 1 μF VREF VREF+
ADC/HSI/Te
ADC,DAC
100 nF mpSensor
VREF-
+ 1 μF
VSSA
In this figure, the 4.7 μF capacitor must be connected to VDD3.
5.1.7 Current consumption measurement
Figure 5-1 Current consumption measurement scheme

IDD
VDD
VDDA
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 8, Table 9, and Table 10
may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Table7. Voltage characteristics

Symbol Ratings Min Max Unit
External main supply voltage (including VDDA
VDD-VSS -0.3 4.0
and VDD)(1)
Input voltage on FT I/O
VSS-
Input voltage on FTa I/O (set as input floating, 6.0 V
0.3
VIN input pull-up, or input pull-down mode)
Input voltage on TC I/O VSS-
4.0
Input voltage on FTa I/O (set as analog mode) 0.3
|ΔVDDx| Variations between different VDD power pins - 50
|VSSx- Variations between all the different ground mV
- 50
VSS| pins (2)
All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
VREF- included.
Table8. Current characteristics

Symbol Ratings Max Unit
IVDD Total current into VDD/VDDA power lines (source)(1) 150
IVSS Total current out of VSS ground lines (sink)(1) 150
mA
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin -25
All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
Table9. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -60 ~ +150
°C
TJ Maximum junction temperature 105
5.3 Operating conditions
5.3.1 General operating conditions
Table10. General operating conditions

Symbol Parameter Conditions Min Max Unit
Internal AHB clock
fHCLK 0 200 MHz
frequency
Internal APB1 clock
fPCLK1 - 0 100 MHz
frequency
Internal APB2 clock
fPCLK2 - 0 100 MHz
frequency
Standard operating
VDD - 2.6 3.6 V
voltage
Analog operating Must be the same potential
VDDA(1) 2.6 3.6 V
voltage as VDD(1)
Backup operating
VDD - 2.2 3.6 V
voltage
Power dissipation: TA
PD - - 373 mW
= 85 °C
TA Ambient temperature - -40 105 °C
It is recommended to power VDD and VDDA from the same source. A maximum difference of
300 mV between VDD and VDDA can be tolerated during power-up and operation.
5.3.2 Operating conditions at power-up/ power-down
The parameters given in the table below are derived from tests performed under the
ambient temperature condition summarized in Table10.
Table11. Operating conditions at power-up / power-down

tVDD VDD rise time rate 0 ∞(1) ms/V

VDD fall time rate - 20 ∞ μs/V
If VDD rising time rate is slower than 120 ms/V, the code should access the backup registers
after VDD higher than VPOR + 0.1V.
5.3.3 Embedded reset and power control block characteristics
The parameters given in the table below are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table10.
Table12. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
PVDS[2:0] = 001
2.19 2.28 2.37 V
(rising edge)(1)
PVDS[2:0] = 001
2.09 2.18 2.27 V
(falling edge)(1)
PVDS[2:0] = 010
2.28 2.38 2.48 V
(rising edge)
PVDS[2:0] = 010
2.18 2.28 2.38 V
(falling edge)
PVDS[2:0] = 011
2.38 2.48 2.58 V
(rising edge)
PVDS[2:0] = 011
2.28 2.38 2.48 V
(falling edge)
Programmable PVDS[2:0] = 100
2.47 2.58 2.69 V
voltage (rising edge)
VPVD
detector level PVDS[2:0] = 100
2.37 2.48 2.59 V
selection (falling edge)
PVDS[2:0] = 101
2.57 2.68 2.79 V
(rising edge)
PVDS[2:0] = 101
2.47 2.58 2.69 V
(falling edge)
PVDS[2:0] = 110
2.66 2.78 2.9 V
(rising edge)
PVDS[2:0] = 110
2.56 2.68 2.8 V
(falling edge)
PVDS[2:0] = 111
2.76 2.88 3 V
(rising edge)
PVDS[2:0] = 111
2.66 2.78 2.9 V
(falling edge)
VPVDhyst(2) PVD hysteresis - - 100 - mV
Power 1.85(
Falling edge 2.0 2.24 V
VPOR/PDR on/power down 3)
reset threshold Rising edge 2.03 2.16 2.42 V
(2)
VPDRhyst PDR hysteresis - - 160 - mV
Reset EOPB0 = 0/1/2/3 - 0.7 -
temporization: EOPB0 = 4 - 70 -
CPU starts EOPB0 = 5 - 200 -
TRSTTEMPO(2)
execution after EOPB0 = 6 - 270 -
ms
VDD keeps
EOPB0 = 7 - 330 -
higher than

VPOR for
TRSTTEMPO
PVDS[2:0] = 001 may be not available for its voltage detector level may be lower than
VPOR/PDR.
Guaranteed by design, not tested in production.
The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
Figure10. Power on reset/power down reset waveform
5.3.4 Embedded reference voltage
Table13. Embedded internal reference voltage

Internal reference
VREFINT - 1.13 1.20 1.27 V
voltage
ADC sampling time
when reading the
TS_vrefint(1) - - 5.1 17.1(2) μs
internal reference
voltage
TCoeff(2) Temperature coefficient - -100 - 100 ppm/°C
Shortest sampling time can be determined in the application by multiple iterations.

5.3.5 Supply current characteristics
Current consumption is a comprehensive index of many parameters and factors,

including operating voltage, ambient temperature, I/O pin load, product software
configuration, operating frequency, I/O pin flip rate, and executed code.
Typical current consumption
The microcontroller is under the following conditions:
⚫ All I/O pins are on analog inputs.
All peripherals are turned off unless otherwise specified.
Instruction prefetch function is turned on (hint: this parameter must be set before
setting clock and bus frequency division).
⚫ Ambient temperature and VDD supply voltage conform to electrical characteristic

parameters
⚫ When the peripheral is turned on:
– If fHCLK > 100 MHz, fPCLK1 = fHCLK/2, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4;
– If fHCLK ≤ 100 MHz, fPCLK1 = fHCLK, fPCLK2 = fHCLK, fADCCLK = fPCLK2/4.
Table14. Typical Current Consumption in Operating Modes

(1)
Typical
Symbol Parameter Condition FHCLK Enable all Close all Unit
peripherals peripherals
200
57.1 39.4
MHz
192
55.7 38.4
MHz
180
53.4 37.1
MHz
100
38.7 27.1
MHz
Supply
External 48 MHz 25.4 19.5
current in (2)
mA
IDD clock 24 MHz 19.4 16.0
operation
8 MHz 13.6 12.5
mode
4 MHz 12.2 11.7
2 MHz 11.7 11.4
1 MHz 11.5 11.3
500
11.3 11.2
KHz
125
11.2 11.1
KHz
Operating 200 48.1 33.2 mA

on high- MHz
speed 192
46.7 32.3
internal MHz
RC 180
44.8 31.2
oscillator MHz
(HSI) 100
32.7 23.0
MHz
48 MHz 21.6 16.7
24 MHz 16.6 13.8
8 MHz 11.8 10.9
4 MHz 10.6 10.2
2 MHz 10.2 10.0
1 MHz 10.0 9.8
500
9.9 9.8
KHz
125
9.8 9.7
KHz
Typical values are measured at TA = 25 °C and VDD = 3.3 V.
The external clock is 8 MHz and PLL is enabled when fHCLK > 8 MHz.
Table15. Typical Current Consumption in Sleep Mode

(1)
Typical
Symbol Parameter Condition FHCLK Enable all Close all Unit
peripherals peripherals
200
36.4 20.7
MHz
192
35.2 18.0
MHz
180
33.7 17.6
MHz
100
24.3 12.9
MHz
Supply 48
External 15.0 9.1
IDD current in (2)
MHz mA
clock
sleep mode 24
10.9 7.6
MHz
8 MHz 6.4 5.4
4 MHz 5.4 5.0
2 MHz 5.1 4.8
1 MHz 4.9 4.7
500
4.8 4.7
KHz
125 4.8 4.7

KHz
200
29.6 18.0
MHz
192
28.6 14.3
MHz
180
27.4 14.0
MHz
100
Operating 19.5 10.0
MHz
on high-
48
speed 11.9 7.0
MHz
internal mA
24
RC 8.4 5.7
MHz
oscillator
8 MHz 4.8 3.9
(HSI)
4 MHz 3.9 3.5
2 MHz 3.6 3.4
1 MHz 3.5 3.4
500
3.4 3.4
KHz
125
3.4 3.3
KHz
Typical values are measured at TA = 25 °C and VDD = 3.3 V.
Maximum current consumption
The microcontroller is under the following conditions:

⚫ All peripherals are turned off unless otherwise specified.
⚫ Instruction prefetch function is turned on (hint: this parameter must be set
before setting clock and bus frequency division).
⚫ When the peripheral is turned on:
– If fHCLK > 100 MHz, fPCLK1 = fHCLK/2, fPCLK2 = fHCLK/2;
– If fHCLK ≤ 100 MHz, fPCLK1 = fHCLK, fPCLK2 = fHCLK.
Table16. Maximum Current Consumption in Operating Mode

(1)
Maximum
Symbol Parameter Condition FHCLK Unit
TA = 85 °C
200 MHz 93.1
(2)
192 MHz 90.5
Supply current External clock
180 MHz 88.0
IDD in operation enables all mA
100 MHz 71.8
mode peripherals
48 MHz 58.5
24 MHz 53.0
8 MHz 47.1
200 MHz 72.8
192 MHz 71.9
The external 180 MHz 70.7
(2)
clock turns off 100 MHz 59.9 mA
all peripherals 48 MHz 52.5
24 MHz 49.7
8 MHz 46.1
It is obtained from comprehensive evaluation and is not tested in production.
Table17. Maximum Current Consumption in Sleep Mode

(1)
Maximum
Symbol Parameter Condition FHCLK Unit
TA = 85 ° C
200 MHz 45.5
192 MHz 44.2
External clock 180 MHz 42.6
(2)
enables all 100 MHz 32.0 mA
peripherals 48 MHz 22.6
24 MHz 19.0
Supply current 8 MHz 14.4
IDD
in sleep mode 200 MHz 27.2
192 MHz 26.7
The external
(2)
180 MHz 26.2
clock turns
100 MHz 20.9 mA
off all
48 MHz 17.3
peripherals
24 MHz 15.9
8 MHz 13.6
It is obtained from comprehensive evaluation and is not tested in production.
Table18. Typical and Maximum Current Consumption in Shutdown and Standby

Modes
(1) (2)
Typical Max
VDD/VB
Symbol Parameter Condition VDD/VBAT TA = Unit
AT = 3.3
= 2.6 V 85 °C
V
High-speed
Supply internal RC
current in oscillator and
IDD 1.5 1.9 10.9 mA
shutdown high-speed
mode external
oscillator are

off (no
independent
watchdog)
The low-
speed
external
3.5 4.4 6.3
oscillator and
Supply
RTC are in
current in
the off state uA
standby
The low-
mode
speed
external 3.8 4.7 6.7
oscillator and
RTC are on
Typical values are measured at TA = 25 ℃.
It is obtained by comprehensive evaluation and is not tested in production.
Figure11. Typical Current Consumption in Shutdown Mode vs. Temperature at

Different VDD
Table19. Comparison of typical current consumption in standby mode with

temperature at different VDD
VDD Voltage (V) Temperature (℃) Max TA = 85 ° C Unit
-40 3.2
2.6 0 3.3 uA
25 3.4
55 3.7
70 4.0
85 4.9
-40 4.0
0 4.2
25 4.2
3.3 uA
55 4.8
70 5.2
85 6.3
-40 119.5
0 4.7
25 5.0
3.6 uA
55 5.8
70 6.3
85 7.7
Internal peripheral current consumption
The current consumption of the built-in peripherals is listed in Table 18, and the
operating conditions of the microcontroller are as follows:
All peripherals are turned off unless otherwise specified.
⚫ The values given are calculated by measuring current consumption

– Turn off all peripheral clocks
– Turn on the clock of only one peripheral
Ambient temperature and VDD supply voltage conditions conform to electrical

characteristics.
Table20. Current Consumption of Built-in Peripherals

Built-in peripheral Typical value Unit
DMA1 3.0
AHB (up to 200 MHz) DMA2 4.6 μA/MHz
CRC 1.0
TMR2 9.2
TMR3 7.7
TMR4 9.2
TMR5 11.5
APB1 (up to 100 MHz) TMR6 6.2 μA/MHz
TMR7 3.8
TMR12 7.6
TMR13 6.5
TMR14 7.1

SPI2/I2S2 6.6
SPI3/I2S3 5.1
SPI4/I2S4 7.8
USART2 6.5
USART3 5.2
UART4 2.6
UART5 7.0
I2C1 7.1
I2C2 7.8
CAN 15.2
WWDG 5.5
PWR 6.2
BKP 6.2
I2C3 7.5
AFIO 7.2
GPIOA 7.2
GPIOB 5.7
GPIOC 3.6
GPIOD 4.0
GPIOE 5.3
SPI1/I2S1 8.4
USART1 7.2
APB2 (up to 100 MHz) USART6 6.1 μA/MHz
UART7 4.7
UART8 3.8
TMR1 11.7
TMR8 13.3
TMR9 8.4
TMR10 9.9
TMR11 9
ADC1+ADC2 5.2
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in the table below result from tests performed using a high-
speed external clock source, and under ambient temperature and supply voltage
conditions summarized in Table10.
Table21. High-speed external user clock characteristics

fOSCIN Crystal frequency 2.2V≤VDD≤3.6V 2 8 30 MHz

OSC_IN input pin 0.7

VHSEH - VDD
high level voltage VDD
V
OSC_IN input pin 0.3
VHSEL VSS -
low level voltage VDD
tw(HSE) OSC_IN high or
5 - -
tw(HSE) low time(1)
ns
tr(HSE) OSC_IN rise or fall
- - 20
tf(HSE) time(1)
CHTAL Recommended - 20 pF
matching
capacitance
DuCy(HSE) Duty cycle - 30 50 70 %
I HSE driving current 3 mA
VDD=3.3V,VIN=VSS
With 20pF load

tsu StatUp time 30 ms
Figure12. High-speed external clock source AC timing diagram
Low-speed external user clock generated from an external source
The characteristics given in the table below result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage
conditions summarized in Table10.
Table22. Low-speed external user clock characteristics


User External clock
fLSE_ext - 32.768 1000 KHz
source frequency(1)
OSC32_IN input pin
VLSEH 0.7 VDD - VDD
high level voltage
V
OSC32_IN input pin 0.3
VLSEL - VSS -
low level voltage VDD
tw(LSE) OSC32_IN high or
450 - -
tw(LSE) low time(1)
ns
tr(LSE) OSC32_IN rise or
- - 50
tf(LSE) fall time(1)
OSC32_IN input
Cin(LSE) - - 5 - pF
capacitance(1)
DuCy(LSE) Duty cycle - 30 - 70 %
OSC32_IN input
IL VSS ≤ VIN ≤ VDD - - ±1 μA
leakage current
Figure13. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 25 MHz

crystal/ceramic resonator oscillator. All the information given in this paragraph are
based on characterization results obtained with typical external components
specified in the table below. In the application, the resonator and the load capacitors
have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table23. HSE 4-25 MHz oscillator characteristics(1)(2)

fOSC_IN Oscillator frequency - 4 8 25 MHz
(3)
tSU(HSE) Startup time VDD is stabilized - 2 - ms
Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Guaranteed by characterization results, not tested in production.
tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a
stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator
and it can vary significantly with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in
the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and
selected to match the requirements of the crystal or resonator. CL1 and CL2 are
usually the same size. The crystal manufacturer typically specifies a load capacitance
which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board
capacitance) when sizing CL1 and CL2.
Figure14. Typical application with an 8 MHz crystal
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz
crystal/ceramic resonator oscillator. All the information given in this paragraph are
based on characterization results obtained with typical external components
specified in the table below. In the application, the resonator and the load capacitors
have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table24. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)


tSU(LSE) Startup time VDD is stabilized - 150 - ms
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF
to 15 pF range selected to match the requirements of the crystal or resonator. CL1
and CL2, are usually the same size. The crystal manufacturer typically specifies a
load capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray
where Cstray is the pin capacitance and board or trace PCB-related capacitance.
Typically, it is between 2 pF and 7 pF.
Figure15. Typical application with a 32.768 KHz crystal
5.3.7 Internal clock source characteristics
High-speed internal (HSI) RC oscillator
Table25. HSI oscillator characteristics(1)

fHSI Frequency - - 48 - MHz
DuCy(HSI) Duty cycle - 45 - 55 %
User-trimmed with
the RCC_CTRL - - 1(2)
%
Accuracy of the HSI register
ACCHSI
oscillator TA = -40 ~ 85 °C -2.5 - 2
TA = 0 ~ 70 °C -1.5 - 1.5
TA = 25 °C -1 - 1
HSI oscillator startup
tSU(HSI)(3) - - - 10 μs
time

HSI oscillator power

IDD(HSI)(3) - 240 275 μA
consumption -
VDD = 3.3 V, TA = -40~85 °C, unless otherwise specified.
Figure16. HSI oscillator frequency accuracy vs. Temperature
Low-speed internal (LSI) RC oscillator
Table26. LSI oscillator characteristics(1)

fLSI(2) Frequency - 30 40 60 kHz
VDD = 3.3 V, TA = -40 to 105 °C, unless otherwise specified.
5.3.8 Wakeup time from low-power mode
The wakeup times given in the table below is measured on a wakeup phase with the
HSI RC oscillator. The clock source used to wake up the device depends from the
current operating mode:
⚫ Stop or Standby mode: the clock source is the HSI RC oscillator

⚫ Sleep mode: the clock source is the clock that was set before entering Sleep
mode
All timings are derived from tests performed under ambient temperature and VDD

supply voltage conditions summarized in Table10.
Table27. Low-power mode wakeup timings
Symbol Parameter Typ Unit
tWUSLE
Wakeup from Sleep mode 3.3 μs
EP(1)
Wakeup from Stop mode (regulator in run mode) 280

（1）
tWUSTOP μs
Wakeup from Stop mode (regulator in low- power
320
mode)
tWUSTDBY Wakeup from Standby mode（EOPB0 = 1） 70

ms
（1）
Wakeup from Standby mode（EOPB0 = 0） 270
wakeup times are measured from the wakeup event to the point in which the user application
code reads the first instruction.
5.3.9 PLL characteristics
Table28. PLL characteristics

Symbol Parameter MIN TYP MAX Unit
Divided reference
fDIV 30 375000 KHz
frequency range
Total output
fOUT 1.88 375 MHz
frequency range
Period jitter (P-P) +/-2.5%
PP ps
(max) output cycle
Power dissipation 20@ 30MHz
IPD uA
(nom) (/1 output)
Reset pulse width
tRST 5 µs
(min)
Lock time (min 500 div.
tLOCK us
allowed) reference cycles
5.3.10 Memory characteristics
The characteristics in Table 30 are given at TA = 25 °C and VDD = 3.3 V.
Table29. Internal Flash memory characteristics

Typ
Symbol Parameter Conditions Unit
Bank Size

1 2 4 8 16 MB
Programming 20 μs
TPROG -
time
Page (4 KB) erase 60 60 50 35 ms
tERASE -
time
tME Mass erase time - 7 10 15 30 60 s
Programming 9.3
IDD Supply current mode mA
Erase mode 2.2
Table30. Internal Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Typ Max Unit
NEND Endurance TA = -40 ~ 105 °C 100 - - kcycles

tRET Data TA = 85 °C 20 - - years
retention
5.3.11 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from
tests performed under the conditions summarized in Table10. All I/Os are CMOS and
TTL compliant.
Table31. I/O static characteristics

Symb Parameter Min Typ Max Unit
Schmitt Trigger Low to High Threshold
VT+ Point with Pull-up/down resistor 1.75 1.97 2.18 V
Disable
Schmitt Trigger High to Low Threshold
VT- Point with Pull-up/down resistor 1.13 1.31 1.52 V
Disable
VT+PUIPD Point with Pull-up/down resistor 1.76 1.97 2.18 V
Enable
VT-PUIPD Point with Pull-up/down resistor 1.13 1.30 1.50 V
Enable
VT+PU 1.72 1.92 2.14 V
Point with Pull-up Resistor Enable
VT-PU Schmitt Trigger High to Low Threshold 1.09 1.27 1.48 V

Point with Pull-up Resistor Enable

VT+PD 1.79 2.02 2.24 V
Point with Pull-down Resistor Enable
VT-PD 1.15 1.34 1.54 V
Point with Pull-down Resistor Enable
Input Leakage Current@VI=3.3V or
2n 51n A
0V@125℃
II
Input Leakage Current@VI=3.3V or
2n 19n A
0V@85℃
Tri-state Output Leakage Current
IOZ 2n 51n A
@Vo=3.3V or 0V
RPU Pull-up Resistor 27.37K 38.26K 59.09K Ω
RPD Pull-down Resistor 26.1K 41.58K 75.84K Ω
VOL Output Low Voltage 0.4 V
VOH Output High Voltage 2.4 V
IOL Low Level Output Current @VOL(max) 9.21 14.1 18.96 mA
IOH High Level Output Current @VOH(min) 22.17 31.45 40.44 mA
The following IOs: IOA0, IOA1, IOC0, IOC4, IOC13, IOC14, IOC15, IOF0, IOF1, IOF2, IOF3,
IOF4, IOF5 do not support the input of Schmitt hysteresis.
5.3.12 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent
pull-up resistor, RPU (see the table below).
Unless otherwise specified, the parameters given in the table below are derived from
tests performed under ambient temperature and VDD supply voltage conditions
summarized in Table10.
Table32. NRST pin characteristics

NRST input low level
VIL(NRST)(1) - -0.5 - 0.8
voltage
V
NRST input high level
VIH(NRST)(1) - 2 - VDD + 0.3
voltage
NRST Schmitt trigger
Vhys(NRST) voltage - 500 - mV
-
hysteresis
Weak pull-up
RPU VIN = VSS 30 40 50 kΩ
equivalent resistor
NRST input filtered
VF(NRST)(1) - - 24 33.3 μs
pulse
VNF(NRST)(1) NRST input not filtered - 66.7 46 - μs

pulse
Guaranteed by design.
Figure17. Recommended NRST pin protection
The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL (NRST) max level
specified in Table 40. Otherwise the reset will not be taken into account by the device.
5.3.13 TMR timer characteristics
The parameters given in the table below are guaranteed by design.
Refer to 5.3.11 for details on the input/output alternate function characteristics

(output compare, input capture, external clock, PWM output).
Table33. TMRx(1) characteristics

- 1 - tTMRxCLK
tres(TMR) Timer resolution tim fTMRxCLK =
5.6 - ns
180MHZ
Timer external clock 0 fTMRxCLK/2 MHz
fEXT frequency on CH1 to -
CH4 0 50 MHz
TMRx is used as a general term to refer to the TMR1 to TMR14.
5.3.14 Communications interfaces
I2C interface characteristics
The V32G410x I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL
mapped to are not ”true” open-drain.

When configured as open-drain, the PMOS connected between the I/O pin and VDD
is disabled, but is still present.
The I2C characteristics are described in the table below. Refer also to 5.3.12 I/O port
characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table34. I2C characteristics

Standard mode Fast mode
(1)(2)
Symbol Parameter I2C I2C(1)(2) Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -
μs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
(3)
th(SDA) SDA data hold time - 3450 - 900(3)
tr(SDA) SDA and SCL rise
- 1000 - 300 ns
tr(SCL) time
tf(SDA) SDA and SCL fall
- 300 - 300
tf(SCL) time
Start condition hold
th(STA) 4.0 - 0.6 -
time
μs
Repeated Start
tsu(STA) 4.7 - 0.6 -
condition setup time
Stop condition setup
tsu(STO) 4.0 - 0.6 - μs
time
Stop to Start
tw(STO:STA) condition time (bus 4.7 - 1.3 - μs
free)
Capacitive load for
Cb - 400 - 400 pF
each bus line
fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4
MHz to achieve the fast mode I2C frequencies.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to
bridge the undefined region on the falling edge of SCL.
Figure18. I2C bus AC waveforms and measurement circuit(1)

Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Table35. SCL frequency (fPCLK1 = 36 MHz, VDD = 3.3 V)(1)(2)

I2C_CLKCTRL value
fSCL(kHz)
RP = 4.7 kΩ
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
RP = External pull-up resistance, fSCL = I2C speed.
For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed
ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy
of the external components used to design the application.
SPI-I2S characteristics
Unless otherwise specified, the parameters given in Table 44 for SPI or in Table 45
for I2S are derived from tests performed under ambient temperature, f PCLKx
frequency and VDD supply voltage conditions summarized in Table10.

Refer to 5.3.11 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table36. SPI characteristics

fSCK SPI clock Master mode - 36
(2)(3)
MHz
(1/tc(SCK))(1) frequency Slave mode - fPCLK/2
tr(SCK) SPI clock rise and Capacitive load: C =
- 8 ns
tf(SCK) fall time 30 pF
(1)
tsu(NSS) NSS setup time Slave mode 4tPCLK - ns
th(NSS)(1) NSS hold time Slave mode 2tPCLK - ns
Master mode, fPCLK =
tw(SCKH)(1) SCK high and low
90 MHz, 22 32 ns
tw(SCKL)(1) time
prescaler = 4
tsu(MI)(1) Data input setup Master mode 5 -
(1)
ns
tsu(SI) time Slave mode 5 -
th(MI)(1) Data input setup Master mode 5 -
(1)
ns
th(SI) time Slave mode 4 -
Data output access Slave mode, fPCLK =
ta(SO)(1)(4) 0 3tPCLK ns
time 20 MHz
Data output disable
tdis(SO)(1)(5) Slave mode 2 10 ns
time
Data output valid Slave mode (after
tv(SO)(1) - 25 ns
time enable edge)
Data output valid Master mode (after
tv(MO)(1) - 5 ns
time enable edge)
Slave mode (after
th(SO)(1) 15 -
Data output hold enable edge)
ns
time Master mode (after
th(MO)(1) 2 -
enable edge)
Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
Figure19. SPI timing diagram - slave mode and CPHA = 0

Figure20. SPI timing diagram - slave mode and CPHA = 1(1)
(1)
Figure21. SPI timing diagram - master mode

Table37. I2S characteristics

Master mode (data: 16
fCK I2S clock bits, audio frequency = 48 1.522 1.525
MHz
1/tc(CK) frequency kHz)
Slave mode 0 6.5
tr(CK) I2S clock rise
Capacitive load: C = 50 pF - 8
tf(CK) and fall time
(1)
tv(WS) WS valid time Master mode 3 -
th(WS)(1) WS hold time Master mode 2 -
tsu(WS)(1) WS setup time Slave mode 4 -
th(WS)(1) WS hold time Slave mode 0 -
tw(CKH)(1) CK high and Master fPCLK = 16 MHz, 312.5 -
tw(CKL)(1) low time audio frequency = 48 kHz 345 -
tsu(SD_MR)(1) Data input Master receiver 6.5 -
tsu(SD_SR)(1) setup time Slave receiver 1.5 -
ns
th(SD_MR)(1)(2) Data input hold Master receiver 0 -
th(SD_SR)(1)(2) time Slave receiver 0.5 -
Data output Slave transmitter (after
tv(SD_ST)(1)(2) - 18
valid time enable edge)
Data output Slave transmitter (after
th(SD_ST)(1) 11 -
hold time enable edge)
Data output Master transmitter (after
tv(SD_MT)(1)(2) - 3
valid time enable edge)
Data output Master transmitter (after
th(SD_MT)(1) 0 -
hold time enable edge)
Guaranteed by design and/or characterization results.
Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPCLK =125 ns.
Figure22. I2S slave timing diagram (Philips protocol)(1)

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent
before the first byte.
Figure23. I2S master timing diagram (Philips protocol)(1)

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent
before the first byte.
CAN (controller area network) interface
Refer to 5.3.11 for more details on the input/output alternate function characteristics
(CAN_TX and CAN_RX).
5.3.15 12-bit ADC characteristics
Table38. ADC Characteristics

Parameter Condition Minimum Typical Maximum Unit
Power supply voltage
AVDD_ADC - 2.6 3.3 3.63 V
VDD_ADC - 0.81 1.1 1.21 V
IAVDD_ADC @ fs=2msps 500 uA
IVREFP_ADC @ fs=2msps 80 uA
IVDD_ADC @ fs=2msps 5 uA
PowerDown 30 nA
Reference voltage
VEREFP_ADC - 1.8 3.3 3.63 V

VREFN_ADC - 0 V
Analog input
Input range ADC_SDIF=0 VREFN VREFP V
ADC_SDIF=1 2* (VREFP-VREFN) V
Input common mode (VREFP-VREFN)/2 V
Input sampling capacitor Single-ended 5 pF
Input equivalent 1000 Ω
impedance
Time sequence
Clock cycle (Ts) 3333 nS
Duty cycle 40% 50% 60% Ts
SOC setup time 2 nS
SOC hold time 2 nS
Sampling time 1.5 Ts
Sampling + conversion 14 Ts
time
Channel selection to EOC 1.5 11 Ts
time
ADC Performance (Single Ended) 1
THD -75 dB
ENOB 10.5 bit
SNDR 65 dB
DNL ± 1.5 LSB
INL ±2 LSB
Calibrable offset -16 16 LSB
ADC Performance (Differential) 1
THD -75 dB
ENOB 11 bit
SNDR 68 dB
DNL ± 1.5 LSB
INL ±2 LSB
Calibrable offset -16 16 LSB
Fin=100kHz, fs=28Msps, power supply voltage 2.97 ~ 3.63 V,-40 ℃ ~ 125 ℃;
In the case of single-ended input, the performance of odd channels passes through two-stage
switches, and the performance decreases slightly;
5.3.16 Temperature sensor characteristics
Table39. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature - ±1 ±2 ºC
(1)(2)
Avg_Slope Average slope 2.2898 mV/ºC
V25(1)(2) Sample value at 25 ºC 2646

tSTART(3) Startup time - - 6 μs

(3)(4)
TS_temp ADC sampling time when reading 2 - - μs
the temperature
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 50 °C from one chip to another).
The internal temperature sensor is more suited to applications that detect temperature
variations instead of absolute temperatures. If accurate temperature readings are needed, an
external temperature sensor part should be used.
Shortest sampling time can be determined in the application by multiple iterations.
Obtain the temperature using the following formula:
Temperature (in °C) = (Vsense - V25) / Avg_Slope. Where,
V25 = VSENSE value for 25° C and
Avg_Slope = Average Slope for curve between Temperature vs. V SENSE (given in mV/°
C).
Figure24. VSENSE vs. temperature
5.4 ESD electricial character
Table40. ESD electricial parameter

Human Body Model(HBM) -4000 4000 V
VESD
Charged Device Model(CDM) -1000 1000 V

stroage V32G410x Datasheet
6 stroage
6.1 Hmidity sensitivity
Table41. MSL summary

MSL Out-of-bag floor life Comments
1 Unlimited ≤30°C / 85%RH
2 1 year ≤30°C / 60%RH
2a 4 weeks ≤30°C / 60%RH
3 168 hours ≤30°C / 60%RH
4 72 hours ≤30°C / 60%RH
5 48 hours ≤30°C / 60%RH
5a 24 hours ≤30°C / 60%RH
6 Time on Label(TOL) ≤30°C / 60%RH
The moisture sensitivity level of V32G410x is MSL3.
6.2 Storage conditions
Table42. Bagged storage conditions

Packaging method method Vacuum
Storage temperature -55°C ~150°C

Reflow soldering process V32G410x Datasheet
7 Reflow soldering process
All Wangao chips provided to customers are lead-free RoHS compliant products.
The reflow soldering process recommended in this article is a lead-free reflow

soldering process, which is suitable for the pure lead-free process of lead-free solder
paste. If customers need to use lead solder paste, please contact the smart chip FAE
connect.
See Table43 for lead-free reflow profile conditions. This table is for reference only.
Table43. Reflow profile conditions

QTI typical SMT reflow profile conditions(for reference
only)
Step Reflow condition
Environment N2 purge reflow usage (yes/no) Yes, N2 purge used
If yes, O2 ppm level O2 < 1500 ppm
A Preheat ramp up temperature 25°C -> 150°C
range
B Preheat ramp up rate 1.5~2.5 °C /sec
C Soak temperature range 150°C -> 190°C
D Soak time 80~110 sec
E Liquidus temperature 217°C
F Time above liquidus 60-90 sec
G Peak temperature 240-250°C
H Cool down temperature rate ≤4°C /sec
The figure below shows a typical lead-free reflow mode.
Figure25. A typical lead-free reflow mode

Package information V32G410x Datasheet
8 Package information
8.1 LQFP100 14 x 14 mm package information
Figure26. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline
Drawing is not in scale.

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.063
A1 0.05 - 0.15 0.002 - 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.20 0.26 0.007 0.008 0.010
c 0.10 0.127 0.20 0.004 0.005 0.008
D 16.00 BSC. 0.630 BSC.
D1 14.00 BSC. 0.551 BSC.
E 16.00 BSC. 0.630 BSC.
E1 14.00 BSC. 0.551 BSC.
e 0.50 BSC. 0.020 BSC.
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF. 0.039 REF.
Values in inches are converted from mm and rounded to 3 decimal digits.

8.2 LQFP64 10x10mm package information
Figure27. LQFP64 10x10mm 64 pin low-profile quad flat package outline
1.60MAX
1.45
1.40
10.10
10.00 SQ
1.35 Unit: mm
0.75
0.60
0.45
9.690 0.69
0.64
0.59
64 49
1 48
1.00 REF
PIN1 13°
12°
11°
0.08
12.00 SQ
12.20
11.80
0.20
0.08
7.0°
3.5°
0.0°
0.15
0.05
16 33
17 32
0.50 BSC 0.27

0.18

8.3 QFN48 7 x 7 mm package information
Figure28. QFN48 – 7 x 7 mm 48 pin low-profile quad flat package outline

8.4 Thermal characteristics
The maximum chip junction temperature (T Jmax) must never exceed the values given
in Table9.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be

calculated using the following equation:
Tjmax = Tamax + (Pdmax x ΘJA)
Where:
⚫ Tamax is the maximum ambient temperature in °C,

⚫ ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
⚫ Pdmax is the sum of PINTmax and PI/Omax (Pdmax = PINTmax + PI/Omax),
⚫ PINTmax is the product of IDD and VDD, expressed in Watts. This is the
maximum chip internal power.
PI/Omax represents the maximum power dissipation on output pins where:
PI/Omax = Σ(VOL x IOL) + Σ((VDD – VOH) x IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level
in the application.
Table44. Package thermal characteristics

symbol Parameter value unit
ΘJA Thermal impedance from junction to environment 53.6 °C/W

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V32G410x

2.2 Overview .......................................................................................... 14

2.2.2 Memory protection unit (MPU) ................................................. 15

2.2.3 Flash memory ....................................................................... 16

2.2.4 Cyclic redundancy check (CRC) calculation unit ......................... 16

2.2.5 Embedded SRAM ................................................................... 16

2.2.6 Nested vectored interrupt controller (NVIC) .............................. 16

2.2.7 External interrupt/event controller (EXTI) ................................. 17

2.2.8 Clocks and startup ................................................................. 17

2.2.9 Boot modes........................................................................... 18

2.2.10 Power supply schemes............................................................ 19

2.2.11 Power supply supervisor ......................................................... 19

2.2.12 Voltage regulator ................................................................... 19

2.2.13 Low-power modes .................................................................. 19

2.2.14 Direct Memory Access Controller (DMA) .................................... 20

2.2.15 Real-time clock (RTC) and backup registers .............................. 20

2.2.16 Timers and watchdogs (TMR/WDG) .......................................... 21

2.2.17 Inter-integrated-circuit interface (I2C) ..................................... 23

2.2.18 Universal synchronous/asynchronous receiver transmitters (USART)

2.2.19 Serial peripheral interface (SPI) ............................................... 24

2.2.20 Inter-integrated sound interface (I2S) ...................................... 25

2.2.21 Controller area network (CAN)................................................. 25

2.2.22 General-purpose inputs/outputs (GPIO) .................................... 25

2.2.23 Remap capability ................................................................... 25

2.2.24 Analog to digital converter (ADC) ............................................. 25

2.2.25 Temperature sensor ............................................................... 26

2.2.26 Serial wire JTAG debug port (SWJ-DP)...................................... 26

Vango Technologies, Inc. 2 / 84

3 Pinouts and pin descriptions ...................................................................... 27

4 Memory mapping ........................................................................................ 44

5.1.1 Minimum and maximum values ............................................... 45

5.1.2 Typical values ....................................................................... 45

5.1.3 Typical curves ....................................................................... 45

5.1.4 Loading capacitor................................................................... 45

5.1.5 Pin input voltage .................................................................... 46

5.1.6 Power supply scheme ............................................................. 46

5.1.7 Current consumption measurement.......................................... 47

5.2 Absolute maximum ratings ................................................................. 48

5.3 Operating conditions .......................................................................... 49

5.3.1 General operating conditions ................................................... 49

5.3.2 Operating conditions at power-up/ power-down ......................... 49

5.3.3 Embedded reset and power control block characteristics ............. 49

5.3.4 Embedded reference voltage ................................................... 51

5.3.5 Supply current characteristics.................................................. 52

5.3.6 External clock source characteristics ........................................ 58

5.3.7 Internal clock source characteristics ......................................... 62

5.3.8 Wakeup time from low-power mode ......................................... 63

5.3.9 PLL characteristics ................................................................. 64

5.3.10 Memory characteristics ........................................................... 64

5.3.11 I/O port characteristics ........................................................... 65

5.3.12 NRST pin characteristics ......................................................... 66

5.3.13 TMR timer characteristics ........................................................ 67

5.3.14 Communications interfaces ..................................................... 67

5.3.15 12-bit ADC characteristics ....................................................... 74

5.3.16 Temperature sensor characteristics .......................................... 75

5.4 ESD electricial character ..................................................................... 76

6.2 Storage conditions ............................................................................. 77

Vango Technologies, Inc. 3 / 84

7 Reflow soldering process............................................................................ 78