 The process of conversion from an analog data to digital is done by using analog to

digital converter i.e. A/D or ADC.

 The process of conversion from an digital data to analog is -done by using digital to
analog converter i.e. D/A or DAC.
 Types of DAC’s are:

(a) Binary weighted resistor DAC (b) R-2R ladder DAC.

 The R-2R ladder DAC is the most popular digital to analog converter.
 The resolution of DAC is the defined as the smallest change that occur in the analog
output as a result of the change in the digital input.
 The disadvantage of weighted resistor DAC is that number of different value resistors
are required for each bit position of the digital input.
 Types of ADC’s are:

(a) Flash-type ADC (b) Single-slope ADC (c) Dual-slope ADC (d) Continuous
counter type ADC (e) Successive-approximation type ADC.

 Quantization is the process of approximation used in digitizing samples.

 Counter type is the simplest ADC and flash type is the fastest.
 The most popular application of ADC is in digital voltmeters.
 The flash type ADC is the fastest ADC.
 The dual-slope ADC is the slowest type but at the same type it is cheaper and gives &
excellent accuracy.

Q 1. Give performance parameters of DAC or D/A converters.

Ans. 1. Resolution: Resolution can be defined in two ways

(a) A DAC that can provide number of different analog output values is called resolution.

For a DAC having n-bits

Resolution .

(b) A DAC is which the ratio of change in output voltage resulting from a change of LSB (i.e. 1
least significant bit) at the digital inputs is known as resolution.

Resolution for n-bit DAC is given by:

Input-output equation can also be obtained for DAC, if resolution is given

Where, Vo = Resolution x D, Vo = Output voltage, D = Decimal vã1ue of the digital input.

2. Accuracy: It is defined as the difference between the actual analog output and the
expected analog output when a given digital input is applied. It is expressed in percentage.

In ideal case, the accuracy of DAC should be, at worst, of its LSB.

3. Conversion Time or Setting Time: It is the time required for conversion of analog signal
into its digital equivalent. It is dependent on amplifiers output and switches response time.

4. Stability: When all the parameters such as gain, linearity error, monotonicity and offset
must be specified over the power supply ranges and full temperature then these
parameters represent the stability of the converter.

5. Monotonicity: If a converter does not miss any step backward during its entire range
stepped by a counter then it is said to have a counter having good monotonicity.

Q -2. An 4 bit DIA converter has an output range of 0 to 1.5 V. Define its resolution.

Ans. Given n = 4 = number of bits, Full scale output

1. Resolution:

Thus the output voltage can have 16 different values including zero.

2. Resolution:

Thus, an input change of 1 LSB changes the output by 100 mV.

Q 3. Calculate the step size and analog output for 8-bit ADC. When input is

10000000. Reference voltage Vr = +50V is given.

Ans. Given

Q 4. Following fig. shows the D1A converter with op-amp. Calculate the output if the input
digital signal is 1110. Assume 1 binary = +5V.

Ans. Binary data:

B3 B2 B1 B0  1110

Let I1, I2 and I3 be the currents flowing through the respective resistors The value of
currents are:
As, the op-amp has a very high input impedance. Thus, the currents I0 to I3 flow through 1K
ohm resistance.

Q 5. Draw only the block diagram of continuous counter type ADC.

Ans.

Block diagram of continuous counter type ADC.

Q 6. On what factors does the percentage resolution of D/A converter depend?

Ans. The percentage resolution of D/A converter is given by:

So, it depends on full scale output voltage ‘V0Fs’ and the number of bits used in DAC

i.e. ‘n’.
Q 7. Which is the fastest ADC and why?

Ans. Flash type ADC is the fastest ADC. Its main advantage is that its conversion of

analog to digital taken place simultaneously and not sequentially. Typically the conversion
time of flash type ADC is l00ns or less: Hence it is the fastest ADC.

Q 8. Comment on the parameters which serve to describe the quality of performance of a

D/A converter.

Ans. There are basic three parameters which describe the quality of performance of D/A
converter.

1. Resolution : It is the smallest possible change in the analog output voltage. Resolution
should be as high as possible.

2. Accuracy: It indicates how close the analog output voltage is to its theoretical value it is
the deviation of actual output from the theoretical value.

3. Linearity : The relation between the digital input and analog output should be linear.

Q 9. Determine the resolution of the output from a DAC that has a 12-bit input.

Ans. Resolution is given by:

Resolution =

Q. 10. List the various types of AID converters.

Ans. Various types of A/D converters use different principles of operation for conversion.

1. Flash type or parallel type A/D converter. 2. Counter type A/D converter.

3. Successive Approximation A/D converter. 4. Dual slope A/D. 5. Single slope A/D.

Q 11. On what basis do we select a particular type of A/D converter, for use?

Ans. There are various parameters on basis of which we select a particular type of A/D
converter like.

1 Conversion time: Time taken to convert a analog signal into digital It must be less1

2 Speed of operation: The speed of operation also decides the type of A/D converter for
particular application It is decided with the help of clock of frequency
3 Cost: Cost must be according to budget of application Cost depends upon number of
comparators used

4 Complexity: Simple applications require less complex circuit ND converter

5 Accuracy: Based on accuracy a particular ND converter is decided

Q 12 What is the need of converting digital data into analog data.

Ans. The digital representation of a signal makes storage, processing simpler and its
transmission is much easier. Once the transmission and processing etc is done the signal we
need should be in analog form. To convert the digital signal to its analog form Digital to
analog conversion is required.

Q 13 What is the advantage of the R-2R ladder DAC over the weighted resistor type DAC?

Ans. Advantages of R-2R Ladder:

1. R/2R ladder DAC need only two value of resistors whereas in weighted resistor DAC
several resistors are required having different values

2. Due to small resistance spread, the R/2R ladder DAC can be fabricated monolithically with
high accuracy and stability In weighted type, it is difficult to achieve and maintain accuracy
and resolution

3. The number of bits can be increased in R/2R ladder DAC by adding more sections of same
R/2R values whereas it is not possible in the weighted type DAC with same value resistors.

Q 14. Draw the circuit of a counter type AID converter and explain its operation.

Ans. There are various types of A/D converter. One of the mostly used is counter method.
The block diagram is as:

Initially “start’ signal is send to Gate and control box Clock pulses are also applied Two input
analog input voltage and Ref voltage are given to comparator. If VA> VR, then comparator
goes high and gate opens, counter starts counting until analog input voltage is greater than
Ref voltage. After that signal is amplified by level amp and given to binary ladder. Binary
ladder provides digital output. Counter may count in upward or downward direction.

This method is simple in construction, easy to design and less expensive.

Q 15. With the help of a neat diagram explain parallel A/D converter.

Ans. Parallel A/D is used is much more due to its high speed. The only disadvantage is that
its hardware (no. of comparators) increase with the no. of bits. Va is analog, voltage and
VR is reference’ voltage.

A 3-bit parallel-comparator AID converter is shown in fig. Va is the analog voltage is be

converted into digital form. The voltage corresponding to full scale is V from which the
reference voltages VR1, VR2…. (See Fig.) are generated using the resistor network. The
voltage Va is

compared simultaneously with the reference voltages by using comparators A 7-bit output
obtained from the comparators which is stored in latches This 7-bit digital signal is convert
to a 3-bit output by using a decoder circuit The comparator outputs and the 3-bit digit
output for each interval of the analog voltage are given in Table (A)

The principle of parallel-comparator AID conversion is the simplest in concept and fasts Its
main disadvantages are rapid increase in the number of comparators with the number bits [
 comparators are required for an N-bit converter] and the corresponding
complications of the decoder circuit

Table (A) Comparator outputs and digital output of parallel-comparator AID converter

17 Explain the operation of successive approximation type of ADC

Ans. Successive approximation is one of the most widely used popular method due its
efficiency The block diagram of SAR ADC s as shown:

Working: Initially, let us set the MSB bit of SAR register i.e. d1 = 1. It is applied to 4-bit D to A
converter i.e. as 1000. The D/A converter will generate its analog value and send to control
logic The output of control logic is VR. Now at the comparator, there are two inputs
VR (Reference voltage) and VA (Input analog).

If VR > VA  output of comparator is low and bit d1 is reset correspondingly.

If VR <VA  output of comparator is high and bit d1 remains high.

The same procedure is repeated for all bits i e for d2, d3,…. dn, and output may be taken in
serial or parallel manner.

Advantage: The conversion time is fixed as it does not depend upon amplitude of analog
input.
 Q.18 An 8-bit successive approximation converter (SAC) has a resolution of 15 mV What
will its, digital output be for an analog input of 2.65 V ?

Ans. Analog input = 2.65 V

Resolution = 15 mV

Now 176 would produce 2.64 V and 177 would produce 2.65 V. Hence VA = 2.65V The digital
result will be (176)10 = (10110000)2

Q 19 Define linearity, settling time, sensitivity and accuracy of A/D and D/A converters.

Ans. For D/A converters

i. Linearity: The linearity of the converter specifies the accuracy with which the ideal
performance is followed Output of DIA converter must be each step up (down) in the digital
input so as to cause an increase (decrease) in the analog output The linearity should be at

least equal to or better then

(ii) Setting Time: Whenever a digital input is applied to D/A converter, sometimes output
sets to a value within some specific limit of the final value The limit range is

LSB or less. This parameter tells the speed of D/A converter and t can be calculated by
use o switches, amplifier, resistors etc. in the device.

i. Accuracy: It is a measure of the difference between actual output and expected output. It is
given as a percentage of the maximum output voltage. If the maximum output voltage i.e.

full scale deflection is 5V and accuracy is then, the maximum error is x 5 =

0.0005 V or 5mV. Ideally the accuracy should be better than 0.5 of LSB.

In an 8-bit converter LSB is or 0.39% of full scale. The accuracy should be better
than 0.2%.

(iv) Sensitivity : Due to change in temperature the output of D/A converter should not
change. But practically the value of resistances and operational amplifier parameters change
with variation in temperature as analog output is a function of temperature.
For AID converters

(i) Linearity: Linearity is basically a ‘best straight line’. Linearity of a converter directly
determines the relative accuracy of the converter. It is the difference of errors betweens the
nominal and actual ratios to the full scale analog value corresponding to a
given digital input and independent of full scale calibration. The linearity error should be less

than

(ii) Conversion Time or Setting Time : It is the -time refers to the time requires for a
complete measurement by analog to digital converter.

OR

It is the time required for conversion of analog signal into its digital equivalent. It is
dependent on the amplifiers output and switches response time.

(iii) Accuracy : The accuracy of a given ADC i.e. analog to digital converter determines the
number of bits which can be usefully provided.

The accuracy of an ADC consists of quantization error system noise etc. Typical values are
0.02% of the full scale reading.

(iv) Sensitivity : Due to change in temperature the output of AID converter should not
change. But the value of resistances and operational amplifier change with change in
temperature.
Q 20. What is a voltage to frequency converter? How is it used for designing AID

converter?

Ans. Voltage to frequency converter:

It is as shown in

Here the input analog voltage is integrated and fed to a comparator. To the comparator, a
reference voltage Vref is applied. Whenever input voltage exceeds the comparator
reference voltage the comparator changes the state. This resets the integrator and the
process repeats itself. The integration cycles are counted in a counter for fixed time
duration. The output of counter gives the desired digital output.

If the integrator is realized by an inverting amplifier and has time constant then the output
of integrator at time ‘t’ is given by:

If the Vref is the comparator reference voltage, then the time t = T and is given by:

The frequency of the integration cycles is given by:

Here, integrator time constant ‘t’ and ‘Vref’ are constants and it will be seen that output
frequency. proportional to input voltage. Such a comparator is able to handle unipolar
analog signals.

Q 21. Describe the working of a successive approximation AID converter with the help of a
suitable diagram and compare its performance in terms of speed, accuracy and resolution
with other ADCs.

Ans. Successive Approximation A/D Converter: It is the most widely used A/D converter. It
has more complex circuitry than the digital ramp A/D converter but it has much shorter
conversion time. For n-bit A/D converter n-successive steps are required for completing the
approximation process.

The various functional brakes of successive approximation A.D converter are

1. Comparator -

2. D/A converter (Binary ladder may be used)

3. Control logic

4. Successive approximation register (SAR)

SAR is consists of flip-flops and level amplifiers. It is as shown in fig.

The control logic is used to set or reset the flip-flops. The O/P of there flip-flops are given to
level amplifiers and then to D/A converter which is a binary ladder network. It gives digital
O/P’s as well as the analog reference voltage.

Initially the control logic resets all the flip-flops. There are three basic conditions:
1. If i.e. reference voltage from D/A converter is. less than the input analog voltage
then MSB (most significant bit) is set to 1 by control logic.

2. . If then MSB is reset to (zero) ‘0’ and next bit is set to ‘1’.

3. If then the control logic disables the clock to flip flops and we can get digital

O/P from SAR by using latches.

For example : If 4 bit SAR is used.

Q 22 Draw and explain the basic block diagram of (i) voltage of frequency conversion and
(ii) voltage of time conversion

Ans. (i) Voltage of frequency A/D Converter: It s as shown in fig.

The output of the voltage to frequency converter is applied at the clock input of the
counter.
Let Va be the analog input given to the integrator at time t = 0. The output Vo is given by:

From (1) it is clear that the output of integrator decreases as it increases As long as Vo> —
VR, the output Vd of comparator will be low i e ‘0’ At time t = T1 Vo will become equal to -
VR and Vd will become high i e ‘1’ Vd is given to the reset logic which closes the switch for
discharging of capacitor in integrator Thus, Vo again return to ‘0’ The capacitor again
discharges in time T2 when T2 <<T1.

When the increasing value of Vo becomes jut greater than —VR, again Vd gives low value
Hence pulse width of Vd is very small. The reset logic closes the switch for sufficient time to
discharge the capacitor completely. Following fig. shows the variation of Vd and Vo w.r.t.
time ‘t’. The Vd output from voltage to frequency converter is given as the clock input to the
counter provided enable i.e.

The frequency of V0 and Vd is given as:

Thus, frequency of voltage to frequency converter is directly proportional to the input-
analog voltage.

(ii) Voltage to time AID Converter:

The block diagram of voltage of time A/D converter is shown above in fig.

Va is given to the comparator and —VR is given to the integrator. If VEN = 1 switch is open
and if VEN = 0 switch is closed in the inegrator circuit.

Let VEN = 1, Thus, switch is open and the output of the integrator will be:

Here, Vo is increasing with time. When Vo <Vs, the output of comparator goes high i.e. thus
circuit is given to the counter. The counter counts at each circuit pulse. When, Vo = Va,
Vd becomes low, thus output of AND gate goes low. No circuit pulse to counter stops
counter bps and the final value is stored in the counter which is the digital equivalent of Va.

When VEN = 0, switch is closed in the integrator, and the capacitor is discharge until Vo

reaches ‘0’.

For t = T and Vo = Va

The equation (1) becomes:

Thus, T is proportional to Va.

Q 23 Write note on the following Binary ladder D/A. converter.

Ans Binary ladder D/A converter In a binary ladder D/A converter only two valued
resistance R and 2R are used as shown in diagram

The OP amp is an inverting amplifier By solving resistance N/W in parallel and series, finally
voltage at node B is.

Q 24. How many bits are required for a DAC, so that Its full scale output is 12.6 V and
resolution 20 mV?

Ans.

So, DAC required 10 bits.

Q 25. Explain the operation of dual-slope A/D converter.

Ans. The dual slop A/D converter provide very much accuracy and so mostly used.

An analog input voltage is applied to Ramp Generator. The output of Ramp Generator
app1ied to comparator. The output of comparator is given to ‘AND’ gate. The second output
‘AND’ gate is clock pulse. When input is high for AND gate clock pulse will be given to m-r.
Counter is initially reset by control logic. Now counter counts up and binary output in form
is provided. When counter stops, switch control again control the whole function.
 Flip-flop
Flip-flop is a sequential circuit or device which is used to store single bit of information
or data i e either ‘0’ or ‘1 Single flip-flop stores single bit at a time

 Flip-flop is a bistable multivibrator as it has two stable states

 An unclocked flip-flop is called a latch A latch Is that circuit which is constructed using
two cross-coupled NAND gates or NOR gates
 NOR gate S-R latch is called an active High SR latch
 NAND gate S-R latch is called an active Low SR latch.
 Flip flops may be level triggered or edge-triggered level triggered are:

High level triggered

Low level triggered

Edge-triggered are Positive edge triggered

Negative edge triggered

 Types of flip-flops are

RS, JK D and T type

 D flip flop is also called as transparent latch as its output follows the input when the
clock is high
 J K flip flop is the most widely used of all flip flops
 For SR flip-flop

When S = R 0 there is NO change condition

When, S= 1, R 0, there is SET state.

When, S = 0, R = 1, there is RESET state.

When S = R = 1, there is invalid state

For J-K flip-flop :.

When J = K = 0 there is NO change condition

When, J = 1, K 0, there is SET state.

When J = 0, K = 1, there is RESET state

When J K = 1 there is Toggle state

 Toggle state is that in which the output changes from its previous state with every clock
pulse when the inputs are J = K = 1
 Master slave flip-flop overcomes the problem of race around condition which is
common in J-K flip-flops using level clocks.
 Register is a set of flip flops used to store binary data or information
 The registers in which shifting of data takes place are called as shift registers
 Types of shift registers are:

SISO i e Serial in Serial Out

SIPO i.e. Serial in Parallel Out.

PISO i e Parallel in Serial Out

PIPO i e Parallel in Parallel Out

 Bidirectional shift register is used to shift data from left to right or right to left
 Universal shift register performs similar function as that of bidirection shift register in
addition to it data can be shifted in and out in serial form or in parallel form.
 Counter is a device used to count clock pulses or number of events
 Counter types are:

Asynchronous Counters

Synchronous Counters

 Asynchronous counters a those in which clock is not simultaneous e output of 1st flip
flop acts as clock to the next and so on
 Synchronous counters are those in which clock is simultaneous i e common to all the
flip flops
 Modulus counters are those which passes through number of states before returning to
the starting state
 A twisted ring counter is known as Johnson counter
 Monostable multivibrator has only one stable state It is also called as one-shot
multivibrator.
 Astable multivibrator has no stable states It is called as free running multivibrator

Q 1. Explain T-flip-flop with suitable internal structure.

Ans. The functional block diagram of T flip-flop is as shown in fig.

T flip-flop is known as Toggle flip-flop

 When, T = 1 both NAND Gates 1 and 2 gets high

A T flip-flop is designed by combining both the inputs of Gate 1 and 2 together. Thus, when J
= K = 0, Q have same previous state i.e. hold state or no change state. When J = K = l, Q
have toggle state i.e. invert the previous state.

Q 2. Convert SR flip-flop to T flip-flop.

Ans. Firstly write the truth table for SR to T flip-flop as shown:

K maps for S & R are:

For S: For R:

Implementation:
Q 3. Give applications of J-K flip-flops.

Ans.1. J-K flip-flops are used in shift registers.

2. J-K flip-flops are used in counters.

Q 4. Give difference between latch and flip-flop.

Ans.

Q 5. How race around condition can be eliminated?

Ans. Race around condition can be eliminated in JK latch by two ways

1. Using the edge triggered J-K flip-flop.

2. Using the master slave J-K flip-flop.

Q 6. What is a Glitch?

Ans. Glitch is a short duration pulse or spike that appears in the outputs of a counter with
MOD number

Q 7. How many flip-flops are required to count 16 clock pulses? Why?

Ans. To count ‘n’ clock pulses ‘m’ flip-flops are required, where,

Thus, for 16 clock pulses to count, 4 flip-flops are required as 2 = 16.

Q 8. Give application of D and T flip-flops.

Ans. D flip-flops are delay flip flops and are extensively used for temporary storage of data
in registers. Hence, registers make use of D flip-flops.

T flip-flops are toggle flip-flops and are used in counters. Hence, counter designing make
use of T flip-flops.

Q 9. Draw the general block diagram of multivibrator.

Ans. It is as shown:

F1 and F2 are the options for the connections of passive components according to the types
of multivibrator to design.

For example

(a) Astable Multivibrator: F1 = C1 and F2 = C2.

(b) Monostable Multivibrator: F1 = C and F2 = R.

(c) Bistable Multivibrator : F1 = F2 = Parallel combination of R and C of different values.

Q 10. For the given state diagram, draw the state reduction diagram.

Stats Diagram:
Ans. State table is as shown:

For modified reduced state diagram:

Q 11. What do you mean by self starting type counter?

Ans. Whenever there is no problem of lock out then the counter is self-starting type. So, if
any time the counter goes into an invalid state, it comes out and goes into a valid state after
application of one clock pulse.

Q 12. Why is gated D latch called transparent latch?

Ans. The edge triggered D flip-flop uses an edge-detector circuits so that the output will
respond to D input only when the active transition of clock takes place. It is as shown in fig.
From fig. when enable is ‘1’, the D input will given a ‘0’ at either the or inputs of
NAND latch. Thus, 0 becomes same as D. Thus, when enable is ‘1’ the output Q will look
exactly like D. Hence, the D latch is said to be transparent latch.

Q 13. A presettable counter has eight flip-flops. If the preset number is 125, what is the
modulus?

Ans.

256 – 125 = 131

Thus, MOD — 131.

Q 14. Differentiate between sequential and combination circuits.

Ans.

Q 15. The clock frequency is 2MHz. How long will it take to serial load the eight shift
register?

Ans.

n=8

Time taken to load serially the eight bit will be given by

Q 16. What is flip-flop?

Ans. Flip-flop : Flip-flop is a sequential circuit which is used to store single bit of

information at a time i.e. either ‘1’ or ‘0’ at a time. It has two stable output states. It can stay
in one of the two stable states unless state is changed by applying external inputs. Thus, it
as a basic memory element for storage of data in binary form.

There are various types of flip-flops

1. S-R flip flop

2. J-K flip-flop

3. D-type flip flop

4. T-type flip-flop

Q 17. Explain about multivibrator.

Ans. Multivibrators : Most of the digital circuits or systems need some kind of a timing

waveform for example, all clocked sequential system required a source of trigger pulses. A
timing circuit which produces a rectangular waveforms are referred to as multivibrators.
There are different types of multivibrators such as:

1. Astable Multivibrator

2. Monostable Multivibrator

3. Bistable Multivibrator.

Q 18. What is shift register?

Ans. Shift register : A register capable of shifting its binary information either from

right to left or left to right is known as shift register. It consists of flip-flops connected is

cascade. All flip-flops receive a common clock pulse which causes the shift from one stage to
the next stage.

It is of four basis types:

1. Serial in serial out register 2. Serial in parallel out register 3. Parallel in serial out register
4. Parallel in parallel out register.

Bi-directional shift register and Universal shift registers are also used for different
applications.

Q 19. What is universal shift register?

Ans. Universal shift register performs similar operation and function as that of bidirectional
shift register i.e. it can shift data from left to right or right to left, in addition to it data can be
shifted in and out and in serial as well as in parallel form.

Q 20. Draw a logic symbol for a D-flip-flop and compare with RS flip-flop.

Ans.

In case of RS two inputs are there hence four possible combined are used. But in case of D
flip-flop it has only one input so and two combinations are used. Also, in D flip-flop whatever
we want to store will be put as input. If we want to store ‘1’. 1 is the input and if ‘0’ is input,
‘0’ will be stored in D flip-flop.

Q 21. Differentiate between synchronous and asynchronous counters.

 Q 22. What is buffer register?

Ans. Buffer registers are also called as storage registers. They are primarily used for
temporary storage, of binary information or data. They provide place to hold data until it is
processed. That is why they are known as buffer registers.

Q 23. Suggest four applications of shift registers.

Ans. Applications of shift registers

1. It is used in ring counters.

2. It is used in sequence generators.

3. It is used for data conversion in computers i.e. serial to parallel, parallel to serial etc.

4. It is used for time delays i.e. serial in serial out shift register are used for this purpose.

5. It is used in Johnson counter / twisted ring counter.

Q 24 Give the truth-table for each flip-flop type: (a) J-K ; (b) D ; and (c) T

Ans. Truth table of J-K Flip-flop:

2. D Flip-flop:

Q output follows D input with each other.

3. T Flip-flop:

Toggle means ‘0’ changes to ‘1 and ‘1’ changes to ‘0’ with the passage of each clock
Q 25 Explain why there may be a race condition in a shift register.

Ans. There is no race condition in Shift register as it make use of D flip flop, R S flip flop as D
and J K flip flop So the condition of J = K = 1 never comes.

Q 26 What is a ripple counter?

Ans. Ripple Counter- Ripple counters are also known as asynchronous counters. It is as
shown in fig for two bits

For ripple counter input clock is given to first flip-flop and the output of first flip-flop acts as
a clock to next flip-flop and so on

Q 27. Differentiate between static and dynamic shift registers.

Ans.

Q 28. What is the Mod of 6 bit Ring Counter ?

Ans. The mod of 6 bit ring counter is given by 2 where n = number of bits.

2 = 64. Thus MOD-64.

Q 29. Give expression for maximum frequency of operation of n-bit Asynchronous and
synchronous counters.

Ans.
Max. frequency of operation for asynchorous counter

It is same for synchronous counter unless no. of flip-flop, where the maximum frequency of
synchronous counter is

Q 30. Compare binary counters with non-binary counters.

Ans.

Q 31. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input,
start input and ‘done’ output. The counter should produce ‘done’ output after completion
of counter in either direction.

Ans. 3-bit synchronous up-down counter:

Q 32. Specially where Master-slave J-K flip flop is preferred for use.

Ans. Master slave J-K flip-flop is preferred where we want to avoid multiple toggling and
race around conduction. In this flip-flop, master F/F is positive edge triggered and slave flip-
flop is negative edge triggered. The slave ftp-flop followed the master flip-flop.

Q 33. Applications of D Flip Flop. -

Ans.1. D Flip-flop can be used as a delay element 2. As a memory element.

3. In counters! timers. 4. in various types of registers, like in SIPO, SIPO etc.

Q 34. Draw the logic circuits and the excitation tables for the T, JK flip-flops.

Ans.

Q 35. Classify the sequential circuits.

Ans.
Q 36. Describe the difference between a gated S-R latch and an edge-triggered S-R flip
flop.

Ans. Gated S-R Flip-Flop : A gate S-A Flop/flop requires an enable (E) input. When enable is
high, the output changes according to the inputs S and R. However when enable is
ineffective, no change of state take place. Clock signal may also act as a enable.

Edge Triggered S-R Flip-flop: In edge-triggered S-R flip-flop, the change of state in flip-flop
takes place only when edge (either +ve or -ve) of clock pulse takes place.

Q 37. What is the difference between level and edge triggering? Explain the working of
master slave J-K flip flop.

Ans.

Master slave JK flip-flop : The master slave flip-flop may be designed using R-S, D and JK
flip-flops. Following figure shows the functional block diagram of master slave JK flip- flop:

In figure m is used for Master and S is used for Slave

Working:

Case 1: When positive clock pulse goes on leading edge is applied, the CLKm is 1 and CLKs is
0, then data transferred to Qm is held upto CLK = 1

Case 2: When the clock pulse goes negative, trailing edge is applied, the CLKm = 0 and CLKs
= 1, then Qm and will be transferred to Q = and at that duration the inputs at J and
K should not change This is overcome by the use of data lockout.

Internal structures of master slave J-K flip-flop, Truth table is as shown in fig
Q 38. Draw a master-slave J-K flip-flop system. Explain its operation and show that the
race-around condition is eliminated.

Ans.

A master-slave J-K flip-flop is constructed from two flip-flops. One flip-flop acts as a master
and the other as a slave and the overall circuit is thus, called as master-slave flip-flop. It
make use of J-K master flip-flop and S-A slave flip-flop. The master is positive edge triggered
and slave is negative edge triggered. Therefore, master responds to J-K inputs before the
slave. V

If J = 1 and K = 0, the master sets on the positive clock edge. The high output of the master
drives the J input of the slave, so when the negative clock edge arrives, the slave sets,
copying the action of the master.

If J = 0 and K = 1, the master resets on the positive clock edge. The high output of master

i.e. goes to R input of the slave. Therefore, slave resets on arrival of negative clock
edge.

If J = K = 1 for master, it toggles on positive clock edge and the slave them toggles on the
negative clock edge.

When J = K = 1

Let clock = 1 then master is active and slave is in active Therefore, output of master

toggle. So S and R also will be inverted

When clock 0 Master becomes in active and slave is active Therefore, output of the

slave will toggle These changed outputs are again returned back to the master inputs as
feedback is connected in fig

But here clock is ‘0’, the master is still in active So it does not respond to these changed
outputs
This ‘voids multiple toggling which is responsible for Race Around Condition Hence

by using Master-Slave J K Flip-flop RACE AROUND CONDITION will be avoided or eliminated.

Q 39 Explain what is universal shift register? Explain its working.

Ans. A universal shift register is one which can function in any of the SISO SIPO PISO or PIPO
modes of operation To operate the register universally it contains serial input serial output,
parallel inputs, parallel outputs and must be able to serially shift data to the right or to the
left, hold the data or to reset Thus, it has bidirectional property also It is a 74194 IC Its
internal structure is as shown in figure.

Operating modes of IC-741 94