21EC63

Model Question Paper with effect from 2022-23 (CBCS Scheme)

Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
Q No Answers Marks
1a With necessary circuit diagram explain the operation of tristate inverter. Also realize
2:1 mux using tristate inverter.

̅̅̅ ̅̅ ̅̅̅ ̅̅̅̅̅̅

B Realize the CMOS gate for the following function Y = A̅̅̅̅ ( ̅̅̅B̅̅
̅̅̅ ̅̅ +̅̅̅C̅̅̅̅̅ ) +̅̅̅̅̅̅ DE
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
c Implement a D flipflop using transmission gate and explain its operation with necessary
timing diagram

2a Draw the circuit diagram of a CMOS inverter and with the help of its transfer
characteristics, explain various regions of operation and derive the Vout equation for
Region C.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

b Derive the equation for drain current of a MOSFET in non-saturated and saturated
region of operation.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
c Compute the output voltage Vout in the pass transistor circuit shown in Fig

3a Explain the various steps in CMOS n-well process with necessary diagrams.

Draw the neat diagrams

 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
B With neat diagrams, explain the lambda design rules for wires, contact cuts and
Transistors.

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c Draw the stick diagram for the function 𝑌 = 𝐴𝐵𝐶 ̅̅̅+D ̅̅̅
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
4a Construct necessary equivalent circuits using RC delay model to compute the
propagation delay of 3-input NAND Gate.

B Make use of necessary waveforms to define the following terms (i) Propagation delay
(ii) Contamination delay (iii)Rise time (iv) Fall time (v) Edge rate.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

c Make use of necessary circuit diagrams to compute logical effort of the following
gates. (i)2-input NOR gate and (ii)3-input NAND Gate
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

5a Make use of necessary circuit diagram explain the operation of three transistor DRAM
cell.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

B Explain the operation of full CMOS SRAM cell with necessary topology.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
6a Explain the operation of 4*4 NAND based ROM array with necessary circuit diagram.

B With necessary circuit diagram explain the operation of NOR flash memory cell with
bias conditions.

NOR Flash Memory is a type of Non-Volatile Memory (NVM) that is used

in electronic devices to store data. It usually comes in the form of
integrated circuits and has been widely used since the early 1990s. NOR
Flash Memory offers many benefits for device manufacturers and
consumers, such as a high read/write speed, low power consumption, and
a compact size.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
In this blog post, we will discuss what NOR Flash Memory is, how it
works, and its benefits. We will also provide some examples of where you
might find NOR Flash Memory in your everyday life. Stay tuned!

c Explain the hysteresis characteristics of ferroelectric capacitor with necessary diagram

7a Differentiate between fault and failure with an example. Explain different types of
stuck at faults with example.

B For the circuit shown in Fig.2 using Boolean difference (i) detect s@0 and s@1 at x2, (ii)
determine partial Boolean difference for x2-l-n-p-F.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

C Explain stuck open faults in CMOS circuits with an example.

Introduction
 used at the circuit level
 each transistor can have one of three states
 working properly
 stuck open (always cut off)
 stuck short (always on)
 When a transistor is stuck open this doesn’t mean that there is an open circuit on
the finished chip,
 it can mean that some defect has caused the threshold voltage of the transistor to
rise to an extent that the transistor never turns on
 or it could be an open circuit
 or a misalignment that failed to create a transistor
 When a transistor is stuck short this doesn’t mean that there is a short circuit
created using metal lines,
 it can mean that the gate is always connected to supply somehow,
 it can mean that the threshold voltage of the transistor is pushed too low by some
kind of accidental implant
 This is just a model used to model defects, and it shouldn’t reflect any
information about the specific defect that has happen
Model
 The number of faulty states per transistor is 2 K=2
 In a circuit with N transistor we have N*K possible faults
 assume a single fault model, single fault at a time, only a single transistor can be
faulty
Example
 Two input NAND gate
 first two columns represent the normal operation truth table
 when A and B are one, the output is zero otherwise it’s Vdd
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

8a What is fault diagnosis? Explain one dimensional path sensitization technique for
combinational circuits with an example
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

b Find the test pattern for line 6 s@0 for the circuit shown in Fig.3 using D Algorithm.

9a For the state table shown in Table.1 find (i) Response for 101 sequence, (ii) Homing
tree, (iii) Distinguishing tree.
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

B Explain the various phases involved in checking experiment based on sequential circuit
structure.

C Explain the process of testing sequential circuit as iterative combinational circuits.

 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS

10 a Define the terms controllability and observability with an example.

B With a neat logic diagram, explain clocked hazard free latches used in LSSD Technique
 21EC63
Model Question Paper with effect from 2022-23 (CBCS Scheme)
Sixth Semester B.E. Degree Examination
VLSI Design and Testing (21EC63)
ANSWERS
c Explain any two Adhoc design rules for improving testability.