Datasheet KW45

KW45B (radio) and KW45Z (MCU)
KW45 Product Family

Highly Secure, Bluetooth Low Energy 5.3 Wireless MCU with CAN FD
Rev. 9 — 12/2022 Data Sheet: Technical Data
KW45B41Zx2AFxBx
The KW45 product family is a low-power, highly secure, single-chip wireless KW45B41Zx3AFxBx
MCU that integrates a high performance Bluetooth Low Energy version 5.3 KW45Z410x2AFxBx
radio and CAN FD for Automotive and Industrial applications.
KW45Z410x3AFxBx
The family integrates a state-of-the-art, scalable security architecture
® ®
including Arm TrustZone -M, a resource domain controller, and an
isolated EdgeLock™ Secure Enclave supporting hardware cryptographic
accelerators, random number generators and key generation, storage and
management and secure debug. Flash memory contents can optionally be
stored as encrypted data and then decrypted on-the-fly enabling protection 40HVQFN 48HVQFN
of sensitive data and algorithms. 6 x 6 x 0.85 mm 7 x 7 x 0.85 mm
For automotive applications, an integrated FlexCAN supporting CAN and Pitch 0.5 mm Pitch 0.5 mm
CAN FD compliant with the ISO 11898-1 standard. The on-chip, low-power Wettable Flanks Wettable Flanks
UARTs have LIN capabilities. The family is AEC-Q100 Grade 2 automotive
certified, with an extended ambient operating temperature range up to +105
°C, MISRA C:2012, and Automotive SPICE (ASPICE) process compliant.
Application core Bluetooth Low Energy radio core

• Up to 96 MHz Arm Cortex®-M33 core • Dedicated CM3 core running at up to 64 MHz
• Up to 1 MB flash memory • 256 kB Flash supporting upgradable software radio
• 128 KB SRAM • 88 KB SRAM optimized for link layer support
• TrustZone-M, IEEE 754 FPU, DSP, MPU, NVIC, SysTick • Up to 24 simultaneous connections
• 8 KB Code Cache to improve performance and efficiency • –106 dBm 125 kbps Long Range Receive Sensitivity
• Secure Boot ROM • –102 dBm 500 kbps Long Range Receive Sensitivity
Target applications • –97.5 dBm 1 Mbps Receive Sensitivity
• Automotive • –95 dBm 2 Mbps Receiver Sensitivity
— Secure Car Access • Programmable Transmit Output Power up to +10 dBm
— Keyless Entry • Data Rates: 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps
— Passive Entry/Passive Start (PEPS) Systems • Modulation Types: 2 Level FSK, GFSK, MSK, GMSK
— Wireless Battery Management Systems (WBMS) • Integrated memories in radio containing Bluetooth LE
Controller Stack and radio drivers
• Industrial/IoT
• On-chip balun with single ended bidirectional RF port
— Positioning/Localization
• Low external component counts for low cost, small form-
— Building Control and Monitoring
factor designs
— Process/Factory Automation
Table continues on the next page...
NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
General Business Information
NXP Semiconductors
— Access Control
EdgeLock Secure Enclave Safety
• Secure boot and debug • Memory Protection Unit (MPU)
• Trusted resource domain controller (TRDC) providing • Register write protection

programmable control mechanisms for independent • Illegal memory access
processing domains including embedded memory and
• Flash area protection
peripherals
• SRAM Error Correction Code (ECC) and SRAM parity
— Privilege/user
error check
— Data only
• Clock Frequency Accuracy Measurement Circuit (CAC)
— Execute only using Signal Frequency Analyzer (SFA) module
— Read-only access • Cyclic Redundancy Check (CRC) calculator
— Secure/Non-secure • Two internal, independent and one external watchdog
Advanced flash access protection timer
— Write/Erase protection, Execute only, Data only • Clock loss detection

access control • Main oscillator stop detection (Loss of lock detection)
— Optional encryption and on-the-fly decryption using • Low voltage / high voltage detection
a PRINCE XEX block cipher mode
Low-power consumption (DCDC 3.6 V, 25 ºC)
• Hardware encryption and decryption
• Typical active core current: <5.3 mA at 96 MHz (<55 μA/
— Symmetric Key Encryption MHz)
◦ AES-128/192/256 • Transceiver current (DC-DC buck mode, 3.3 V supply)
◦ ECB, CBC, CTR, GCM, CMAC, and CCM — Typical RX: 4.7 mA
Modes
— Typical TX at 0 dBm: 4.6 mA and 18.7 mA at 10
— Asymmetric Key Encryption dBm
◦ ECC NIST P–192/224/256/384/521 • Less than 3 μA in power-down mode with real-time clock
◦ Curve25519 (RTC) active and 32 KB SRAM retention
— Key Exchange Algorithms • Less than 1.5 μA in Deep Power-Down mode with RTC
active
◦ ECDH(E)
• Multiple power-down modes supporting currents as low
◦ SPAKE2+ as 300 nA
◦ JPAKE • Ultra-low leakage Smart Power Switch with less than 100
— Digital Signature Algorithms nA sleep current with exit from internal timer or GPIO.
◦ ECDSA Clocks
◦ Ed25519 • 32 MHz RF crystal oscillator
— Hash Algorithms • 32.768 kHz crystal oscillator
◦ SHA2-224/256/384/512 • Internal 192 MHz high frequency free running oscillator

providing 48/64/96 MHz clock
◦ Poly1305
• Internal low frequency free running oscillator providing 6
• Secure key generation, storage, and management MHz clock
• Internal low power free running oscillator providing 32
kHz clock
KW45 Product Family, Rev. 9, 12/2022

Data Sheet: Technical Data General Business Information 2 / 94
NXP Semiconductors
• Pseudo (PRNG) and True Random Number Generator Analog modules

(TRNG) with 512-bits entropy supporting NIST SP • 16-bit single ended SAR Analog-to-digital converter
800-90A and SP 800-90B (ADC) up to 2 Msps
• Support for secure over-the-air (OTA) firmware updates • Two high-speed analog comparators (CMP) with 8-bit
• Four digital tamper pins with optional interrupt and digital-to-analog converter (DAC)
seconds timestamp upon trigger • 1.0 V to 2.1 V Voltage Reference (Vref)
• Universally Unique ID (UUID) programmed by NXP Communication interfaces
during factory programming
• FlexCAN with CAN and CAN FD supporting the full
• 24-bit unique IEEE media access control (MAC) implementation of the CAN Specification Version 2.0,
subaddress Part B. FD Support.
• Factory Root of Trust programming • Two Low Power UART (LPUART) modules with LIN
System peripherals support
• DC/DC converter supporting buck and bypass operating • Two Low Power SPI modules and one MIPI-I3C module
modes • Two Low Power I2C (LPI2C) modules supporting the
• Asynchronous DMA controller with per channel access System Management Bus (SMBus) Specification, version
permissions (secure/non-secure) 2
• Two internal and one external watchdog monitors • One programmable FlexIO module supporting emulation
of UART, I2C, SPI, Camera IF, LCD RGB, PWM/
• Nested vectored interrupt controller Waveform generation
• Wake-up unit for power-down modes Human Machine Interface modules
Timers • General-purpose input/output (GPIO)
• Two 6-channel 32-bit timers (TPM) with PWM capability Operating characteristics
and DMA support
• Temperature range (ambient): –40 °C to 105 °C
• Two 32-bit low-power timers (LPTMR) or pulse counters
with compare features • Temperature range (junction): –40 °C to 125 °C
• 4-channel 32-bit low-power periodic interrupt timer (LPIT) • DC/DC voltage range: 1.8 V to 3.6 V
with DMA support • Bypass voltage range: 1.8 V to 3.6 V
• One 56-bit timestamp timer • Qualification: AEC-Q100 Grade 2
• 32-bit seconds real time counter (RTC) with 32-bit alarm
and independent power supply
• Signal frequency analyzer (SFA) provides facilities for
measurement of clock period/frequency as well as time
between triggers
Input supply voltage options:
• Integrated DCDC regulator 1.8–3.6 V providing power to
Core_LDO regulator, SYS_LDO regulators, and Radio
• Integrated Core_LDO regulator 1.2 V–3.6 V powering the
core digital domain
• Integrated SYS_LDO regulator 1.71 V to 3.6 V powering
the SYS domain
• DCDC and Core_LDO regulators can support bypass
modes

NXP Semiconductors
Table 1. Ordering Information of radio parts 1
Part Number Packaging Radio Protocol Memory (Flash/ Packages CAN Qualification
Type RAM)
KW45B41Z53AFTBT Tray Bluetooth LE 5.3 512 KB/128 KB 7x7 48-pin Yes AEC-Q100 Grade
HVQFN 2
KW45B41Z53AFTBR Tape and
“Wettable”
Reel
KW45B41Z53AFPBT Tray 6x6 40-pin

HVQFN
KW45B41Z53AFPBR Tape and
“Wettable”
Reel
KW45B41Z52AFTBT Tray 7x7 48-pin No

HVQFN
“Wettable”
Reel
KW45B41Z52AFPBT Tray 6x6 40-pin

HVQFN
“Wettable”
Reel
KW45B41Z83AFTBT Tray 1 MB/128 KB 7x7 48-pin Yes

HVQFN
“Wettable”
Reel
KW45B41Z82AFTBT Tray No

Reel
KW45B41Z83AFPBT Tray 6x6 40-pin Yes

HVQFN
“Wettable”
Reel
KW45B41Z82AFPBT Tray No

Reel
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
Table 2. Ordering Information of non-radio parts 1
Part Number Packaging Protocol Memory (Flash/RAM) Packages CAN Qualification

Type
KW45Z41053AFTBT Tray MCU only 512 KB/128 KB 7x7 48-pin Yes AEC-Q100 Grade
HVQFN 2
KW45Z41053AFTBR Tape and
“Wettable”
Reel
KW45Z41052AFTBT Tray No

Reel

NXP Semiconductors
Table 2. Ordering Information of non-radio parts 1 (continued)
Part Number Packaging Protocol Memory (Flash/RAM) Packages CAN Qualification

Type
KW45Z41053AFPBT Tray 6x6 40-pin Yes

HVQFN
KW45Z41053AFPBR Tape and
“Wettable”
Reel
KW45Z41052AFPBT Tray No

Reel
KW45Z41083AFTBT Tray 1 MB/128 KB 7x7 48-pin Yes

HVQFN
“Wettable”
Reel
KW45Z41082AFTBT Tray No

Reel
KW45Z41083AFPBT Tray 6x6 40-pin Yes

HVQFN
“Wettable”
Reel
KW45Z41082AFPBT Tray No

Reel
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
NOTE
• In case of Tray 7x7 48-pin HVQFN "Wettable" - Minimum Package Quantity is 260 pcs
• In case of Tray 6x6 40-pin HVQFN "Wettable" - Minimum Package Quantity is 490 pcs
• In case of Tape and Reel 7x7 48-pin and 6x6 40-pin HVQFN "Wettable" - Minimum Package Quantity is 2 kpcs
Table 3. Device Revision Number
Device Mask Set Number SIM_SDID[REVID]
P43C 0b11
Table 4. Related Resources
Type Description Resource
Reference The Reference Manual contains a comprehensive description of the KW45B41ZRM

Manual structure and function (operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal This document
connections.
Chip Errata The chip mask set Errata provides additional or corrective information KW45_K32W1_2P43C
for a particular device mask set.

NXP Semiconductors
Table 4. Related Resources (continued)
Type Description Resource
Package Package dimensions are provided in package drawings. • 48 HVQFN:SOT619-17(D)

drawing
• 40 HVQFN:SOT618-13(DD)
MCU(CPU0) Domain SECURITY

SYSTEM
CRC
AXBS ARM Cortex-M33
96 MHz EdgeLock
DMA
Secure Enclave (ELE)
CACHE-CODE
MSCM (8 KB) Message Unit (MU)
SMSCM Key Storage
FPU DSP
TRGMUX Crypto Accelerators
WDOG (x2) MPU NVIC TRNG
EWM eFuses
SysTick TZ-M
WUU
PRINCE
SEMA42
TRDC
CLOCK TIMER COMMUNICATION
MEMORY
FRO-6M LPTMR 32-bit (x2) CAN and CAN FD
1 MB Flash
FRO-192M LPIT 4-ch 32-bit LPUART w/LIN (x2)
SRAM (128 KB)
MRCC TPM 6-ch 32-bit (x2) LPSPI (x2)
FMU
SCG TSTMR 56-bit LPI2C (x2)
Secure Boot ROM
SFA I3C
DEBUG ANALOG FlexIO Smart Power Switch
CTI 16-bit ADC
Power Switch
ITM LPCMP (x2) RTC
OSC-RTC FRO16K
TPIU VREF
DAP HMI FRO-32K Wakeup Timer
DWT GPIO (A-D) RTC RAM Standby Regulator

SWD PORT (A-D) REGFILE-RTC (x2)
Power Subsystem Radio Subsystem

CMC LDO-SYS RFMC ARM Cortex-M3
RF - 2.4G AES
DCDC SPC
OSC-RF Memory
LDO-CORE
RF - NBU FRO-192M
Figure 1. KW45 block diagram

Contents
1 Ratings............................................................... 9 3.2.5 Free-running oscillator FRO-32K specifications

1.1 Thermal handling ratings................................ 9 ...................................................................... 38
1.2 Moisture handling ratings................................9 3.2.6 Free-running oscillator FRO-16K specifications
1.3 ESD and Latch-Up Ratings.............................9 ...................................................................... 39
1.4 Voltage and current maximum ratings............ 9 3.3 Memories and memory interfaces.................39
1.5 Required Power-On-Reset (POR) Sequencing 3.3.1 Flash electrical specifications....................... 39
...................................................................... 10 3.3.1.1 Flash Read wait state control specifications 39
1.6 Power Sequence...........................................11 3.3.1.2 Flash timing specifications............................ 40
2 General.............................................................11 3.3.1.3 Flash high voltage current behavior..............41
2.1 AC electrical characteristics.......................... 11 3.3.1.4 Flash reliability specifications........................41
2.2 Nonswitching electrical specifications........... 12 3.4 Radio modules.............................................. 41
2.2.1 Voltage and current operating requirements.12 3.4.1 2.4 GHz radio transceiver electrical
2.2.2 HVD, LVD, and POR operating requirements specification.................................................. 41
...................................................................... 13 3.4.2 Receiver Feature Summary.......................... 42
2.2.3 Voltage and current operating behaviors...... 15 3.4.3 Transmit and PLL Feature Summary............ 46
2.2.4 On-chip regulator electrical specifications.... 16 3.5 Analog...........................................................53
2.2.4.1 DCDC converter specifications..................... 16 3.5.1 ADC electrical specifications.........................53
2.2.4.2 LDO_SYS electrical specifications................ 19 3.5.1.1 16-bit ADC operating conditions................... 53
2.2.4.3 LDO_CORE electrical specifications.............20 3.5.1.2 16-bit ADC electrical characteristics............. 55
2.2.5 Smart power switch.......................................21 3.5.2 CMP and 8-bit DAC electrical specifications.57
2.2.6 Power mode transition operating behaviors..22 3.5.3 Voltage reference electrical specifications.... 60
2.2.7 Power consumption operating behaviors......22 3.6 Timers........................................................... 61
2.2.7.1 Power Consumption Operating Behaviors ... 22 3.7 Communication interfaces............................ 61
2.2.7.2 SoC Power Consumption..............................27 3.7.1 LPUART........................................................61
2.2.7.3 Typical power-down mode RAM current adders 3.7.2 LPSPI switching specifications..................... 61
...................................................................... 27 3.7.3 Inter-Integrated Circuit Interface (I2C)
2.2.7.4 Low power mode peripheral power specifications................................................ 64
consumption adders......................................28 3.7.4 Improved Inter-Integrated Circuit Interface
2.2.8 EMC radiated emissions operating behaviors (MIPI-I3C) specifications............................... 66
...................................................................... 31 3.7.5 CAN switching specifications........................ 70
2.2.9 Designing with radiated emissions in mind... 31 3.8 Human Machine Interface (HMI) modules.... 70
2.2.10 Capacitance attributes.................................. 31 3.8.1 General Purpose Input/Output (GPIO)..........70
2.3 Switching specifications................................ 31 3.8.2 Flexible IO controller (FlexIO)....................... 70
2.3.1 Device clock specifications........................... 31 4 Package dimensions........................................ 71
2.3.2 General switching specifications...................32 4.1 Obtaining package dimensions.....................71
2.4 Thermal specifications.................................. 33 5 Pinout............................................................... 71
2.4.1 Thermal operating requirements...................33 5.1 Pinout Table..................................................71
2.4.2 Thermal attributes......................................... 33 5.2 Recommended connection for unused analog
3 Peripheral operating requirements and behaviors and digital pins.............................................. 75
......................................................................... 33 5.3 Pinouts diagram............................................ 77
3.1 Core modules................................................34 6 Ordering parts.................................................. 79
3.1.1 SWD electricals ............................................34 6.1 Determining valid orderable parts................. 79
3.2 Clock modules.............................................. 35 7 Part identification..............................................79
3.2.1 Reference oscillator specification................. 35 7.1 Part number format....................................... 80
3.2.2 32 kHz oscillator electrical specifications...... 37 7.2 Example........................................................ 80
3.2.3 Free-running oscillator FRO-192M 7.3 Package marking.......................................... 80
specifications................................................ 37 7.3.1 Package marking information....................... 81
3.2.4 Free-running oscillator FRO-6M specifications 8 Terminology and guidelines............................. 81
...................................................................... 38 8.1 Definitions..................................................... 81
8.2 Examples...................................................... 82
8.3 Typical-value conditions................................83 9 Abbreviations and Acronyms............................83
8.4 Relationship between ratings and operating 10 Revision history................................................ 85
requirements................................................. 83 Legal information............................................................... 91
8.5 Guidelines for ratings and operating
requirements................................................. 83
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings

Table 5. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings

Table 6. Moisture handling ratings
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD and Latch-Up Ratings

Table 7. ESD and Latch-Up Ratings
Description Rating Notes
Electrostatic discharge voltage, human body model ±2000 V 1
Electrostatic discharge voltage, charged-device model (corner pins and antenna ±500 V 2
pin excluded)
Electrostatic discharge voltage, charged-device model (corner pins) ±750 V
Electrostatic discharge voltage, charged-device model (antenna pin) ±250 V
Latch-up immunity level (Class II at 125 °C junction temperature) Immunity Level A 3
1. Determined according to JEDEC Standard JS-001-2017, For Electrostatic Discharge (ESD) Sensitivity Testing, Human
Body Model (HBM) - Component Level.
2. Determined according to JEDEC Standard JS-002-2018, For Electrostatic Discharge (ESD) Sensitivity Testing, Charged-
Device Model (CDM) - Device Level .
3. Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.
1.4 Voltage and current maximum ratings
Table 8. Voltage and current maximum ratings
Symbol Description Min. Max. Unit
VDD_CORE Supply voltage for most digital domains –0.3 1.26 V
VDD_SYS Supply voltage for PMC, EFUSE, SRTC, and FROs –0.3 1.98 1 V

NXP Semiconductors
Ratings
Table 8. Voltage and current maximum ratings (continued)
VDD_DCDC Supply voltage for DCDC regulator –0.3 3.63 V
VDD_IO_D Supply voltage for LDO_SYS regulator, and PortD –0.3 3.63 V
VDD_LDO_C Supply voltage for LDO_CORE regulator –0.3 3.63 V

ORE
VDD_RF Supply voltage for OSC and radio analog –0.3 3.6 V
VPA_2P4GH Supply voltage for 2.4 GHz radio power amplifier –0.3 2.8 V
Z
VDD_IO_ABC Supply voltage for Port A, Port B, Port C, Flash and CMP0/1 –0.3 3.63 V
VDD_ANA Supply voltage for ADC, DAC, and VREF –0.3 3.63 V
VIN Port input voltage –0.3 3.63 2 V
ID Maximum current single pin limit (digital output pins) –25 25 mA
VOUT_SWIT Smart power switch output voltage 1.78 3 3.63 V

CH
1. The part supports 2.75 V for up to 20 s over lifetime to allow fuse programming
2. The Max. of the VIN cannot be greater than the voltage applied to the VDD_IO_x.
3. Current loading is less than 40 mA
1.5 Required Power-On-Reset (POR) Sequencing

When VDD_CORE is supplied by one of the internal regulators, VDD supply inputs can be powered up in any order. VDD supply
inputs on power-up must not exceed VDD voltage maximums.
When powering VDD_CORE with an external supply, VDD_CORE must not be enabled until VDD_IO_ABC ≥ 1.65 V, as
shown below.

NXP Semiconductors
General
Figure 2. VDD_CORE/VDD_IO_ABC Powering Sequence
1.6 Power Sequence

Table 9. Power Sequence
Symbol Description Order in Notes

sequence
VDD_SWITCH Smart Power Switch input 1 1
VDD_DCDC/ DCDC / PORT D / LDO_SYS regulator input 2 1
VDD_IO_D
VDD_IO_ABC Ports A, B, and C power rail input 2 1
VDD_ANA Analog source input 2 1
VDD_LDO_COR Core power rail input 2 1
VDD_RF RF power rail input 3 1
VPA_2P4GHz RF PA voltage input 4 1
1. All domains can be powered at the same time. If external sources are used, make sure they start at the same time or they
follow the order in the sequence.
2 General
2.1 AC electrical characteristics

Unless specified, propagation delays are measured from the 50 % to the 50 % point, and rise and fall times are measured at the
20 % and 80 % points, as shown in the following figure.

NXP Semiconductors
General
Low High
VIH
80%
Input Signal Midpoint1 50%
20%
VIL
Fall Time Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 3. Input signal measurement reference
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements

Table 10. Voltage and current operating requirements
VDD_CORE VDD_CORE input supply voltage V
Mid Drive (1.0 V) Operation 1.0 1.1
Normal Drive (1.1 V) Operation 1.04 1.21
Safe-Mode Voltage (1.15 V) Operation 1.04 1.21
VDD_SYS Supply voltage for System Voltage Domain V

1.8 1.98
• Normal mode
2.25 2.75
• Fuse Programming
VDD_DCDC Supply voltage DCDC regulator 1.8 3.6 V 1
VDD_IO_D Supply voltage for LDO_SYS regulator, PortD 1.86 3.6 V 2
VDD_LDO_ Supply voltage for LDO_CORE regulator 1.25 3.6 V

CORE
VDD_RF Supply voltage for OSC and radio analog 1.175 3.6 V
VPA_2P4GH Supply voltage for 2.4 GHz radio power amplifier 0.9 2.4 V
z
VDD_IO_AB Supply voltage for PortA, PortB, Port C, and CMPs 1.71 3.6 V 3
VDD_ANA Supply voltage for ADC, DAC, and VREF 1.71 3.6 V
VSS - VSS-to-VSS_ANA differential voltage –0.1 0.1 V

VSS_ANA
VIH 4
Input high voltage
• 1.71 V ≤ VDD_IO_ABC ≤ 3.6 V 0.7 × VDD_I — V
O_ABC
• 1.86 V ≤ VDD_IO_D ≤ 3.6 V —

NXP Semiconductors
General
Table 10. Voltage and current operating requirements (continued)
0.7 × VDD_I
O_D
VIL 4
Input low voltage
0.3 × VDD_I
• 1.71 V ≤ VDD_IO_ABC ≤ 3.6 V — O_ABC V
• 1.86 V ≤ VDD_IO_D ≤ 3.6 V — 0.3 × VDD_I

O_D
VHYS Input hysteresis 0.1 × VDD_I — V

O_X
IICIO 5, 6
IO pin DC injection current — single pin
mA
0 —
• VIN < VSS – 0.3 V (negative current injection)
• VIN > VDD + 0.3 V (positive current injection) — 0
VODPU Open drain pullup voltage level VDD_IO_X VDD_IO_X V 7
1. If DCDC is unused, then input supply should be tied to GND through a 10 kΩ resistor.
2. When LDO_SYS is bypassed, the input supply voltage is 1.8 V to 1.98 V and VDD_IO_D must be externally connected to
VDD_SYS
3. If none of the PortA, PortB, and PortC pins are being used, then the VDD_IO_ABC can be left floating.
4. VIH and VIL for PTD0 are based of VDD_SYS instead of VDD_IO_D
5. All I/O pins are internally clamped to VSS and VDD_IO_x through an ESD protection diode. If VIN is greater than
VDD_IO_x_MIN(= VSS – 0.3 V) or is less than VDD_IO_x_MAX(= VDD + 0.3 V), then there is no need to provide current
limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required.
6. This device does not allow pin injection current. User must ensure that VIN is kept within the Voltage Maximum Ratings.
7. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_IO_X as appropriate.
2.2.2 HVD, LVD, and POR operating requirements

The device includes low-voltage detection (LVD) and high-voltage detection (HVD) power supervisor circuits for following
power supplies:
• VDD_IO_ABC
• VDD_CORE
• VDD_SYS
For VDD_SYS, it has Power-on-reset (POR) power supervisor circuits.
Table 11. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings
Symbol Description Min. Typ. Max. Unit Notes
VHVDH_IO_A VDD_IO_ABC Rising high-voltage detect 3.730 3.810 3.890 V

BC threshold
VHVDH_HYS VDD_IO_ABC High-voltage inhibit reset/recover — 38 — mV

_IO_ABC hysteresis
VLVDH_IO_A VDD_IO_ABC Falling low-voltage detect 2.567 2.619 2.673 V

BC threshold - high range

NXP Semiconductors
General
Table 11. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings (continued)
VLVDH_HYS VDD_IO_ABC Low-voltage inhibit reset/recover — 27 — mV

_IO_ABC hysteresis - high range
VLVDL_IO_A VDD_IO_ABC Falling low-voltage detect 1.618 1.651 1.684 V

BC threshold - low range
VLVDV_HYS VDD_IO_ABC Low-voltage inhibit reset/recover — 20 — mV

_IO_ABC hysteresis - low range
Table 12. VDD_CORE supply HVD and LVD Operating Ratings
VHVD_CORE VDD_CORE Rising high-voltage detect V 1
threshold (HVD assertion)

Target VDD_CORE = 1.05 V
Target VDD_CORE = 1.1 V 1.230 1.257 1.285
Target VDD_CORE = 1.15 V (safe mode LVD)
VHVD_HYS_CORE VDD_CORE High-voltage inhibit reset/recover mV 1
hysteresis
— 14 —
VLVD_CORE VDD_CORE Falling low-voltage detect V

threshold (LVD assertion)
0.944 0.963 0.983
0.989 1.009 1.029
1.043 1.064 1.086
VLVD_HYS_CORE VDD_CORE Low-voltage inhibit reset/ mV

recover hysteresis
Target VDD_CORE = 1.05 V — 14 —
Target VDD_CORE = 1.1 V — 14 —
Target VDD_CORE = 1.15 V (safe mode LVD) — 17 —
1. Same value applies to all conditions.
Table 13. VDD_SYS supply HVD and LVD Operating Ratings
VHVD_SYS V 1
VDD_SYS Rising high-voltage detect
threshold (HVD assertion)
Target VDD_SYS = 1.8 V 2.035 2.077 2.120

NXP Semiconductors
General
Table 13. VDD_SYS supply HVD and LVD Operating Ratings (continued)
Target VDD_SYS = 1.9 V (safe mode LVD) 2.035 2.077 2.120
VHVD_HYS_SYS VDD_SYS High-voltage inhibit reset/recover — 22 — mV

hysteresis
VPOR_SYS Falling VDD_SYS POR detect voltage (POR 0.8 1.0 1.5 V
assertion)
VLVD_SYS VDD_SYS Falling low-voltage detect V

threshold (LVD assertion)
Target VDD_SYS = 1.8 V 1.616 1.649 1.683
Target VDD_SYS = 1.9 V (safe mode LVD) 1.700 1.735 1.770
VLVD_HYS_SYS VDD_SYS Low-voltage inhibit reset/recover — 19 — mV

hysteresis
VBG Bandgap voltage reference voltage — 1.0 — V
1. When fuses are being programmed VDD_SYS is raised to 2.5 V nominal. This is outside the HVD bounds, so HVD
detection for VDD_SYS must be disabled when programming fuses
2.2.3 Voltage and current operating behaviors

Table 14. Voltage and current operating behaviors
VOH 1
Output high voltage — Normal drive strength
• 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 4 mA VDD_IO_X — — V
– 0.5
• 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 2.5 mA
• 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA
VOH 1,2
Output high voltage — High drive strength
• 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 6 mA VDD_IO_X — — V
– 0.5
• 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 3.75 mA
• 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 3.75 mA
IOHT Output high current total for all ports — — 100 mA
VOL 1,3
Output low voltage — Normal drive strength
• 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 4 mA — — 0.5 V
• 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 2.5 mA

• 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA
VOL 1,3,2
Output low voltage — High drive strength
• 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 6 mA — — 0.5 V

NXP Semiconductors
General
Table 14. Voltage and current operating behaviors (continued)
• 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 3.75 mA

• 1.86 V ≤ VDD_IO_D < 2.7 V, IOL = 3.75 mA
IOLT Output low current total for all ports — — 100 mA
IIN Input leakage current (per pin) for full — — 1 μA 4
temperature range
IIN Input leakage current (per pin) at 25 °C — — 0.025 μA 4
IIN Input leakage current (total all pins) for full — — 41 μA 4
temperature range
IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA
RPU Internal pullup resistors 33 50 75 kΩ
RPU (I3C) Internal pullup resistors 1.1 2 2.833 kΩ 5
RPD Internal pulldown resistors 33 50 75 kΩ
RHPU High-resistance pullup option 0.67 — 1.5 MΩ 6
(PORTx_PCRy[PV] = 1)
RHPD High-resistance pulldown option 0.67 — 1.5 MΩ 6
(PORTx_PCRy[PV] = 1)
1. When setting DSE1=1, the same VOH / VOL is met with IOH / IOL doubled.
2. RTC signals are always configured in high drive mode
3. Open drain outputs must be pulled to VDD_IO_X.
4. Measured at VDD_IO_X = 3.6 V.
5. Only I3C pins support this option
6. Only Port D pins support this option.
2.2.4 On-chip regulator electrical specifications
2.2.4.1 DCDC converter specifications
Table 15. DCDC Converter Specifications
VDD_DCDC DCDC input voltage 1.71 — 3.6 V
VOUT_DCDC DCDC output voltage 1, 2

1.25 — 2.5 V
ILOAD 1, 3
DCDC load current
• Normal drive strength — — 105 mA
• Low drive strength — — 15 mA
• SPC_DCD_CFG[FREQ_CNTRL_ON]=1 — — 45 mA
LX DCDC inductor value 0.47 1 2.2 µH 4
ESR External inductor equivalent series resistance — 110 — mΩ 5

NXP Semiconductors
General
Table 15. DCDC Converter Specifications (continued)
COUT DCDC capacitance value 6 22 30 µF 6
VRIPPLE DCDC voltage ripple

— 1 — %
• In normal drive strength
• In low drive strength — 25 — mV
fburst DCDC burst frequency 3 5 8 MHz 7
fburst_acc DCDC burst frequency accuracy — 10 — % 7
1. The system DCDC converter generates 1.8 V at DCDC_LX by default. The DCDC can be used to power VDD_RF,
VDD_LDO_CORE, and external components as long as the max ILOAD is not exceeded.
2. The VDD_DCDC input supply to DCDC must be at least 500 mV higher than the desired output at DCDC_LX.
3. The maximum load current during boot up shall not exceed 60 mA.
4. Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed
5. The maximum recommended ESR is 250 mΩ (not a hard limit).
6. The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not
exceed the Min./Max. values.
7. FREQ_CNTRL_ON = 1.

NXP Semiconductors
General
DCDC Efficiency plots
Figure 4. Efficiency vs Load current in Normal drive

NXP Semiconductors
General
Figure 5. Efficiency vs Load current in Low-power drive
2.2.4.2 LDO_SYS electrical specifications
Table 16. LDO_SYS electrical specifications
VDD_IO_D LDO_SYS input supply voltage V 1
• LDO_SYS input supply voltage 1.86 — 3.6

(Regulation mode)
• LDO_SYS input supply voltage (Bypass 1.8 — 1.98
mode)
2.75 — 3.6
• Fuse programming mode
VOUT_SYS LDO_SYS regulator output voltage V 2,3,4,5
• Normal drive mode 1.71 1.8 1.98
• Fuse Programming mode 2.25 2.5 2.75
ILOAD LDO_SYS maximum load current

NXP Semiconductors
General
Table 16. LDO_SYS electrical specifications (continued)
• Normal drive mode — — 50 mA

• Low drive mode — — 2 mA
• Fuse programming mode — — 40 mA
IDD 6
LDO_SYS power consumption
• Normal drive mode — 100 — μA
• Low drive mode — 70 — nA
COUT External output capacitor — 1.5 10 μF
CDEC External output decoupling capacitor — 0.1 — μF
ESR External output capacitor equivalent series — 30 — mΩ

resistance
IINRUSH LDO_SYS inrush current — — 120 mA 7
1. Regulator will automatically switch to passthrough (means the regulator driver is fully ON) with the supply is below 1.95 V.
2. The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS,
VDD_RF, VDD_IO_X, VDD_ANA, and external components as long as the max ILOAD is not exceeded.
3. VOUT_SYS and VDD_SYS are connected together.
4. VDD_IO_D must be at least 150 mV higher than the desired VOUT_SYS.
5. LDO_SYS can be used to program efuse and in this configuration the output voltage can range between 2.25 V and 2.75 V
6. In normal drive strength, LDO_SYS draws ~100 μA for every 20 mA of load current.
7. This is for 1.5 μF external output capacitor. If the capacitor has 10 μF value, this value should be 300 mA instead.
2.2.4.3 LDO_CORE electrical specifications
Table 17. LDO_CORE electrical specifications
VDD_LDO_CO LDO_CORE input supply voltage 1.25 — 3.6 V 1, 2
RE
VOUT_CORE LDO_CORE regulator output voltage V

1.0 — 1.15
• Normal drive strength
1.0 1.15
• Low drive strength —
ILOAD LDO_CORE max load current

• Normal mode - VDD_LDO_CORE ≥ mA
— — 60
1.5 V
• Normal mode - VDD_LDO_CORE < — — 30
1.5 V
• Low-power mode - VDD_LDO_CORE ≥ — — 5
1.5 V
— — 5
• Low-power mode - VDD_LDO_CORE <
1.5 V

NXP Semiconductors
General
Table 17. LDO_CORE electrical specifications (continued)
IDD 3
LDO_CORE current consumption
μA
• Normal drive strength - — — 150
VDD_LDO_CORE ≥ 1.5 V
• Normal drive strength - — — 75
VDD_LDO_CORE < 1.5 V
• Low drive strength - VDD_LDO_CORE ≥ — — 0.05
1.5 V
• Low drive strength - VDD_LDO_CORE < — — 0.05
1.5 V
IINRUSH LDO_CORE inrush current — — 5 x ILOAD mA
1. To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE

2. The VDD_LDO_CORE input supply must also be at least 250 mV higher than the desired output at VOUT_CORE.
3. In normal drive strength, LDO_CORE draws ~40 μA for every 20 mA of load current. In low drive strength, LDO_CORE
draws ~50 nA for every 100 μA of load current.
Table 18. LDO_CORE external device electrical specifications
COUT External output capacitor 3.7 4.7 10 μF
CDEC External output decoupling capacitor — 0.1 — μF
ESR External output capacitor equivalent series — 10 — mΩ

resistance
2.2.5 Smart power switch

NOTE
SWITCH_WAKEUP_B pad is internally pulled up to the switch input through a resistor, it can be pulled down to
wake up the smart power switch. To generate a valid internal wake-up signal successfully, maximum value of
SWITCH_WAKEUP_B pulldown voltage is 0.7 V, duration time should be larger than 1 µs.
Table 19. Smart power switch
Vsupply Input voltage (VDD_SWITCH) 1.9 — 3.6 V
RON Switch resistor at 'on' state — — 3 Ω
Iload Load current — — 40 mA
Ileakage1 Typical leakage current when Vsupply = 2.7 — 4 — nA

V, 25 °C
Ileakage2 Maximum leakage current when Vsupply = — — 1 µA

3.3 V

NXP Semiconductors
General
NOTE
If battery (with peak current limitation) is used to power VDD_SWITCH which power rest of chip supplies, it is not
recommended to go to deep-power-down mode constantly. Because DCDC startup will introduce big peak current
when wakeup.
2.2.6 Power mode transition operating behaviors

All specifications in the following table assume that the default clock configuration will be 96 MHz CPU_CLK/BUS_CLK and 24
MHz slow clock.
Table 20. Power mode transition operating behaviors
tSLEEP SLEEP → ACTIVE — 8.95 9.4 μs
tDSLEEP DEEP SLEEP → ACTIVE — 9.6 10.1 μs
tPWDN POWER DOWN → ACTIVE 233.86 234.33 234.59 μs
tDPWDN Deep Power DOWN → ACTIVE 747.59 816.12 835.00 μs
2.2.7 Power consumption operating behaviors

The KW45B41Z device has multiple power supplies that can be connected in different configurations, where the total current
consumption of the device is the accumulative result of each individual power supply's current consumption. All current
consumption specifications are measured with a bench power supply that provides externally the different voltage levels required
by each power domain in the corresponding KW45 power mode configuration.
When calculating the total MCU current consumption, the following considerations should be made:
• Specifications below only include power for the MCU itself
• On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
• Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered
The maximum values stated in the following sections represent characterized results equivalent to the mean plus three times the
standard deviation (mean + 6 sigma).
2.2.7.1 Power Consumption Operating Behaviors
Table 21. Power Consumption Operating Behaviors
DCDC Power Configuration
Mode# Symbol Description Temp Typ Max Unit Notes
IDD_ACT IDD_ACT1 Active 1 mode –40 °C 4.9 – mA 1,2
8 current - DCDC
25 °C 5.1 –
in low strength,
Core voltage = 1.0 85 °C 5.4 –
V, all peripherals
disabled, executing 105 °C 5.8 –
while(1) from
FLASH in both
CM33 at 48 MHz
and NBU at 32 MHz

NXP Semiconductors
General
Table 21. Power Consumption Operating Behaviors (continued)
IDD_ACT IDD_ACT2 Active 2 mode 25 °C 5.5 – 2,3
15 current - DCDC
in normal strength,
Core voltage = 1.1
V, all peripherals
enabled, executing
while(1) from
FLASH in both
CM33 at 48 MHz
and NBU at 32 MHz
16 current - DCDC
in normal strength,
Core voltage = 1.1
V, all peripherals
enabled, executing
while(1) from
FLASH in both
CM33 at 48 MHz
and NBU at 32 MHz
17 current - DCDC
in normal strength,
Core voltage = 1.1
V, all peripherals
disabled, executing
while(1) from
FLASH in both
CM33 at 96 MHz
and NBU at 32 MHz
IDD_CM IDD_CM1 CoreMark 1 mode –40 °C 6.0 – mA 2,3
1 current - DCDC
25 °C 6.2 –
in normal strength,
Core voltage = 1.1 85 °C 6.4 –
V, all peripherals
105 °C 7.7 –
disabled, executing
CoreMark® code
from FLASH in
CM33 at 96MHz,
NBU in sleep mode.
IDD_CM IDD_CM2 CoreMark 2 mode 25 °C 4.6 – 1,2
22 current - DCDC
in low strength,
Core voltage = 1.0
V, all peripherals
disabled, executing
CoreMark® code
from FLASH in

NXP Semiconductors
General
CM33 at 48MHz,
NBU in sleep mode.
IDD_DS1 IDD_DS1 Deep Sleep 1 –40 °C 3.0 – µA 4
mode current -
25 °C 2.8 –
All regulators in
low-power mode, 85 °C 12.5 –
all RAM retained,
all peripherals, 105 °C 26.2 –
NBU, and
EdgeLock disabled,
OSC32K enabled
IDD_DS2 IDD_DS2 Deep Sleep 2 –40 °C 2.9 – µA 4
mode current - All

25 °C 2.5 –
regulators in low
power, 16 KB of 85 °C 9.2 –
RAM retained, all
105 °C 18.4 –
radio RAM retained,
all peripherals,
NBU, and Edge
Lock disabled,
OSC32K enabled
IDD_PD2 IDD_PD1 Power Down 1 –40 °C 3.8 – µA 4
mode current - All

25 °C 3.4 –
regulators in low
power, 16 KB of 85 °C 9.8 –
RAM retained, all
105 °C 18.3 –
radio RAM retained,
all peripherals,
NBU, and Edge
Lock disabled,
FRO32K enabled
IDD_DP IDD_DPD1 Deep Power Down –40 °C 1.70 – µA 4
D2 1 mode current
25 °C 1.2 –
- LDO_CORE
and DCDC off, 85 °C 3.7 –
LDO_SYS in low
105 °C 7.2 –
power, no RAM
retained, no radio
RAM retained,
all peripherals,
NBU, and
EdgeLock disabled,
FRO32K enabled
PMIC Power Configuration
Mode Symbol Description Temp Typ Max Unit Notes
IDD_ACT IDD_ACT5 Active 5 mode –40 °C 6.9 – mA 2,5
14 current - Core
25 °C 7.0 –

NXP Semiconductors
General
voltage = 1.0 85 °C 7.7 –

V, all peripherals
105 °C 8.4 –
disabled, executing
while(1) from
FLASH in both
CM33 at 48 MHz
and NBU at 32 MHz
IDD_ACT IDD_ACT6 Active 6 mode 25 °C 10 – mA 2, 6
18 current - Core
voltage = 1.1 V, all
peripherals enabled,
executing while(1)
from FLASH in both
CM33 at 48 MHz
and NBU at 32 MHz
IDD_ACT IDD_ACT7 Active 7 mode 25 °C 17 – mA 2,6
19 current - Core
voltage = 1.1 V, all
peripherals enabled,
executing while(1)
from FLASH in both
CM33 at 96 MHz
and NBU at 32 MHz
IDD_ACT IDD_ACT8 Active 8 mode 25 °C 9.9 – mA 2,6
20 current - Core
voltage = 1.1
V, all peripherals
disabled, executing
while(1) from
FLASH in both
CM33 at 96 MHz
and NBU at 32 MHz
IDD_CM IDD_CM3 CoreMark 3 mode –40 °C 10.7 – mA 2,6
13 current - Core
25 °C 10.8 –
voltage = 1.1
V, all peripherals 85 °C 11.9 –
disabled, executing
105 °C 12.7 –
CoreMark® code
from FLASH in
CM33 at 96 MHz,
NBU in sleep mode.
IDD_CM IDD_CM4 CoreMark 4 mode 25 °C 6.9 – mA 2,5
23 current - Core
voltage = 1.0
V, all peripherals
disabled, executing
CoreMark® code
from FLASH in

NXP Semiconductors
General
CM33 at 48MHz,
NBU in sleep mode.
IDD_DS5 IDD_DS3 DeepSleep 3 mode –40 °C 7.1 – µA 5
current - all
25 °C 5.4 –
RAM retained,
all peripherals, 85 °C 24.9 –
NBU, and
EdgeLock disabled, 105 °C 53.2 –
OSC32K enabled
IDD_DS6 IDD_DS4 DeepSleep 4 mode –40 °C 5.4 – µA 5
current - 16 KB of
25 °C 4.5 –
RAM retained, all
radio RAM retained, 85 °C 17.3 –
all peripherals,
105 °C 34.9 –
NBU, and Edge
Lock disabled,
OSC32K enabled
IDD_PD6 IDD_PD2 PowerDown 2 mode –40 °C 12.0 – µA 5
current - 16 KB of
25 °C 6.5 –
RAM retained, all
all peripherals,
NBU, and Edge 105 °C 34.8 –
Lock disabled,
FRO32K enabled
IDD_DP IDD_DPD2 DeepPowerDown 2 –40 °C 9.7 – µA 5
D4 mode current - no
25 °C 2.9 –
RAM retained, no
all peripherals,
105 °C 9.5 –
NBU, and
EdgeLock disabled,
FRO32K enabled
Smart Power Switch
Mode Symbol Description Temp Typ Max Unit Notes
IDD_SW IDD_SW_DP Smart Power Switch –40 °C 0.3 – µA 7,8
_DPD2 D1 Deep Power Down

25 °C 0.4 –
2 mode current - All
regulators off, 8 KB 85 °C 2.2 –
RAM retained, no
105 °C 3.3 –
radio RAM retained,
all peripherals,
NBU, and
EdgeLock disabled,
FRO16K enabled
1. All regulators enabled, 3.3 V supply upstream from the DCDC. DCDC output is 1.8 V, VDD_CORE =1.0. SYS_LDO input=3.3,
output = 1.8 V.
2. FRO-192M as clock source

NXP Semiconductors
General
3. All regulators enabled, 3.3 V supply upstream from the DCDC. DCDC output is 1.35V, VDD_CORE =1.1. SYS_LDO input=3.3,
output = 1.8 V.
4. All regulators enabled, 3.3 V supply upstream from the DCDC. DCDC output is 1.25V, VDD_CORE =1.0. SYS_LDO input=3.3,
output = 1.8V.
5. All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
VDD_IO_ABC and VDD_IO_D/DCDC_IN. External 1.8V supply for VDD_SYS and VDD_RF. External 1.0V supply
for VDD_CORE.
6. All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
VDD_IO_ABC and VDD_IO_D/DCDC_IN. External 1.8V supply for VDD_SYS and VDD_RF. External 1.1V supply
for VDD_CORE.
7. 8 KB of retained RAM correspond to the last RAM block and is powered by the standby LDO in smart power switch domain
8. External 3.3 V supply to Smart Power Switch. Power switch output connected to DCDC_IN, LDO_SYS, VDD_ANA, VDD_IO_D
and VDD_IO_ABC; DCDC output connected to LDO_CORE, VDD_RF
2.2.7.2 SoC Power Consumption

SoC Power Consumption table is as follows:
Table 22. SoC POwer Consumption
CM33 Radio state DCDC state Typical Average IC Unit

current
Deep Sleep 2 Rx Buck (Vdcdc_in =3.3 V) 6.6 mA
Deep Sleep 2 Rx (scan) Buck (Vdcdc_in =3.3 V) 4.1 mA
Deep Sleep 2 Tx (+0 dBm) Buck (Vdcdc_in =3.3 V) 5.2 mA
Deep Sleep 2 Rx Disabled/Bypass 8.7 mA
Deep Sleep 2 Rx (scan) Disabled/Bypass 6.5 mA
Deep Sleep 2 Tx (+0 dBm) Disabled/Bypass 11.4 mA
2.2.7.3 Typical power-down mode RAM current adders

The table below shows typical current consumption adders on the VDD_CORE domain for different SRAM configurations. All
currents are measured in power-down mode, but RAM adder should be similar for other modes.
Table 23. Typical power-down mode RAM current adders
SRAM array Non-Secure Non-Secure Size -40 °C 25 °C 85 °C 105 °C Unit

Start Address End Address
CTCM0 0x40000000 0x40001FFF 8 KB 0.061 0.070 1.49 2.44 μA
CTCM1 0x40002000 0x40003FFF 8 KB 0.020 0.026 1.80 2.70 μA
STCM0 0x20000000 0x20003FFF 16 KB 0.142 0.151 2.95 4.68 μA

NXP Semiconductors
General
Table 23. Typical power-down mode RAM current adders (continued)
SRAM array Non-Secure Non-Secure Size -40 °C 25 °C 85 °C 105 °C Unit

Start Address End Address
STCM1 0x20004000 0x20007FFF 16 KB 0.176 0.186 3.06 5.02 μA
STCM2 0x20008000 0x2000FFFF 32 KB 0.321 0.362 4.92 8.93 μA
STCM3 0x20010000 0x20017FFF 32 KB 0.207 0.215 3.76 6.17 μA
STCM4 0x20018000 0x20019FFF 8 KB 0.045 0.046 2.02 2.33 μA
STCM5 0x2001A000 0x2001BFFF 8 KB 1.12 1.16 1.33 1.38 μA
2.2.7.4 Low power mode peripheral power consumption adders

The following measurements were performed in DCDC mode with low drive strength configured at 1.25 V. Supply voltage is at
3.3 V
Table 24. Low power mode peripheral power consumption adders
Symbol Description Temperature Unit
25 °C
LPTMR LPTMR peripheral adder 252.9 nA

measured by placing the
device in Deep Power-down
mode using the FRO-32K
configured for 1 second
prescaler with 1 minute
match. Include the FRO-32K
power consumption.
LPIT LPIT peripheral adder 3.2 µA

device in Sleep mode with
Wake Domain place in Sleep.
Using FRO6M, configured for
a 1 minute match. Does not
include selected clock source
power consumption.
TSTMR TSTMR peripheral adder 4.0 µA

device in Power-down mode
with Wake Domain place in
Sleep. Incrementing on the
1MHz clock output from the
FRO6M. Does not include the
selected clock source power
consumption.
TPM0 TPM0 peripheral adder 4.1 µA

device in Power-down
mode with Wake Domain

NXP Semiconductors
General
Table 24. Low power mode peripheral power consumption adders (continued)
place in Sleep. Using

FRO32K configured for
output compare generating a
10Hz clock signal. No load
is placed on the I/O pin
generating the clock signal.
Includes the clock source
power consumption
RTC RTC peripheral adder 210.7 nA

measured with external 32
kHz OSC enabled with an
alarm of 1 minute, by placing
the device in Deep Power-
down mode. Includes OSC-
RTC (32 kHz external crystal)
power consumption.
LPUART1 LPUART1 peripheral adder 4.2 µA

device in Sleep mode
with Wake Domain Sleep.
Selected clock source
FRO6M as clock source
waiting for Rx data at 115200
BR, configuring CC=10b for
MRCC_LPUART1. Does not
power consumption.
LPI2C1 LPI2C1 peripheral adder 3.2 µA

measured by placing
the device in Sleep
mode configured as Slave
with digital glitch filter
disabled. Does not include
consumption.
I3C LPI3C peripheral adder 3.3 µA

Wake Domain place in Sleep,
while configured as slave.
Does not include the clock
source power
LPSPI0 LPSPI0 peripheral adder 4.0 µA

Wake Domain place in Sleep,
while configured as Slave
in SPI. Does not include

NXP Semiconductors
General
the clock source power

consumption.
FlexCAN FlexCAN peripheral adder 6.8 µA

device in Deep Sleep mode
with Wake Domain placed in
Deep Sleep and configured
to receive the message
and waiting for the next
transmission of the user
initiated. Does not include the
clock source power
FlexIO FlexIO peripheral adder 3.3 µA

Wake Domain Sleep, while
Using FRO6M, emulating
UART waiting for RX data at
115200 baudrate. Does not
power consumption.
ADC ADC peripheral adder by 4.1 µA

placing the device in Sleep
mode with Wake Domain
place in Sleep. ADC in
low power single ended
mode using the FRO6M
and 10Ksps continuous
conversion. Does not include
consumption.
CMP CMP peripheral adder 3.3 µA

measured with CMP enabled
8-bit DAC and single input
for compare. The device is
placed in Sleep mode with
Does not include 6-bit DAC
power consumption
VREF VREF peripheral adder 3.9 µA

Generating a 1.2V reference
output voltage
WDOG WDOG peripheral adder 2.8 µA


NXP Semiconductors
General

The peripheral is configured
Using OSC-RTC (External
32kHz) using the longest
timeout period possible.
Includes the OSC_RTC
current consumption
2.2.8 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.
2.2.9 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions:
1. Go to https://www.nxp.com/.
2. Perform a keyword search for “EMC design”.
2.2.10 Capacitance attributes

Table 25. Capacitance attributes
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications

Table 26. Device clock specifications
VDD_CORE = 1.1 V
fCPU CPU clock (CPU_CLK) — 96 MHz
fBUS Bus clock (BUS_CLK) — 96 MHz
fSLOW Slow clock (SLOW_CLK) — 24 MHz
VDD_CORE = 1.0 V
fCPU CPU clock (CPU_CLK) — 48 MHz
fBUS Bus clock (BUS_CLK) — 48 MHz
fSLOW Slow clock (SLOW_CLK) — 24 MHz
NOTE
By default, VDD_CORE = 1.0 V, fCPU_CLK/fBUS_CLK = 32 MHz, fSLOW_CLK = 16 MHz.

NXP Semiconductors
General
2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPTMR, TPM, CAN, LPI2C, LPI3C,
LPSPI, or FlexIO functions.
Table 27. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) — 1.5 — Bus clock 1
Synchronous path cycles
GPIO pin interrupt pulse width (digital glitch filter disabled, 150 — ns
analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter disabled, 50 — ns

analog filter disabled) — Asynchronous path
External RESET and NMI pin interrupt pulse width — 330 — ns 2
Asynchronous path
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise/fall time

3
Normal I/O pins
• 2.7 ≤ VDD_IO_x ≤ 3.6 V 2.9 7 ns
— Fast slew rate (SRE = 0; DSE = 0) 6 15 ns
— Slow slew rate (SRE = 1; DSE = 0)
• 1.71 ≤ VDD_IO_x < 2.7 V 2.4 7 ns
— Fast slew rate (SRE = 0; DSE = 1) 6.1 20 ns
4
Fast I/O pins
• 2.7 ≤ VDD_IO_x ≤ 3.6 V 0.6 1.6 ns
— Fast slew rate (SRE = 0; DSE = 0) 0.8 1.8 ns
• 1.71 ≤ VDD_IO_x < 2.7 V 0.4 1.6 ns
— Fast slew rate (SRE = 0; DSE = 1) 0.6 1.9 ns

5
I2C/I3C I/O pins
• 2.7 ≤ VDD_IO_x ≤ 3.6 V
— Normal drive, fast slew rate (SRE = 0; DSE = ) 3 7 ns
— Normal drive, slow slew rate (SRE = 1; DSE = 0) 6.1 15 ns
— High drive, fast slew rate (SRE = 0; DSE = 1)

2.8 7 ns
— High drive, slow slew rate (SRE = 1; DSE = 1)
5.6 15 ns
• 1.71 ≤ VDD_IO_x < 2.7 V

NXP Semiconductors
Peripheral operating requirements and behaviors
Table 27. General switching specifications (continued)
Description Min. Max. Unit Notes
— Normal drive, fast slew rate (SRE = 0; DSE = 0) 2.8 7 ns

— Normal drive, slow slew rate (SRE = 1; DSE = 0) 6.4 20 ns
— High drive, fast slew rate (SRE = 0; DSE = 1)
2.3 7 ns
— High drive, slow slew rate (SRE = 1; DSE = 1)
5.7 20 ns
6
Reset and NMI pins
ns
3.3 6.7
• 2.7 ≤ VDD_IO_x ≤ 3.6 V
ns
4.3 20
• 1.71 ≤ VDD_IO_x < 2.7 V
1. The synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.
3. Load is 25 pF. Drive strength and slew rate are configured using PORTx_PCRn[DSE] and PORTx_PCRn[SRE].
4. These are effectively Port C pins.
5. Load is 25 pF for DSE=0 or DSE=1. Load is 50 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using
PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE].
6. Load is 25 pF.
2.4 Thermal specifications
2.4.1 Thermal operating requirements

Table 28. Thermal operating requirements
Symbol Description Min. Typical Max. Unit Notes
TJ Die junction temperature –40 25 125 °C
TA Ambient temperature –40 25 105 °C 1
1. Maximum TA can be met only if the user ensures that TJ does not exceed the maximum. The simplest method to determine
TJ is: TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes

Table 29. Thermal attributes
Board type Symbol Description 40 48 Unit Notes

HVQFN HVQFN
Four-layer (2s2p) RθJA Thermal resistance, junction to ambient 28 26 °C/W 1, 2
Four-layer (2s2p) ΨJT Thermal characterization parameter, 0.2 0.2 °C/W 1, 2
junction to package top center
1. Thermal test board meets JEDEC specification for this package (JESD51-7).
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors

NXP Semiconductors
3.1 Core modules
3.1.1 SWD electricals

Table 30. SWD timing
Operating voltage 1.71 3.6 V
S1 SWD_CLK frequency of operation — 25 MHz
S2 SWD_CLK cycle period 1/S1 — ns
S3 SWD_CLK clock pulse width 20 — ns
S4 SWD_CLK rise and fall times — 3 ns
S5 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
S6 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
S7 SWD_CLK high to SWD_DIO data valid — 25 ns
S8 SWD_CLK high to SWD_DIO high-Z 5 — ns
S2
S3 S3
SWD_CLK
S4 S4
Figure 6. Serial wire clock input timing

NXP Semiconductors
SWD_CLK
S5 S6
SWD_DIO Input data valid
S7
SWD_DIO Output data valid
S8
SWD_DIO
Figure 7. Serial wire data timing
3.2 Clock modules
3.2.1 Reference oscillator specification
This chip is designed to meet targeted specifications with a ±50 ppm frequency error over the life of the part, which includes the
temperature, mechanical, and aging excursions.
The table below shows typical specifications for the Crystal Oscillator.
Table 31. Reference Crystal Specification
Symbol Description F0 = 32.0 MHz Unit Footnotes
Min Typ Max
TA Operating Temperature –40 — 105 °C 1
Crystal frequency –33 — 30 ppm 2,3
tolerance over Aging and

Temperature
Oscillator variation –17 — 20 ppm 4
Total reference oscillator –50 — 50 ppm 5
tolerance
CL 6 8 10 pF 2,6
Load capacitance
C0 Shunt capacitance 0.469 0.67 0.871 pF 2,6
Cm1 Motional capacitance 1.435 2.05 2.665 fF 2, 6
Lm1 Motional inductance 8.47 12.1 15.73 mH 2,6
Rm1 Motional resistance — 25 50 Ohms 2

NXP Semiconductors
Table 31. Reference Crystal Specification (continued)
Symbol Description F0 = 32.0 MHz Unit Footnotes
Min Typ Max
ESR Equivalent series — 50 60 Ohms 2, 7
resistance
Pd Maximum crystal drive — — 200 µW 2
TS Trim sensitivity 6.30 9.00 11.70 ppm/pF 2,6
TOSC Oscillator Startup Time — 500 — μs 8
1. Full temperature range of this device. A reduced range can be chosen to meet application needs.
2. Recommended crystal specification.
3. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over
desired lifetime of system.
4. Variation due to temperature, process, and aging of MCU.
5. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB manufacturing
variation must not exceed this value.
6. Typical is target. 30 % tolerances shown.
7. ESR = Rm1 * (1 + [C0/CL])^2.
8. Time from oscillator enables to clock ready. Dependent on the complete hardware configuration of the oscillator.
Figure 8. Crystal Electrical Block Diagram

NXP Semiconductors
3.2.2 32 kHz oscillator electrical specifications

Table 32. 32 kHz oscillator electrical specifications
fosc_32k Crystal frequency — 32.768 — kHz
Tol Frequency tolerance — ±100 — ppm
Jitosc Jitter ns
• Period jitter (RMS) — 10 —
• Accumulated jitter over 1 ms (RMS) — 50 —
ESR Crystal equivalent series resistance — — 80/150 kΩ 1
Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 1 2 pF
tstart Crystal start-up time — 1000 8000 ms 2
IOSC_32k Current consumption

• OFF mode — 0.5 —
• ON mode — 100 — nA
Vpp Peak-to-peak amplitude of oscillation V 3

— 0.2 —
fec_extal32 Externally provided input clock frequency — 32.768 — kHz 4
vec_extal32 Externally provided input clock amplitude — VDD_SYS — mV 4, 5
Cextal/xtal EXTAL, XTAL Load Capacitance 0 — 30 pF 6
1. Maximum value is 80 kOhms for parasitic capacitances higher than 1 pF, and 150 kOhms for parasitic capacitances
around 1 pF.
2. Proper PC board layout procedures must be followed to achieve specifications.
3. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
4. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
5. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VDD_IO_D.
6. With 2 pF steps.
NOTE
It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal.
3.2.3 Free-running oscillator FRO-192M specifications

Table 33. FRO-192M specifications
Symbol Characteristic Min. Typ. Max. Unit Notes
ffro192m FRO-192M frequency (nominal) 96/192 MHz
Δffro192m Frequency deviation (–40 °C – 125 °C)

• Open loop — — ±3 %
— — ±0.25 %

NXP Semiconductors
Table 33. FRO-192M specifications (continued)
• Closed loop (using accurate clock source as

reference)
tstartup Start-up time

• Oscillation time with initial accuracy of ±20 — 2 — μs
% to ±2 % of enable signal assertion
— 10 — μs
• Oscillation time within ±2 % from enable
signal assertion
fos Frequency overshoot during startup — — 2 %
jitper • Period jitter RMS 1 — 50 — ps
• Accumulated jitter over 1 μs — 375 —
jitcyc Cycle to Cycle jitter RMS — 60 — ps
Ifro192m Current consumption — 40 100 μA
1. Reference clock = 192 MHz.
3.2.4 Free-running oscillator FRO-6M specifications

Table 34. FRO-6M specifications
ffro6m FRO-6M frequency (nominal) — 6 — MHz
Δffro6m Frequency deviation (–40 °C – 125 °C)

• open loop — — ±3 %
• closed loop (using accurate clock source as

— — ±0.6 %
reference)
tstartup Start-up time

• Oscillation time with initial accuracy of -20 % — 5 — μs
to +2 % of enable signal assertion
— 10 — μs
• Oscillation time within ± 2 % from enable
signal assertion
fos Frequency overshoot during startup — 10 — %
Ifro6m Current consumption — — 4 μA
3.2.5 Free-running oscillator FRO-32K specifications

Table 35. FRO-32K specifications
ffro32k FRO-32K frequency (nominal) — 32.768 — kHz

NXP Semiconductors
Table 35. FRO-32K specifications (continued)
Δffro32k Frequency deviation(– 40 °C –125 °C)

— — ±2 %
• open loop
TRIMstep Trimming step — 0.03 — %
tstartup Start-up time — — 120 μs
fos Frequency overshoot during startup — 10 — %

• Trimmed
Ifro32k Current consumption — 350 — nA
3.2.6 Free-running oscillator FRO-16K specifications

Table 36. FRO-16K specifications
VBAT Supply voltage operating range 1.9 2.7 3.6 V 1
Temp Temperature range –40 25 125 °C
ffro16K FRO-16K frequency (nominal) — 16.384 — kHz
Δffro16K Frequency deviation

— — ±6 %
• Over –40 °C~125 °C temperature range
TRIMstep Frequency trimming step — 1.5 — %
Ifro16k Current consumption — 50 — nA 2
Ipor Current consumption — 26 — nA
1. FRO-16K is in Power Switch block, which is powered by min 1.9 V VDD_SWITCH

2. The Typical value (70 nA) of current consumption includes 20 nA POR current consumption in stable running period.
3.3 Memories and memory interfaces
3.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.
3.3.1.1 Flash Read wait state control specifications

FCTRL[RWSC] defines the number of read wait-states in the flash module for FMC read access to the flash array during full power
and low-power modes. The following requirements must be met.
Table 37. Recommend RWSC settings on KW45 (for MCU flash and Radio Flash)
Mode Typical Frequency (MHz) FCTRL[RWSC]
SD – 1.1 V 96 0010b
SD – 1.1 V 64 0001b
SD – 1.1 V 48 0001b

NXP Semiconductors
Table 37. Recommend RWSC settings on KW45 (for MCU flash and Radio Flash) (continued)
Mode Typical Frequency (MHz) FCTRL[RWSC]
MD – 1.0 V 48 0001b
MD – 1.0 V 32 0000b
3.3.1.2 Flash timing specifications

The following command times assume a flash bus clock frequency of 24 MHz.This clock come from SLOW_CLK. Command times
will be increased by up to 10 µs at 24 MHz if the module is exiting sleep mode when the command is launched. The time to abort
a command is not included in the following table.
Table 38. Flash command time specifications
Symbol Description Typ. Max. Unit Notes
trd1all1024k Read 1s All execution time (1024 KB) — 6200 µs
trd1blk1024k Read 1s Block execution time (1024 KB) — 6000 µs
trd1scr Read 1s Sector execution time — 50 µs 1
trd1pg Read 1s Page execution time — 4.4 µs 1
trd1pglv Read 1s Page at low voltage execution time — 5.8 µs 1
trd1phrlv Read 1s Phrase at low voltage execution time — 4.8 µs 1
trd1ipglv Read 1s IFR Page at low voltage execution time — 5.8 µs 1
trd1iphrlv Read 1s IFR Phrase at low voltage execution time — 4.8 µs 1
trd1phr Read 1s Phrase execution time — 3.8 µs 1
trdmisr8k Read into MISR (8 KB) — 50 µs 1
trdmisr1024k Read into MISR (1024 KB) — 6000 µs 1
trd1iscr Read 1s IFR Sector execution time — 50 µs 1
trd1ipg Read 1s IFR Page execution time — 4.4 us 1
trd1iphr Read 1s IFR Phrase execution time — 3.8 µs 1
trdimisr8k Read IFR into MISR (8 KB) — 50 µs 1
trdimisr32k Read IFR into MISR (32 KB) — 190 µs 1
tpgmpg Program Page execution time 450 1000 µs 2
tpgmphr Program Phrase execution time 135 375 µs 2
tersall1024k Erase All execution time (1024 KB) — 2800 ms
tmasers1024k Mass Erase execution time (1024 KB) — 2800 ms
tersscr Erase Sector execution time 2 22 ms 2
1. Time to abort the command may significantly impact the time to execute the command.
2. Measured from the time PERDY is cleared.

NXP Semiconductors
3.3.1.3 Flash high voltage current behavior
Table 39. Flash high voltage current behavior
IDD_IO_PGM Average current adder to VDD_IO_x during flash — — 6 mA 1
programming operation
IDD_IO_ERS Average current adder to VDD_IO_x during flash — — 4 mA 1
erase operation
1. See the Power Management chapter in the reference manual for the specific VDD_IO_x voltage supply powering the flash
array.
3.3.1.4 Flash reliability specifications
Table 40. Flash reliability specifications
Symbol Description Min. Typ.1 Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 10 50 — years
nnvmcycscr Sector cycling endurance 10 K 500 K — cycles 2
Tnvmretp1k Data retention after up to 1 K cycles 20 100 — years
Tnvmretp100 Data retention after up to 100 K cycles 5 50 — years

k
Nnvmcyc256 Sector cycling endurance for 256 KB per array 100 K 500 K — cycles 3
k block
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile.
2. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40 °C ≤ Tj ≤ 125 °C.
3. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices
with two flash blocks, sectors must be located within the last 256 KB of each flash main memory.
3.4 Radio modules
3.4.1 2.4 GHz radio transceiver electrical specification
Table 41. 2.4 GHz radio transceiver specifications
VDD_RF RF supply voltage 1.175 1.2 3.6 V
VPA_2P4 Supply voltage for 2.4 GHz radio power amplifier 0.9 — 2.4 V 1, 2
GHZ
fin Input RF frequency 2.360 — 2.4835 GHz
fc Output RF frequency 2.360 — 2.4835 GHz
Pmax RF input power — — 10 dBm
fref Crystal reference oscillator frequency — 32 — MHz

NXP Semiconductors
Table 41. 2.4 GHz radio transceiver specifications (continued)
ftol Frequency tolerance — ±50 — ppm
Trx_tx Rx - Tx turnaround time — 150 — μs 3
1. Voltage required at this rail depends on the desired output power. See Transmit and PLL Feature Summary for the
required voltages.
2. VPA_2P4GHZ is internally connected to the VDD_RF pin. When not powered externally, VPA_2P4GHZ = VDD_RF - 0.275
V. An internal regulator prevents VPA_2P4GHZ from going above 2.4 V when powered through the VDD_RF pin.
3. Bluetooth LE. Other modes have different requirements
3.4.2 Receiver Feature Summary

Table 42. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted)
Characteristic1 Symbol Min. Typ. Max. Unit
Receiver Active Power Consumption
Supply current Rx On with DC-DC converter enable IRxon — 4.68 — mA

(Buck; VDD_DCDC =3.3 V, VDD_RF=VDD_LDO_CORE
= 1.25 V) 2
Supply current Rx On with DC-DC converter disabled IRxon — 10.01 — mA

(Bypass, VDD_RF = VDD_LDO_CORE = 3.3. V) 2
Receiver General Specifications
Input RF Frequency Fin 2.360 — 2.4835 GHz
GFSK Rx Sensitivity(250 kbps GFSK-BT = 0.5, h = 0.5)3 SENSGFSK — –103 — dBm
Max RX RF Input Signal Level RFinMax — — 10 dBm
Noise Figure for maximum gain mode @ typical NFHG — 6.5 — dB

sensitivity4
Receiver Signal Strength Indicator Range5 RSSIRange -100 — 06 dBm
Receiver Signal Strength Indicator Resolution RSSIRes — 1 — dB
Typical RSSI variation over frequency –2 — 2 dB
Typical RSSI variation over temperature –2 — 2 dB
Narrowband RSSI accuracy7 RSSIAcc –3 — 3 dB
Spurious Emission < 1.6 MHz offset (Measured with 100 — — –54 — dBc
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc| < 1.6
MHz
Spurious Emission > 2.5 MHz offset (Measured with 100 — — –70 — dBc
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc| > 2.5
MHz8
Bluetooth LE coded 125 kbps (Long Range, 8x Spreading)

NXP Semiconductors
Table 42. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued)
Bluetooth LE LR 125 kbps Sensitivity9,3 SENSBLELR125 — –106 — dBm
Bluetooth LE LR 125 kbps Co-channel Interference COSELBLELR125 –2 dB

(Wanted signal at –67 dBm, BER < 0.1 %. Measurement
resolution 1 MHz).
Adjacent/Alternate Channel Performance10

Bluetooth LE LR 125 kbps Adjacent ±1 MHz Interference SELBLELR125, 1 — 8 — dB
offset (Wanted signal at –67 dBm, BER < 0.1 %. MHz
Measurement resolution 1 MHz.)
Bluetooth LE LR 125 kbps Adjacent ± 2 MHz Interference SELBLELR125, 2 — 50/35 — dB

Bluetooth LE LR 125 kbps Alternate ±3 MHz Interference SELBLELR125, 3 — 55/45 — dB

Bluetooth LE LR 125 kbps Alternate ≥ ±4 MHz SELBLELR125, 4+ — 55 — dB

Interference offset (Wanted signal at –67 dBm, BER < MHz
0.1 %. Measurement resolution 1 MHz.)11
Bluetooth LE coded 500 kbps (Long Range, 2x Spreading)
Bluetooth LE LR 500 kbps Sensitivity9,3 SENSBLELR500 — –102 — dBm
Bluetooth LE LR 500 kbps Co-channel Interference COSELBLELR500 –3 dB

(Wanted signal at –67 dBm, BER < 0.1 %. Measurement
resolution 1 MHz).

Bluetooth LE LR 500 kbps Adjacent ±1 MHz Interference SELBLELR500, 1 — 8 — dB
Bluetooth LE LR 500 kbps Adjacent ±2 MHz Interference SELBLELR500, 2 — 50/35 — dB

Bluetooth LE LR 500 kbps Alternate ±3 MHz Interference SELBLELR500, 3 — 55/45 — dB

Bluetooth LE LR 500 kbps Alternate ≥ ±4 MHz SELBLELR500, 4+ — 52 — dB

Interference offset (Wanted signal at –67 dBm, BER < MHz
0.1 %. Measurement resolution 1 MHz.)11
Bluetooth LE un-coded 1 Mbps
Bluetooth LE 1 Mbps Sensitivity9,3 SENSBLE1M — –97.5 — dBm
Bluetooth LE 1 Mbps Co-channel Interference (Wanted COSELBLE1M –6 dB

signal at –67 dBm, BER < 0.1 %. Measurement
resolution 1 MHz).

NXP Semiconductors
Adjacent/Alternate Channel Selectivity Performance10

Bluetooth LE 1 Mbps Selectivity ±1 MHz Interference SELBLE1M, 1 MHz — 0 — dB
offset (Wanted signal at –67 dBm, BER < 0.1 %.
Bluetooth LE 1 Mbps Adjacent ±2 MHz Interference SELBLE1M, 2 MHz — 45/35 — dB

Bluetooth LE 1 Mbps Selectivity ±3 MHz Interference SELBLE1M, 3 MHz — 53/45 — dB

Bluetooth LE 1 Mbps Alternate ≥ ±4 MHz Interference SELBLE1M, 4+ MHz — 52 — dB

Measurement resolution 1 MHz.)11
Intermodulation Performance
Bluetooth LE 1 Mbps Intermodulation with continuous IM3-6BLE1M — –27 — dBm
wave interferer at ±3 MHz and modulated interferer is at
IM4-8BLE1M
±6 MHz (or ±8 MHz) – Wanted signal at –67 dBm, BER <
0.1 %.

wave interferer at ±5 MHz and modulated interferer is at
±10 MHz – Wanted signal at –67 dBm, BER < 0.1 %.
Blocking Performance
Bluetooth LE 1 Mbps Out of band blocking from 30 MHz — –2 — — dBm
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted signal
at –67 dBm, BER < 0.1 %. Interferer continuous wave
signal.)12
Bluetooth LE 1 Mbps Out of band blocking from 1000 — –10 — — dBm

MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted
signal at –67 dBm, BER < 0.1 %. Interferer continuous
wave signal.)

wave signal.)13
Bluetooth LE 1 Mbps Out of band blocking from 5000 — 2 10 — dBm

MHz to 12750 MHz (Wanted signal at –67 dBm, BER < 0.
1 %. Interferer continuous wave signal.)13
Bluetooth LE un-coded 2 Mbps (High Speed)
Bluetooth LE 2 Mbps Sensitivity9,3 SENSBLE2M — –95 — dBm
Bluetooth LE 2 Mbps Co-channel Interference (Wanted COSELBLE2M –7 dB

signal at –67 dBm, BER < 0.1 %. Measurement
resolution 1 MHz).

NXP Semiconductors

Bluetooth LE 2 Mbps Adjacent ±2 MHz Interference SELBLE2M, 2 MHz — 5 — dB
Bluetooth LE 2 Mbps Alternate ±4 MHz Interference SELBLE2M, 4 MHz — 42/30 — dB

Bluetooth LE 2 Mbps Selectivity ±6 MHz Interference SELBLE2M, 6 MHz — 50 — dB

Bluetooth LE 2 Mbps Selectivity ≥±8 MHz Interference SELBLE2M, 8+ MHz — 52 — dB

Measurement resolution 1 MHz.)11
Intermodulation Performance
wave interferer at ±6 MHz and modulated interferer is
at ±12 MHz (or ±16 MHz) -- Wanted signal at –67 dBm,
BER < 0.1 %.

wave interferer at ±8 MHz (±10 MHz) and modulated
IM4-10BLE2M
interferer is at ±16 MHz (or ±20 MHz) – Wanted signal at
–67 dBm, BER < 0.1 %.)
Blocking Performance
Bluetooth LE 2 Mbps Out of band blocking from 30 MHz — –4 — — dBm
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted signal
at –67 dBm, BER < 0.1 %. Interferer continuous wave
signal.)12

wave signal.)

wave signal.)13
Bluetooth LE 2 Mbps Out of band blocking from 5000 — 2 10 — dBm

MHz to 12750 MHz (Wanted signal at –67 dBm, BER <
0.1 %. Interferer continuous wave signal.)13
1. All the RX parameters are measured at the RF pins.

2. Transceiver power consumption.
3. Variation across temperature (-40 °C to 105 °C) is up to 3 dB.
4. Receiver noise Figure is computed from RF pin to composite (I+jQ) ADC output
5. Narrow-band RSSI mode.
6. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
7. With one point calibration over frequency and temperature.

NXP Semiconductors
8. Exceptions allowed for twice the reference clock frequency(fref) multiples.

9. Measured at 0.1 % BER using 37 byte long packets in maximum gain mode and nominal conditions.
10. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
11. Exceptions allowed for multiple of XTAL frequency
12. Exceptions allowed for carrier frequency sub harmonics.
13. Exceptions allowed for carrier frequency harmonics.
Table 43. Receiver Specifications with Generic FSK Modulations
Adjacent/Alternate channel selectivity (dB)1
Modulation Data Channel Typical Desired Interferer Interferer Interferer Interferer Co-
type rate BW (kHz) sensitivity signal at ±1* at ±2* at ±3* at ±4* channel
(kb/s) (dBm)2 level channel channel channel channel
(dBm) BW offset BW offset BW offset BW offset
GFSK BT = 2000 4000 -95 -67 5 45/35 52 55 7

0.5, h = 0.5
1000 2000 -98 -67 0 42/32 52/42 55 7
500 1000 -101 -85 40 50/35 55 55 6
250 500 -103 -85 38 48 52 55/35 6
1. Selectivity measured with an unmodulated blocker.

3.4.3 Transmit and PLL Feature Summary

• Supports constant envelope modulation of 2.4 GHz ISM frequency band.
• Fast PLL Lock time: < 25 µs
• Reference Frequency:
— 32 MHz crystals supported for Bluetooth LE and Generic FSK modes
Table 44. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted)
Transmitter Active Power Specifications
Supply current Tx On with PRF = 0 dBm and DC-DC ITX0dBm — 4.60 — mA

converter enabled (Buck; VDD_DCDC = 3.3 V, VDD_RF
= VDD_LDO_CORE = 1.25 V) 2
Supply current Tx On with PRF = 0 dBm and ITX0dBmb — 9.83 — mA

DC-DC converter disabled (Bypass, VDD_RF =
VDD_LDO_CORE = 3.3 V) 2
Supply current Tx On with PRF = +4 dBm and DC-DC ITX4dBm — 7.63 — mA

Supply current Tx On with PRF = +4 dBm and ITX4dBm — 11.89 — mA

VDD_LDO_CORE = 3.3 V) 2


NXP Semiconductors
Table 44. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued)
Supply current Tx On with PRF = +7 dBm and ITX7dBmb — 16.81 — mA

VDD_LDO_CORE = 3.3 V, LDO_ANT ≥ 1.61 V)2
= VDD_LDO_CORE = LDO_ANT = 2.4 V)2
Supply current Tx On with PRF = +10 dBm ITX10dBmb — 20.99 — mA

and DC-DC converter disabled (Bypass, VDD_RF =
VDD_LDO_CORE = 3.3 V, LDO_ANT ≥ 2.21 V)2
Transmitter General Specifications
Output RF Frequency fRFout 2.360 — 2.4835 GHz
Maximum RF Output Power; 10 dBm configuration 3,4 PRF,maxV — 10 — dBm
Minimum RF Output power 5,4 PRF,minn — -30 — dBm
RF Output power control range (nominal power supply) PRFCR — 32 — dB
Bluetooth LE Maximum Deviation of the Carrier Fcdev,BLE — ±3 — kHz

Frequency6
Bluetooth LE Frequency Hopping Support YES
2nd Harmonic of Transmit Carrier Frequency (Pout = TXH2 — –53 — dBm/MHz

PRF,max)7,8
3rd Harmonic of Transmit Carrier Frequency (Pout = TXH3 — –50 — dBm/MHz

PRF,max)8
Bluetooth LE un-coded 1 Mbps/coded 125 kbps/coded 500 kbps
Bluetooth LE 1 Mbps TX Output Spectrum 20 dB BW TXBWBLE1M 1.0 — MHz
Bluetooth LE 1 Mbps average frequency deviation using Δf1avg,BLE1M 250 kHz

a 00001111 modulation sequence
Bluetooth LE 1 Mbps average frequency deviation using Δf2avg,BLE1M 220 kHz

Bluetooth LE 1 Mbps RMS FSK Error FSKerr,BLE1M 3%
Bluetooth LE 1 Mbps Adjacent Channel Transmit Power PRF2MHz,BLE1M — — -55 dBc

at 2 MHz offset8

at ≥ 3 MHz offset8
Bluetooth LE un-coded 2 Mbps
Bluetooth LE 2 Mbps TX Output Spectrum 20 dB BW TXBWBLE2M 2.0 — MHz
Bluetooth LE 2 Mbps average frequency deviation using Δf1avg,BLE2M — 500 — kHz

Bluetooth LE 2 Mbps average frequency deviation using Δf2avg,BLE2M — 440 — kHz


NXP Semiconductors
Table 44. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued)
Bluetooth LE 2 Mbps RMS FSK Error FSKerr,BLE2M — 4% —

at 4 MHz offset8

at ≥ 6 MHz offset8
1. All the TX parameters are measured at test hardware SMA connector.

2. Transceiver power consumption. NBU running at @16 MHz.
3. Measured at RF pins, with VPA_2P4GHz ≥ 2.4 V.
5. Measured at the RF pins single supply configuration VDD_RF = VDD_LDO_CORE = 1.25V
6. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
7. Harmonic levels based on recommended 2 component match for TX output power ≤ 5 dBm. Transmit harmonic levels
depend on the quality of matching components. Additional harmonic margin using a 3rd matching component (1x shunt
capacitor) is possible.
8. Measured at Pout > 5 dBm and recommended high-power TX match.
Transmit PA driver output as a function of the TX-PA_POWER[5:0] field when measured at the IC pins is as follows:
Figure 9. TX Pout (dBm) as function TX-PA Power Code at RF pins

NXP Semiconductors
Table 45. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1 V / 0 dBm output power target
TX Pout (dBm)
PA_POWER LDO ANT T = –40 °C T = 25 °C T = 105 °C
1 2 –31.27 –32.44 –30.36
2 2 –25.34 –26.44 –24.92
4 2 –19.42 –20.5 –19.15
6 2 –16.01 –17.09 –15.7
8 2 –13.67 –14.73 –13.24
10 2 –11.77 –12.83 –11.36
12 2 –10.24 –11.28 –9.91
14 2 –8.94 –10 –8.65
16 2 –7.92 –8.97 –7.57
18 2 –6.92 –7.97 –6.61
20 2 –6.04 –7.08 –5.79
22 2 –5.26 –6.3 –5.04
24 2 –4.59 –5.64 –4.38
26 2 –3.94 –4.97 –3.77
28 2 –3.34 –4.37 –3.25
30 2 –2.8 –3.83 –2.75
32 2 –2.33 –3.36 –2.26
34 2 –1.86 –2.87 –1.85
36 2 –1.4 –2.4 –1.5
38 2 –0.99 –1.98 –1.18
40 2 –0.64 –1.61 –0.89
42 2 –0.28 –1.25 –0.63
44 2 0.05 –0.91 –0.41
46 2 0.36 –0.6 –0.2
48 2 0.57 –0.36 –0.04
50 2 0.85 –0.08 0.12
52 2 1.09 0.19 0.27
54 2 1.32 0.42 0.42
56 2 1.5 0.63 0.54
58 2 1.69 0.85 0.65
60 2 1.87 1.04 0.75

NXP Semiconductors
Table 45. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1 V / 0 dBm output power target
(continued)
TX Pout (dBm)
PA_POWER LDO ANT T = –40 °C T = 25 °C T = 105 °C
62 2 2.02 1.22 0.86
Figure 10. TX Pout (dBm) as function TX-PA Power Code at 7 dBm
Table 46. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1.6 V / 7 dBm output power target
TX Pout (dBm)
PA_POWER LDO_ANT T =–40 °C T = 25 °C T =105 °C
1 8 –23.66 –24.11 –24.37
2 8 –18.06 –18.45 –18.72
4 8 –12.13 –12.54 –12.81
6 8 –8.72 –9.11 –9.38
8 8 –6.29 –6.68 –6.96
10 8 –4.42 –4.79 –5.07
12 8 –2.9 –3.29 –3.56
14 8 –1.62 –2.01 –2.28
16 8 –0.45 –0.85 –1.12

NXP Semiconductors
Table 46. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1.6 V / 7 dBm output power target
(continued)
TX Pout (dBm)
PA_POWER LDO_ANT T =–40 °C T = 25 °C T =105 °C
18 8 0.51 0.13 –0.14
20 8 1.38 0.99 0.72
22 8 2.15 1.75 1.49
24 8 2.79 2.39 2.12
26 8 3.42 3.03 2.75
28 8 3.98 3.59 3.28
30 8 4.49 4.1 3.78
32 8 4.99 4.6 4.25
34 8 5.41 5.03 4.66
36 8 5.79 5.41 5.01
38 8 6.13 5.75 5.33
40 8 6.42 6.05 5.6
42 8 6.69 6.32 5.85
44 8 6.91 6.57 6.06
46 8 7.13 6.79 6.26
48 8 7.31 6.97 6.41
50 8 7.49 7.15 6.58
52 8 7.65 7.33 6.72
54 8 7.8 7.48 6.86
56 8 7.91 7.61 6.96
58 8 8.05 7.74 7.08
60 8 8.15 7.85 7.18
62 8 8.26 7.96 7.27

NXP Semiconductors
Figure 11. TX Pout (dBm) as function TX-PA Power Code at 10 dBm
Table 47. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output
TX Pout (dBm)
PA_POWER LDO_ANT T = -40 °C T = 25 °C T = 105 °C
1 12 –21.93 –22.25 –22.52
2 12 –16.29 –16.59 –16.86
4 12 –10.39 –10.67 –10.95
6 12 –6.97 –7.24 –7.52
8 12 –4.55 –4.82 –5.09
10 12 –2.66 –2.93 –3.19
12 12 –1.16 –1.43 –1.69
14 12 0.11 –0.16 –0.42
16 12 1.27 1.01 0.76
18 12 2.27 1.99 1.74
20 12 3.13 2.85 2.6
22 12 3.9 3.62 3.37
24 12 4.55 4.26 4.01
26 12 5.19 4.9 4.63

NXP Semiconductors
Table 47. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output (continued)
TX Pout (dBm)
PA_POWER LDO_ANT T = -40 °C T = 25 °C T = 105 °C
28 12 5.74 5.46 5.18
30 12 6.26 5.97 5.68
32 12 6.78 6.5 6.19
34 12 7.23 6.95 6.62
36 12 7.63 7.36 7
38 12 7.99 7.72 7.35
40 12 8.31 8.05 7.65
42 12 8.61 8.35 7.94
44 12 8.87 8.62 8.18
46 12 9.12 8.87 8.42
48 12 9.32 9.07 8.6
50 12 9.54 9.29 8.81
52 12 9.74 9.49 8.99
54 12 9.91 9.66 9.15
56 12 10.06 9.82 9.28
58 12 10.21 9.98 9.42
60 12 10.34 10.11 9.55
62 12 10.47 10.24 9.67
3.5 Analog
3.5.1 ADC electrical specifications
3.5.1.1 16-bit ADC operating conditions
Table 48. 16-bit ADC operating conditions
VDD_ANA Supply voltage 1.71 — 3.6 V
ΔVDD_ANA Supply voltage delta to VDD (VDD – VDD_ANA) –0.1 0 +0.1 mV 2
ΔVSS_ANA Ground voltage delta to VSS (VSS – VSS_ANA) –0.1 0 +0.1 mV 2
VREFH ADC reference voltage high 0.99 VDD_ANA VDD_ANA V
VREFL ADC reference voltage low VSS_ANA VSS_ANA VSS_ANA V 3
VADIN Input voltage VREFL — VREFH V 3, 4,5

NXP Semiconductors
Table 48. 16-bit ADC operating conditions (continued)
fADCK ADC input clock frequency

• Low-power mode (PWRSEL=00) 6 — 20 MHz
• High-speed 16b mode (PWRSEL = 10) 6 — 48 MHz

• High-speed 12b mode (PWRSEL = 10)
6 — 60 MHz
CADIN Input capacitance — 3.7 4.63 pF
Cp Parasitic Cap of pad /package — 2 3 pF
RAS Analog source resistance (external) — — 5 kΩ 6
RADIN kΩ 7,8
• High-speed dedicated input channel (CH0:3)
— VDD_ANA ≥ 1.71 V — 0.95 1.7
— VDD_ANA ≥ 2.1 V — 0.95 1.6
— VDD_ANA ≥ 2.5 V — 0.95 1.4
• Standard external input channel (Ch4:7)

— VDD_ANA ≥ 1.71 V — 1.35 3.25
— VDD_ANA ≥ 2.1 V — 1.35 2.15
— VDD_ANA ≥ 2.5 V — 1.35 1.75
• Standard muxed input channel (Ch4:11)

— VDD_ANA ≥ 1.71 V — 1.65 7.25
— VDD_ANA ≥ 2.1 V — 1.65 3.05
— VDD_ANA ≥ 2.5 V — 1.65 2.35
1. Typical values assume VDD_ANA= 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
4. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a full
scale conversion result
5. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected
muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD_IO_X) when a
conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used
between the source and the ADC input pin.
6. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible.
7. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index
map in reference manual
8. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel
type

NXP Semiconductors
Figure 12. ADC input impedance equivalency diagram
3.5.1.2 16-bit ADC electrical characteristics
Table 49. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA)
IDDA Supply current 2
• PWREN=0, Conversions triggered at 1 kS/s — 2.2 — μA

• PWREN=1, No Conversions — 160 215 μA
• Low-power, single-ended mode, 6 MHz — 340 440 μA
• Low-power, or dual-SE mode, 6 MHz — 500 640 μA
• Low-power, single-ended mode, 24 MHz — 415 530 μA
• Low-power, or dual-SE mode, 24 MHz — 580 750 μA
• High-speed, single-ended mode, 48 MHz — 940 1200 μA
• High-speed, or dual-SE mode, 48 MHz — 1500 1950 μA
ITS Temp Sensor Current Adder — 40 50 μA
CSMP ADC Sample cycles 3.5 — 131.5 cycles 3
CCONV ADC conversion cycles 24 — 152 cycles
CRATE ADC conversion rate MS/s 4

— — 0.857

NXP Semiconductors
Table 49. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA) (continued)
• Low-power mode — — 2
• High-speed mode (16-bits) — — 3.16
• High-speed mode (12-bits)
TSMP_REQ Required Sample Time ns 5

See — —
equation
TAZ_REQ Required Auto-zero Time ns 5

291.7 — —
• Low-power mode
72.9 — —
• High-power mode (16-bits)
58.3 — —
• High-power mode (12-bits)
TSMP Sample Time External inputs See — — ns 5
equation
TSMP_INT Internal channel sample time 1.5 — — μs 6
DNL Differential non-linearity — ±0.7 +1.4/–0.95 LSB7 8
INL Integral non-linearity — ±2.0 +4.0/–2.0 LSB7 8
ZSE Zero-scale error (VADIN = VREFL) — ±1.0 ±2.0 LSB7 8
FSE Full-scale error (VADIN=V REFH) — ±2.0 +2.0/–8.0 LSB7 8
TUE Total unadjusted error — ±4.0 ±10.0 LSB7 8
ENOB 8,9
Effective number of bits
• Differential mode bits
12.7 13.5 —
— 0.5 MS/s
— 2 MS/s 12.0 12.7 —
• Single-ended mode
— 0.5 MS/s 12.4 13.1 —
— 2 MS/s 11.5 12.2 —
SINAD Signal-to-noise plus distortion 8,9

dB
• Differential mode
80 86 —
— 0.5 MS/s
75 79 —
— 2 MS/s
• Single-ended mode
77 81 —
— 0.5 MS/s
71 75 —
— 2 MS/s
THD Total harmonic distortion 85 92 — dB 8,10
SFDR Spurious free dynamic range 86 94 — dB 8,10

NXP Semiconductors
Table 49. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA) (continued)
TSU ADC/VREF start-up time 5 — — μs 11
EIL Input leakage error — Ilkg × RAS — mV 12
ETS Temperature sensor error °C 13

— ±1 ±3
• T=–40 °C to 105 °C
— ±1.5 ±4
• T=–40 °C to 125 °C
1. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. The ADC supply current depends on the ADC conversion clock speed, conversion rate and power mode. Typical value
show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00.
3. Must meet minimum TSMP requirement.
4. Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is
FADCK = 24 MHz and 7.5 sample cycles (to meet the minimum auto-zero time requirement).
5. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired
sample accuracy in bits. Calculated it with formula: T SMP_REQ = B*IN(2)*[RAS*(CAS*CP)+ (RAS + R ADIN)* CADIN(typ).
Required auto-zero time is for ADC comparator offset cancellation. The chosen sample time should be no less than
maximum of the two: TSMP = max(TSMP_REQ,TAZ_REQ).
6. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap).
7. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16-bit specifications, multiply by 4.
8. All accuracy numbers assume the ADC is calibrated with VREFH=VDD_ANA and using a high-speed dedicated input channel.
9. Dynamic results assume Fin = 1 kHz sinewave, AVGS = 0 for 2 MS/s, AVGS = 4 for 0.5 MS/s.
10. Dynamic results assume Fin = 1 kHz sinewave, no averaging.
11. Set the power up delay (PUDLY) according to the ADC start-up time if PWREN=0.
12. Ilkg = leakage current (Refer to pin leakage specification in the packaged device's voltage and current operating ratings).
13. The temperature sensor can be calibrated to a ± 0.5% precision after board assembly by using a 3 temperature calibration
flow with accurate ± 0.15 % temperature chamber.
3.5.2 CMP and 8-bit DAC electrical specifications

Table 50. Comparator and 8-bit DAC electrical specifications
VDD_IO_A Supply voltage 1.71 — 3.6 V

BC
VREFH 8-bit DAC reference voltage high 0.97 — VDD_IO_A V

BC
IDD_CMP Supply current

— 200 — μA
• High-speed mode (EN=1, HPMD=1)
— 10 — μA
• Normal mode (EN=1, HPMD=0, NPMD=0)
• Nano mode (EN=1, HPMD=0, NPMD=1) — 400 — nA
VAIN Analog input voltage VSS_ANA — VDD_ANA V 1
VAIO Analog input offset voltage

• High-speed mode — — 20 mV
• Normal mode
— — 20 mV

NXP Semiconductors
Table 50. Comparator and 8-bit DAC electrical specifications (continued)
• Nano mode — — 40 mV
VH Analog comparator hysteresis 2

— 0 — mV
• CR0[HYSTCTR] = 00
— 10 — mV
— 20 — mV
— 30 — mV
tD 3
Propagation delay
• High-speed mode, 100 mV overdrive, power — — 25 ns
> 1.71 V
• High-speed mode, 30 mV overdrive, power — — 50 ns
> 1.71 V
• Normal mode, 30 mV overdrive, power > — — 600 ns
1.71 V
μs
— — 5
• Nano mode, 30 mV overdrive, power > 1.71
V
tinit Analog comparator initialization delay — — 40 μs 4
IDAC8b 8-bit DAC current adder (enabled)

— 10 — μA
• High-power mode (EN=1, PMODE=1)
— 1 — μA
• Low-power mode (EN=1, PMODE=0)
INL 8-bit DAC integral non-linearity LSB 5
• Low/High power mode, supply power > 1.71 –1.0 — +1.0

V
DNL 8-bit DAC differential non-linearity LSB 5
• Low/High power mode, power > 1.71 V –1.0 — +1.0
1. For devices that do not have a dedicated VSS_ANA pin, VSS_ANA is tied to VSS internally.
2. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V.
3. Overdrive does not include input offset voltage or hysteresis.
4. Comparator initialization delay is defined as the time between software writes to change control inputs
(Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]), and the comparator output settling to a stable level.
5. 1 LSB = Vreference/256.
Typical hysteresis

NXP Semiconductors
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1)
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0)

NXP Semiconductors
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)
3.5.3 Voltage reference electrical specifications
Table 51. VREF operating requirements
VDD_ANA Supply voltage 1.71 3.0 3.6 V
CL Output load capacitance 130 220 470 nF 1
1. CL must be connected to VREFO if the VREFO functionality is being used for either an internal or external reference.
Table 52. VREF operating behaviors
1.0 V low-power reference voltage
Vvrefo_lpbg Voltage reference output 1.0 V - LP bandgap 1.0 — 1.1 V 1
Iq_lpbg Quiescent current - LP bandgap — 16 — μA
Iout_lpbg Output current - LP bandgap — 10 — μA
tst_lpbg Start-up time - LP bandgap — 6 20 μs
ΔV/ Voltage variation - LP bandgap — ±5 — %

Vrefo_lpbg
High precision reference voltage
Vvrefo Voltage reference output 2.0 V 1.0 — 2.1 V 2,1
Vstep Fine trim step — 0.5 x Vrefo — mV
Iq Quiescent current — 750 — μA

NXP Semiconductors
Table 52. VREF operating behaviors (continued)
Iout Output current ±1 — — mA
tst_lpbg Start-up time — — 400 μs
ΔVLOAD Load regulation — 100 200 µV/mA 3
Vacc Absolute voltage accuracy (room temp) — ±1.5 ±6.5 mV
Vdev Voltage deviation over temperature — 15 — ppm/℃
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Vvrefo max is also ≤ VDD_ANA - 600 mV.
3. Load regulation voltage is the difference between the VREFO voltage with no load vs. voltage with defined load.
3.6 Timers
See General switching specifications.
3.7 Communication interfaces
3.7.1 LPUART
3.7.2 LPSPI switching specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many
of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes.
Table 53. LPSPI master mode timing
LP1 Frequency of operation 1

— 12 MHz
• LPSPI0
— 24 MHz
• LPSPI1
LP2 SPSCK period 2 x tperiph 2048 x tperiph ns 2
LP3 Enable lead time 1/2 — tperiph 2
LP4 Enable lag time 1/2 — tperiph 2
LP5 Clock (SPSCK) high or low time tSPSCK/2 - 3 tSPSCK/2 ns —
LP6 Data setup time (inputs) 8 — ns —
LP7 Data hold time (inputs) 0 — ns —
LP8 Data valid (after SPSCK edge) — 6 ns —
LP9 Data hold time (outputs) 2 — ns —
1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI
peripheral functional clock.
2. tperiph = 1/fperiph.

NXP Semiconductors
SS1
(OUTPUT)
LP3 LP2 LP4

SPSCK LP5
(CPOL=0)
(OUTPUT) LP5
SPSCK
(CPOL=1)
(OUTPUT)
LP6 LP7
MISO
MSB IN2 BIT 6 . . . 1 LSB IN
(INPUT)
LP8 LP9
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. LPSPI master mode timing (CPHA = 0)
SS1
(OUTPUT)
LP2
LP3 LP4
SPSCK
(CPOL=0)
(OUTPUT)
LP5 LP5
SPSCK
(CPOL=1)
(OUTPUT)
LP6 LP7
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
LP8 LP9
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA
1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. LPSPI master mode timing (CPHA = 1)
Table 54. LPSPI slave mode timing
LP1 Frequency of operation 1

— 12 MHz
• LPSPI0-LPSPI1
LP2 SPSCK period 4 x tperiph 2048 x ns 2
tperiph

NXP Semiconductors
Table 54. LPSPI slave mode timing (continued)
LP3 Enable lead time 1 — tperiph 2
LP4 Enable lag time 1 — tperiph 2
LP5 Clock (SPSCK) high or low time tSPSCK/2 - 5 tSPSCK/2 ns —
LP6 Data setup time (inputs) 8 — ns —
LP7 Data hold time (inputs) 1 — ns —
LP8 Slave access time — tperiph ns 2,3
LP9 Slave MISO disable time — tperiph ns 2,4
LP10 Data valid (after SPSCK edge) — 28 ns —
LP11 Data hold time (outputs) 1 — ns —
1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI
peripheral functional clock.
2. tperiph = 1/fperiph.
3. Time to data active from high-impedance stat.
4. Hold time to high-impedance state.
SS
(INPUT)
LP2 LP4
SPSCK
(CPOL=0)
(INPUT)
LP3 LP5 LP5
SPSCK
(CPOL=1)
(INPUT)
LP9
LP8 LP10 LP11 LP11
MISO see SEE

note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) NOTE
LP6 LP7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE: Not defined
Figure 18. LPSPI slave mode timing (CPHA = 0)

NXP Semiconductors
SS
(INPUT)
LP2 LP4
LP3
SPSCK
(CPOL=0)
(INPUT)
LP5 LP5
SPSCK
(CPOL=1)
(INPUT)
LP10 LP11 LP9
MISO see
SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) note
LP8 LP6 LP7

MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE: Not defined
Figure 19. LPSPI slave mode timing (CPHA = 1)
3.7.3 Inter-Integrated Circuit Interface (I2C) specifications

Table 55. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Min. Max. Min. Max.
SCL Clock Frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. tHD; STA 4 — 0.6 — µs

After this period, the first clock pulse is
generated.
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START tSU; STA 4.7 — 0.6 — µs

condition
Data hold time for I2C bus devices tHD; DAT 01,2 3.453 04,2 0.91 µs
Data set-up time tSU; DAT 2505 — 1003,6 — ns
Rise time of SDA and SCL signals tr — 1000 20 +0.1Cb7 300 ns
Fall time of SDA and SCL signals tf — 300 20 +0.1Cb6 300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and tBUF 4.7 — 1.3 — µs

START condition
Pulse width of spikes that must be tSP N/A N/A 0 50 ns

suppressed by the input filter
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.

NXP Semiconductors
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT =
1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
Table 56. I 2C 1 Mbps timing
Characteristic Symbol Min. Max. Unit
SCL Clock Frequency fSCL 0 1 MHz
Hold time (repeated) START condition. After this tHD; STA 0.26 — µs
period, the first clock pulse is generated.
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr 20 +0.1Cb 1 120 ns
Fall time of SDA and SCL signals tf 20 +0.1Cb1 120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by tSP 0 50 ns

the input filter
1. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.
Table 57. I2C HS mode timing1
Parameter Symbol Min Max Units
SCL Clock Frequency fSCL 0 3.4 MHz
Hold time (repeated) START condition. After this period, the tHD; STA 0.26 – µs
first clock pulse is generated.
LOW period of the SCL clock tLOW 0.5 – µs
High period of the SCL clock tHIGH 0.26 – µs
Set-up time for a repeated START condition tSU; STA 0.26 – µs
Data hold time for I2C bus devices tHD; DAT 02 – µs
Data setup time tSU; DAT 34 _ ns
Rise time of SDA and SCL signals tr 20 +0.1Cb3 120 ns


NXP Semiconductors 
Table 57. I2C HS mode timing1 (continued)
Fall time of SDA and SCL signals tf 20 +0.1Cb3 120 ns
Setup time for STOP condition tSU; STO 0.26 _ µs
Bus free time between STOP and START condition tBUF 0.5 _ µs
Pulse width of spikes that must be suppressed by the input tSP 0 50 ns

filter
1. Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.
2. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this
hold time.
3. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.
SDA
tSU; DAT tf
tf tLOW tr tHD; STA tSP tr tBUF
SCL
HD; STA tSU; STA tSU; STO

S tHD; DAT tHIGH SR P S
Figure 20. Timing definition for devices on the I2C bus
3.7.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points.
Table 58. MIPI-I3C specifications when communicating with legacy I2C devices
Symbol Characteristic 400 kHz/Fast mode 1 MHz/ Fast+ mode Unit
Min. Max. Min. Max.
fSCL SCL Clock Frequency 0 0.4 0 1.0 MHz
tSU_STA Set-up time for a repeated START condition 600 — 260 — ns
tHD_STA Hold time (repeated START condition) 600 — 260 — ns
tLOW LOW period of the SCL clock 1300 — 500 — ns
tHIGH HIGH period of the SCL clock 600 — 260 — ns
tSU_DAT Data set-up time 100 — 50 — ns
tHD_DAT Data hold time for I2C bus devices 0 — 0 — ns
tf Fall time of SDA and SCL signals 20 + 300 20 + 120 ns

0.1Cb1 0.1Cb1
tr Rise time of SDA and SCL signals 20 + 300 20 + 120 ns

0.1Cb1 0.1Cb1
tSU_STO Set-up time for STOP condition 600 — 260 — ns

NXP Semiconductors
Table 58. MIPI-I3C specifications when communicating with legacy I2C devices (continued)
Symbol Characteristic 400 kHz/Fast mode 1 MHz/ Fast+ mode Unit
Min. Max. Min. Max.
tBUF Bus free time between STOP and START 1.3 — 0.5 — µs
condition
tSP Pulse width of spikes that must be suppressed 0 50 0 50 ns

by the input filter
Table 59. MIPI-I3C open drain mode specifications
Symbol Characteristic Min. Max. Unit Notes
tLOW_OD LOW period of the SCL clock 200 — ns
tDIG_OD_L tLOW_OD + — ns
tfDA_OD
(min)
tHIGH HIGH period of the SCL clock tCF 12 ns
tfDA_OD Fall time of SDA signal 20 +0.1Cb 120 ns 1
tSU_OD Data set-up time during open drain mode 3 — ns
tCAS Clock after START (S) Condition

38.4 n 1μ s
• ENTAS0
38.4 n 100 μ s
• ENTAS1
38.4 n 2m s
• ENTAS2
38.4 n 50 m s
• ENTAS3
tCBP Clock before STOP (P) condition tCAS(min)/2 — ns
tMMOverlap Current master to secondary master overlap time tDIG_OD_L — ns

during handoff
tAVAL Bus available condition 1 — μs
tIDLE Bus idle condition 1 — ms
tMMLock Time internal where new master not driving SDA low tAVAL — μs
Table 60. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes
fSCL SCL Clock Frequency 0.01 — 12.5 MHz
tLOW LOW period of the SCL clock 24 — — ns
tDIG_L 32 — — ns
tHIGH_MIXE HIGH period of the SCL clock for a mixed bus 24 — — ns

D

NXP Semiconductors
Table 60. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes (continued)
tDIG_H_MIXE 32 — 45 ns 1
tHIGH HIGH period of the SCL clock 24 — — ns
tDIG_H 32 — — ns
tSCO Clock in to data out for slave
Load capacitance = 50 pF — — 38 ns
tCR SCL clock rise time — — 150 x 1/ ns

fSCL
(capped at
60)
tCF SCL clock fall time — — 150 x 1/ ns

fSCL
(capped at
60)
tHD_PP SDA signal data hold ns

tCR + 3 and — —
• Master mode tCF + 3
— —
• Slave mode 0
tSU_PP SDA signal setup 3 — — ns
tCASr Clock after repeated START (Sr) tCAS (min) — — ns
tCBSr Clock before repeated START (Sr) tCAS — — ns

(min)/2
Cb Capacitive load per bus line — — 50 pF
1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make
sure that I2C devices do not interpret I3C signaling as valid I2C signaling.

NXP Semiconductors
Sr Sr P
tfDA trDA tHD_DAT
0.7 X VDD
SDA
0.3 X VDD
tSU_STA
tHD_STA
tSU_DAT tSU_STO
tfCL trCL
0.7 X VDD
SCL
0.3 X VDD
tHIGH tLOW tLOW tHIGH
= Open Drain With Weak Pullup = High Speed Active Push-Pull Drive
Figure 21. I3C legacy mode timing
tHIGH tCF tLOW
0.7xVDD
0.3xVDD
tCR tDIG_H tDIG_L
Figure 22. tDIG_H and tDIG_L

NXP Semiconductors
Peripheral
 operating requirements and behaviors
Figure 23. Timing definition for devices on the I3C bus
3.7.5 CAN switching specifications

3.8 Human Machine Interface (HMI) modules
3.8.1 General Purpose Input/Output (GPIO)

3.8.2 Flexible IO controller (FlexIO)

Table 61. FlexIO Timing Specifications
Symbol Description Min Typ Max Unit Notes
tODS Output delay skew between any two FlexIO_Dx pins configured 0 — 10 ns 1
as outputs that toggle on same internal clock cycle

NXP Semiconductors
Package dimensions
Table 61. FlexIO Timing Specifications (continued)
Symbol Description Min Typ Max Unit Notes
tIDS Input delay skew between any two FlexIO_Dx pins configured as 0 — 10 ns 1
inputs that are sampled on the same internal clock cycle
1. Assumes pins muxed on same VDD_IO domain with same load
4 Package dimensions
4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number:
If you want the drawing for this package Then use this document number
40-pin HVQFN SOT618-13(DD)
48-pin QFN SOT619-17(D)
5 Pinout
5.1 Pinout Table
48H 40H Pin ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 ALT1 ALT1 Wake
VQ VQ Name 0 1 up
FN FN
2 1 PTB4 PTB4 LPSPI LPUA LPI2C I3C0_ TRG FLEXI WUU

1_PC RT1_ 1_SD SDA MUX0 O0_D 0_P15
S3 CTS_ A _IN0 30
b
3 2 PTB5 PTB5 LPSPI LPUA LPI2C I3C0_ TRG FLEXI

1_PC RT1_ 1_SC SCL MUX0 O0_D
S2 RTS_ L _OUT 31
b 0
4 3 VDD_I VDD_I
O_AB O_AB
C C
5 4 SWIT SWIT
CH_W CH_W
AKEU AKEU
P_B P_B
6 5 VDD_ VDD_
SWIT SWIT
CH CH

NXP Semiconductors
Pinout
Table continued from the previous page...
VQ VQ Name 0 1 up
FN FN
7 6 VOUT VOUT
_SWI _SWI
TCH TCH
8 7 PTA0 PTA0 CMP0 LPUA RF_G TPM0 FLEXI SWD_ WUU

_OUT RT0_ PO_1 _CH4 O0_D DIO 0_P0
CTS_ 11 0
b
9 8 PTA1 PTA1 CMP1 LPUA RF_G TPM0 FLEXI SWD_

_OUT RT0_ PO_1 _CH5 O0_D CLK
RTS_ 01 1
b
10 9 PTA4 ADC0 PTA4 RF_G TPM0 TRAC FLEXI BOOT WUU

_A10/ PO_9 _CLKI E_SW O0_D _CON 0_P2/
CMP0 1 N O 4 FIG RF_X
_IN0 TAL_
OUT_
ENAB
LE1
11 PTA1 ADC0 PTA1 LPSPI EWM LPI2C TPM0 LPUA RF_G FLEXI RF_N
6 _A12 6 0_PC 0_OU 0_SC _CH4 RT0_ PO_8 O0_D OT_A
S0 T_b LS RX 1 5 LLOW
ED1
12 10 PTA1 ADC0 PTA1 LPSPI EWM LPI2C TPM0 LPUA RF_G RF_G FLEXI RF_E WUU
7 _A13 7 0_SIN 0_IN 0_SD _CH5 RT0_ PO_7 PO_8 O0_D XT_X 0_P3/
AS TX 1 1 6 TAL_ RF_N
REQU OT_A
EST/ LLOW
RF_G ED1
PO_7
1
13 11 PTA1 CMP1 PTA1 LPSPI LPUA LPI2C TPM0 RF_G LPUA SPC0
8 _IN1 8 0_SO RT0_ 0_SD _CH3 PO_0 RT0_ _LPR
UT CTS_ A 1 RX EQ
b
14 12 PTA1 CMP1 PTA1 LPSPI LPUA LPI2C TPM0 RF_G WUU

9 _IN0/ 9 0_SC RT0_ 0_SC _CH2 PO_1 0_P4
K RTS_ L 1
15 13 VDD_ VDD_
LDO_ LDO_
CORE CORE

NXP Semiconductors
Pinout
VQ VQ Name 0 1 up
FN FN
16 14 VOUT VOUT
_COR _COR
E/ E/
VDD_ VDD_
CORE CORE
17 15 PTA2 ADC0 PTA2 LPSPI LPUA EWM TPM0 RF_G FLEXI

0 _A14/ 0 0_PC RT0_ 0_IN _CH1 PO_2 O0_D
CMP0 S2 TX 1 7
_IN3
18 16 PTA2 ADC0 PTA2 LPSPI LPUA EWM TPM0 RF_G RF_G FLEXI RF_G WUU
1 _A15/ 1 0_PC RT0_ 0_OU _CH0 PO_3 PO_7 O0_D PO_1 0_P5
CMP0 S3 RX T_b 1 1 8 01
_IN2
19 17 VSS_ VSS_
DCDC DCDC
20 18 DCDC DCDC
_LX _LX
21 19 VDD_I VDD_I
O_D/ O_D/
VDD_ VDD_
DCDC DCDC
22 20 VOUT VOUT
_SYS/ _SYS/
VDD_ VDD_
SYS SYS
23 21 PTD0 ADC0 PTD0 RESE

_A5 T_b
24 PTD1 ADC0 PTD1 SPC0 NMI_b RF_G

_B5 _LPR PO_4
EQ 1
25 PTD2 ADC0 PTD2 LPTM TAMP RF_G

_A6 R0_A ER0 PO_5
LT3 1
26 PTD3 ADC0 PTD3 LPTM TAMP RF_G TRG

_B6 R1_A ER1 PO_6 MUX0
LT3 1 _IN2
27 22 PTD4 XTAL PTD4 LPTM TAMP

32K R0_A ER2
LT2

NXP Semiconductors
Pinout
VQ VQ Name 0 1 up
FN FN
28 23 PTD5 EXTA PTD5 LPTM

L32K R1_A
LT2
29 24 VDD_ VDD_
ANA ANA
30 25 VREF VREF
O O
49 41 VREF VREF
L2 L
31 XTAL XTAL
_OUT _OUT
32 26 XTAL XTAL
33 27 EXTA EXTA
L L
34 28 VDD_ VDD_
RF RF
35 29 ANT_ ANT_
2P4G 2P4G
HZ1,3 HZ1
36 30 VPA_ VPA_
2P4G 2P4G
HZ1,3 HZ1
37 PTC0 PTC0 LPSPI CAN0 I3C0_ TPM1 LPI2C FLEXI WUU

1_PC _TX4 SDA _CH0 1_SC O0_D 0_P7
S2 L 16
38 PTC1 PTC1 LPSPI CAN0 I3C0_ TPM1 LPI2C FLEXI WUU

1_PC _RX4 SCL _CH1 1_SD O0_D 0_P8
S3 A 17
39 31 PTC2 PTC2 LPSPI LPUA LPI2C TPM1 I3C0_ FLEXI WUU

1_SO RT1_ 1_SC _CH2 PUR O0_D 0_P9
UT RX LS 18
40 32 PTC3 PTC3 LPSPI LPUA LPI2C TPM1 FLEXI

1_SC RT1_ 1_SD _CH3 O0_D
K TX AS 19
41 33 VDD_ VDD_
CORE CORE
42 34 PTC4 PTC4 LPSPI CAN0 LPI2C TPM2 FLEXI WUU

1_SIN _TX4 1_SC _CH0 O0_D 0_P10
L 1 20

NXP Semiconductors
Pinout
VQ VQ Name 0 1 up
FN FN
43 35 PTC5 PTC5 LPSPI CAN0 LPI2C TPM1 TPM2 FLEXI

1_PC _RX4 1_SD _CH4 _CH1 O0_D
S0 A 1 21
44 5 PTC6 ADC0 PTC6 LPSPI TPM1 FLEXI WUU

_A8 1_PC _CH5 O0_D 0_P11
S1 22
45 36 PTC7 PTC7 TRG TRG SFA0 TPM1 TPM2 CLKO FLEXI WUU
MUX0 MUX0 _CLK _CLKI _CLKI UT O0_D 0_P12
_IN3 _OUT N N1 23 /
3 NMI_
b/
RF_N
OT_A
LLOW
ED 1
46 37 PTB0 ADC0 PTB0 LPSPI TPM1 FLEXI WUU

_B10 1_PC _CH0 O0_D 0_P13
S0 26
47 38 PTB1 ADC0 PTB1 LPSPI TPM1 FLEXI

_B11 1_SIN _CH1 O0_D
27
48 39 PTB2 ADC0 PTB2 LPSPI LPUA TPM1 FLEXI

_B12 1_SC RT1_ _CH2 O0_D
K TX 28
1 40 PTB3 ADC0 PTB3 LPSPI LPUA TPM1 FLEXI WUU

_B13 1_SO RT1_ _CH3 O0_D 0_P14
UT RX 29
49 41 VSS VSS
1. This signal is not available for the parts without Radio modules.
2. VREF shorts to VSS.
3. For the parts that have no radio modules, this pin is not connected.
4. This signal is not available for the parts without CAN module.
5. PTC6_WUU0_P11 pin signal available only as a wake up source for FlexCAN module on signal CAN0_RX from pin PTC5.
Other configuration on PTC6 shall not be used.
5.2 Recommended connection for unused analog and digital pins

Table 62 shows the recommended connections for pins if those pins are not used in the customer's application

NXP Semiconductors
Pinout
Table 62. Recommended connection for unused interfaces
Pin Type Pin Function Recommendation Comments
Power VDD_LDO_CORE Connect to When the LDO is not used, the input and output
VOUT_CORE and VSS should be connected together and tied to ground
through a 10 kΩ resistor. The regulator should
also be disabled in software.
Power VOUT_CORE Connect to When the LDO is not used, the input and output
VDD_LDO_CORE and should be connected together and tied to ground
VSS through a 10 kΩ resistor. The regulator should
also be disabled in software.
Power VOUT_SYS Connect to VDD_IO_D When the LDO is bypassed, the input and
output should be connected together and tied
to an external supply that shall not exceed
the maximum input voltage for VDD_SYS. The
regulator should also be disabled in software.
Power VDD_DCDC Ground When the DCDC is not used, the input should be
tied to VSS through a 10 kΩ resistor.
Power DCDC_LX Float
Power VDD_IO_D Must be powered VDD_IO_D is used to power parts of the system
power controller (SPC) and must be powered
to use the chip. If LDO_SYS is not being used,
then tie VDD_IO_D to VOUT_SYS and supply
power from an external source. The regulator
should also be disabled in software.
Power VDD_SWITCH Must be powered Powers FRO16 and a portion of RAM.
Power VOUT_SWITCH Float
Power VDD_IO_ABC Must be powered VDD_IO_ABC powers the mux logic for PORTA,
PORTB and PORTC. It must be powered
during POR. The recommendation is to keep it
powered, but it can be connected to the output
of the Smart Power Switch and be left floating in
shelf storage mode.
Power VPA_2P4GHz Float
Power VDD_ANA Float
Power VREFH Always connect to Always connect to VDD_ANA potential

VDD_ANA potential
Power VREFL Always connect to VSS Always connect to VSS potential

potential
Power VSS_ANA Always connect to VSS Always connect to VSS potential

potential
Power VREFO 220 nF capacitor 220 nF capacitor if VREF is used otherwise

Float
Power VSS_DCDC Always connect to VSS Always connect to VSS potential

potential

NXP Semiconductors
Pinout
Table 62. Recommended connection for unused interfaces (continued)
Pin Type Pin Function Recommendation Comments
Power VSS_RF Always connect to VSS Always connect to VSS potential

potential
Analog/non-GPIO ADCn_x Float
Analog/non-GPIO VREFO Float Analog output - Float
Analog/non-GPIO TAMPERx Float
Analog/non-GPIO RTC_WAKEUP_B Float
Analog/non-GPIO RTC_RTCCLKOUT Float
Analog/non-GPIO EXTAL32K Float
Analog/non-GPIO XTAL32K Float Analog output - Float
Analog/non-GPIO EXTAL_32M Float
Analog/non-GPIO XTAL_32M Float Analog output - Float
GPIO/Analog PTx/CMPn_INx Float Float (default is analog input)
GPIO/Digital PTD1/NMI_b 10kΩ pullup or disable Pull high or disable in PCR & FOPT and float
and float
GPIO/Digital PTx Float Float (default is disabled)
Digital/non-GPIO SWITCH_WAKEUP_B Float Enable internal pull-up
5.3 Pinouts diagram

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto
a single pin. To determine what signals can be used on which pin, see the previous section.

NXP Semiconductors
Pinout
VDD_CORE
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
PTB2
PTB1
PTB0
41
42
45
48
46
47
44
43
39
40
38
37
PTB3 1 36 VPA_2P4GHZ
PTB4 2 35 ANT_2P4GHZ
49
PTB5 3 34 VDD_RF
VDD_IO_ABC 4 33 EXTAL
SWITCH_WAKEUP_B 5 32 XTAL
VDD_SWITCH 6 31 XTAL_OUT
VOUT_SWITCH 7 30 VREFO
PTA0 8 29 VDD_ANA
PTA1 9 28 PTD5
PTA4 10 27 PTD4
PTA16 11 26 PTD3
PTA17 12 21 25 PTD2
22
23
24
13
14
15
16
17
18
19
20
VDD_LDO_CORE
VSS_DCDC
VOUT_CORE/VDD_CORE
PTA21
PTA20
DCDC_LX
PTA18
PTA19
VDD_IO_D/VDD_DCDC
VOUT_SYS/VDD_SYS
PTD0
PTD1
*pin 49 is VSS
Figure 24. 48-pin HVQFN package pinout diagram

NXP Semiconductors
Ordering parts
VDD_CORE
PTC7
PTC5
PTC4
PTC3
PTC2
PTB3
PTB2
PTB1
PTB0
31
32
39
35
38
36
40
37
34
33
PTB4 1 30 VPA_2P4GHZ
PTB5 2 41 29 ANT_2P4GHZ
VDD_IO_ABC 3 28 VDD_RF
SWITCH_WAKEUP_B 4 27 EXTAL
VDD_SWITCH 5 26 XTAL
VOUT_SWITCH 6 25 VREFO
PTA0 7 24 VDD_ANA
PTA1 8 23 PTD5
PTA4 9 22 PTD4
PTA17 10 21 PTD0
20
11
12
13
14
15
16
17
18
19
PTA18
PTA19
PTA20
VDD_IO_D/VDD_DCDC
PTA21
DCDC_LX
VOUT_SYS/VDD_SYS
VDD_LDO_CORE
VOUT_CORE/VDD_CORE
VSS_DCDC
*pin 41 is VSS
*PTC5 is internally
bonded with PTC6 pin
for wakeup purposes.
See to the pinout
table for details
Figure 25. 40-pin HVQFN package pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com
and perform a part number search for the following device numbers: KW45
7 Part identification
Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

NXP Semiconductors
Part identification
7.1 Part number format

Part numbers for this device have the following format:
B R PF R FS SF T PG SR PT
Table 63. Part number fields descriptions
Field Description Values
B Brand • KW45
R Radio • B = Bluetooth LE
• Z = No Radio
PF Product Family • 41
R Radio • Z = Upgradable
• 0 = Not Applicable (No Radio)
FS Flash Size • 5 = 512 KB

• 8 = 1 MB
SF Sub Feature • 2 = Secure Enclave

• 3 = Secure Enclave and CAN
T Temperature • A = Automotive, –40 ºC to +105 ºC (Ta), -40 ºC

to +125 ºC (Tj)
PG Package • FP = 40 HVQFN “Wettable”, 6 mm x 6 mm, 0.5p

• FT = 48 HVQFN “Wettable”, 7 mm x 7 mm, 0.5p
SR Silicon Revision • A = Initial Mask Set

• B = Production Release Mask Set
PT Packaging Type • R = Tape and Reel

• T = Tray
7.2 Example
This is an example part number:
KW45B41Z82AFTBT
7.3 Package marking

Package marking for this device have the following format:
B R PF R FS SF T PG

NXP Semiconductors
Terminology and guidelines
Table 64. Package marking
Field Description Values
B Brand • KW45
R Radio • B = Bluetooth LE
• Z = No Radio
PF Product Family • 41
R Radio • Z = Upgradable
• 0 = Not Applicable (No Radio)
FS Flash Size • 5 = 512 KB

• 8 = 1MB
SF Sub Feature • 2 = Secure Enclave

• 3 = Secure Enclave and CAN
T Temperature • A = Automotive, –40 ºC to +105 ºC (Ta), -40 ºC

to +125 ºC (Tj)
PG Package • FP = 40 HVQFN “Wettable”, 6 mm x 6 mm, 0.5p

• FT = 48 HVQFN “Wettable”, 7 mm x 7 mm, 0.5p
7.3.1 Package marking information

The KW45 package has the following top-side marking:
• First line: aaaaaaa
• Second line: aaaaaa
• Third line: mmmmm
• Fourth line: xxxywwxx
Table 65. Package marking
Identifier Description
a Reduced part number code, refer to Package marking table
m Mask set
y Year
w Work week
x NXP internal use
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:

NXP Semiconductors
Terminology and guidelines
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE
The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation
if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE
Typical values are provided as design guidelines and are neither tested
nor guaranteed.
8.2 Examples
Operating rating:
E
PL
M
A
EX
Operating requirement:
E
PL
M
A
EX
Operating behavior that includes a typical value:

E
PL
M
A
EX

NXP Semiconductors
Abbreviations and Acronyms
8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified):
Symbol Description Value Unit
TA Ambient temperature 25 °C
VDD Supply voltage 3.3 V
8.4 Relationship between ratings and operating requirements

in.
)
ax.)
(m (m
n.) nt nt x.)
mi rem
e
em
e ma
g( ui uir ng
(
a tin eq req rat
i
gr gr ng ing
tin tin rat
i
rat
era era e e
Op Op Op Op
Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range
Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure
- Possible decreased life - Correct operation - Possible decreased life
- Possible incorrect operation - Possible incorrect operation
–∞ ∞
Operating (power on)
n.) .)
i ax
(m (m
i ng ing
rat rat
ng lin
g
n dli nd
Ha Ha
Fatal range Handling range Fatal range
Expected permanent failure No permanent failure Expected permanent failure
–∞ ∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power
sequencing), limit the duration as much as possible.
9 Abbreviations and Acronyms

The following table provides the list of abbreviations and acronyms their definitions.
Table 66. Abbreviations and Acronyms and their definition
Abbreviations and Acronyms Definitions
ADC Analog-to-Digital Converter
AXBS Crossbar Switch
CMC Core Mode Controller

NXP Semiconductors
Abbreviations and Acronyms
Table 66. Abbreviations and Acronyms and their definition (continued)
CRC Cyclic Redundancy Check
CTI Cross Trigger Interface
DAP Debug Access Port
DMA Direct Memory Access
DSP Digital Signal Processing
DWT Data Watchpoint and Trace
EWM External Watchdog Monitor
FRO Free Running Oscillator
FMC Flash Memory Controller
FPU Floating Point Unit
GPIO General-purpose Input and Output
I3C Improved Inter-Integrated Circuit
ITM Instruction Trace Macrocell
LPCMP Low Power Comparator
LPI2C Low Power Inter-Integrated Circuit
LPIT Low Power Periodic Interrupt Timer
LPSPI Low Power Serial Peripheral Interface
LPTMR Low-Power Timer
LPUART Low Power Universal Asynchronous Receiver/ Transmitter
MPU Memory Protection Unit
MRCC Module Reset and Clock Control
MSCM Miscellaneous System Control Module
MU Messaging Unit
NBU Narrowband Unit
NPX FMC with NVM PRINCE Encryption and Decryption
NVIC Nested Vectored Interrupt Controller
NVM Non-Volatile Memory
OSC Oscillator
RFMC Radio Mode Controller
RTC Real Time Clock
SEMA42 Semaphore Module
SCG System Clock Generator

NXP Semiconductors
Revision history
Table 66. Abbreviations and Acronyms and their definition (continued)
SFA Signal Frequency Analyzer
SMSCM Secure Miscellaneous System Control Module
SPC System Power Controller
SWD Serial Wire Debug
TPIU Trace Port Interface Unit
TPM Timer/PWM Module
TRDC Trusted Resource Domain Controller
TRNG True Random Number Generator
TRGMUX Trigger Multiplexer
TSTMR Time Stamp Timer
VREF Voltage Reference
WDOG Watchdog
WUU Wake-Up Unit
10 Revision history
The following table provides a revision history for this document.
Table 67. Revision History
Rev. No. Date Substantial Changes
0 June 2020 Initial internal release
1 September • Editorial updates in the front matter

2020
• Updated the partnumber from K32W to KW45 all over the document
• Added Device Mask Set Number in Device Revision Number table
• Added the package drawing resource in Related Resource Table
• Removed VRAM and VDD_IO_X- VDD_ANA from Voltage and current operating
requirements
• Updated Power consumption operating behaviors table
• Updated the description of Δffro6m in FRO-6M specifications table and Δffro32k in
FRO-32K specifications table
• Updated Ifro16k and added I por in Free-running oscillator FRO-16K specifications
• Updated the maximum values in Flash timing specifications
• Updated Receiver Specifications with Generic FSK Modulations table
• Updated Part number format
• Updated LDO_CORE electrical specifications

NXP Semiconductors
Revision history
Table 67. Revision History (continued)
• Updated VDD_IO_D in LDO_SYS electrical specifications

• Updated Smart power switch
• Updated Receiver Feature Summary
• Added Package marking section
• Added Power Sequence table
2 November • Editorial updates in the front matter

2020
• Updated minimum voltage of DC/DC voltage range from 1.8 V to 1.71 V
• Added the names of Reference Manual and Chip errata in Related Resources Table
• Updated the K4W1 block diagram in front matter
• Removed IICIO, IICcont, VOPDU, and VRFSYS from Voltage and current operating
requirements
• Removed VHVD_HYS_SYS and VLVD_HYS_SYS from VDD_SYS supply HVD and LVD
Operating Ratings table in HVD, LVD, and POR operating requirements
• Removed IOHT, RPU(I3C), RHPU, RHPD, and IOLT from Voltage and current operating
behaviors
• Updated Power Switch to Smart Power Switch
• Updated the values of Power mode transition operating behaviors
• Removed EMC radiated emissions operating behaviors section and Designing with
radiated emissions in mind
• Updated the General switching specificationssection
• Updated 16-bit ADC electrical characteristicssection
• Updated LPI values from LPSPI master mode timing table and LP10 value from LPSPI
slave mode timing
• Updated Timing definition for devices on the I3C bus diagram
• Updated Package marking and Package marking information
• Added pinout table and pinout diagram and removed excel sheet format
3 May 2021 • Changed VREF_OUT to VREFO to make it aligned in the whole book.
• Updated the Timers section in front matter content
• Updated DCDC converter specifications
• Updated the tstartup and jitper in Free-running oscillator FRO-192M specifications table
• Updated the tstartup in Free-running oscillator FRO-6M specifications
• Updated Free-running oscillator FRO-32K specifications
• Updated the Low power mode peripheral power consumption adders
• Updated Voltage and current maximum ratings

NXP Semiconductors
Revision history
• Removed VRFSYS and under-drive (0.9) Operation, updated note to the IICIO in the
Voltage and current operating requirements.
• Removed Target VDD_Core = 0.9 V from VDD_CORE supply HVD and LVD Operating
Ratings table in HVD, LVD, and POR operating requirements
• Updated 32 MHz to 64 MHz in Power mode transition operating behaviors.
• Updated the Power Consumption Operating Behaviors
• Updated the Typical power-down mode RAM current adders
• Updated Thermal attributes.
• Added VPA_2P4GHz, VREFO and Digital/non-GPIO rows in Recommended connection
for unused analog and digital pins.
• Updated CPU_CLK and slow clock frequency in Power mode transition operating
behaviors
• Updated the values in General switching specifications
• Updated Transmit and PLL Feature Summary
• Updated Pinout Table
• Updated tsco in MIPI-I3C push-pull specifications for SDR and HDR-DDR modes table
and added figures in Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications
• Updated the descriptions to the VOUT_SYS, ILOAD and IDD in the LDO_SYS electrical
specifications
• Updated the comments to the DCDC_LX in the Recommended connection for unused
analog and digital pins
4 September • Editorial changes

2021
• Updated the front matter content
• Updated the part numbers to add 'T' for Tray or 'R' for Reel in the end
• Updated ESD and Latch-Up Ratings
• Removed IDD from Voltage and current maximum ratings
• Updated the Voltage and current operating requirements table
• Updated the typical value of VLVDV_HYS_IO_ABC, VHVD_HYS_SYS and VLVD_HYS_SYS in HVD,
LVD, and POR operating requirements
• Updated the typical values of VDD_CORE supply HVD and LVD Operating Ratings table
• Updated the EdgeLock Secure Enclave in KW45 block diagram
• Updated the description and values of VDD_IO_D in LDO_SYS electrical specifications
• Updated Voltage and current operating behaviors table
• Updated the description of I2C/I3C I/O pins in General switching specifications
• Updated the minimum value of VBAT in Free-running oscillator FRO-16K specifications
and added footnote

NXP Semiconductors
Revision history
• Removed the bullet of 0 to 40 °C in Δffro16K in Free-running oscillator FRO-16K

specifications
• Added four low voltage command times in Flash timing specifications table
• Added tPORFAST and updated tPOR in Power mode transition operating behaviors table
• Updated the values in Power mode transition operating behaviors table
• Added Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1) chart, Typical
hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1), and Typical hysteresis
vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0) in CMP and 8-bit DAC electrical
specifications
• Updated Power Consumption Operating Behaviors table
• Updated maximum value of CL in VREF operating requirements and VREF operating
behaviors in Voltage reference electrical specifications
• Updated VDD_ANA symbol to VDD_IO_ABC and the maximum value of VREFH to
VDD_IO_ABLC in CMP and 8-bit DAC electrical specifications
• Removed the references of NVM and added footnote for CAN in pinout table Pinout
Table
• Updated Receiver Feature Summary and Transmit and PLL Feature Summary
• Removed the references of SUOX and SOX from 32 kHz oscillator electrical
specifications
4.1 December • Added parts

2021
• Updated the Front matter content
5 December • Editorial updates

2021
• Removed the Note below package drawings
• Updated the Reel to Tape and Reel in Ordering Information table
• Added SIM_SDID value in Device Revision table
• Removed IICcont parameter, updated the values of IICIO, and added another footnote to
IICIO in Table 10
• Updated the first footnote in Table 15
• Updated the maximum value of ILOAD at Normal drive mode in Table 16
• Updated ILOAD parameter in Table 17
• Updated Table 21
• Updated the values of Jitosc and vec_extal32 in Table 32
• Added typical values to all parameters in Table 40
• Added new parameter VPA_2P4GHz in Table 41
• Added footnotes in Table 42

NXP Semiconductors
Revision history
• Updated the values of fADCK and RADIN in Table 48

• Updated typical and maximum value of Vacc in Table 52
• Added maximum value of fSCL and minimum value of tSU_PP in Table 60
• Added Abbreviations and Acronyms
• Removed RF_UART signal from Pinout Table
6 September • Updated the Front Matter Content content

2022
• Updated Bluetooth Low Energy 5.2 to Bluetooth Low Energy 5.3 all over the datasheet
• Updated the minimum value and maximum value of VOUT_CORE for low drive strength
in LDO_CORE electrical specifications
• Updated the values of tPWDN and tDPWDN in Power mode transition operating behaviors
• Updated the values to TBD in Power Consumption Operating Behaviors and added IDD
tables for phantoms: 512M + RF, 1M + non-RF and 512 + non_RF.
• Updated the ambient temperature range from 120 °C to 105 °C
• Removed the values for ambient temperature 120 °C all over the document
• Updated the range of Target VDD_CORE in Table 12
• Updated the values of VLVD_COREat Target VDD_CORE = 1.05 in Table 12
• Updated the values of VOUT_DCDC in Table 15
• Updated Table 24 to show only 25 °C
• Updated Typical power-down mode RAM current adders
• Added footnotes to Receiver Feature Summary and Transmit and PLL Feature Summary
• Update the minimum value of VDD_CORE, VDD_LDO_CORE and maximum value of
VDD_RF in Voltage and current operating requirements
• Added footnotes to Table 42
7 September • Updated the Ordering information of radio parts and non-radio parts in Front Matter
2022 Content content to reflect "B" instead of "A" as Silicon Revision
8 December • Updated Front matter content

2022
• Updated Power Consumption Operating Behaviors and removed IDD tables for phantom
parts
• Updated minimum and maximum value of Electrostatic discharge voltage, charged-
device model (antenna pin) in ESD and Latch-Up Ratings to -250 V and +250 V

NXP Semiconductors
Revision history
• Updated Power mode transition operating behaviors to remove tPOR and tPORFAST
• Updated description and IDD values in Low power mode peripheral power consumption
adders
• Removed 26.0 MHz information from Reference oscillator specification
• Merged crystal and frequency tolerance entry and crystal frequency stability and aging
information entry to single entry in Reference oscillator specification
• Removed the maximum value of SELBLE1M, 4+ MHz in Table 42
• Removed 26 MHz from Reference frequency bullet in Transmit and PLL Feature
Summary
• Added SoC Power Consumption section
• Updated typical value of fref in 2.4 GHz radio transceiver electrical specification to show
32 MHz only
• Updated the typical value of TRIMstep in Free-running oscillator FRO-32K specifications
to 0.03
• Added footnote to PTC6 pin in 40 HVQFN package in Pinout Table
• Added footnote to PTC5 in 40HVQFN pinout diagram
• Removed VswitchWakeup and t switchWakeup from Smart power switch
• Updated Part number format and Package marking
9 December • Updated the frequency from 48 MHz to 64 MHz in "Dedicated CM3 core running at up to
2022 48MHz" in front matter
• Updated the complete ESD and Latch-Up Ratings table

NXP Semiconductors
Legal information
Legal information
Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices.
The latest product status information is available on the Internet at URL http://www.nxp.com.
Definitions Disclaimers
Draft — A draft status on a document indicates that the content is still Limited warranty and liability — Information in this document is believed
under internal review and subject to formal approval, which may result to be accurate and reliable. However, NXP Semiconductors does not give
in modifications or additions. NXP Semiconductors does not give any any representations or warranties, expressed or implied, as to the accuracy
representations or warranties as to the accuracy or completeness of or completeness of such information and shall have no liability for the
information included in a draft version of a document and shall have no consequences of use of such information. NXP Semiconductors takes no
liability for the consequences of use of such information. responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Short data sheet — A short data sheet is an extract from a full data sheet with
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the same product type number(s) and title. A short data sheet is intended for
punitive, special or consequential damages (including - without limitation -
quick reference only and should not be relied upon to contain detailed and full
lost profits, lost savings, business interruption, costs related to the removal or
information. For detailed and full information see the relevant full data sheet,
replacement of any products or rework charges) whether or not such damages
which is available on request via the local NXP Semiconductors sales office.
are based on tort (including negligence), warranty, breach of contract or any
In case of any inconsistency or conflict with the short data sheet, the full data
other legal theory.
sheet shall prevail.
Notwithstanding any damages that customer might incur for any reason
Product specification — The information and data provided in a Product data whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
sheet shall define the specification of the product as agreed between NXP customer for the products described herein shall be limited in accordance with
Semiconductors and its customer, unless NXP Semiconductors and customer the Terms and conditions of commercial sale of NXP Semiconductors.
have explicitly agreed otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors product is deemed to Right to make changes — NXP Semiconductors reserves the right to make
offer functions and qualities beyond those described in the Product data sheet. changes to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.

NXP Semiconductors
Legal information
Applications — Applications that are described herein for any of these Suitability for use in automotive applications — This NXP product has been
products are for illustrative purposes only. NXP Semiconductors makes no qualified for use in automotive applications. If this product is used by customer
representation or warranty that such applications will be suitable for the in the development of, or for incorporation into, products or services (a)
specified use without further testing or modification. used in safety critical applications or (b) in which failure could lead to death,
personal injury, or severe physical or environmental damage (such products
Customers are responsible for the design and operation of their applications
and services hereinafter referred to as “Critical Applications”), then customer
and products using NXP Semiconductors products, and NXP Semiconductors
makes the ultimate design decisions regarding its products and is solely
accepts no liability for any assistance with applications or customer product
responsible for compliance with all legal, regulatory, safety, and security
design. It is customer’s sole responsibility to determine whether the NXP
related requirements concerning its products, regardless of any information
Semiconductors product is suitable and fit for the customer’s applications and
or support that may be provided by NXP. As such, customer assumes all risk
products planned, as well as for the planned application and use of customer’s
related to use of any products in Critical Applications and NXP and its suppliers
third party customer(s). Customers should provide appropriate design and
shall not be liable for any such use by customer. Accordingly, customer will
operating safeguards to minimize the risks associated with their applications
indemnify and hold NXP harmless from any claims, liabilities, damages and
and products.
associated costs and expenses (including attorneys’ fees) that NXP may incur
NXP Semiconductors does not accept any liability related to any default,
related to customer’s incorporation of any product in a Critical Application.
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s Quick reference data — The Quick reference data is an extract of the product
third party customer(s). Customer is responsible for doing all necessary testing data given in the Limiting values and Characteristics sections of this document,
for the customer’s applications and products using NXP Semiconductors and as such is not complete, exhaustive or legally binding.
products in order to avoid a default of the applications and the products or of the
application or use by customer’s third party customer(s). NXP does not accept Export control — This document as well as the item(s) described herein may be
any liability in this respect. subject to export control regulations. Export might require a prior authorization
from competent authorities.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent Translations — A non-English (translated) version of a document, including
damage to the device. Limiting values are stress ratings only and (proper) the legal information in that document, is for reference only. The English
operation of the device at these or any other conditions above those version shall prevail in case of any discrepancy between the translated and
given in the Recommended operating conditions section (if present) or the English versions.
Characteristics sections of this document is not warranted. Constant or

Security — Customer understands that all NXP products may be subject to
repeated exposure to limiting values will permanently and irreversibly affect the
unidentified vulnerabilities or may support established security standards or
quality and reliability of the device.
specifications with known limitations. Customer is responsible for the design
Terms and conditions of commercial sale — NXP Semiconductors products and operation of its applications and products throughout their lifecycles
are sold subject to the general terms and conditions of commercial sale, to reduce the effect of these vulnerabilities on customer’s applications
as published at http://www.nxp.com/profile/terms, unless otherwise agreed and products. Customer’s responsibility also extends to other open and/or
in a valid written individual agreement. In case an individual agreement proprietary technologies supported by NXP products for use in customer’s
is concluded only the terms and conditions of the respective agreement applications. NXP accepts no liability for any vulnerability. Customer should
shall apply. NXP Semiconductors hereby expressly objects to applying the regularly check security updates from NXP and follow up appropriately.
customer’s general terms and conditions with regard to the purchase of NXP Customer shall select products with security features that best meet rules,
Semiconductors products by customer. regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
No offer to sell or license — Nothing in this document may be interpreted or
for compliance with all legal, regulatory, and security related requirements
construed as an offer to sell products that is open for acceptance or the grant,
concerning its products, regardless of any information or support that may be
conveyance or implication of any license under any copyrights, patents or other
provided by NXP.
industrial or intellectual property rights.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at [email protected]) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.

NXP Semiconductors
Legal information
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio,

CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali,
Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision,
Versatile — are trademarks or registered trademarks of Arm Limited (or its
subsidiaries) in the US and/or elsewhere. The related technology may be
protected by any or all of patents, copyrights, designs and trade secrets. All
rights reserved.
Bluetooth — the Bluetooth wordmark and logos are registered trademarks

owned by Bluetooth SIG, Inc. and any use of such marks by NXP
Semiconductors is under license.
EdgeLock — is a trademark of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
Kinetis — is a trademark of NXP B.V.
NXP SECURE CONNECTIONS FOR A SMARTER WORLD — is a trademark

of NXP B.V.

Please be aware that important notices concerning this document and the product(s) described
herein, have been included in section 'Legal information'.
© NXP B.V. 2022. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12/2022

Document identifier: KW45

Datasheet KW45

Uploaded by

Copyright:

Available Formats

Datasheet KW45

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Datasheet KW45

Uploaded by

Copyright:

Available Formats

KW45B (radio) and KW45Z (MCU)

KW45 Product Family

Application core Bluetooth Low Energy radio core

Table continues on the next page...

• Secure boot and debug • Memory Protection Unit (MPU)

• Trusted resource domain controller (TRDC) providing • Register write protection

— Write/Erase protection, Execute only, Data only • Clock loss detection

◦ Ed25519 • 32 MHz RF crystal oscillator

— Hash Algorithms • 32.768 kHz crystal oscillator

◦ SHA2-224/256/384/512 • Internal 192 MHz high frequency free running oscillator

Table continues on the next page...

KW45 Product Family, Rev. 9, 12/2022

• Pseudo (PRNG) and True Random Number Generator Analog modules

KW45 Product Family, Rev. 9, 12/2022

Table 1. Ordering Information of radio parts 1

KW45B41Z53AFPBT Tray 6x6 40-pin

KW45B41Z52AFTBT Tray 7x7 48-pin No

KW45B41Z52AFPBT Tray 6x6 40-pin

KW45B41Z83AFTBT Tray 1 MB/128 KB 7x7 48-pin Yes

KW45B41Z82AFTBR Tape and

KW45B41Z83AFPBT Tray 6x6 40-pin Yes

KW45B41Z82AFPBR Tape and

Table 2. Ordering Information of non-radio parts 1

Part Number Packaging Protocol Memory (Flash/RAM) Packages CAN Qualification

KW45Z41052AFTBR Tape and

Table continues on the next page...

KW45 Product Family, Rev. 9, 12/2022

Table 2. Ordering Information of non-radio parts 1 (continued)

Part Number Packaging Protocol Memory (Flash/RAM) Packages CAN Qualification

KW45Z41053AFPBT Tray 6x6 40-pin Yes

KW45Z41052AFPBR Tape and

KW45Z41083AFTBT Tray 1 MB/128 KB 7x7 48-pin Yes

KW45Z41082AFTBR Tape and

KW45Z41083AFPBT Tray 6x6 40-pin Yes

KW45Z41082AFPBR Tape and

Table 3. Device Revision Number

Device Mask Set Number SIM_SDID[REVID]

Table 4. Related Resources

Type Description Resource

Reference The Reference Manual contains a comprehensive description of the KW45B41ZRM

Table continues on the next page...

KW45 Product Family, Rev. 9, 12/2022

Table 4. Related Resources (continued)

Type Description Resource

Package Package dimensions are provided in package drawings. • 48 HVQFN:SOT619-17(D)

MCU(CPU0) Domain SECURITY

WDOG (x2) MPU NVIC TRNG

DWT GPIO (A-D) RTC RAM Standby Regulator

Power Subsystem Radio Subsystem

Figure 1. KW45 block diagram

KW45 Product Family, Rev. 9, 12/2022

1 Ratings............................................................... 9 3.2.5 Free-running oscillator FRO-32K specifications

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes