Chapter 3 Boolean Algebra and Logic Simplification
Chapter 3 Boolean Algebra and Logic Simplification
Chapter 3 Boolean Algebra and Logic Simplification
University of Gondar
Institute of Technology
Department of Electrical Engineering
Digital Logic Design:
Chapter 3:Boolean Algebra and Logic Simplification
By:
Habtamu Maru
Outline
Boolean Theorem
In 1849 George Boole published a scheme for the algebraic de-
scription of processes involved in logical thought and reasoning .
Subsequently, this scheme and its further refinements became
known as Boolean algebra.
The algebra can, therefore, be used to describe logic circuits.
Axioms of Boolean Algebra
Boolean algebra is based on a set of rules that are derived from a small
number of basic assumptions. These assumptions are called axioms.
I 0·0=0 I 0·1=1·0=0
I 1+1=1 I 1+0=0+1=1
I 1·1=1 I If x = 0, then x = 1
I 0+0=0 I If x = 1, then x = 0
Single-Variable Theorems
From the axioms we can define some rules for dealing with single vari-
ables. These rules are often called theorems.
Commutative Distributive
I A·B=B·A I A · ( B + C) = A · B + A · C
I A+B=B+A I A + B · C = (A + B) · (A + C)
Associative Absorption
I A · ( B · C) = (A · B) · C I A + A · B= A
I A + ( B + C) = (A + B) + C I A · (A + B) = A
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Digital Logic Design
Laws and Rules of Boolean Algebra
Combining Consensus
I A·B+B·C+A·C=A·B+A·C
I A·B+A·B=A I (A + B) · (B + C) · (A + C) = (A + B) · (A + C)
I (A + B) · (A + B) = A
Others theorem
DeMorgan’s theorem
I A.B =A +B I A +A · B = A + B
I A+B = A . B I A · (A +B) = A · B
Boolean function
A binary variable can take the value of 0 or 1.
A Boolean function is an expression formed with binary variables,
the two binary operators OR and AND, and unary operator NOT,
parentheses, and an equal sign.
For a given value of the variables, the function can be either 0 or 1.
Algebraic Manipulation
A literal is a primed or unprimed variable. When a Boolean func-
tion is implemented with logic gates, each literal in the function
designates an input to a gate, and each term is implemented with
a gate.
The minimization of the number of literals and the number of
terms results in a circuit with less equipment.
It is not always possible to minimize.
When the operation of a circuit is defined by a Boolean expres-
sion, we can draw a logic-circuit diagram directly from that ex-
pression.
Exercise: Draw the circuit diagram for the expression;
1 F1 =ABC(A + D), F2 =AC+BC+ABC, and F3 = [D + (A + B)C)].E.
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Digital Logic Design
Boolean Analysis of Logic Circuits
Truth table
Any Boolean function can be represented in a truth table, to rep-
resent a function in a truth table.
The number of rows in the table is 2n , where n is the number of
binary variables in the function.
The 1’s and 0’s combinations for each row is easily obtained from
the binary numbers by counting from 0 to 2n - 1.
For each row of the table, there is a value for the function equal
to either 1 or 0.
The advantage of this method are:
I It allows you to analyze one gate or logic combination at a time.
I It allows you to easily double-check your work.
I When you are done, you have a table that is of tremendous benefit
in troubleshooting the logic circuit.
Habtamu M. Digital Logic Design March 13, 2023 23 / 45
Digital Logic Design
Simplification Using Boolean Algebra
Boolean Expression and Truth Table
Determine the truth table for the following standard POS expres-
sion: (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)
The binary values that make the sum term in the expression equal
to 0 are A+B+C:000; A+B+C:010;(A+B+C):011; A+B+C:101 and
A+B+C:110. For each of the remaining binary combination a 1 is
placed in the output column.
Figure
K-Map Format
The K map, like a truth table, is a means for showing the relation-
ship between logic inputs and the desired output.
The K map develop by the following criteria:
The truth table gives the value of output X for each combination of input
values. The K map gives the same information in a different format. Each
case in the truth table corresponds to a square in the K map.
The K-map squares are labeled so that horizontally adjacent squares dif-
fer only in one variable. Similarly, vertically adjacent squares differ only
in one variable.
I Note that each square in the top row is considered to be adjacent
to a corresponding square in the bottom row. Similarly, squares in
the leftmost column are adjacent to corresponding squares in the
rightmost column.
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method
In the above table d: The two 1s in the top row are horizontally
adjacent. The two 1s in the bottom row are also adjacent be-
cause, in a K map, the leftmost column and the rightmost column
of squares are considered to be adjacent.
I When the top pair of 1s is looped, the D variable is eliminated
(because it appears as both D and D ) to give the term A BC.
I Looping the bottom pair eliminates the C variable to give the term
AB D.These two terms are ORed to give the final result for X.
Step 3:: Next, look for those 1s that are adjacent to only one other
1. Loop any pair containing such a 1.
Step 4: Loop any octet even if it contains some 1s that have al-
ready been looped.
Step 5: Loop any quad that contains one or more 1s that have not
already been looped, making sure to use the minimum number
of loops.
Step 6: Loop any pairs necessary to include any 1s that have not
yet been looped, making sure to use the minimum number of
loops.
Step 7: Form the OR sum of all the terms generated by each loop.
F1 =C(A B D+D)+ABC+D
F2 =(A+B+C)(A+B+C)(A+B+C)(A+B+C)
F3 = (A+B+C+D)(A+B+C+D)(A+B+C+D)
(A+C+D)
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method
Don’t-Care Conditions
Some logic circuits can be designed so that there are certain input
conditions for which there are no specified output levels, usually
because these input conditions will never occur.
In other words, there will be certain combinations of input levels
where we “don’t care” whether the output is HIGH or LOW.
In K-map don’t-care condition is represented by X.
Don’t care conditions should be changed to 0 or 1 to produce K-
map looping that yields the simplest expression.
A circuit designer is free to make the output for any don’t-care
condition either a 0 or a 1 to produce the simplest output expres-
sion.
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method
Example:
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OU
K Y
A N
T H
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