Chapter 3 Boolean Algebra and Logic Simplification

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Digital Logic Design

University of Gondar
Institute of Technology
Department of Electrical Engineering
Digital Logic Design:
Chapter 3:Boolean Algebra and Logic Simplification
By:
Habtamu Maru

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Digital Logic Design

Outline

1 Describing logic circuits algebraically

2 Laws and Rules of Boolean Algebra

3 Boolean Analysis of Logic Circuits

4 Simplification Using Boolean Algebra


Standard form of Boolean Expression
Boolean Expression and Truth Table
Karnaugn Map (K-Map) Method

5 Digital Logic Family

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Digital Logic Design
Describing logic circuits algebraically

Describing logic circuits algebraically


Any logic circuit, no matter how complex, can be described com-
pletely using the three basic Boolean operations because the OR
gate, AND gate, and NOT circuit are the basic building blocks of
digital systems.
Operator Precedence
The operator precedence for evaluating Boolean expressions is
(1) parentheses, (2) NOT, (3) AND, and (4) OR.
In other words, the expression inside the parentheses must be
evaluated before all other operations. The next operation that
holds precedence is the complement, then follows the AND, and
finally the OR.

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Digital Logic Design
Laws and Rules of Boolean Algebra

Boolean Theorem
In 1849 George Boole published a scheme for the algebraic de-
scription of processes involved in logical thought and reasoning .
Subsequently, this scheme and its further refinements became
known as Boolean algebra.
The algebra can, therefore, be used to describe logic circuits.
Axioms of Boolean Algebra
Boolean algebra is based on a set of rules that are derived from a small
number of basic assumptions. These assumptions are called axioms.

I 0·0=0 I 0·1=1·0=0
I 1+1=1 I 1+0=0+1=1
I 1·1=1 I If x = 0, then x = 1
I 0+0=0 I If x = 1, then x = 0

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Digital Logic Design
Laws and Rules of Boolean Algebra

Single-Variable Theorems
From the axioms we can define some rules for dealing with single vari-
ables. These rules are often called theorems.

I A·0=0 I A·1=A I A · A = A= A I A·A=0


I A+1=1 I A + 0 =A I A +A =A I A +A = 1

Two and Three-Variable Properties

Commutative Distributive

I A·B=B·A I A · ( B + C) = A · B + A · C
I A+B=B+A I A + B · C = (A + B) · (A + C)

Associative Absorption

I A · ( B · C) = (A · B) · C I A + A · B= A
I A + ( B + C) = (A + B) + C I A · (A + B) = A
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Digital Logic Design
Laws and Rules of Boolean Algebra

Combining Consensus
I A·B+B·C+A·C=A·B+A·C
I A·B+A·B=A I (A + B) · (B + C) · (A + C) = (A + B) · (A + C)
I (A + B) · (A + B) = A
Others theorem
DeMorgan’s theorem
I A.B =A +B I A +A · B = A + B
I A+B = A . B I A · (A +B) = A · B

DeMorgan’s theorem provide mathematical verification of the equiv-


alency of the NAND and negative OR gates and the equivalency of
the NOR and negative AND gates.
Apply DeMorgan’s theorem to the expression
I F1 =A + B + C , F2 = A B C D
I F3 = ABC + D + E
I F4 = AB(C + D) + E
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Digital Logic Design
Boolean Analysis of Logic Circuits

Boolean function
A binary variable can take the value of 0 or 1.
A Boolean function is an expression formed with binary variables,
the two binary operators OR and AND, and unary operator NOT,
parentheses, and an equal sign.
For a given value of the variables, the function can be either 0 or 1.

For example, the Boolean function;


I F1 =ABC

The function F1 , is equal to 1 if A = 1 and B = 1 and C = 1; otherwise


F1 , =0. The above is an example of a Boolean function represented
as an algebraic expression.
A Boolean function may also be represented in a truth table.
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Digital Logic Design
Boolean Analysis of Logic Circuits

Algebraic Manipulation
A literal is a primed or unprimed variable. When a Boolean func-
tion is implemented with logic gates, each literal in the function
designates an input to a gate, and each term is implemented with
a gate.
The minimization of the number of literals and the number of
terms results in a circuit with less equipment.
It is not always possible to minimize.
When the operation of a circuit is defined by a Boolean expres-
sion, we can draw a logic-circuit diagram directly from that ex-
pression.
Exercise: Draw the circuit diagram for the expression;
1 F1 =ABC(A + D), F2 =AC+BC+ABC, and F3 = [D + (A + B)C)].E.
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Digital Logic Design
Boolean Analysis of Logic Circuits

Circuits Containing Inverters


Whenever an INVERTER is present in a logic-circuit diagram, its
output expression is simply equal to the input expression with a
bar over it.

Note that the bar is over the A


alone, indicating that A is first
inverted and then ORed with
B.

It inverts the complete input


expression. Note that the bar
covers the entire expression
(A + B).
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Digital Logic Design
Simplification Using Boolean Algebra

Simplifying Logic Circuits


Once the expression for a logic circuit has been obtained, it may
be able to reduce to a simpler form containing fewer terms or
fewer variables in one or more terms.
The new expression can then be used to implement a circuit that
is equivalent to the original circuit but that contains fewer gates
and connections.
Both circuits perform the same logic, so it should be obvious that
the simpler circuit is more desirable because it contains fewer
gates & will therefore be smaller & cheaper than the original.
Furthermore, the circuit reliability will improve because there are
fewer interconnections that can be potential circuit faults.

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Digital Logic Design
Simplification Using Boolean Algebra

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Digital Logic Design
Simplification Using Boolean Algebra

Simplify the following Boolean expression


1 AB+A(B + C)+B(B + C)
2 A+AB+ABC
3 (AB(C+B D)+AB)CD

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

Standard form of Boolean Expression


All Boolean expression, regardless of their form, can be converted
into either of two standard form: the sum-of-product (SOP) form
and product-of-sum (POS) form.
Standardization makes the evaluation, simplification, & implemen-
tation of Boolean expression much more systematic & easier.
n variables forming an AND term, with each variable being primed
or unprimed, provide 2n possible combinations, called minterms,
or standard products.
n variables forming an OR term, with each variable being primed
or unprimed, provide 2n possible combinations, called maxterms,
or standard sums.

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

SOP expression simply requires ORing the outputs of two or


more AND gates. eg. AB+BCD+AC
POS expression simply requires ANDing the outputs of two or
more OR gates. eg. (A+B)(B+C+D)(A+C)
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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

A Boolean function may be expressed algebraically from a given


truth table by forming a minterm for each combination of the vari-
ables that produces a 1 in the function, and then taking the OR of
all those terms,& in case the output is 0 then it corresponds to 0.
Example: Express the following in corresponding minterm and max-
term expression.
(a) F1 = ABC + ABC + ABC + AB C
(b) F2 = (A+B+C) (A+ B+C) (A+ B+ C)
Solution (a): F1 = ABC + ABC + ABC + ABC , is an example of standard
(canonical) SOP expression, so its each term can be represented in
minterm notation. Therefore,
Y = ABC + ABC + ABC + AB C = m7 + m3 + m5 + m4 = ∑(3, 4, 5, 7)
∑ is used to denote CSOP
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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

Solution (b): F2 = (A+B+C) (A+ B+C) (A+ B+ C), is an example of standard


(canonical) POS expression, so its each term can be represented in
maxterm notation.
Y= (A+B+C) (A+ B+C) (A+ B+ C) = M0 + M5 + M7 = ∏ (0, 5, 7)
∏ is used to denote CPOS
Consider the Boolean function given in table below:

F=A BC+AB C+ABC+ABC+ABC


F=m1 +m4 +m5 +m6 +m7
F=∑(1,4,5,6,7)
F=M0 M2 M3 =∏(0,2,3)

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

There are few different forms of Sum of Product.


I Canonical SOP Form
I Non-Canonical SOP Form
I Minimal SOP Form

Canonical is the standard form of SOP. It is formed by ORing the


minterms of the function for which the output is true (1). This is
also known as Sum of Minterms.
Canonical form contains all inputs either complemented or non-
complemented in its product terms.
Example from the above table;
I Minterms in the expression F=A BC+AB C+ABC+ABC+ABC
I The canonical SOP expression is F=m1 +m4 +m5 +m6 +m7 =∑(1,4,5,6,7)

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

Non-Canonical SOP Form is the non-standardized form of SOP ex-


pressions.
The product terms are not the minterms but they are simplified.
This expression is still in SOP form but it is non-canonical or non-
standardized form.
Let’s take the above function in canonical form as an example.
I F=A BC+AB C+ABC+ABC+ABC
F=A BC+AB(C+C) +ABC+ABC where C+C=1
F=A BC+AB +ABC+ABC

This expression is still in SOP form but it is non-canonical or non-


standardized form.

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

Minimal SOP Form is the most simplified SOP expression of a func-


tion. It is also a form of non-canonical form.
Minimal SOP form can be made using Boolean algebraic theorems
but it is very easily made using Karnaugh map (K-map).
Minimal SOP form is preferred because it uses the minimum num-
ber of gates and input lines.
It is commercially beneficial because of its compact size, fast speed,
and low fabrication cost.
Conversion from Minimal SOP to Standard SOP Form
Multiply each minimal (non-standard) product term by a term made
up of the sum of missing variable and its complement.
example; F=AB+ABC=AB(C+C)+ABC=ABC+ABC+ABC
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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

The Product - of - Sum (POS) Form


POS expression simply requires ANDing the outputs of two or
more OR gates. eg. (A+B)(B+C+D)(A+C)
The standard POS
A standard POS expression is one in which all the variables in the
domain appear in each sum term in the expression.
eg.(A+B+C) (A+B+C) (A+B+C)
Convert the following Boolean expression into standard POS form:

I (A+B)(B+C) :-The domain of this POS expression is A,B,C. Take one


term at a time.

The first term, A+B, is missing variable C or C, so add CC.


A+B+CC=(A+B+C)(A+B+C)
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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

The second term, B+C is missing variable A or A, so add AA.


B+C+AA=(A+B+C)(A+B+C)
∴ (A+B)(B+C)= (A+B+C)(A+B+C)(A+B+C)(A+B+C)
Converting Standard SOP to Standard POS
The binary value of the product term in a given standard SOP ex-
pression aren’t present in the equivalent standard POS expres-
sion.
Also, the binary values that are not represented in the SOP ex-
pression are present in the equivalent POS expression.

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Digital Logic Design
Simplification Using Boolean Algebra
Standard form of Boolean Expression

Eg. Convert the following SOP expression to an equivalent POS


expression. A B C+AB C+ABC+ABC+ABC
The evaluation is: 000+010+011+101+111
There are total of eight (23 ) possible combination. The SOP ex-
pression contains five of these combinations, so the POS must
contain the other three which are 001,100,and 110. Remember
these are the binary values that make the sum term 0.
∴ The equivalent POS expression is: (A+B+C) (A+B+C)(A+B+C)

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Digital Logic Design
Simplification Using Boolean Algebra
Boolean Expression and Truth Table

Truth table
Any Boolean function can be represented in a truth table, to rep-
resent a function in a truth table.
The number of rows in the table is 2n , where n is the number of
binary variables in the function.
The 1’s and 0’s combinations for each row is easily obtained from
the binary numbers by counting from 0 to 2n - 1.
For each row of the table, there is a value for the function equal
to either 1 or 0.
The advantage of this method are:
I It allows you to analyze one gate or logic combination at a time.
I It allows you to easily double-check your work.
I When you are done, you have a table that is of tremendous benefit
in troubleshooting the logic circuit.
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Digital Logic Design
Simplification Using Boolean Algebra
Boolean Expression and Truth Table

A truth table is a common way of presenting, in a concise format,


the logical operation of a circuit. Also, standard SOP or POS ex-
pression can be determined from a truth table.
Develop a truth table for the standard SOP expression
A BC+AB C+ABC and ABC+ABC
The binary values that make the product term in the expression
equal to 1 are 001;100;111. For each of the remaining binary com-
bination a 0 is placed in the output column.

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Digital Logic Design
Simplification Using Boolean Algebra
Boolean Expression and Truth Table

Determine the truth table for the following standard POS expres-
sion: (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)
The binary values that make the sum term in the expression equal
to 0 are A+B+C:000; A+B+C:010;(A+B+C):011; A+B+C:101 and
A+B+C:110. For each of the remaining binary combination a 1 is
placed in the output column.

Figure

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Digital Logic Design
Simplification Using Boolean Algebra
Boolean Expression and Truth Table

Determined the standard SOP expression and the equivalent


standard POS expression.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

The Karnaugh map (K map) is a graphical tool used to simplify a


logic equation or to convert a truth table to its corresponding logic
circuit in a simple, orderly process.
Although a K map can be used for problems involving any number
of input variables, its practical usefulness is limited to five or six
variables.
A K-map is similar to a truth table because it presents all of the
possible values of input variable and the resulting output for each
value.
Instead of being organized into columns and rows like a truth ta-
ble, the k map is an array of cells in which each cell represents a
binary value of the input variable.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

K-Map Format
The K map, like a truth table, is a means for showing the relation-
ship between logic inputs and the desired output.
The K map develop by the following criteria:
The truth table gives the value of output X for each combination of input
values. The K map gives the same information in a different format. Each
case in the truth table corresponds to a square in the K map.
The K-map squares are labeled so that horizontally adjacent squares dif-
fer only in one variable. Similarly, vertically adjacent squares differ only
in one variable.
I Note that each square in the top row is considered to be adjacent
to a corresponding square in the bottom row. Similarly, squares in
the leftmost column are adjacent to corresponding squares in the
rightmost column.
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

In order for vertically and horizontally adjacent squares to differ


in only one variable, the top-to-bottom labeling must be done in
the order shown: A B, AB,AB,AB. The same is true of the left-to-
right labeling: C D, CD,CD,CD.
Once a K map has been filled with 0s and 1s, the sum-of-products
expression for the output X can be obtained by ORing together
those squares that contain a 1.
Looping
The expression for output X can be simplified by properly combin-
ing those squares in the K map that contain 1s. The process for
combining these 1s is called looping.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Looping Groups of Two (Pairs)


Looping a pair of adjacent 1s in a K map eliminates the variable
that appears in complemented and uncomplemented form.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

In the above table d: The two 1s in the top row are horizontally
adjacent. The two 1s in the bottom row are also adjacent be-
cause, in a K map, the leftmost column and the rightmost column
of squares are considered to be adjacent.
I When the top pair of 1s is looped, the D variable is eliminated
(because it appears as both D and D ) to give the term A BC.
I Looping the bottom pair eliminates the C variable to give the term
AB D.These two terms are ORed to give the final result for X.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Looping Groups of Four (Quads)


A K map may contain a group of four 1s that are adjacent to each
other. This group is called a quad.
Looping a quad of adjacent 1s eliminates the two variables that
appear in both complemented and uncomplemented form.
Looping Groups of Eight (Octets)
A group of eight 1s that are adjacent to one another is called an
octet.
Looping an octet of adjacent 1s eliminates the three variables that
appear in both complemented and uncomplemented form.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Complete Simplification Process


When a variable appears in both complemented and uncomple-
mented form within a loop, that variable is eliminated from the
expression. Variables that are the same for all squares of the loop
must appear in the final expression.
It should be clear that a larger loop of 1s eliminates more vari-
ables. a loop of two eliminates one variable, a loop of four elimi-
nates two variables, and a loop of eight eliminates three variables.
The steps below are followed in using the K-map method for simplify-
ing a Boolean expression:
Step 1: Construct the K map and place 1s in those squares corresponding
to the 1s in the truth table. Place 0s in the other squares.
Step 2: Examine the map for adjacent 1s and loop those 1s that are not
adjacent to any other 1s. These are called isolated 1s.
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Step 3:: Next, look for those 1s that are adjacent to only one other
1. Loop any pair containing such a 1.
Step 4: Loop any octet even if it contains some 1s that have al-
ready been looped.
Step 5: Loop any quad that contains one or more 1s that have not
already been looped, making sure to use the minimum number
of loops.
Step 6: Loop any pairs necessary to include any 1s that have not
yet been looped, making sure to use the minimum number of
loops.
Step 7: Form the OR sum of all the terms generated by each loop.

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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Filling a K Map from an Output Expression


When the desired output is presented as a Boolean expression
instead of a truth table, the K map can be filled by using the fol-
lowing steps:
I 1. Get the expression into SOP form if it is not already in that form.
I 2. For each product term in the SOP expression, place a 1 in each
K-map square whose label contains the same combination of input
variables. Place a 0 in all other square.

Use a K map to simplify

F1 =C(A B D+D)+ABC+D

F2 =(A+B+C)(A+B+C)(A+B+C)(A+B+C)

F3 = (A+B+C+D)(A+B+C+D)(A+B+C+D)
(A+C+D)
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Don’t-Care Conditions
Some logic circuits can be designed so that there are certain input
conditions for which there are no specified output levels, usually
because these input conditions will never occur.
In other words, there will be certain combinations of input levels
where we “don’t care” whether the output is HIGH or LOW.
In K-map don’t-care condition is represented by X.
Don’t care conditions should be changed to 0 or 1 to produce K-
map looping that yields the simplest expression.
A circuit designer is free to make the output for any don’t-care
condition either a 0 or a 1 to produce the simplest output expres-
sion.
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Digital Logic Design
Simplification Using Boolean Algebra
Karnaugn Map (K-Map) Method

Example:

Exercise:- Design of 4-bit BCD-to-XS-3 code converter.


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Digital Logic Design

!! !
OU
K Y
A N
T H
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