A VHDL Implementation of BIST Technique in UART Design

Mohd Yamani Idna ldris Mashkuri Yaacob Faculty of Computer Science and Infonnation Technology University of Malaya Kuala Lumpur, Malaysia
-s'tt11.1tlt(~t I I I I I t d t I
1111, I I I ' I \ ~ ~ U I lir(,unt

ctlutnl

A h s t r m t - To increase reliability, manufacturers must be able to discover a high percentage of defective chips during their testing procedures. This paper will highlight the attention given by most customers who are expecting the designer to include testability features that will increase their product reliability. This paper focuses on the design of a UART chip with embedded Built-In-SelfTest (BIST) architecture using FPGA technology. The paper starts by describing the behavior of UART circuit using VHISC IHardware Description Language (VHDL). In the implementation phase, the BlST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements.

and a multiple input signature register (MISR) depending on its operating mode [5]. BILBO testability technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.

2. VHDL IMPLEMENTATION
As integrated circuit technology has become more complex, detailed design of systems at the gate and flipflop level has become very tedious and time consuming. For this reason, use of hardware description languages in the digital design process has significantly improved in the last few years, especially for FPGA design. A hardware description language allows a digital system to be designed and debugged at a higher level before conversion to the gate and flip-flop level. One of the most popular hardware description languages is VHISC hardware description language (VHDL) [6]. I t is used to describe and simulate the operation of a variety of digital systems, ranging in complexity from a few gates to an interconnection of inany complex integrated circuits. There are inany excellent hardware description languages (HDL) were prior to VHDL but VHDL offers a number of benefits over other HDL's [ 7 ] . A number of the advantages are: i. ii. VIHDL as a Standard Language Increase productivity Better design Reusability for new technology Tools independence Minimum cost 2nd time

1. INTRODUCTION
A universal asynchronous receive/transmit (UART) [ I , 2 and 31 is an integrated circuit which plays the most important role in serial cominunicatioii. It handles the conversion between seIial and parallel data. Serial comniunication reduces the distortion of a signal, therefore makes data transfer between two systems separated in great distance possible (i.e. hundreds of feet and millions of miles apart). The embedded BlST architecture provides opportunities for the sharing of system and test logic. BlST is a method of self-testing on a system on chip due to the complexity to determine stuck at logic error using conventional methods such as bed of nails. The technique proposed for BlST architecture in this paper is built-in-logic-block-observer (BILBO). The BILBO tcchnique has been recognized as a method that can help to reduce the test and maintenance cost of chip production. It offers advantages concerning fault covcrage, detection of delay faults, and test application time [4]. By implementing BILBO architecture to a design. an external tester feature, such as a test pattern generator (TPG) and an output response analyzer (ORA) will be cmbedded into the part that contains the circuit rinder test (CUT). This can be done since BILBO can act as a shift register, a linear feedback shift register (LFSR)
0-7803-765 I-X/O3/$17.00 02003 IEEE

111.

...

iv. v. vi.

2.1 VHDL nnd BIST

It is becoming increasingly coininon for design for testability (DFT) issues to be addressed at design reviews prior to circuit tape-out approval. Previously, in the age of schematics, this often require design and test engineers to sift through pages of-manuals and data sheets looking for things like asynchronous setheset circuit

Poster Papers / 1451

configurations. derived or internally generated clocks, and combinatorial arid sequential feedback loops. The review inevitably occurred late in the design cycle: adversely affecting project schedules if glitches were found, and making for ail uncomfortable process for the circuit designer. With todays design practices, however, schematics are niostly outdated [SI. Designers can take inore coiitrol of the DFT rcvicw by performing DFT rule checking at the register transfer language (RTL) (VHDL) level. I-lowevcr, finding DFT problems in language-based designs is still not a simple task for humans. Thc acceptance of tho design for test iechniques has been largcly due to the possibility of VHDL siippoit to this design style. I t is desirable to eventually have availablc a IjIS1 approach with similarly VI IDL support. The high dcgrw of st:intlardizatioti makes possible to have most testability feature prcviotisly added to a dcsign using VIHDL. (MISR). The test starts with the initialization of the BILBO by applying a seed to its serial-in (si) pin. The initialization can be obtained by configuring BILBOs operating mode (bilbo-modc) to 00 (shift register mode). Following the initialization, the bilbo-mode is set to 01 so that Register A is configured as LFSR (bilbo-mode = 01) and Register B as MISR (bilbo-mode = I I (Note: XOR force 01 to 1 I)).

. Ir

_.
n

*.
1 .

3. UART WITH BILBO REGISTER AND

TEST E R
The problem of testing scquential network is simplified by observing thc state of all thc flip-flops instead ofjust observing the outputs. For each state of the flip-flops and for each input combination, the network outputs need to bc vcritictl :ind goes to the correct next state. Onc approach \ w d be to conncct thc output of each tlip-tlop w i t h i n the IC being-tested t o otic of the IC pins. Sincc the number of pins on the IC is limited, this approach is nor practical. The solirtion to the question is by arranging tlip-tlops to form a shift register. The state of the flip-flop will be shifted out bit-by-bit using a single scrial-output pin on the IC. This is called scan path tcs t i ng . L31L130 is a scan register that can be modified to serve iis ii state register, a pattern generator, a signature register. or ii shift register. I n summary the BILBO operating modcs arc rcprcsentcd as follows [ 6 ] :

Figure 2: UART with BILBO Register and Tester

Register A (LFSR) produces an %bits pseudo random pattern data in parallel. The parallel data is then fed to the UARTs transmitter. The UART converts the pseudo random parallel data to serial data which is then looped back to its receiver to create an internal diagnostic capability. The UARTs receiver converts the serial data back to parallel and will be accepted by Register B (MISR). A signature will be produced after 255 clock iterations (8 data bits produce 2 = 256 PRPG) and this completes the test. The signature is scanned out from serial output (so) pin by configuring bilbo-mode to 00. Following the scan. i t is compared with the correct signature achieved from the simulation of the entire selftest sequence approach i n a tester. If the signaturc produced by MISR is similar to the correct. signature, i t can be concluded that the UART is working properly.

U1 B2
00
01

Operating Mode
Shift register LFSRIPRPG No rnia 1 MISR

4. SIMULATION
During BILBOs normal mode (BI B2 = IO), the chip will act as a normal UART chip. The transmitter and receiver simulation under nomial mode will be shown next. The simulation of UART under testing mode will be carried out in the following section.
4. I UART Normul Mode

IO I1

Fiyirc I : 1311,BO Operating Modes Figure 2 illustrates how to apply BlLBO registcrs to test the UART design. I n this structure, Rcgistcr A and Register B may be configured by mode control (bilbo-mode) signal to act as either a shift register. a test pattein generator (PRPG). normal application mode function (normal) or a data compressor

4.1. I Trrmsnii!tcrSiniiiltrtioii The simulation will show the transmission of an 8-bit UART frame format with 1 stop bit and without a parity bit. The transmission was set by the user to perform

TENCON 2003 / 1452

at 115.2kbps using 40MHz clock, which is equal to 25ns (1/40MHz = 2511s) period.
................................................................................................................ ....... ........ ........I..--'--'..$.. ..... ......... ........ ........

..............

..........

.......

8 ........I ..... ........ .....

..................................................................

.............. ... ...

I'

Figure 5: BlST Setup

Figure 3: Serial 8-bits Data Transmission at TXD Figure 3 shows the signal results of the 8-bit transmission via DATA[7:O]. The data ("00000 1 1 1 transmitted UART frame format can be observed at TXD ( I low start bit, 8 data bits (LSB to MSB), and 1 high stop ~. bit). The 3-bit high data is equal to 2 6 . 0 5 ~ 1Therefore I data bit is equal to 26.05us/3 = 8 . 6 8 ~ s . From this information, the baud rate can be calculated as 1/8.68us, which is equal to 115,207 = 115.2k.
4.1.2 Receiver Sindution

E''#

.................................................................................... .;...... ...................................................

.. ..

...I...+.

......................... .........................
I

... ... ... ...

Figure 6: BILBO Acts as a Shift Register

T o start the test. the BILBO-MODE (bcfore 3us) is set to " 0 1; to operate in normal mode. From 3us to 13us, the BILBO-MODE is set to "0O1<' and acts as a shift register. BILBO shift register then shifts the value of S-DATA-IN from right to left (LSB to MSB) by using a serial in (si) pin (Figure 5 & 6). The shifting is conducted to initialize the LFSR and MlSR with a 'secd' data. S-DATA-IN then pushes the data to S-QOUT after 2clock delay. Table 1 shows S-QOUT and S-DATA-IN in
binary. A s can b e observed at the end of Table I , the

........................................................................................

+..................

Figure 4: 8-bits Data Received at DATA[7:0] when Data

Output Enabled. Internal Data Received at S-RXDATA.

LFSR is initialized to "OF,," and MlSR is initialized to "%2Ell".

Figure 4 shows how an S-bit serial data from RXD is received. The data consists of 4 high bits and 4 low bits ( 1 bit = 8.675~s). The data is then converted to 'parallel S-RXDATA at 9 3 . 0 1 ~ s . S-RXDATA is the internal parallel data received at the receiver. The output of the received parallel data is then routed to DATA[7:O] output's pin. The parallel data will be activated when the data output is enabled (s-dataoe = '0'). The received data can be observed between the high impedance "ZZI," at DATA[7:O] (if the time/div is widened). 4.2 UAR T Testing Mode

Table 1: S-QOUT and S-DATA-IN in binary

S-QOUT

S-QOUT
(BINARY)

S-DATAZIN

S-DATA-IN
(BINARY)

(CI EX)
01 02 04

(HEX)
2E

ns

0000000 I 000000 IO 00000 IOU oonn I ooo

001000 I U

U O I O I I10
U I0 I I I O 0

5c
I8 3 70

io1 I
01 I

ioon inooo

I I ono000

dJ.1 BlST Simulation

2E

01 000101 1000101I 000101 1 I 00101 110

10000001 oonooo I I
07 0F

oonon I I I
nnoo I I I I

In this particular simulation case, the UART is set to-internal loop back mode. This mode will be used to test both the transmitter and receiver of the UART. The mode will loop-back the serial data and transmit the data back to the receiver.

Poster Papers / 1453

;EyETK

....................................................................................................

..................................................................
.................................................................................

Figure 7: BILBO Acts as an LFSR and MISR Figure 7 shows that the BILBO-MODE is set to 01 ll. In this mode, the BILBO at the transmitter is configured as an LFSR and BILBO at the receiver is configured as an MISR. During BILBOLMODE = 0 1 ~ DATA[7:O] can be ignored. S-DATA-IN acts as an LFSR that produces parallcl psciido random pattern (PRPG) signals to the UARTs transmitter. These parallel signals are then converted to serial data in a communication line and will be looped back to the receiver. The receiver converts the data back to parallel and forwards it to S-RXDATA. S-QOUT (MISR) compresses all the received pseudo randoin parallel data (S-RXDATA) into one signature. The produced signature is then conipared with the correct signature. S-DATA-IN (PRPG) is achieved by XOR-ing bit 1,2,3 and 7 (MSB ... LSB. b7 ...bo) and the XORed result is placed to bit 0 (LSB). The other remaining bits (b6...h0) are shifted to the left. The S-QOUT (MISR) is achieved as S-DATA-IN except that the produced data (PRPG) is then XORed with S-RXDATA.

Figure 8: Final value of MlSR (S-QOUT) to be shifted out as a serial signature The process of feeding the transmitter with pseudo random data and compressing it with MlSR is complete after 255 clocks iteration. The final result of MlSR (S-QOUT) in Figure 8 can be observed as 010l0001~. However. S-QOUT (MISR) is the internal data of the designed UART. Therefore, there should be R method to send out the signature without sacrificing extra observance output pins. The signature is shifted out at serial data out (so) outputs pin. To shift out the signature, BILBO-MODE is set back to OO1l) and acts as a shift register. In Figure 9, bilboen signal enables the signature to be transmitted as a serial out data (so). As can be observed, so is transmitted as the following sequence: 1 low bit, 1 high, 1 low, 1 high, 3 low and 1 high. The result is the serial data of 0I O IO001U), which is equal to the value of MlSR at S-QOUT. The signature produced is also similar with the correct signature achieved from the simulation of the entire self-test sequence approach using C programming.

.... ....... ............................................................................................................................... BDATA[7 0 1 BADDR[3 01 ( h h :8 C i C

Y .\w

......................................

Bbilben :1 ....... Bbilbs_made[l C 0

BS-RXDATk[l 0
BS_@OUT[7 01 BS-DATA-INL7 B so
I

.......
Figure 9: Serial Data Out Signature at so

OF

TENCON 2003 / 1454

5. CONCLUSION
The simulated waveforms presented in this paper have proven the reliability of the VHDL implementation to describe the characteristics and the architecture of the designed UART with embedded BIST. The simulated waveforms also have shown the observer how long the test result can be achieved by using the Built-In-Self-Test technique. The test as shown in Figure 9 is completed at 22.2ms using 40 MHz clock speed transmitting at I15.2k baud rate. Even though it seems not to be as fast as it should be when BIST is implemented (the receiver needs to wait the signal from the transmitter), the UART module still takes advantage of the 100% fault coverage. This is the most important thing that should not be left out by any designer to ensure the reliability of their design. The next target for this research is to verify the RTL, implement and download it on Xilinxs FPGA chip.

REFERENCES
Martin S. Michael, A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs National Seiniconductor Application Note 493, April 1989 PC I6550D Universal Asynchronous FIFOs, National Receiver/Transmitter with Semiconductor Application Note, June 1995 M. S. Harvey, Generic UART Manual SiliconValley. December 1999. Albrecht P. Strode, and Hans-Joachim Wunderlich, Hardware-Optimal Test Register Insertion IEEE Transactions On Computer-Aided Design of integrated Circuits and Systems, Vol. 17, No. 6, pp 53 1-539. June 1998 Petlin, O.A.; Furber, Built-In-Self-Testing of Micropipelines S.B. Advanced Research in Asynchronous Circuits and Systems, pp 22-29, 1997 IEEE Charles M Roth, Jr., Digital System Design Using VHDL PWS Publishing Company, 1998 Zainalabedin Navabi, VHDL Analysis and Modeling of Digital Systems McGraw-Hill Inc. 1991 Jon Turino, RTL DFT Rule Checking - The Circuit Designers Secret Weapon Integrated System Design Magazinq, 2000