Exercise 2 - Assignment 2

Name: Lê Phước
Class: SE17C01
ID: DE170008
5.4 Figure 5.6 indicates how to construct a module of chips that can store 1 MByte
based on a group of four 256-Kbyte chips. Let’s say this module of chips is
packaged as a single 1-Mbyte chip, where the word size is 1 byte. Give a high-
level chip diagram of how to construct an 8-Mbyte computer memory using eight
1-Mbyte chips. Be sure to show the address lines in your diagram and what the
address lines are used for.
Answer:
5.6 The memory of a particular microcomputer is built from 64K * 1 DRAMs.

According to the data sheet, the cell array of the DRAM is organized into 256
rows. Each row must be refreshed at least once every 4 ms. Suppose we refresh the
memory on a strictly periodic basis.
a. What is the time period between successive refresh requests?
b. How long a refresh address counter do we need?
Answer:
a. The refresh period from row to row must be no greater than
4/256 = 0.015625 (ms).
b. An 8-bit counter is needed to count 256 rows.
6.3 Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64
sectors per track. Sector size is 1 kB. The average seek time is 8 ms, the track-to-
track access time is 1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in
a cylinder can be read without head movement.
a. What is the disk capacity?
b. What is the average access time? Assume this file is stored in successive sectors
and tracks of successive cylinders, starting at sector 0, track 0, of cylinder i.
c. Estimate the time required to transfer a 5-MB file.
d. What is the burst transfer rate?
Answer:
a, Capacity =8 * 512 * 64 * 1 KB = 256 MB
b, Rotational latency = rotation time/2 =60/(3600 * 2) = 8.3 ms.
Average access time = seek time + rotational latency = 16.3 ms
c, Each cylinder consists of 8 tracks * 64 sectors/ track * 1KB/sector = 512 KB;
 5MB requires exactly 10 cylinders
Read 8 tracks on one cylinder: 8 * 8.3 * 2 = 133.3 ms;
 Access Time= 8+9 *(8.3+133.3+1.5) - (8.3+133.3) = 1425.5 ms
d, Burst rate = (revolutions/second) * (sectors/revolution) * (bytes/secter)
= (3600 / 60) * 64 * 1 = 3.84 MB/s
6.4 Consider a single-platter disk with the following parameters: rotation speed:
7200 rpm; number of tracks on one side of platter: 30,000; number of sectors per
track: 600; seek time: one ms for every hundred tracks traversed. Let the disk
receive a request to access a random sector on a random track and assume the disk
head starts at track 0.
a. What is the average seek time?
b. What is the average rotational latency?
c. What is the transfer time for a sector?
d. What is the total average time to satisfy a request?
Answer:
a, On average the number of tracks traversed is (30,000-1)/2 = 14,999.5 tracks.
At 100 tracks/ms, the average seek time is 14,999.5/100 = 149.995 (ms)
b, 7200 rpm => 7200/(1*60*100) = 0.12 rpms => 8.333 (ms)
c, The transfer time for one sector is 8.333/600 = 0.01389ms
d, 149.995 + 8.333/2 + 0.01389 = 154.17539 ms
7.14 Examination of the timing diagram of the 8237A indicates that once a block
transfer begins, it takes three bus clock cycles per DMA cycle. During the DMA
cycle, the 8237A transfers one byte of information between memory and I/O
device.
a. Suppose we clock the 8237A at a rate of 5 MHz. How long does it take to
transfer one byte?
b. What would be the maximum attainable data transfer rate?
c. Assume that the memory is not fast enough and we have to insert two wait states
per DMA cycle. What will be the actual data transfer rate?
Answer:
a, 5MHz => 1/(5*106) (s) = 0.2*10-6 (s)
Because it takes three bus clock cycles per DMA cycle
 0.2*10-6*3=0.6*10-6(s)
b, => The data rate: 1/(0.6*10-6) B = 1.67MB/s
c, A transfer of byte takes: 0.2*10-6*(3+2)=10-6 (s)
=> The data rate: 1/(10-6) B =1MB/s
7.18 A computer consists of a processor and an I/O device D connected to main
memory M via a shared bus with a data bus width of one word. The processor can
execute a maximum of 106 instructions per second. An average instruction
requires five machine cycles, three of which use the memory bus. A memory read
or write operation uses one machine cycle. Suppose that the processor is
continuously executing “background” programs that require 95% of its instruction
execution rate but not any I/O instructions. Assume that one processor cycle equals
one bus cycle. Now suppose the I/O device is to be used to transfer very large
blocks of data between M and D.
a. If programmed I/O is used and each one-word I/O transfer requires the processor
to execute two instructions, estimate the maximum I/O data-transfer rate, in words
per second, possible through D.
b. Estimate the same rate if DMA is used.
Answer:

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Name: Lê Phước

5.6 The memory of a particular microcomputer is built from 64K * 1 DRAMs.

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