MEL G642 VLSI ARCHITECTURE

ASSIGNMENT 1

Implement a 5-stage pipelined processor in Verilog. This processor supports the instructions:
load upper immediate (lui), or immediate (ori), set on less than (slt), load word (lw), store word
(sw), jump (j). The processor should implement forwarding to resolve data hazards. The
processor has Reset, CLK as inputs and no outputs. The processor has instruction fetch, decode,
execution, memory, and writeback units. The processor also contains four pipelined registers
IF/ID, ID/EX, EX/MEM, and MEM/WB. When reset is activated, the PC, IF/ID, ID/EX,
EX/MEM, and MEM/WB registers are initialized to 0. The instruction memory and register file
get loaded by predefined values.

The pipelined registers contain unknown values when the instruction unit starts fetching the first
instruction. When the second instruction is being fetched in the IF unit, the IF/ID register will
hold the instruction code for the first instruction. When the third instruction is being fetched by
the IF unit, the IF/ID register contains the instruction code of the second instruction, the ID/RR
register contains information related to the first instruction, and so on. (Assume a 32-bit PC.
Also, Assume Address and Data size as 32-bit).

The instruction and its 32-bit instruction format are shown below:

lui destReg, imm (loads the highest 16 bits of the register rt with a constant (immediate value),
and clears the lowest 16 bits to zeros. Opcode for lui is 001111.)

(Note: This instruction does not use bits 25-21 (rs), preferably set them to 00000)

op rs rt offset

6 bits (31-26) 5-bits (25-21) 5-bits (20-16) 16-bits (15-0)

ori destReg, sourceReg, imm (“or immediate” will perform a bitwise OR operation on the
register rs and the immediate value, and store the result in register rt. Opcode for ori is 001101.)

op rs rt offset

6 bits (31-26) 5-bits (25-21) 5-bits (20-16) 16-bits (15-0)

slt destReg , sourceReg1, sourceReg2 (“set less than” sets rd value as 1 if the value in the rs
register is less than the rt value, else sets it to 0. Opcode for slt is 000000 and func value is
101010).

op rs rt rd shamt func

6 bits (31- 5-bits (25- 5-bits (20- 5-bits 5 bits 6 bits

26) 21) 16) (15-11) (10-6) (5-0)

lw destReg, offset [sourceReg] (sign extends 16-bit immediate offset to 32-bits, adds it with
register rs to get the memory address and loads the data from memory in register rt. Opcode for
lw is 101000).

op rs rt offset

6 bits (31-26) 5-bits (25-21) 5-bits (20-16) 16-bits (15-0)

sw sourceReg, offset [destReg] (sign extends 16-bit immediate offset to 32 bits, adds it with
register rs to get the memory address, and stores the data from register rt at the obtained memory
address. Opcode for sw is 100011).

op rs rt offset

6 bits (31-26) 5-bits (25-21) 5-bits (20-16) 16-bits (15-0)

j target (jumps to an address generated by appending 00 to the right and 4 higher order bits of
the program counter [31:28] to the left, of the 26 bit address field in the instruction. Opcode for j
is 000010). For clarity, jump address(32-bit) = {PC[31:28], 26-bit immediate value, 00}

op address

6 bits (31-26) 26-bits (25-0)

Assume the register file contains 32 registers (R0-R31) each register can hold 32-bit data. On
reset, PC and all register file registers should get initialized to 0. Ensure r0 is always zero. Each
location in DMEM has 8-bit data. So, to store a 32-bit value, you need 4 locations in the DMEM,
stored in big-endian format. Also ensure that on reset, the instruction memory gets initialized
with the following instructions, starting at address 0:

LW R1, 12[R2]
 LW R3, 18[R4]
SLT R5, R1, R3
ORI R6, 200[R5]
SW R6, 2[R7]
j L1
LW R7, 12[R7]
L1: LUI R0, 128[R6]

The above code should run correctly on the processor implementation. Ensure that you handle
the data hazards present if any.

A partial block-level representation of the 5-stage pipelined processor is shown below. Please
note that for register file implementation, write should be on the positive edge, and read
should be on the negative edge of the clock. Write operation depends on the control signal.

Ins Inst Ex M Wr
tru ruc ec e ite
cti tion ut m Ba

I I E ME
F D X/ M/

C
L RE
K
As part of the assignment, three files should be submitted in a zipped folder.

1. PDF version of this Document with all the Questions below answered with the file name
IDNO_NAME.pdf.
2. Design Verilog Files for all the Sub-modules (instruction fetch, Register file, forwarding
unit).
3. Design a Verilog file for the main processor.

The name of the zipped folder should be in the format IDNO_NAME.zip

NAME: Nivedita Acharyya ID
No:2022H1400070G

Questions Related to Assignment

1. Draw the complete Datapath and show control signals of the 5-stage pipelined
processor. A sample Datapath for a 5-stage pipelined MIPS processor has been
discussed in class. A ppt named Assignmenthelp.ppt contains this 5-stage
processor and is shared with you. You can modify this according to your
specification.

Answer:

2. Suppose we have to load a 32-bit constant value in one of the registers. (A single
instruction only supports giving a 16-bit immediate value.) Implement the
functionality to load a 32-bit constant value into the register, and then store it in
memory. [Hint: Use the instructions discussed in this file]
For example, store 1101010010101110 1010110000110100 in reg R1, then store
R1 in a memory location.

Answer:
3. List the control signals used and also the values of control signals for different
instructions in a tabular format as follows:

Answer:

Instructions Control Signals

RegWrit RegDst ALU_src ALU_op Mem_rea Mem_W

e d rite

lw 1’b1 1’b0 1’b1 2'b00 1’b1 1’b0

sw 1’b0 1’b0 1’b1 2'b00 1’b0 1’b1

slt 1’b1 1’b0 1’b1 2’b11 1’b0 1’b0

lui

ori

j 1’b0 1’b0 1’b0 1’b0

4. In a program, there are 25% stores instructions, 1/x of which are immediately
followed by an instruction that uses a result, requiring a stall. 10% are loads.
50% are R-type. 10% are branch, 1/y of which are taken. 5% are jumps. What is
the average CPI of this program? If the number of instructions is 10^9, and the
clock cycle is 100 ps, how much time does a MIPS single-cycle pipelined processor
take to execute all instructions? Assume the processor always predicts branch
not-taken.
Where x, y, z are related to last 3 digits of your ID No.
If ID number: 20XXXXXXABCG, then x = (A % 8) + 1, y = ((B + 2) % 8) + 1,
and z= ((C + 3) % 8) + 1.

Answer:assume there are 1000 instructions

CPI = 5+(1000-1)+125+(100/4)*3=1.204
Time=1.204*10^(9)*10^(-10)=0.1204

5. Implement the Instruction Fetch block. Copy the image of Verilog code of the
Instruction fetch block here

Answer:
6. Implement the Instruction Decode block. Copy the image of Verilog code of the
Instruction decode block here

Answer:
7. What is the data hazard in the given instruction snippet? Determine the condition
that can detect the data hazard in the given instruction snippet.

Answer: EX Hazard Detection

1a. EX/MEM.RegWrite = 1

and EX./MEM RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRs

1b. EX/MEM.RegWrite = 1

and EX./MEM RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRt

MEM Hazard Detection

2a. MEM/WB.RegWrite = 1

and MEM/WB.RegisterRd ≠ $zero

and MEM/WB.RegisterRd = ID/EX.RegisterRs

and not ( EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRs )

2b. MEM/WB.RegWrite = 1

and MEM/WB.RegisterRd ≠ $zero

and MEM/WB.RegisterRd = ID/EX.RegisterRt

and not (EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRt )

These conditions are used for Forwarding

 8. Implement the Register File and copy the image of Verilog code of Register file
unit here.
Answer:

8. Implement the forwarding unit and copy the image of Verilog code of forwarding
 unit here.

Answer:

9. Implement a complete processor in Verilog (using all the Datapath blocks). Copy
the image of Verilog code of the processor here. (Use comments to describe your
Verilog implementation)

Answer:
10. Test the processor design by generating the appropriate clock and reset. Copy
the image of your testbench code here.

Answer:
11. Verify if the register file and data memory is getting updated according to the set
of instructions (mentioned earlier).

Copy verified Register file waveform here (show only the Registers that get
updated, CLK, and RESET), along with the Data Memory location getting
updated:
12. What is the total number of cycles needed to issue the program given above on
the pipelined MIPS Processor? What is the CPI of the program?

Answer: 9

CPI=9/5=1.8

13. Make a diagram showing the clock by clock execution of each instruction,
indicating stalling, forwarding etc wherever necessary.

Answer:I did diagram without stalling

15. Your design synthesisable? Which target FPGA was used for synthesis?

Answer:my design is synthesizable

16. Provide the synthesis report in tabular form (resources consumed)?

Answer:
Unrelated Questions

What were the problems you faced during the implementation of the processor?

Answer: there were some problems related to write back, data hazard and alu in the processor
 Did you implement the processor on your own? If you took help from someone whose help
did you take? Which part of the design did you take help for?

Answer: Yes,I implemented processor on my own

Honor Code Declaration by student:

● My answers to the above questions are my own work.

● I have not shared the codes/answers written by me with any other students. (I might have
helped clear doubts of other students).
● I have not copied other’s code/answers to improve my results. (I might have got some
doubts cleared from other students).

Name: Nivedita Acharyya Date: 4-04-2023

ID No.: 2022H1400070G