Ade9000 Ug 1098

ADE9000 Technical Reference Manual
UG-1098
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Functionality and Features of the ADE9000 High Performance, Multiphase Energy

and Power Quality Monitoring IC
SCOPE
This reference manual provides a detailed description of the ADE9000 functionality and features. This document must be used in
conjunction with the ADE9000 data sheet.
FUNCTIONAL BLOCK DIAGRAM
1.25V ADE9000
REFERENCE
DIGITAL BLOCK
IAP CLKIN
PGA ADC CLKOUT

IAN SINC + DECIMATION
RESET
VAP
DSP ENGINE
PGA ADC
VAN
TOTAL AND FUNDAMENTAL:
EVENT IRQ0
{ IRMS, VRMS, ACTIVE,
IBP INTERRUPTS
REACTIVE, IRQ1
APPARENT POWER
IBN AND ENERGY }
VTHD, ITHD, FREQUENCY,
PHASE ANGLE,
VBP POWER FACTOR, CF1
VPEAK, IPEAK, DIP,
PGA ADC SWELL, OVERCURRENT,
VBN FAST RMS, DIGITAL TO CF2
10/12 CYCLE RMS, FREQUENCY
PHASE SEQ ERROR CONVERSION
(CF) CF3/ZX
ICP
PGA ADC CF4/EVENT/DREADY
ICN DIGITAL TO
FREQUENCY
CONVERSION (CF)
VCP
PGA ADC USER ACCESSIBLE
VCN REGISTERS CS
SPI SCLK
INP RESAMPLING INTERFACE MISO
ENGINE
PGA ADC MOSI
INN
TEMP SAR
SENSOR WAVEFFORM BUFFER
(32ksps, 8ksps ADC SAMPLES
15523-001
GND OR RESAMPLED DATA)
Figure 1.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 86
UG-1098 ADE9000 Technical Reference Manual
TABLE OF CONTENTS
Scope .................................................................................................. 1 Additional Communication Verification Registers ............... 34
Functional Block Diagram .............................................................. 1 CRC of Configuration Registers............................................... 35
Revision History ............................................................................... 2 Waveform Buffer ............................................................................ 36
Analog-to-Digital Converter (ADC) ............................................. 3 Fixed Data Rate Waveforms ...................................................... 36
Overview........................................................................................ 3 Fixed Data Rate Waveforms Filling and Trigger-Based
Analog Input Configuration ....................................................... 3 Modes........................................................................................... 37
Internal RF Immunity Filter ....................................................... 4 Resampled Waveforms .............................................................. 39
Modes of Operation ..................................................................... 4 Configuring the Waveform Buffer ........................................... 40
Output Data Rates and Format................................................... 4 Burst Read Waveform Buffer Samples from SPI .................... 40
Voltage Reference ......................................................................... 5 Interrupts/EVENT ......................................................................... 43
Crystal Oscillator/External Clock .................................................. 6 Interrupts (IRQ0 and IRQ1) ..................................................... 43
Power Management .......................................................................... 7 EVENT......................................................................................... 43

Power Modes ................................................................................. 7 Status Bits in Additional Registers ........................................... 43
Power-On Sequence ..................................................................... 7 Applying the ADE9000 to Different Metering
Brownout Detection ..................................................................... 8 Configurations ................................................................................ 44
Reset ............................................................................................... 8 Non-Blondel Compliant Meters ............................................... 45
Changing Power Modes............................................................... 8 Applying the ADE9000 to a 4-Wire Wye Service .................. 46
Measurements ................................................................................... 9 Applying the ADE9000 to a 3-Wire Delta Service ................. 47
Current Channel Measurement Update Rates ......................... 9 Applying the ADE9000 to a Non-Blondel Compliant 4-Wire
Wye Service ................................................................................. 48
Full-Scale Codes ......................................................................... 13
Applying the ADE9000 to a Non-Blondel Compliant 4-Wire
Power and Filter-Based RMS Measurement Algorithms ...... 13 Delta Service ............................................................................... 48
Energy Measurements Overview ............................................. 17 ADE9000 Service Type Summary ............................................ 48
Energy Accumulation ................................................................ 18 Quick Start....................................................................................... 50
Power Accumulation .................................................................. 23 Calibration ....................................................................................... 51
Power Quality Measurements ................................................... 24 System Parameters ..................................................................... 51
Temperature ................................................................................ 31 RMS Calibration ......................................................................... 51
Accessing On-Chip Data ............................................................... 32 Phase Calibration ....................................................................... 51
SPI Protocol Overview............................................................... 32 Power Calibration....................................................................... 52
SPI Write ...................................................................................... 33 Conversion Constants................................................................ 52
SPI Read ....................................................................................... 33 Register Information ...................................................................... 53
SPI Burst Read ............................................................................ 33 Register Details ........................................................................... 65
SPI Protocol CRC ....................................................................... 34
REVISION HISTORY
3/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 86
ADE9000 Technical Reference Manual UG-1098
ANALOG-TO-DIGITAL CONVERTER (ADC)

OVERVIEW xP INPUT PIN
+0.6V
The ADE9000 incorporates seven independent, second-order,
Σ-Δ ADCs that sample simultaneously. Each ADC is 24 bits and +0.1V
supports fully differential and pseudo differential inputs, which
can go above and below ground. The ADE9000 includes a low –0.4V
noise, low drift, internal band gap reference. Set the EXT_REF xM INPUT PIN
bit in the CONFIG1 register if using an external voltage +0.6V
reference. Each ADC contains a programmable gain amplifier

+0.1V
which allows a gain of 1, 2, or 4.
ANALOG INPUT CONFIGURATION –0.4V
There is no internal buffering; the impedance of the ADE9000 CHANNEL (x_PCF) WAVEFORM
depends on the programmable gain selected. DATA RANGE WITH x_GAIN = 1
0x0471 44AD =
Fully Differential Inputs +74,532,013
0
The input signals on the IAP, IAN, IBP, IBN, ICP, ICN, VAP,
VAN, VBP, VBN, VCP, and VCN pins must not exceed 0.6 V. 0xFB8E BB53 =
The differential full-scale input range of the ADCs is ±1 V peak –74,532,013
(0.707 V rms).
15523-002
NOTES
1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
AFTER GAIN AND PHASE COMPENSATION.
Figure 2 and Figure 3 show two common types of input signals
for an energy monitoring application. Figure 2 shows the Figure 2. Maximum Input Signal with Differential Antiphase Input with
Common Mode Voltage = 0.1 V, Gain = 1
maximum input allowed with differential antiphase signals.
A current transformer with center tapped burden resistor
generates differential, antiphase signals. Figure 3 shows the xP INPUT PIN
maximum input signal with pseudo differential signals, similar +0.6V
to those obtained when sensing the mains voltage signal through

+0.1V
a resistive divider or using a Rogowski coil current sensor.
The following conditions must be met for the input signals with –0.4V
gain = 1:
xM INPUT PIN
• |IAP, IAN, IBP, IBN, ICP,ICN, VAP, VAN, VBP, VBN, VCP,
and VCN| ≤ +0.6 V peak +0.1V
• |IxP − IxN| ≤ +1 V peak, |VxP − VxN| ≤ +1 V peak CHANNEL (x_PCF) WAVEFORM

DATA RANGE WITH x_GAIN = 2
Each ADC contains a programmable gain amplifier which allows 0x0471 44AD =
a gain of 1, 2, or 4. The ADC produces full-scale output codes +74,532,013
with an input of ±1 V. With a gain of 1, this full-scale output 0
corresponds to a differential antiphase input of 0.707 V rms,

0xFB8E BB53 =
as shown in Figure 2. At a gain of 2, full-scale output codes are –74,532,013
produced with an input of 0.353 V rms, as shown in Figure 3. At

15523-003
NOTES
1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
gain of 4, full-scale output codes are generated with a 0.1765 V rms AFTER GAIN AND PHASE COMPENSATION.
input signal. Note that the voltages on the xP and xN pins must Figure 3. Maximum Input Signal with Pseudo Differential Input with
be within ±0.6 V, as specified in the data sheet. Common Mode Voltage = 0.1 V, Gain = 2
Write the x_GAIN bits in the PGA_GAIN register to configure

the gain for each channel.
Interfacing to Current and Voltage Sensors MODES OF OPERATION
Figure 4 and Figure 6 show the recommended circuits to Each ADC has two modes of operation: normal mode and
connect to current transformer sand Rogowski coil current disabled mode.
sensors. Figure 5 shows the interface circuit to measure the
In the normal mode of operation, ADCs are turned on and
mains voltage.
sample continuously. The CHNL_DIS register can be used to
The antialiasing filter corner is chosen around 7 kHz to provide disable the ADCs individually.
sufficient attenuation of out of band signals near the modulator
There are 2 different power modes available in the ADE9000
clock frequency. The same RC filter corner is used on voltage
(see the Power Modes section). All ADCs are turned on in
channels as well, to avoid phase errors between current and
PSM0 power mode. In PSM3 mode, all ADCs are disabled and
voltage signals. Note that the Rogowski coil input network has a
cannot be turned on.
second-order antialias filter to further reduce out of band noise
because the Rogowski sensor has a 1/f response. Table 1. ADC Operation in PSMx Power Modes
I 1kΩ PSMx Power Mode ADC Mode of Operation
IxP
PSM0 Normal (on)
Rb1 22nF
PSM3 Disabled (always off )
AGND AGND
Rb2 22nF 0.707Vrms max
CT
OUTPUT DATA RATES AND FORMAT
15523-004
IxN
1kΩ
When a conversion has been completed, the DREADY bit of the
Figure 4. Application Circuit with Current Transformer Current Sensor STATUS0 register is set to 1. If the CF4_CFG[3:2] bits in the
1MΩ CONFIG1 register are equal to 11, the CF4/EVENT/DREADY
PHASE VxP
pin corresponds to DREADY and pulses high to indicate when
seven new ADC results are ready.
1kΩ 22nF
240V rms 0.240V rms In the ADE9000, the modulator sampling rate (MODCLK) is
fixed at 2.048 MHz (CLKIN/12 = 24.576/12). The output data
NEUTRAL VxN
AGND
rate of the sinc filter is MODCLK/64, whereas the low-pass
filter/decimator stage yields an output rate 4 times slower than
1kΩ 22nF
the sinc filter output rate. Figure 7 shows the digital filtering
that takes the 2.048 MHz ADC samples and creates waveform
15523-005
information at a decimated rate of 32 kHz or 8 kHz.

AGND
Figure 5. Application Circuit with Voltage Sensed Through Resistor Divider (×7 CHANNELS)
ANALOG
100Ω 1kΩ INPUT
DIGITAL
MULTIBIT IIR LPF/
IxP Σ-Δ × 7 SINC4 DECIMATOR
22nF 22nF
2.048MHz 32kHz 8kHz

0.3535V rms DIGITAL
WAVEFORM
100Ω 1kΩ
IxN
WAVEFORM
15523-006
22nF 22nF 15523-007

BUFFER
Figure 6. Application Circuit with Rogowski Coil Current Sensor Figure 7. Datapath Following ADC Stage
INTERNAL RF IMMUNITY FILTER The output data rates are summarized in Table 2.
Energy metering applications require the meter to be immune
Table 2. Output Data Rates
to external radio frequency fields of 30 V/m, from 80 MHz up
Parameter Output Data Rate
to 10 GHz, according to IEC 61000-4-3. The ADE9000 has
CLKIN Frequency 24.576 MHz
internal antialiasing filters to improve performance in this
ADC Modulator Clock, MODCLK 2.048 MHz
testing because it is difficult to filter these signals externally.
SINC Output Data Rate, SINC_ODR 32 kHz
The second-order, internal low-pass filter (LPF) has a corner
Low-Pass Filter Output Data Rate 8 kHz
frequency of 10 MHz. Note that external antialias filters are
3 dB Bandwidth 3.2 kHz
required to attenuate frequencies above 7 kHz, as shown in the
Interfacing to Current and Voltage Sensors section.
The ADC data in the waveform buffer is stored as 32-bit data by VOLTAGE REFERENCE
shifting left by 4 bits and sign extending, as shown in Table 3. The ADE9000 supports a 1.25 V internal reference. An external
Table 3. 32-Bit ADC Data Format reference can be connected between the REFIN and REFGND
Bits[31:28] Bits[27:4] Bits[3:0] pins. When using an external voltage reference, set the
EXT_REF bit of the CONFIG1 register, which disables the
SE ADC_DATA[23:0] 0000
internal reference buffer.
The expected output code in the waveform buffer from the sinc
filter when input is at 1 V peak is 67,107,786 (decimal). The
expected output code in the waveform buffer from the decimator
filter when input is at 1 V peak is 74,518,668. See the Waveform
Buffer section for more information.
CRYSTAL OSCILLATOR/EXTERNAL CLOCK

The ADE9000 contains a crystal oscillator. Alternatively, a The gain of the crystal oscillator circuit in the ADE9000, gm,
digital clock signal can be applied at the CLKIN pin of the provided in the data sheet is more than 5 times gmCRITICAL;
ADE9000. therefore, there is sufficient margin to start up this crystal.
When a crystal is used as the clock source for the ADE9000, Load Capacitor Calculation
attach the crystal and the ceramic capacitors, with capacitances Crystal manufacturers specify the combined load capacitance
of CL1 and CL2, as shown in Figure 8. It is not recommended to across the crystal, CL. The capacitances in Figure 8 can be
attach an external feedback resistor in parallel to the crystal. described as follows:
When a digital clock signal is applied at the CLKIN pin, the • CP1 and CP2: parasitic capacitances on the clock pins
inverted output is available at the CLKOUT pin. This output is formed due to printed circuit board (PCB) traces.
not buffered internally and cannot be used to drive any other
• Cin1 and Cin2: internal capacitances of the CLKIN and
external devices directly. Note that CLKOUT is available in
CLKOUT pins respectively.
PSM0 operating mode only.
• CL1 and CL2: selected load capacitors to get the correct
2.5MΩ combined CL for the crystal.
2.5kΩ 1.75kΩ
The internal pin capacitances, Cin1 and Cin2, are 4 pF each, as
shown in the data sheet. To find the values of CP1 and CP2,
CIN1 CIN2 measure the capacitance on each of the clock pins of the PCB,
CLKIN 29 30 CLKOUT CLKIN and CLKOUT, respectively, with respect to the AGND
pin. If the measurement is done after soldering the IC to the
PCB, subtract out the 4 pF internal capacitance of the clock pins
CP1 CL1 24.576MHz CL2 CP2 to find the actual value of parasitic capacitance on each of the
crystal pins.
15523-008
To select the appropriate capacitance value for the ceramic

Figure 8. Crystal Application Circuit capacitors, calculate CL1 and CL2 from the following equation:
Crystal Selection CL = [(CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2)]/(CL1 +
The transconductance of the crystal oscillator circuit in the CP1 + CIN1 + CL2 + CP2 + CIN2) (1)
ADE9000, gm, is provided in the data sheet. It is recommended Select CL1 and CL2 such that the total capacitance on each clock
to have 3 to 5 times more gm than the calculated gmCRITICAL for pins is
the crystal.
CL1 + CP1 + CIN1 = CL2 + CP2 + CIN2 (2)
The following equation shows how to calculate the gmCRITICAL
Using Equation 1 and Equation 2, the values of CL1 and CL2 can
for the crystal from information given in the crystal data sheet:
be calculated.
gmCRITICAL = 4 × ESRMAX × 1000 × (2 × π × fCLK(Hz))2 × (C0 + CL)2
Load Capacitor Calculation Example
where:
If a crystal with load capacitance specification of 8 pF is selected
gmCRITICAL is the minimum gain required to start the crystal,
and the measured parasitic capacitances from the PCB traces
expressed in mA/V.
are CP1 = CP2 = 2 pF, Equation 1 implies that
ESRMAX is the maximum ESR, expressed in ohms.
fCLK is 24.576 MHz, expressed in Hz as 24.576 × 106. CL = [(CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2)]/(CL1 +
C0 is the maximum shunt capacitance, expressed in farads. CP1 + CIN1 + CL2 + CP2 + CIN2)
CL is the load capacitance, expressed in farads. 8 pF = [(CL1 + 2 pF + 4 pF) × (CL2 + 2 pF + 4 pF)]/(CL1 +
Crystals with low ESR and smaller load capacitance have a 2 pF + 4 pF + CL2 + 2 pF + 4 pF)
lower gmCRITICAL and are easier to drive. Assuming that CL1 = CL2, to satisfy Equation 2,
The ADE9000 evaluation board uses a crystal manufactured by 8 pF = [(CL1 + 6 pF) × (CL1 + 6 pF)]/(CL1 + 6 pF + CL1 + 6 pF)
Abracon (Part Number ABLS-24.576MHZ-8-L4Q-F-T), which
8 pF = [(CL1 + 6 pF) × (CL1 + 6 pF)]/[2 × (CL1 + 6 pF)]
has a maximum ESR of 40 Ω, load capacitance of 8 pF, and
maximum shunt capacitance of 7 pF, which results in a gmCRITICAL 8 pF = (CL1 + 6 pF)/2
of 0.86 mA/V: Therefore, CL1 = CL2 = 10 pF.
gmCRITICAL = 4 × ESRMAX × 1000 × (2 × π × fCLK(Hz))2 × (C0 + CL)2 Based on this example, 10 pF ceramic capacitors are selected for
gmCRITICAL = 4 × 40 × 1000 × (2 × π × 24.576 × 106)2 × (7 × CL1 and CL2.
10−12 + 8 × 10−12)2 = 0.86
POWER MANAGEMENT
POWER MODES potentials (VDD between 2.97 V and 3.6 V, AVDD at 1.9 V, and
The ADE9000 offers two operating modes, PSM0 and PSM3. DVDD at 1.7 V). After this timer has elapsed, the crystal
The entry into the power modes is controlled by the PM1 and oscillator is started.
PM0 pins. These pins are checked continuously to determine The RSTDONE interrupt is triggered 26 ms later, bringing the
which operating mode to enter. If it is desired to place the IRQ1 pin low and setting the RSTDONE bit in the STATUS1
ADE9000 into a low power reset state, PSM3 can be used. register. The RSTDONE bit being set indicates to the user that
POWER-ON SEQUENCE the ADE9000 has finished its power-up sequence. The user can
now configure the IC via the serial peripheral interface (SPI).
After power is applied to the VDD pin of the ADE9000 IC, the After configuring the device, write the RUN register to start the
device checks the state of the PM0 and PM1 pins to check the DSP so that it starts making measurements. Note that registers
power supply mode (see the Power Modes section for more from Address 0x000 through Address 0x0FF and Address 0x400
information). If in PSM0 mode (PM1 and PM0 = 00 or 01) and through Address 0x5FF are restored to their default values
the RESET pin is high, the AVDD and DVDD low dropout during power-on. Registers from Address 0x200 through
regulators (LDOs) are turned on when VDD reaches 2.4 V to Address 0x3FF are cleared within 500 μs from when the RUN
2.6 V. If the RESET pin is low, the AVDD and DVDD LDOs are register value changes from 0x0000 to 0x0001. Also note that
not turned on. Note that there is a clamp that limits the current the waveform buffer, Address 0x800 through Address 0xFFF, is
used to charge the AVDD and DVDD LDOs to 17 mA per LDO. not cleared after reset.
When AVDD and DVDD are both above 1.3 V to 1.5 V and In PSM3 mode, the AVDD and DVDD LDOs are not turned
VDD is above 2.4 V to 2.6 V, a 20 ms timer is started to allow on. The RSTDONE interrupt does not occur, and the SPI port is
additional time for the supplies to come to their normal not available
VDD
2.97V TO 3.63V
ADE9000
VOLTAGE (V)
2.4V TO 2.6V
1.9V AVDD
1.7V DVDD
1.3 TO 1.5V VREF
0.5ms 20ms ~26ms

HOST CONFIGURES
IC VIA SPI AND THEN
WRITES RUN
15523-009
POWER APPLIED AVDD, DVDD POR TIMER CRYSTAL RSTDONE REGISTER TO START
TO IC LDO TURNED TURNED ON OSCILLATOR INTERRUPT MEASUREMENTS
IN PSM0 ON STARTS TRIGGERED
Figure 9. ADE9000 Power-On Sequence for PSM0
Table 4. Power Modes (PSM0 and PSM3)

PSMx Power Mode Description PM1 Pin PM0 Pin Functions Available SPI Available?
PSM0 Normal mode 0 0 or 1 All functions Yes
PSM3 Idle 1 1 None No
BROWNOUT DETECTION that require putting the ADE9000 into a low power reset state,
Power-on reset (POR) circuits monitor the VDD, AVDD, and it is recommended to use PSM3, which consumes roughly 2 µA,
DVDD supplies. If AVDD or DVDD drops below 1.3 V to 1.5 V, or instead of holding the IC in reset with the RESET pin low, which
VDD drops below 2.4 V to 2.6 V, the IC is held in reset and the consumes 100 µA (see the data sheet for the exact current
power-on sequence begins again, waiting until AVDD and DVDD consumption).
are above 1.3 V to 1.5 V and VDD is above 2.4 V to 2.6 V before CHANGING POWER MODES
starting the 20 ms POR timer. A RSTDONE interrupt on IRQ1
The state of the PM1 and PM0 pins is continuously monitored.
indicates when the ADE9000 can be reinitialized via the SPI. If the power mode changes from PSM0 to PSM3 (PM1 and
RESET PM0 = 11) for 1 µs, the AVDD and DVDD LDOs are turned off.
If the RESET pin goes low for 1 µs or the SWRST bit is set in the When the power mode switches back to PSM0, the power-on
sequence resumes from the point where the AVDD and DVDD
CONFIG1 register to initiate a software reset, the AVDD and
LDOs are turned on.
DVDD LDOs are turned off. The power-on sequence resumes
from the point where the AVDD and DVDD LDOs are turned on
(see the Power-On Sequence section for details). For applications
MEASUREMENTS
CURRENT CHANNEL MEASUREMENT UPDATE The neutral current channel does not offer a zero-crossing output
RATES or angle measurements. To calibrate the phase of the neutral
current NI_PCF signal, direct the neutral current ADC output
Table 5 indicates the registers that hold current channel
to, for example, the Phase B digital current channel and check
measurements and the rate at which they update.
how its angles correspond to Phase A by writing IA_DIN = 111.
Table 5. Current Channel Measurement Update Rates IA MODULATOR IA DIGITAL DATAPATH
IA_MOD
Register Update IB_MOD
000
Name Description Rate REFERENCE

IC_MOD
001
010
AI_SINC_DAT IA sinc4 filter output 32 ksps Σ-Δ
IN_MOD
011
VIN VA_MOD
BI_SINC_DAT IB sinc4 filter output 32 ksps MODULATOR
VB_MOD
100
101
CI_SINC_DAT IC sinc4 filter output 32 ksps VC_MOD 110
IA_MOD 111
NI_SINC_DAT IN sinc4 filter output 32 ksps
15523-010
AI_LPF_DAT IA sinc4 + IIR LPF filter output fDSP = 8 ksps AI_SINC_DAT AI_LPF_DAT
IA_DIN[2:0]
BI_LPF_DAT IB sinc4 + IIR LPF filter output fDSP = 8 ksps
CI_LPF_DAT IC sinc4 + IIR LPF filter output fDSP = 8 ksps Figure 10. ADC_REDIRECT Modulator to Digital Datapath Multiplexing
NI_LPF_DAT IN sinc4 + IIR LPF filter output fDSP = 8 ksps Current Channel Gain, xIGAIN
AI_PCF Instantaneous current on IA fDSP = 8 ksps
There are many sources of gain error in an energy metering
BI_PCF Instantaneous current on IB fDSP = 8 ksps
system. The current sensor, including current transformer
CI_PCF Instantaneous current on IC fDSP = 8 ksps
burden resistors, may have some error. There is part to part gain
NI_PCF Instantaneous current on IN fDSP = 8 ksps
error in the ADE9000 device itself, and the voltage reference
AIRMS Filtered-based total rms of IA fDSP = 8 ksps
may have some variation (see the data sheet for the device
BIRMS Filtered-based total rms of IB fDSP = 8 ksps specifications).
CIRMS Filtered-based total rms of IC fDSP = 8 ksps
NIRMS Filtered-based total rms of IN fDSP = 8 ksps The ADE9000 provides a current gain calibration register so
ISUMRMS Filtered rms of vector sum (AI_PCF + fDSP = 8 ksps that each metering device has the same current channel scaling.
BI_PCF + CI_PCF ± NI_PCF); see the The current channel gain varies with xIGAIN as shown in the
Neutral Current RMS, Vector Current following equation:
Sum section
xIGAIN 
Current Channel Gain = 1 +
IPEAK Peak current channel sample; see the fDSP = 8 ksps
Peak Detection section 
 2 27 
ANGLx_xxx Voltage to current or current to CLKIN/24 =
current phase angle; see the Angle 1024 ksps Use this equation to calculate the xIGAIN value for a given
Measurement section current channel gain:
xIGAIN = ROUND((Current Channel Gain − 1) × 227
ADC_REDIRECT Multiplexer
The current channel gain can be positive or negative.
The ADE9000 provides a multiplexer that allows any ADC
For example, to gain the current channel up by 10% to 1.1,
output to be redirected to any digital processing datapath.
xIGAIN = ROUND((1.1 − 1) × 227 = 13421773 =
By default, each modulator is mapped to its corresponding
0x00CC_CCCD
datapath. For example, the IAP and IAN pins go into the IA
modulator, which is mapped to the IA digital processing To gain it down by 10% to 0.9,
datapath. Write to the ADC_REDIRECT register to change the xIGAIN = ROUND((0.9 − 1) × 227 = −1 × 107 =
ADC to digital channel mapping. 0xFF33_3333
The redirection can be useful to simplify layout, depending on if It is also possible to use the current channel gain register to
the ADE9000 is on the top or bottom of the PCB, by redirecting change the sign of the current channel, which can be useful if
the IA ADC output to the IC digital datapath and the IC ADC the current sensor was installed backwards. To compensate for
output to the IA digital datapath. To redirect the IA and IC this, use current channel gain = −1.
ADC outputs, write IA_DIN = 010 and IC_DIN = 000 in the
xIGAIN = ROUND((−1 − 1) × 227 = −268435456 =
ADC_REDIRECT register.
0xF000_0000
Alternatively, the VA voltage channel output can be used for all
If the multipoint phase and gain feature is used, it is recommended
three datapaths by writing VB_DIN = 101 and VC_DIN = 101
to use the xIGAIN for the main correction, done at the nominal
in the ADC_REDIRECT register.
current for the meter (see the Multipoint Phase/Gain Calibration
section for more information).
Note that for a given phase, The ADE9000 high-pass filter on the current and voltage
|Current Channel Gain × Voltage Channel Gain × channels is enabled by default. It can be disabled by writing the
Power Gain| ≤ 3.75 DISPHPF bit in the CONFIG0 register equal to 1.
IB Calculation Using ICONSEL It is recommended to leave the high-pass filter enabled to

achieve the metering performance listed in the specifications
Write the ICONSEL bit in ACCMODE to calculate IB = −IA − IC.
in the data sheet.
This setting can help save the cost of a current transformer in some
3-wire delta configurations. See the Applying the ADE9000 to a For some applications, it is desirable to increase the high-pass
3-Wire Delta Service section for more information. filter corner, such as to improve performance when a Rogowski
coil current sensor is used.
High-Pass Filter
The high-pass filter corner is selectable using the HPF_CRN bits
A high-pass filter is provided to remove dc offsets for accurate
in the CONFIG2 register (see Table 6).
rms and energy measurements.
Table 6. HPF Corner Gain with 50 Hz Input Signal

HPF_CRN f−3 dB (Hz) HPF_GAIN Settling Time to 1% for DC Step (sec) Settling Time to 0.1% for DC Step (sec)
0 77.4 0.537 0.009 0.013
1 39.3 0.790 0.018 0.027
2 19.8 0.935 0.037 0.055
3 9.9 0.984 0.073 0.110
4 5.0 0.997 0.147 0.221
5 2.5 0.999 0.294 0.442
6 (default) 1.25 1.001 0.589 0.883
7 0.625 1.001 1.179 1.768
Digital Integrator To achieve this calibration range, the voltage channel is delayed
A digital integrator is included to allow easy interfacing to di/dt by one 8 ksps sample, 2.25° at 50 Hz:
current sensors, also known as Rogowski coils. The di/dt sensor f 
output increases by 20 dB/decade over the frequency range. Voltage Channel Delay ° =  LINE × 360° 
To compensate for this increase, the digital integrator applies  f DSP 
−20 dB/decade gain with a phase shift of approximately −90°. 50
Voltage Channel Delay ° =  × 360°  = 2.25°
A second-order antialiasing filter is required to avoid noise  8000 
aliasing back in the band of interest when the ADC is sampling. The current channel is then delayed by a digital filter, according
To enable the digital integrator on the IA, IB, and IC channels, to the value programmed into the xPHCALx register. The
set the INTEN bit in the CONFIG0 register. To enable the resulting phase correction depends on the value in the
digital integrator on the neutral current, IN channel, set the xPHCALx register. The following equation provides the phase
ININTEN bit in the CONFIG0 register. correction between the input current and voltage after the
combined voltage and current delays. In this formula,
Figure 11 and Figure 12 show the magnitude and phase
PhaseCorrection° is positive to correct a current that lags the
response of the ADE9000 digital integrator with the default
voltage, and PhaseCorrection° is negative to correct a situation
DICOEFF = 0xFFFFE000.
where the current leads the voltage, such as occurs with a
100
MAGNITUDE (dB)
50 current transformer:
0
 − sin ω 
Phase Correction° = arctan 
–50
–100  xPHCALx × 2 −27 + cos ω 
–150  
10–2 10–1 100 101 102 103
−27
FREQUENCY (Hz)  − xPHCALx × 2 × sin ω 
0
− arctan 
PHASE (Degrees)
–10
 −27 
–20
–30  1 + xPHCALx × 2 + cos ω 
–40
–50
–60 where ω = 2 × π × fLINE/fDSP.
–70
–80
The xPHCALx register value can be calculated from the desired
15523-011
–90
0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz) phase correction according to this equation:
Figure 11. Digital Integrator Magnitude and Phase Response with
DICOEFF = 0xFFFFE000  sin(ϕ − ω) + sin ω  27
xPHCALx =  ×2
 sin(2 × ω − ϕ) 
 
MAGNITUDE (dB)
4
2
0 For example, if fLINE = 50 Hz, fDSP = 8 kHz, and the current leads
–2 the voltage by 0.1 degrees, Phase Correction° = −0.1°. Write
–4
xPHCALx = 0xFFD3_7760 to correct for this.
–6
35 40 45 50 55 60 65 70 75 80 85 90
FREQUENCY (Hz) ω = 2 × π × 50/8000 = 0.03927
–89.94
 sin(RADIANS(−0.1) − 0.03927) + sin 0.03927  27
PHASE (Degrees)
–89.86 xPHCALx =  ×2

 sin(2 × 0.03927 − RADIANS(−0.1)) 
–89.88  
–89.90
= −2918553 = 0 xFFD3 _ 7767
–89.92
INPUT
15523-012
–89.94
35 40 45 50 55 60 65 70 75 80 85 90 VOLTAGE
INPUT
FREQUENCY (Hz) CURRENT OUTPUT
VOLTAGE
Figure 12. Digital Integrator Magnitude and Phase Response from CURRENT
TRANSFORMER
40 Hz to 80 Hz with DICOEFF = 0xFFFFE000 SENSOR:
CURRENT LEADS OUTPUT
If the integrator is enabled, set DICOEFF = 0xFFFFE000. VOLTAGE CURRENT
Phase Compensation
DELAY I
The ADE9000 phase compensation uses a digital filter to BY UP TO
17.25°
achieve a phase adjustment of ±0.001°. This high resolution DELAY V BY
ONE SAMPLE
improves the total active energy and reactive energy 2.25° AT 50Hz
performance at low power factors.
The phase calibration range is −15° to +2.25° at 50 Hz.
15523-013
I LEADS V BY UP TO 15°
PHASE COMPENSATION = –15° ADE9000
Figure 13. Phase Compensation Example for Current Transformer,
where the Current Leads the Voltage
INPUT xIGAIN4
GAIN, xPHCAL4
VOLTAGE PHASE
INPUT OUTPUT CORRECTION
xIGAIN3 X
xIGAIN2 xPHCAL3
CURRENT VOLTAGE xIGAIN1 xPHCAL2
CURRENT LAGS xIGAIN0 xPHCAL1 X
VOLTAGE xPHCAL0 X
X
X
OUTPUT
CURRENT
15523-015
MTTHR_L0 MTTHR_L1 , MTTHR_L2 , MTTHR_L3 , MTTHR_L4 , MTTHR_H4 =
=0 MTTHR_H0 MTTHR_H1 MTTHR_H2 MTTHR_H3 FULL SCALE
REGION0 REGION1 REGION2 REGION3 REGION4
DELAY I Figure 15. Multipoint Phase and Gain Calibration

BY 0°
DELAY V BY The MTTHR_Lx and MTTHR_Hx registers set up the ranges
ONE SAMPLE
2.25° AT 50Hz in which to apply each set of corrections, allowing hysteresis.
The decision of which coefficients to apply is done according to
the following rules:
15523-014
I LAGS V BY UP TO 2.25°
PHASE CORRECTION = +2.25° ADE9000 If xIRMS >MTTHR_H[current_region]
Figure 14. Phase Compensation Example where Current Lags Voltage If current_region <=3
Using the previous equations, it can be seen that at 60 Hz, the Current_region++;
voltage channel delay is 2.7°: Else If xIRMS >MTTHR_L[current_region]
60 If current_region >=1
Voltage Channel Delay ° =  × 360°  = 2.7°
 8000  current_region--;
This leads to a phase calibration range of −15° to +2.7° at 60 Hz. xIGAIN = xIGAIN[current_region];
xPHCAL = xPHCAL[current_region];
Multipoint Phase/Gain Calibration
The ADE9000 allows the current channel gain and phase For example, if AIRMS goes above MTTHR_H2, the phase and
compensation to vary as a function of the calculated input gain correction is set to AIGAIN3 and APHCAL3, respectively.
current rms amplitude in xIRMS. This feature corrects for the Then, if AIRMS goes below MTTHR_L3, the phase and gain
nonlinearities of current transformer sensors to achieve very correction is set to AIGAIN2 and APHCAL2, respectively.
high meter accuracy, for example in Class 0.2 meters. For proper operation, the value of the registers must be
Multipoint Gain and Phase MTTHR_L[0] < MTTHR_L[1] < MTTHR_H[0] <
MTTHR_L[2] < MTTHR_H[1] < MTTHR_L[3] <
There is a current channel gain, xIGAIN, that is applied regardless
MTTHR_H[2] < MTTHR_L[4] < MTTHR_H[3] <
of the xIRMS input signal level. This gain compensates for the
MTTHR_H[4].
nominal gain error of the current channel, including the current
transformer and burden resistors. If multipoint phase and gain Multipoint phase and gain calibration is disabled by default. To
compensation is enabled, an additional current gain value is enable it, set the MTEN bit in the CONFIG0 register.
applied in based on the xIRMS value to compensate for the Single Point Gain and Phase
current transformer gain shift over input signal amplitude.
When multipoint phase and gain calibration is disabled, single-
If multipoint gain and phase compensation is enabled, with point phase and gain calibration is allowed.
MTEN = 1, an additional gain factor, xIGAIN0 through xIGAIN5,
In this case, the xIGAIN register is applied. No additional
is applied based on the xIRMS current rms amplitude and the
current channel gain is applied based on xIRMS amplitude.
MTTHR_Lx and MTTHR_Hx register values, as shown in
Figure 15. When multipoint phase and gain calibration is disabled, the
xPHCAL0 phase compensation is always applied regardless of
Similarly, for the phase compensation, if multipoint phase and
the xIRMS value.
gain compensation is enabled, the applied current channel phase
compensation varies based on the xIRMS input signal level.
Voltage Channel Measurements POWER AND FILTER-BASED RMS MEASUREMENT
Table 7 indicates the registers that hold voltage channel ALGORITHMS
measurements and the rate at which they update. Filter-Based Total RMS
Table 7. Voltage Channel Measurement Update Rates The ADE9000 offers current and voltage rms measurements
Register Name Description Update Rate
that are calculated by squaring the input signal, low-pass
filtering, and then taking the square root of the result.
AV_SINC_DAT VA sinc4 filter output 32 ksps
BV_SINC_DAT VB sinc4 filter output 32 ksps The low-pass filter, LPF2, extracts the rms value, attenuating
CV_SINC_DAT VC sinc4 filter output 32 ksps harmonics of a 50 Hz or 60 Hz fundamental by at least 64 dB so
AV_LPF__DAT VA sinc4 + IIR LPF filter output fDSP = 8 ksps that, at full scale, the variation in the calculated rms value is
BV_LPF__DAT VB sinc4 + IIR LPF filter output fDSP = 8 ksps very small, ±0.064% error. Note that the rms reading variation
CV_LPF__DAT VC sinc4 + IIR LPF filter output fDSP = 8 ksps increases as the input signal gets smaller because the noise in
AV_PCF Instantaneous current on VA fDSP = 8 ksps the measurement increases.
BV_PCF Instantaneous current on VB fDSP = 8 ksps Note that the xRMS register does not read 0 with the xP and xN
CV_PCF Instantaneous current on VC fDSP = 8 ksps inputs shorted together.
AVRMS Filtered-based total rms of VA fDSP = 8 ksps
The filter based rms has a bandwidth of 3.2 kHz
BVRMS Filtered-based total rms of VB fDSP = 8 ksps
CVRMS Filtered-based total rms of VC fDSP = 8 ksps The rms calculations, one for each channel, AIRMS, BIRMS,
VPEAK Peak current channel sample; see fDSP = 8 ksps CIRMS, NIRMS, AVRMS, BVRMS, and CVRMS, are updated
the Peak Detection section every 8 ksps. The ISUMRMS calculation uses the same method
APERIOD Line period measurement on VA fDSP = 8 ksps to calculate ISUMRMS, where ISUM = IA + IB + IC ± IN, and
BPERIOD Line period measurement on VB fDSP = 8 ksps also updates at 8 ksps (see the Neutral Current RMS, Vector
CPERIOD Line period measurement on VB fDSP = 8 ksps Current Sum section for more information).
COM_PERIOD Line period measurement on fDSP = 8 ksps The xRMS value at full scale is 52,702,092 (decimal). The full
combined signal from VA, VB, VC;
see the Combined Voltage Zero- scale is a function of PGA gain.
Crossing section full scale input at PGA GAIN1
ANGLx_xxx Voltage to current or current to CLKIN/24 = full scale =
PGA GAIN
current phase angle; see the 1024 ksps
Angle Measurement section For high performance at small input signals, below 1000:1, it is
recommended to calibrate the offset of this measurement using
Voltage Channel Gain the xRMSOS register. It is recommended to calibrate the offset
The xVGAIN registers can be used to calibrate the voltage at the smallest input signal that requires good performance; do
channel of each phase. The xVGAIN register has the same not calibrate this measurement with zero input signal.
scaling as the xIGAIN register. See the Current Channel Gain, The following equation indicates how the xRMSOS register
xIGAIN section for the equation. value modifies the result in the xRMS register.
FULL-SCALE CODES
xxRMS = xxRMS0 2 + 215 × xxRMSOS
Table 8 gives the expected codes when the ADC inputs are at
full scale with PGA gain set to 1. where xxRMS0 is the initial xRMS register value before offset
calibration.
Table 8. Full-Scale ADC Codes
For example, if the expected the AIRMS at 1000:1 is
Parameter Output Code
52,702,092/1000 = 52,702 (decimal) and the AIRMS register
Sinc4 Output at 32 ksps 67,107,786
reading is 53280 (decimal), the offset calibration register is
Dec Output at 8 ksps 74,518,668
xPCF at 8 ksps 74,532,013 52702 2 − 53280 2
AIRMSOS = = − 1869d = 0 xFFFF8B8
Total IRMS and VRMS 52,702,092 215
Fundamental IRMS and VRMS 52,702,092 Table 9 shows the rms settling time to 99% of full scale for a
Total WATT, VAR, and VA 20,694,066 50 Hz signal.
Fundamental WATT, VAR, and VA 20,694,066
Fast RMS½ 52,702,092 Table 9. RMS Settling Time
10 Cycle RMS/12 Cycle RMS 52,702,092 RMS Settling Time,
Resampled Data 18,196 Configuration FS = 99% (sec)
Integrator On, HPF On, and LPF2 On 0.54
Integrator Off, HPF On, and LPF2 On 0.48
Neutral Current RMS, Vector Current Sum For example, to set ISUMLVL to warn about a vector current
The ADE9000 calculates the neutral current rms from a neutral sum greater than 10,000:1 from full scale, X = 10,000 in the
current sensor input into the INP and INN pins, and stores the previous equation.
result in the NIRMS register. A NIRMSOS register allows offset Total Active Power
calibration of this measurement. The scaling is the same as for Total active power is commonly used for billing purposes. It
the other xIRMS and xIRMSOS registers (see the Filter-Based includes power on the fundamental and on the harmonics.
Total RMS section for more information).
The total active power on each phase is calculated by first
The ADE9000 also calculates the rms of the sum of multiplying the xI_PCF and xV_PCF waveforms. Then the
IA + IB + IC ± IN and stores the result in the ISUMRMS register. result is low-pass filtered, unless the DISAPLPF bit in the
The ISUMRMSOS register allows offset calibration of this CONFIG0 register is equal to 1. Finally, the xPGAIN is applied
measurement. The scaling is the same as for the other xIRMS to perform a gain correction and the xWATTOS value is applied
and xIRMSOS registers (see the Filter-Based Total RMS section to correct the watt offset.
for more information).
Figure 16 shows the relationship between the I and V input
If a neutral current sensor is not used, write the signals and the instantaneous active power and low-pass filtered
ISUM_CFG[1:0] bits in the CONFIG0 register equal to 0, and active power, assuming that I and V are at full scale with only
then ISUMRMS approximates the neutral current from the sum the fundamental is present and a power factor of 1.
of IA, IB, and IC.
If the DISAPLPF bit in the CONFIG0 is equal to 1, xWATT
If the measured neutral current, NI_PCF, deviates from the sum reflects the instantaneous active power; and if it is equal to 0,
of AI_PCF + BI_PCF + CI_PCF current channel waveforms, there xWATT reflects the low-pass filtered active power, in Figure 16,
may be a fault in the system. assuming xPGAIN = 0 and xWATTOS = 0.
To determine how large the mismatch is between the measured INSTANTANEOUS
ACTIVE POWER
neutral current and the measured A, B, and C currents, select
ISUM_CFG[1:0] to 01 or 10 based on the direction of the neutral
current with respect to the other current channel waveforms.
LOW-PASS FILTERED
ACTIVE POWER
Table 10. ISUM Configuration Options
+0.062%
CONFIG0. 20,694,066
–0.062%
ISUM_CFG[1:0] ISUM calculation
00, 11 ISUM = AI_PCF + BI_PCF + CI_PCF
01 ISUM = AI_PCF + BI_PCF + CI_PCF + NI_PCF
10 ISUM = AI_PCF + BI_PCF + CI_PCF − NI_PCF 0
ISUMRMS has the same scaling as xIRMS. Note that if AI_PCF, I, V FUNDAMENTAL
BI_PCF, and CI_PCF are all at full scale and in phase with each INPUT SIGNAL
other, with the ISUM_CFG[1:0] equal to 00 or 11, ISUMRMS is

3 × 52,702,092 = 158,106,276 (decimal). If AI_PCF, BI_PCF,
CI_PCF, and NI_PCF are all at full scale and in phase with each Figure 16. Instantaneous Active Power and Low-Pass Filtered Active Power at
a Power Factor of 1
other, with the ISUM_CFG[1:0] equal to 01, ISUMRMS is
4 × 52,702,092 = 210,808,368 (decimal). The low-pass filter, LPF2, extracts the total active power,
attenuating harmonics of a 50 Hz or 60 Hz fundamental by
To obtain an indication if ISUMRMS exceeds a threshold,
64 dB so that, at full scale, the variation in the low-pass filtered
configure ISUMLVL. Then the MISMTCH bit in STATUS0
active power is very small, ±0.062%.
and associated interrupt indicate if there is a change in the
relationship between ISUMRMS and ISUMLVL. The resulting xWATT signal has an update rate of 8 ksps and a
bandwidth of 3.2 kHz.
Calculate the desired value of ISUMLVL according to the
following equation: The xPGAIN register has the same scaling as the xIGAIN
register. xWATTOS has the same scaling as xWATT. xWATT
xIRMS _ FULL _ SCALE 
ISUMLVL =   can be calibrated using the energy or power registers. When
 X  using the power registers, xWATTOS is calculated using the
where: following equation:
xIRMS_Full_Scale is the nominal xIRMS value with full-scale xWATTOS = xWATTEXPECTED − xWATTMEASURED
inputs, 52,702,092.
X is the desired current level to indicate a MISMTCH error. The xWATT value with full-scale inputs and no gain is
20,694,066. Note that xVAR and VA have the same scaling;
therefore, the same equation can be used for all three offsets.
The variable X is the smallest power level to calibrate. For example, Table 12. Total Reactive Power Settling Time
to calibrate the energy at 10,000 from full scale, X = 10,000 in the Total Reactive Power Settling Time (sec)
previous equation. Configuration FS = 99% FS = 99.90%
1 Integrator On, HPF On, 0.43 0.59
xWATTOS = = 0.05% and LPF2 On
20694066
Integrator Off, HPF On, 0.43 0.59
10,000
and LPF2 On
Then each bit in the xWATTOS register can correct an error of Integrator Off, HPF On, 0.02 0.05
0.05% at 10,000:1. Note that in most applications, the total and LPF2 Off
active power performance with small inputs is sufficient with
xWATTOS at zero. Total Apparent Power
Table 11 shows the settling times for total active power for a Apparent power is generated by multiplying the current rms
50 Hz signal. measurement, xIRMS, by the corresponding voltage rms,
xVRMS, and then applying a gain correction, xPGAIN. The
Table 11. Total Active Power Settling Time result is stored in the xVA register. Note that the offset of the
Total Active Power Settling Time (sec) total apparent power calculation is performed by calibrating the
Configuration FS = 99% FS = 99.90% xIRMS and xVRMS measurements, using the xIRMSOS and
Integrator On, HPF On, 0.43 0.66 xVRMSOS registers; see the Filter-Based Total RMS section for
and LPF2 On more information on the rms calculation.
Integrator Off, HPF On, 0.43 0.66
and LPF2 On The resulting xVA signal has an update rate of 8 ksps and a
Integrator Off, HPF On, 0.01 0.06 bandwidth of 3.2 kHz.
and LPF2 Off In some applications, if there is a tamper detected on the voltage
channel inputs, it is desirable to accumulate the apparent energy
Total Reactive Power assuming that the voltage were at a nominal level. The ADE9000
Total reactive power includes reactive power on the fundamental offers a register, VNOM, which can be set to a value to correspond
and on the harmonics. The current channel, xI_PCF, is shifted to, for example, 240 V rms. If the VNOMx_EN bits in the
by 90° at the fundamental and at all harmonics. This signal is CONFIG0 register are set, VNOM is multiplied by xIRMS when
then multiplied by the voltage waveform, xV_PCF. The result is calculating xVA.
then low-pass filtered, unless the DISRPLPF bit in the Table 13 shows the settling times for total apparent power for a
CONFIG0 register 1. Finally, the xPGAIN value is applied to 50 Hz signal.
perform a gain correction, and the xVAROS value is applied to
correct the VAR offset. Note that in most applications, the total Table 13. Total Apparent Power Settling Time
reactive power performance with small inputs is sufficient with Total Apparent Power Settling Time,
xVAROS at zero. Configuration FS = 99% (sec)
Integrator On, HPF On, 0.54
The total reactive power at a power factor of 0 has a similar ripple
and LPF2 On
to the total active power at a power factor of 1 (see Figure 16).
The resulting AVAR signal has an update rate of 8 ksps and a Fundamental Measurements
bandwidth of 3.2 kHz. The ADE9000 uses a proprietary algorithm to extract the
It is possible to disable the reactive power calculation by setting fundamental from the total measured signal to make
the VARDIS bit in the VAR_DIS register. This bit must be set measurements including fundamental IRMS, VRMS, WATT,
before writing the RUN bit for proper operation. VAR, VA, ITHD, and VTHD. This algorithm requires
The total reactive power offset can be calibrated for even better initialization of the network frequency and of the nominal
performance over a wide dynamic range using the xVAROS voltage measured in the voltage channel. The SELFREQ bit in
register. xVAROS has the same scaling as xVAR; see the Total the ACCMODE register selects whether the system is 50 Hz or
Active Power section to understand how to calculate this 60 Hz. For a 50 Hz system, clear the SELFREQ bit; for a 60 Hz
register value. Table 12 shows the settling times for total reactive system, set the SELFREQ bit to 1. The SELFREQ selection must
power for a 50 Hz signal. be made prior to writing the RUN register to 1.
The VLEVEL register indicates the nominal value of the voltage
channel. Calculate VLEVEL according to this equation:
VLEVEL = X × 1,114,084
where X is the dynamic range that nominal input signal is at
with respect to full scale.
It is recommended to set the voltage channel input so that the The xFWATTOS register allows offset calibration to provide
nominal voltage (for example, 240 V rms) corresponds to one even better performance with low input signal levels. Figure 17
half of the analog input signal range of the ADE9000. The shows the signal chain for the AFWATT measurement.
ADE9000 can support ±1 V peak, 0.707 V rms inputs; therefore,
it is recommended to scale the voltage channel inputs to APGAIN AFWATTOS
0.353 V rms. Then, with a nominal 240 V, the input signal is at

AI_PCF
half of full scale and X is equal to 2. Write 574,042 (decimal) to FUNDAMENTAL AFWATT ENERGY/
15523-017
AV_PCF WATT POWER/CF
ACCUMULATION
the VLEVEL register to configure this feature:
VLEVEL = 2 × 1,114,084 = 2,288,168 Figure 17. Fundamental WATT, AFWATT Calculation
After configuring these two parameters, SELFREQ and xFWATTOS has the same scaling as xFWATT; see the Total Active
VLEVEL, the ADE9000 tracks the fundamental line frequency Power section to understand how to calculate this register value.
within ±5 Hz of the 50 Hz or 60 Hz frequency selected in Fundamental Reactive Power
SELFREQ. If a larger frequency range than ±5 Hz is required in
The ADE9000 offers fundamental reactive power measurements
the application, monitor the line period, xPERIOD, and change
using the proprietary fundamental estimation technique. This is
the SELFREQ selection accordingly. Note that the RUN register
then gained by xPGAIN and offset correction is applied according
must be set to zero before changing the SELFREQ setting and
to the xFVAROS register. Figure 18 shows the signal chain for the
then be set to one again.
AFVAR measurement.
Fundamental RMS
APGAIN AFVAROS
The ADE9000 offers fundamental current and voltage rms
measurements using the proprietary fundamental estimation AI_PCF
ENERGY/
technique described in the Fundamental Measurements section. FUNDAMENTAL AFVAR
15523-018
AV_PCF VAR POWER/CF
ACCUMULATION
The xIFRMSOS and xVFRMSOS registers allow the offset to be
calibrated for even better performance at low input signal levels. Figure 18. Fundamental Reactive Power, AFVAR
Note that the xFRMS register does not read 0 with the xP and The fundamental reactive power at a power factor of 0 has a
xN inputs shorted together. similar ripple to the total active power at a power factor of 1
The fundamental rms calculations, one for each channel, (see Figure 16).
AIFRMS, BIFRMS, CIFRMS, AVFRMS, BVRMS, and CVRMS, xFVAROS has the same scaling as xFVAR; see the Total Active
are updated every 8 ksps. Note that there the neutral current Power section to understand how to calculate this register value.
channel does not have a fundamental rms measurement.
Fundamental Apparent Power
The xFRMS value at full scale is 52,702,092 (decimal). The ADE9000 offers fundamental rms measurements using the
For high performance at small input signals, below 1000:1, it is proprietary fundamental estimation technique described in the
recommended to calibrate the offset of this measurement using Fundamental Measurements and Fundamental RMS sections.
the xFRMSOS register. It is recommended to calibrate the offset The fundamental rms measurements, xIFRMS and xVFRMS,
at the smallest input signal which requires good performance; are multiplied together to obtain fundamental apparent power.
do not calibrate this measurement with zero input signal. This is then gained by xPGAIN and stored in the xFVA register.
The following equation indicates how the xFRMSOS register Figure 19 shows the signal chain for the AFVA measurement.
value modifies the result in the xFRMS register. Note that offset correction can be performed by calibrating the
AIFRMS and AVFRMS measurements.
xxFRMS = xxFRMS0 2 + 215 × xxFRMSOS
APGAIN
where xxFRMS0 is the initial xFRMS register value before offset
calibration.
AIFRMS ENERGY/
Fundamental Active Power FUNDAMENTAL AFVA
15523-019
AVFRMS POWER/CF
VA ACCUMULATION
The ADE9000 offers fundamental active power measurements
using the proprietary fundamental estimation technique. The Figure 19. Fundamental Apparent Power, AFVA
fundamental active power is then gained by xPGAIN and offset
correction is applied according to the xFWATTOS register.
ENERGY MEASUREMENTS OVERVIEW
ADE9000 PER PHASE AWATTHR

ENERGY AFWATTHR
ACCUMULATION AVARHR
AFVARHR
AVAHR
AFVARHR
AWATT
AI_PCF PER PHASE AFWATT CF1 PULSE OUTPUT
RMS AND AVAR ENERGY TO CF2 PULSE OUTPUT
AV_PCF POWER AFVAR FREQUENCY CF3 PULSE OUTPUT
CALCULATION CF4 PULSE OUTPUT
AIRMS
AVRMS
AVA
AIFRMS
AVFRMS
AFVA AWATT_ACC
PER PHASE AFWATT_ACC
POWER AVAR_ACC
ACCUMULATION AFVAR_ACC
15523-020
AVA_ACC
AFVA_ACC
Figure 20. Per Phase Power and Energy Calculations from xI_PCF and xV_PCF Waveforms
Figure 20 shows how AI_PCF and AV_PCF are used to calculate Table 14. Watt Related Register Update Rates
per phase rms and power calculations and how these are Register
accumulated into the AWATTHR and AWATT_ACC registers, Name Description Update Rate
as well as the CFx pulse outputs. AWATT Low-pass filtered total 8 ksps
Per Phase Energy Measurements Update Rate active power on
Phase A
Instantaneous power measurements, including as xWATT, BWATT Low-pass filtered total 8 ksps
xVAR, xVA, and xFVAR, update at a rate of fDSP = 8 ksps. active power on
These measurements are accumulated into power measurements Phase B
in the xWATT_ACC register, which updates at a user defined CWATT Low-pass filtered total 8 ksps
active power on
interval of up to 1 sec, depending on the selection in the
Phase C
PWR_TIME register.
AWATT_ Accumulated total After the PWR_TIME 8 ksps
Energy measurements update every fDSP = 8 ksps by default and ACC active power on samples, from 250 µs to
can store up to 106 sec of accumulation at full scale. Alternatively, Phase A 1.024 sec
these registers can be set into a different accumulation mode BWATT_ Accumulated total After the PWR_TIME 8 ksps
ACC active power on samples, from 250 µs to
where they update after a user defined number of line cycles or
Phase B 1.024 sec
samples.
CWATT_ Accumulated total After the PWR_TIME 8 ksps
Power factor, ITHD, and VTHD measurements update every ACC active power on samples, from 250 µs to
4096/8 ksps = 1.024 sec. Phase C 1.024 sec
AWATTHR Accumulated total According to the settings in
RMS½ measurements update every ½ line cycle (10 ms at active energy on EP_CFG and EP_TIME; holds
50 Hz). Phase A up to 106 sec of energy at
10 cycle rms/12 cycle rms measurements update every 10 cycles full scale.
on a 50 Hz network, or 12 cycles on a 60 Hz network. The BWATTHR Accumulated total According to the settings in
active energy on EP_CFG and EP_TIME; holds
SELFREQ bit in the ACCMODE register defines which network Phase B up to 106 sec of energy at
is being used. full scale.
CWATTHR Accumulated total According to the settings in
active energy on EP_CFG and EP_TIME; holds
Phase C up to 106 sec of energy at
full scale.
APF Phase A power factor 1 Every 1.024 sec
BPF Phase B power factor1 Every 1.024 sec
CPF Phase C power factor1 Every 1.024 sec
1
See the Power Factor section.
ENERGY ACCUMULATION
WATTACC[1:0] fDSP
CHECK SIGN
TO DETERMINE + 41 31 13 12 0
WHETHER +
0 INTERNAL ENERGY
TO ACCUMULATE ACCUMULATOR
0 1
EGYRDY
ANOLOAD
ACT_NL_LVL AWATTHR_HI AWATTHR_LO
NO LOAD
EP_CFG.
CHECK + 31 0 31 12 0
+
NOLOAD_TMR 0
0 1
INTERNAL ENERGY ACCUMULATOR
VALUE ADDED TO AWATTHR
EGY_LD_ACCUM OR LATCHED INTO AWATTHR
AT EGYRDY RATE
4.096MHz
CFx
WTHR
DIGITAL
CF1DEN TO CFx
FREQUENCY
CF_LCFG CONVERTER
AWATT REVPSUMx
LOW-PASS CFMODE
FILTERED
TOTAL ACTIVE
POWER ENERGY
POWER fDSP
+ 41 31 0
+
INTERNAL POWER ACCUMULATOR
PWRRDY
AWATT_ACC INTERNAL POWER ACCUMULATOR VALUE

31 0 LATCHED IN TO AWATT_ACC
WHEN PWR_TIMER SAMPLES
15523-021
HAVE BEEN ACCUMULATED
Figure 21. AWATT Accumulation into Energy and Power, Using No-load Threshold and Signed Accumulation Mode
Figure 21 shows how AWATT is accumulated into the AWATTHR registers indicates whether the accumulated energy is negative
and AWATT_ACC registers. A no-load threshold is applied and or positive.
the energy is checked to determine whether to accumulate the Other accumulation modes include absolute accumulation mode
AWATT sample into the internal energy accumulator. with WATTACC[1:0] equal to 01 (where the absolute value of
The internal energy accumulator is either added to the AWATT is accumulated), and negative only accumulation mode
AWATTHR register or overwrites it at a EGYRDY rate. Set the with WATTACC[1:0] equal to 11 (where only negative active
EGY_PWR_EN bit in EP_CFG register to run the energy and energy is accumulated).
power accumulator.
Reactive Energy Accumulation Modes
Signed Energy Accumulation Modes
In some installations, because reactive energy can change
Total Active Energy Accumulation Modes
frequently between positive and negative values with inductive
In some installations, it is desirable to bill for only positive total and capacitive loads, it is desirable to bill for the absolute value
active energy. The ADE9000 offers a way to do this using the of reactive energy. The ADE9000 offers a way to do this using
WATTACC[1:0] bits in the ACCMODE register. To set the the VARACC[1:0] bits in the ACCMODE register. To set the
total and fundamental active energy accumulation and any total and fundamental reactive energy register and any
corresponding CF pulse output for positive energy only, write corresponding CF pulse output to accumulate the absolute
WATTACC[1:0] to 10. value of reactive energy, write VARACC[1:0] to 01.
If WATTACC[1:0] is equal to zero, the energy accumulation is If VARACC[1:0] is equal to zero, the total and fundamental
signed. The MSB of the AWATTHR_HI and AFWATTHR_HI reactive energy accumulation is signed. The MSB of the
AVARHR_HI and AFVARHR_HI registers indicates whether Then, for a 50,000:1 no-load threshold level, xNL_LVL is
the energy is negative or positive. 0x6804:
Other accumulation modes offered include positive only  20,694,066  64 
accumulation mode with VARACC[1:0] equal to 10, and xNL _ LVL     26,488  0x6778
 50000 
negative only accumulation mode (where only negative reactive
energy is accumulated) with VARACC[1:0] equal to 11. When a phase is in no-load, every fDSP = 8 ksps, zero energy is
accumulated into the energy registers and CF accumulation.
No-Load Detection
Note that the x_ACC registers are not affected by no-load
No-load detection prevents energy accumulation due to noise,
detection. Even when in no-load, any power calculated in the
when the input currents are below a given meter start current.
respective xWATT, xVAR, and xVA registers is accumulated
To determine if a no-load condition is present, the ADE9000 into the corresponding x_ACC register every fDSP = 8 ksps.
evaluates if the accumulated energy is below a user defined
No-Load Indications
threshold over a user defined time period, which is done on a
per phase and per energy basis. The PHNOLOAD register indicates whether each phase of
energy is in no-load. For example, the PHATNL[2:0] bits in
The NOLOAD_TMR[2:0] bits in the EP_CFG register determine
the PHNOLOAD register indicate whether the Phase A total
whether to evaluate the no-load condition over 64 samples to 4096
apparent energy, reactive energy, and active energy are in phase
samples, 64/8 ksps = 8 ms to 512 ms, by writing to the bits in the
on Bit 2 through Bit 0, respectively. If a bit is set, it indicates that
EP_CFG register, as described in Table 15. No-load detection is
the phase energy is in no-load; if it is clear, the phase is not in
enabled by default, over the minimum time of 64/8 ksps = 8 ms.
no-load.
No-load detection is disabled when the NOLOAD_TMR[2:0] bits
in the EP_CFG are equal to 111 (binary). The user can enable an interrupt to occur when one of the per
phase energy no-load status changes, either going into or out of
Table 15. No-Load Condition Evaluation Time no-load. There is an interrupt enable bit for each type of energy.
Samples to Time that No-Load Set the VAFNOLOAD, RFNOLOAD, AFNOLOAD, VANLOAD,
Evaluate No Detection is RNLOAD, and ANLOAD bits in the STATUS1 register to
NOLOAD_TMR[2:0] Load Over Evaluated Over
enable an interrupt on IRQ1 when one or more phases of
0 64 8 ms
fundamental VA, fundamental VAR, fundamental watt, total
1 128 16 ms
VA, total VAR, and total watt no-load changes status.
2 256 32 ms
3 512 64 ms There is also an option to indicate the no-load status on the
4 1024 128 ms EVENT pin; see the Interrupts/EVENT section for more
5 2048 256 ms information.
6 4096 512 ms Figure 22 shows what happens when the xWATT, low-pass
7 No-load disabled No-load disabled filtered watt, value goes above the user configured no-load
The user defined no-load thresholds are written into the threshold and then back down below it again. The same concept
ACT_NL_LVL, REACT_NL_LVL, and APP_NL_LVL registers. applies to all of the energy values (total and fundamental VAR,
The ACT_NL_LVL register sets the no-load threshold for total total VA) with the corresponding REACT_NL_LNL and
and fundamental active energy. Correspondingly, the APP_NL_LVL no-load thresholds.
REACT_NL_LVL register sets the no-load threshold for total
and fundamental reactive energy while the APP_NL_LVL sets
the no-load threshold for total and fundamental apparent energy. LOW-PASS
FILTERED
ACTIVE POWER (xWATT)
The no load thresholds are calculated according to the following
equation: ACTIVE ENERGY
NO LOAD THRESHOLD
(ACT_NL_LVL)
 xWATT _ FULL _ SCALE  64 
xNL _ LVL    ACTIVE ENERGY
 
NO LOAD ACCUMULATOR
X
where: NO LOAD INDICATION
STATUS1.ANOLOAD)
xWATT_Full_Scale is the nominal xWATT value with full-scale
inputs, 20,694,066. Note that xVAR and VA have the same ACTIVE ENERGY,
xWATTHR
scaling; therefore, the same value can be used for all three
thresholds.
15523-022
X is the desired no-load input power level. For example, to set the NO LOAD ACCUMUL ATION INTERVAL IS
no-load threshold to zero out energy below 50,000 from full scale, SET IN EP_CFG.NOLOAD_TMR
X = 50,000 in the previous equation. Figure 22. No-Load Detection and Indication
Energy Accumulation Details Internal Energy Accumulation Time (sec)
Internal Energy Register Overflow Rate  EGY _ TIME + 1 
= 
There are 42-bit internal signed energy accumulators for each  ZX Rate 
 
phase of each energy accumulation, as shown in Figure 21. These
accumulators update at a rate of fDSP = 8 ksps. The following With a 50 Hz line frequency, the ZX interrupt rate is 100 Hz,
equation shows how to calculate the time until the internal then the maximum accumulation time is 81.92 sec with
accumulator overflows with full-scale inputs and all digital gain EGY_TIME equal to 0x1FFF, 8191 (decimal):
and offset factors at zero, where AWATT_AT_FULL_SCALE Internal Energy Accumulation Time (sec)
refers to the nominal AWATT value with full scale inputs.
 8191 + 1 
=  = 81.92 sec
Maximum Internal Energy Accumulator Time (sec)  100 
 2 41  Note that the internal energy register overflows in 13.3 sec with
= 
 AWATT _ AT _ FULL _ SCALE × f  full-scale inputs; therefore, EGY_TIME must be set lower than
 DSP 
1329 (decimal) to prevent overflow when EGY_TMR_MODE is 1.
For example, with CONFIG0.MTEN equal to zero, for single-
fDSP
point gain compensation and AIGAIN, AVGAIN, APGAIN, ENERGY
0 COUNTER EGYRDY UPDATERATE
and AWATTOS all equal to zero, the Phase A total active energy 1
EGY_TIME[12:0] + 1
EQUAL?
STATUS0.EGYRDY
has a digital gain of 1. Then, the Phase A total active energy ZXVA
ZXVB
00
01
EP_CFG.EGY_TMR_MODE
accumulated in the internal accumulator overflows in 13.3 sec ZXVC

ZXCOMB
10
11 CF3 CF3/ZXPIN
0
with the nominal full-scale AWATT value of 20,694,066. ZX_LP_SEL. 1
ZX_SEL
CONFIG1.
Maximum Internal Energy Accumulator Time (sec) CF3_CFG
 2 41 
=  = 13.3 sec POWER
 20,694,066 × 8000  fDSP
  COUNTER PWRRDY UPDATE RATE
EQUAL?
15523-023
STATUS0.PWRRDY
User Energy Register Update Rate, EGYRDY PWR_TIME[12:0] + 1
As shown in Figure 21, the internal energy accumulator is Figure 23. EGYRDY and PWRRDY Update Rate
latched into a user accessible energy register or added to user
Reloading or Accumulating User Energy Register
accessible register at a rate of EGYRDY. Figure 23 further
describes how the EGYRDY update rate is generated. When the EGYRDY event happens, the internal energy
accumulation is either directly loaded into the xWATTHR register
The EGYRDY update rate occurs after EGY_TIME + 1 fDSP
or added to the existing accumulation based on the state of the
samples or EGY_TIME + 1 half line cycles, according to the
EGY_LD_ACCUM bit in the EP_CFG register. The internal
EGY_TMR_MODE bit in the EP_CFG register.
energy register is reset and starts counting again from zero.
If EGY_TMR_MODE is zero, the internal energy register
If EGY_LD_ACCUM is equal to zero, the internal energy register is
accumulates for EGY_TIME + 1 samples at 8 ksps. This mode
added to the user accessible energy register. If EGY_LD_ACCUM
is called sample-based accumulation.
is equal to one, the internal energy register overwrites the user
Internal Energy Accumulation Time (sec) accessible energy register.
 EGY _ TIME + 1  User Energy Register Overflow Rate
=  

 f DSP  The energy registers in the ADE9000 are signed and 45 bits
The EGY_TIME[12:0] register allows up to (8191 + 1) = wide, split between two 32-bit registers, as shown in Figure 24.
8192 samples to be accumulated, which corresponds to These accumulators update at a rate according to EGYRDY, as
8192/8000 = 1.024 sec if EGY_TMR_MODE is equal to zero. described in the User Energy Register Update Rate, EGYRDY
section. The following equation shows how to calculate the time
Internal Energy Accumulation Time (sec) until the user accessible accumulator overflows with full-scale
 8191 + 1  inputs and all digital gain and offset factors at zero, where
=  = 1.024 sec
 8000  AWATT_AT_FULL_SCALE refers to the nominal AWATT
value with full-scale inputs. For this example, assume that the
If EGY_TMR_MODE is 1, the internal energy register
internal energy register is updating at every fDSP = 8 ksps sample.
accumulates for EGY_TIME + 1 half line cycles at 8 ksps. This
mode is called half line cycle-based accumulation. In this mode, Maximum Internal Energy Accumulator Time (sec)
the zero-crossing source to monitor is set by ZX_SEL bits in the  2 44 
ZX_LP_SEL register, as shown in Figure 23. = 
 AWATT _ AT _ FULL _ SCALE × f 
 DSP 
For example, with the MTEN bit in the CONFIG0 register equal To read energy register with reset, use the following settings:
to zero, for single-point gain compensation and AIGAIN,
• Configuration register settings:
AVGAIN, APGAIN, and AWATTOS all equal to zero, the
• EP_CFG register, EGY_LD_ACCUM bit = 0.
Phase A total active energy has a digital gain of 1. Then, the
• EP_CFG register, EGY_TMR_MODE bit = 0.
Phase A total active energy accumulated in the user accessible
accumulator overflows in 106.4 sec with the nominal full-scale • EP_CFG register, RD_RST_EN bit = 1.
AWATT value of 20,694,066. • EP_CFG register, EGY_PWR_EN bit = 1.
• EGY_TIME register = 1.
Maximum Internal Energy Accumulator Time (sec)
• Output: read just the xHR_HI register, which has enough
 2 44  resolution for most applications. The xHR_LO register is
=  = 106.3 sec
 20,694,066 × 8000  maintained and accumulated and does not need to be read
 
by the user.
Accessing the User Energy Registers • Maximum time before reading xHR_HI to prevent
Each 45-bit user accessible signed energy accumulator is overflow with full-scale inputs: 106 sec.
divided into two registers: a register containing the 32 most To accumulate energy over a defined number of half line cycles,
significant bits, xHR_HI, and a register containing the 13 least use the following settings:
significant bits, xHR_LO, as shown in Figure 24.
fDSP
• Configuration register settings:
• EP_CFG register, EGY_LD_ACCUM bit = 1.
+
INTERNAL ENERGY ACCUMULATOR • EP_CFG register, EGY_TMR_MODE bit = 1.
• EP_CFG register, RD_RST_EN bit = 0.
AWATTHR_HI
• EP_CFG register, EGY_PWR_EN bit = 1.
31 0
31 12 0
• EGY_TIME register = desired number of half line
cycles.
15523-024
AWATTHR_LO • Output:
Figure 24. Internal Energy Register to AWATTHR_HI and AWATTHR_LO • The xHR_HI register has enough resolution for most
The expected user energy accumulation can be calculated applications.
according to this formula based on the average AWATT value. • To maintain perfect synchronization with CF pulse
output, the xHR_LO register must be read as well,
USER_ENERGY_ACCUMULATION
because it is cleared at every EGYRDY cycle.
= AWATT × (EGY_TIME + 1)
• Maximum time before reading xHR_HI to prevent
Then, AWATTHR_HI contains the 32 most significant bits, overflow with full-scale inputs: 13.3 sec.
which can be calculated by rounding the following equation
down to the nearest whole number: To accumulate energy over a defined number of samples, use
the following settings:
AWATTHR_HI
= ROUNDDOWN(USER_ENERGY_ACCUMULATION × 2−13) • Configuration register settings:
• EP_CFG register, EGY_LD_ACCUM bit = 1
The 13 LSBs of USER_ENERGY_ACCUMULATION are stored
• EP_CFG register, EGY_TMR_MODE bit = 0
in the AWATTHR_LO register.
• EP_CFG register, RD_RST_EN bit = 0
Read User Energy Register with Reset • EP_CFG register, EGY_PWR_EN bit = 1
If the RD_RST_EN bit is set in the EP_CFG register, its contents • EGY_TIME register = desired number of samples
are reset when a user accessible energy register is read. • Output:
For example, if AWATTHR_HI is read, the AWATTHR_HI register • The xHR_HI register has enough resolution for most
value goes to zero. The AWATTHR_LO register contents are applications.
not modified. • To maintain perfect synchronization with CF pulse
output, the xHR_LO register must be read as well,
User Energy Register Use Models
because it is cleared at every EGYRDY cycle.
There are three main use models for energy accumulation: • Maximum time before reading xHR_HI to prevent
• Read energy register with reset overflow with full-scale inputs: 13.3 sec.
• Accumulate energy over a defined number of line cycles
• Accumulate energy over a defined number of samples
Digital to Frequency Conversion—CF Output Then, the maximum recommended CF pulse output frequency
Many electricity meters are required to provide a pulse output is 78.862 kHz.
that is proportional to the energy being accumulated, with a MAXIMUM _ CF (Hz)
given pulse per kWh meter constant.
 4.096 × 10 6 × 20,694,066 
The ADE9000 includes four pulse outputs that are proportional =  = 78.9 kHz
 0 x0010 _ 0000 × 512 × 2 
to the energy accumulation, in the CF1 through CF4 output pins.  
Energy and Phase Selection where:

fDTOF is 4.096MHz.
The CFxSEL[2:0] bits in the CFMODE register select which AWATT is the value at full scale, 20,694,066.
type of energy to output on the CFx pin, including total or xTHR is 0x0010_0000.
fundamental watt, VAR, and VA. Then, the TERMSELx bits in CFDEN is 2.
the COMPMODE register select which phase energies to
include in the CF output. The default CF pulse output using power-on reset values of
xTHR and CFxDEN with full-scale inputs is
For example, with the CFMODE register, CF1SEL[2:0] bits = 000
and the COMPMODE register, TERMSEL1[2:0] bits = 111, CF1 MAXIMUM _ CF (Hz)
indicates the total watt output of Phase A, Phase B, and Phase C.  4.096 × 10 6 × 20,694,066 
=  = 38.5 Hz
To calibrate the Phase A, Phase B, and Phase C total watt  0 x0000 _ FFFF × 512 × 0 xFFFF 
 
accumulation at the same time, using CF1 for total AWATT,
CF2 for total BWATT, and CF3 for total CWATT, configure the Configuring the CF Pulse Width
CFMODE register, the CF1SEL, CF2SEL, and CF3SEL bits = 000; The pulse width is determined by the CFx_LT bit in the
the COMPMODE register, TERMSEL0[2:0] bits = 001; the CF_LCFG register and the CF_LTMR register value.
COMPMODE register, TERMSEL1[2:0] bits = 010; and the
With CFx_LT equal to zero, the active low pulse width is set at
COMPMODE register, TERMSEL2[2:0] bits = 100
80 ms for frequencies lower than 1/(2 × 80 ms) = 6.25 Hz. For
Configuring the Maximum CF Pulse Output Frequency higher frequencies, the duty cycle is 50% if CFxDEN is even, or
It is recommended to write xTHR = 0x0010_0000. CFxDEN (1 + 1/CFxDEN) × 50% if CFxDEN is odd.
can range from 2 to 65535. Configure CFxDEN to tune the CF If CFx_LT is set to 1, the CF active low pulse width is
frequency output. The relationship between the xTHR, CFxDEN, CF_LTMR × 6/CLKIN. The maximum CF_LTMR is 327680 =
and AWATT values is given in the following equation: 0x0005_0000, which results in a 327680/(6/CLKIN) = 80 ms
pulse. CF_LTMR must be greater than zero.
 f DTOF × AWATT 
CF (Hz) =  
 xTHR × 512 × CFxDEN 
 
Table 16. CF Active Low Pulse Width and Duty Cycle based on CFx_LT and CF_LTMR
Active Low Pulse Width for Active Low Pulse Width for
Active Low Pulse Width High Frequencies when High Frequencies when Behavior when
CFx_LT for Low Frequencies (ms) CFxDEN is Even CFxDEN is Odd Entering No-Load
0 80 50% (1 + 1/CFxDEN) × 50% If CFx is low, finish current pulse,
then return high.
1 CF_LTMR × 6/CLKIN × 1000 50% (1 + 1/CFxDEN) × 50% If CFx is low, keep CFx low until
no-load state is finished.
CF Pulse Sign The PWR_TIME[12:0] register allows up to (8191 + 1) =
Some applications must record positive and negative energy usage 8192 samples to be accumulated, which corresponds to
separately. To facilitate this, the SUMxSIGN bits in the PHSIGN 8192/8000 = 1.024 sec:
register indicate whether the sum of the energy that went into Internal Power Accumulation Time (sec)
the last CFx pulse was positive or negative. SUMxSIGN is zero
 8091 + 1 
if the sum of the energy that went into the CFx pulse is positive, =  = 1.024 sec
 8000 
and equal to one if the sum of the energy was negative.
The internal power accumulator overflows at the same rate as
Furthermore, the REVPSUMx bits in the STATUS0 register and
the internal energy accumulator (see the Internal Energy
EVENT_STATUS register indicate if the CF polarity changed sign.
Register Overflow Rate section).
For example, if the last CF2 pulse represents positive reactive
energy and the next CF2 pulse represents negative reactive energy, Accessing the User Power Registers
the REVPSUM2 bit in the STATUS0 and EVENT_STATUS Each 42-bit user accessible signed power accumulator is divided
registers is set. This event can be enabled to generate an interrupt into a register containing the 32 most significant bits, x_ACC,
on IRQ0. as shown in Figure 24.
Clearing the CF Accumulator fDSP
It can be desirable to clear out a partial CF accumulation, for AWATT +

+
INTERNAL
example, during the power-up and initialization process. To POWER
ACCUMUL ATOR
41 31
clear the accumulation in the digital to frequency converter and 13 0
AWATT_ACC
CFDEN counter, write the CF_ACC_CLR bit in the CONFIG1
15523-025
31 0
register to 1. The CF_ACC_CLR bit automatically clears itself.
Disabling the CF Pulse Output and CFx Interrupt Figure 25. Internal Power Register to AWATT_ACC
To disable the CFx pulse output and keep the CFx output high, The expected user power accumulation can be calculated
write a 1 to the CFx_DIS bit in the CFMODE register. If the according to this formula based on the average AWATT value.
CFx output is disabled, the CFx bit in STATUS0 is not set when USER_POWER_ACCUMULATION =
a new CF pulse is ready. Note that the REVPSUMx bits, which AWATT × (PWR_TIME + 1)
indicate if CF pulses were positive or negative, are not affected
by the CFx_DIS setting. Then, expected data in the 32-bit power accumulation registers
(xWATT_ACC, xVAR_ACC, and xVA_ACC) can be calculated
POWER ACCUMULATION as follows:
Figure 21 shows how AWATT low-pass filtered active power Power accumulation register =
samples are accumulated to provide an accurate active power ROUNDDOWN(USER_POWER_ACCUMULATION × 2−13)
value in the AWATT_ACC register. The sign of the Phase A
total active power accumulation is monitored in the REVAPA For example, if 4000 samples of AWATT are accumulated, at
status bit, and interrupts can be enabled if the power changes 8 ksps with full-scale inputs, the expected value of
sign. There are corresponding x_ACC accumulations for each AWATT_ACC is 0x009B_0003:
power on each phase and REVx status bits in STATUS0 to USER_POWER_ACCUMULATION =
indicate if the power changes sign. 20,694,066 × (3999 + 1) = 82776264000
Power Accumulation Details AWATT_ACC = ROUNDDOWN(82776264000 × 2−13) =
Figure 21 shows how AWATT values are accumulated into an 10104524 = 0x009A_2ECC
internal power accumulator and then are latched into the To determine the consumption in watts, multiply xWATT_ACC
xWATT_ACC register at a rate of PWRRDY. by the W/LSB constant: xWATT_ACC × W/LSB.
PWRRDY is set after PWR_TIME + 1 samples at 8 ksps have Note that W/LSB varies with PWR_TIME accumulation time.
been accumulated. The power accumulation time can be Power Sign Detection
calculated according to the following equation:
The REVRPC, REVRPB, REVRPA, REVAPC, REVAPB, and
Internal Power Accumulation Time (sec) REVAPA bits in the STATUS0 register allow the user to monitor
 PWR _ TIME + 1  if the active or reactive power on any phase has changed sign.
= 
 8000  The PWR_SIGN_SEL[1:0] bits allow the user to select whether
the power sign change follows the total or fundamental
energies. To have the REVAPx power sign status bits track total
watt, PWR_SIGN_SEL[0] = 0. To track fundamental VAR on
REVRPx bits, write PWR_SIGN_SEL[1] = 1.
The CVARSIGN, CWSIGN, BVARSIGN, BWSIGN, AVARSIGN, POWER QUALITY MEASUREMENTS
and AWSIGN bits in the PHSIGN register indicate whether the Zero-Crossing Detection
total or fundamental VAR and WATT selected in the
The ADE9000 offers zero-crossing detection on the VA, VB, VC,
PWR_SIGN_SEL[1:0] bits are positive or negative.
IA, IB, and IC input signals. The neutral current channel, IN,
The power signs are updated at the same time as the does not contain a zero-crossing detection circuit. The zero-
xWATT_ACC, xFWATT_ACC, xVAR_ACC, and xFVAR_ACC crossing circuit is used as the time base for resampling, line
registers and correspond to the sign of these registers. Note that period, angle measurements, and energy accumulation using
the power registers and signs are updated after the number of line cycle accumulation mode. The xV_PCF and xI_PCF are the
fDSP = 8 ksps samples configured in the PWR_TIME register voltage and current channel waveforms processed by the DSP,
have elapsed, from 250 µs to 1.024 sec. The power sign change and which can be stored into the waveform buffer at a 8 ksps data
indication in the REVxPx bits are updated at the same time; see rate (see the Waveform Buffer section for more information).
the Power Accumulation Details section for more information.
The ZX_SRC_SEL bit in the CONFIG0 register sets whether
The ADE9000 allows the user to accumulate total watt and VAR data going into the zero-crossing detection circuit comes before
powers into separate positive and negative registers: or after the high-pass filter, integrator, and phase compensation.
PWATT_ACC and NWATT_ACC, PVAR_ACC and By default, the data after phase compensation is used. Note that
NVAR_ACC. This is done by evaluating the AWATT, low-pass the high-pass filter has 500 ms settling time with a step change
filtered active power every 8 ksps. If the AWATT is positive, it is in the input; therefore, for a fast response, it is recommended to
added to the PWATT_ACC accumulation. If the AWATT is set ZX_SRC_SEL to look for a zero-crossing before the high-
negative, the absolute value is added to the NWATT_ACC pass filter. If a high-pass filter is disabled with the HPFDIS bit in
accumulation. A new accumulation from zero begins when the the CONFIG0 register equal to 1, or if the ZX_SRC_SEL bit in
power update interval set in PWR_TIMER has elapsed. The the CONFIG0 register is equal to 1, note that a dc offset on the
positive and negative total watt and total VAR from all three input may cause the time between negative to positive and
phases are added into the positive/negative watt and VAR positive to negative zero-crossings and positive to negative to
accumulations. negative to positive zero-crossings to change, indicating that the
ZX detection does not have a 50% duty cycle.
AWATT, LOW PASS
FILTERED
ACTIVE POWER The current and voltage signals are low-pass filtered to remove
harmonics. The low-pass filter, LPF1, has a corner of 82 Hz and
the equation is as follows:
AWATT
INTERNAL POWER 2 −4
ACCUMULATOR H (z ) =
1 − (1 − 4)z −1
The low-pass filter settling time is 71 samples, 71/8 ksps, which
ACCUMULATED
ACTIVE POWER, equals 8.875 ms.
AWATT_ACC
Figure 27 shows the delay between the detected zero-crossing
signal and the input. Note that there is a 4.3 ms delay between
POSITIVE
the input signal zero-crossing and the ZX zero-crossing
ACTIVE POWER,
PWATT_ACC
indication, with a 50Hz input signal. Zero-crossings are
generated on both negative to positive and positive to negative
NEGATIVE
ACTIVE POWER, transitions.
NWATT_ACC
4.3ms AT 50Hz
PHASE A ACTIVE POWER
SIGN INDICATION: 1
AWSIGN, IN PHSIGN 0.86
PHASE A ACTIVE POWER

SIGN CHANGE INDICATION:
REVAPA, IN STATUS0 ZX
0V
ZX ZX ZX
15523-027
CLEARED AFTER USER WRITES STATUS0

REGISTER WITH REVAPA BIT SET, IA, IB, IC, LPF1 OUTPUT
15523-026
POWER UP DATE INTERVAL

OR VA, VB, VC
SET IN PWR_TIME
Figure 27. Zero-Crossing Detection on Voltage and Current Channels
Figure 26. Power Accumulation and Power Sign
To provide protection from noise, the voltage channel zero-
crossing events (ZXVA, ZXVB, and ZXVC) are not generated if
the absolute value of the LPF1 output voltage is smaller than the
threshold, ZXTHRSH. The current channel ZX detection outputs
(ZXIA, ZXIB, and ZXIC) are active for all input signals levels.
The zero-crossing threshold, ZXTHRSH, can be calculated Combined Voltage Zero-Crossing
from the following equation: Phase A, Phase B, and Phase C voltage channel signals are
ZXTHRSH = combined to generate one zero-crossing signal, ZX_COMB, that
(V _ PCF at Full Scale) × (LPF1 _ ATTENUATION ) is stable even if one or more phases drops out.
X × 32 × 2 8 The input to the zero-crossing detection is (VA + VB − VC)/2
with the signal chain corresponding to Figure 28. As described
where: in the Applying the ADE9000 to Different Metering
V_PCF at full scale is ±74,532,013 (decimal). Configurations section, the ADE9000 can be used to meter
X is the dynamic range that the zero-crossing must be blocked different polyphase configurations. The VCONSEL[2:0] bits in
below. the ACCMODE register are used to indicate this selection. If
LPF1_ATTENUATION is 0.86 at 50 Hz and 0.81 at 60 Hz, the VCONSEL[2:0] is not equal to 0, the VB component in the
gain attenuation of the LPF1 filter. combined zero-crossing circuit is set to zero.
For example, to prevent signals 100 times lower than full scale The same precautions are used to prevent noise from generating
from generating a ZX output, set ZXTHRSH to 78 (decimal): zero-crossing interrupts on this output. As described in the
ZXTHRSH = Zero-Crossing Detection section, signals below the ZXTHRSH
(74,532,013) × (0.86) threshold do not generate ZXCOMB outputs, and a minimum
= 78d of 1 ms is required between ZXCOMB generation.
100 × 32 × 2 8
Additionally, to prevent false zero-crossings, after a ZX is
generated, 1 ms must elapse before the next ZX can be output.
ZX_SRC_SEL
HPFDIS
PHASE A
PHASE
HPF COMP
AV_PCF
ZX_SRC_SEL
HPFDIS (VA + VB – VC)/2
PHASE B ZX DETECTION,
PHASE 0 ÷2
COMP LINE PERIOD
VCONSEL[2:0] CALCULATION
HPF BV_PCF LPF1
ZX_SRC_SEL
HPFDIS
PHASE C
PHASE
15523-028
HPF COMP
CV_PCF
Figure 28. Combined Zero-Crossing Detection
Zero-Crossing Output Rates Table 17 indicates which zero-crossing edges (negative to
There are seven zero-crossing detection circuits that monitor positive and positive to negative) are used for each function and
IA, IB, IC, VA, VB, VC, and the combined (VA + VB − VC)/2 indicates what happens if a zero-crossing is blocked because the
signal. The zero-crossing detection circuits have two different input signal is below the user configured ZXTHRSH.
output rates: 8 ksps and 1024 ksps. The 8 ksps zero-crossing The CF3/ZX output pin goes from low to high when a negative
signal is used to calculate the line period, sent to the ZXx bits in to positive transition is detected and from high to low when a
the STATUS1 register, and is monitored by the zero-crossing positive to negative transition occurs. The ZX_SEL[1:0] bits in
timeout, phase sequence error detection, resampling and energy the ZX_LP_SEL register select the zero-crossing output used for
accumulation functions. The 1024 ksps signal is used for angle line cycle energy accumulation and the ZX output pin.
measurements and is output on the CF3/ZX pin if the
CF3_CFG bit in the CONFIG1 register is equal to 1.
fDSP
ZX_SRC_SEL ZX INDICATION IN STATUS1

ZERO-CROSSING TIMEOUT
PHASE SEQUENCE ERROR DETECTION
RESAMPLING, ENERGY ACCUMULATION
÷32 ZX DETECTION LINE PERIOD
LPF1
CLKIN/24UPDATE
xx_PCF ANGLE MEASUREMENT

ZX OUTPUT ON CF3/ZX PIN
15523-029
Figure 29. Zero-Crossing Output Rates
Table 17. Zero-Crossing Use in Other Functions

Corresponding
Functions Using ZX Transitions STATUS1 Selecting which Phase
Zero-Crossing Used Register Bits to Use for Measurement Effect if ZX Does Not Occur
ZX Indication in Negative to ZXIA, ZXIB, ZXIC, Not applicable ZXx bit is latched in STATUS1. If cleared, it is
STATUS1 Register positive, and ZXVA, ZXVB, not set again. ZXx interrupt does not occur.
positive to negative ZXVC, ZXCOMB
Zero-Crossing Timeout Negative to ZXTOVA, Not applicable Zero-crossing timeout is indicated by the
positive, and ZXTOVB, ZXTOUT bit in the STATUS1 register and an
positive to negative ZXTOVC interrupt can be enabled to occur.
Phase Sequence Error Depends on SEQERR Not applicable If one to two ZX events are missing, SEQERR
Detection VCONSEL[2:0] is generated. If all ZX are missing then
setting SEQERR bit is note set.
Energy Accumulation Negative to Not applicable ZX_LP_SEL.ZX_SEL[1:0] Line cycle accumulation does not update.
positive, and selects the zero-crossing
positive to negative output used for line cycle
energy accumulation and
ZX output pin.
Line Period Measurement Negative to Not applicable Not applicable Coerced to default value: 0x00A0_0000 if
positive ACCMODE.SELFREQ = 0, for a 50 Hz network;
0x0085_5554 if ACCMODE.SELFREQ = 1, for a
60 Hz network.
Resampling, RMS½, None Not applicable ZX_LP_SEL.LP_SEL[1:0] If the selected line period is invalid because
10 Cycle RMS/12 Cycle selects the phase voltage zero-crossings are not detected or the
RMS line period used as the calculation results in something outside a
basis for for these 40 Hz to 70 Hz range, the line period used for
calculations. the calculation is coerced to the default line
period: 0x00A0_0000 if ACCMODE.SELFREQ
= 0, for a 50 Hz network; 0x0085_5554 if
ACCMODE.SELFREQ = 1, for a 60 Hz network.
Angle Measurements Negative to Not applicable Not applicable Does not update; keeps last value.
positive
ZX Output on CF3/ZX Pin Negative to Not applicable ZX_LP_SEL.ZX_SEL[1:0] Remains at current state; high or low.
positive, and selects the zero-crossing
positive to negative output used for line cycle
energy accumulation and
ZX output pin.
Zero-Crossing Timeout The line period calculation is used for the resampling
The zero-crossing timeout feature alerts the user if a zero- measurement. Select which phase voltage line period is used as
crossing event is not generated after a user configured amount of the basis for resampling calculation using the LP_SEL[1:0] bits
time. If a zero-crossing on is not received after ZXTOUT 8 ksps in the ZX_LP_SEL register, or select a user configured value
clocks, the corresponding ZXTOx bit in the STATUS1 register is written in USER_PERIOD using the UPERIOD_SEL bit in the
set. For example, if ZXTOUT is equal to 8000, if a zero-crossing is CONFIG2 register.
not then received on Phase A for 8000/8 ksps = 1 sec, the ZXTOA The user period selection can help in applications where the
bit is set in the STATUS1 register. The maximum value that can user has another algorithm to determine the line frequency, or
be written to the ZXTOUT register is 0xFFFF/8000 = 8.19 sec. if it is preferred to always assume a certain line frequency when
resampling or calculating a fast rms measurement.
Line Period Calculation
USER_PERIOD[31:0] has the same scaling as the xPERIOD
The ADE9000 line period measurement is done by taking the registers. Write USER_PERIOD[31:0] to 0x00A0_0000 for
values low-pass filtered by LPF1, as described in the Zero- 50 Hz and 0x0085_5554 for 60 Hz.
Crossing Detection section, and then using the two values near
the positive to negative zero-crossing to calculate the exact Angle Measurement
zero-crossing point using linear interpolation. This information The ADE9000 measures the time between zero-crossings on
is used to precisely calculate the line period, which is stored in each phase. This measurement helps to determine if the system
the xPERIOD register. is balanced properly or to figure out if there was an installation
error. The user can check if the phase angles correspond to the
4.3ms AT 50Hz
ones in the phasor diagrams in the Applying the ADE9000 to
0.86
Different Metering Configurations section.
Ix,Vx
0V
x x LPF1 OUTPUT The times between positive to negative zero-crossings are
x x measured using a CLKIN/24 = 24.576/24 = 1024 kHz clock.
15523-030
The time between the zero-crossing on Phase A and Phase B is

POS1 POS2 POS1 POS2
stored in the ANGL_VA_VB register. The resolution of the
Figure 30. Line Period Calculation using Zero-Crossing Detection and
ANGLx_x2x register is (1/(1024 × 1000))/20 ms × 360° =
Linear Interpolation
0.017578125° at 50 Hz.
The line period, TL, can be calculated from the xPERIOD
The time between the zero-crossing on Phase B and C is stored
register according to the following equation:
in the ANGL_VB_VC register, and the time in between the
xPERIOD + 1 zero-crossings on Phase A and C is stored in the
TL = (sec)
8000 × 216 ANGL_VA_VC register, as shown in Figure 31.
Similarly, the line frequency can be calculated from the
xPERIOD register, using the following equation:
8000 × 216
fL = (Hz)
xPERIOD + 1
With a 50 Hz input, the xPERIOD register is 0x00A0_0000,
ANGL_VA_VB ANGL_VB_VC
10485760 (decimal), and with 60 Hz, it is 0x0085_5554,
15523-031
8738132 (decimal). ANGL_VA_VC
If the calculated period value is outside the range of 40 Hz to Figure 31. Voltage to Voltage Phase Angle
70 Hz, or if the negative to positive zero-crossings for that phase
are not detected, the xPERIOD register be coerced to The angle in degrees can be calculated from the following
correspond to 50 Hz or 60 Hz, according to the setting of the equation with a 50 Hz line period:
SELFREQ bit in the ACCMODE register. With SELFREQ equal Angle (degrees) = ANGL_VA_VB × 0.017578125/LSB
to 0 for a 50 Hz network, the xPERIOD register is coerced to For a 4-wire wye configuration, the expected ANGL_VA_VB
0x00A0_0000. If SELFREQ is 1, indicating a 60 Hz network, the and ANGL_VB_VC is 120°/0.017578125 = 3413 (decimal). Note
xPERIOD register is coerced to 0x0085_5554. that the expected ANGL_VA_VC from the Phase A voltage to
The line period is calculated for the Phase A, Phase B, and Phase C voltage is 240°/0.017578125 = 13653 (decimal), which
Phase C voltages and the combined voltage signal, as described corresponds to a 120° angle between Phase C and Phase A.
in the Combined Voltage Zero-Crossing section, and stored in The current to current zero-crossings are also measured. This
the APERIOD, BPERIOD, CPERIOD, and COM_PERIOD measurement is done similarly to the voltage to voltage phase
registers, respectively. angle described previously, except the current channel zero-
crossings are used as the reference. The time between the zero- For a 4-wire wye or 4-wire delta system, VCONSEL[2:0] is 000,
crossing on Phase A and Phase B is stored in the ANGL_IA_IB 010, or 011, as described in the Applying the ADE9000 to
register. The time between the zero-crossing on Phase B and Different Metering Configurations section. In these 4-wire
Phase C is stored in the ANGL_IB_IC register, and the time in systems, the negative to positive transitions on ZXVA, ZXVB,
between the zero-crossings on Phase A and Phase C is stored in and ZXVC are monitored to determine if there is a phase
the ANGL_IA_IC register. sequence error, as shown in Figure 35. To detect a phase
The voltage to current phase angles are measured as well. sequence error, set how many sequences to observe in the
These angles can be used to determine the power factor at the SEQ_CYC register. It is recommended to set SEQ_CYC to 1.
fundamental. ANGL_VA_IA reflects the phase angle between Figure 34 shows a phase sequence error for a 4-wire wye or 4-
the Phase A voltage and current, as shown in Figure 32. wire delta due to a wiring or installation error.
ANGL_VB_IB holds the Phase B voltage to current phase angle,
and ANGL_VC_IC holds the Phase C voltage to current phase
angle.
A,B,C
PHASE
PHASE A VOLTAGES
VOLTAGE AFTER
PHASE A LPF1
CURRENT
ZXC ZXB ZXA

15523-032
SEQERR
15523-034
ANGL_VA_IA
PHASE SEQUENCE ERROR
(SEQERR = 1)
Figure 32. Voltage to Current Phase Angles
Figure 34. 4-Wire Wye and 4-Wire Delta Phase Sequence Error (Wiring Error)
Note that if the magnitude of the voltage channel is below the
user configured zero-crossing threshold, the zero-crossing Figure 35 shows that in an installation with the normal phase
output for that phase is not generated. In this event, the sequence, a phase sequence error is generated if a phase voltage
corresponding ANGLx_x2x measurements are not updated; the drops below the ZXTHRSH.
last value remains in the register. The current channel does not
have these thresholds. With a low input signal level, spurious
zero-crossing events may be generated on the current channel, A,B,C
PHASE
which results in ANGLx_I2I and ANGLx_V2I readings that are

VOLTAGES
AFTER
LPF1
not meaningful.
Phase Sequence Error Detection ZXA ZXB ZXC ZXB ZXC ZXB ZXC
4-Wire Wye and 4-Wire Delta
15523-035
SEQERR
For 4-wire wye and 4-wire delta meters, the normal phase PHASE SEQUENCE ERROR
sequence is shown in Figure 33. Figure 35. 4-Wire Wye, 4-Wire Delta Phase Sequence Error from a Phase
Voltage Dropping Below ZXTHRSH with SEQ_CYC = 1
PHASE A PHASE B PHASE C
3-Wire Delta
A,B,C PHASE For a 3-wire delta system, VCONSEL[2:0] is 001 or 100, as
VOLTAGES AFTER
LPF1 described in the Applying the ADE9000 to Different Metering
Configurations section. In a 3-wire delta system, the ZXVC and
ZXVA positive to negative and negative to positive transitions
ZXA ZXB ZXC
are monitored to detect a phase sequence error. Figure 36 shows
the normal phase sequence for a 3-wire delta with
15523-033
NORMAL PHASE SEQUENCE VCONSEL[2:0] = 001.

SEQERR = 0
Figure 33. 4-Wire Wye and 4-Wire Delta Normal Phase Sequence
Fast RMS½ and 10/12 RMS Measurements
PHASE C PHASE A
= VCB = VAB RMS½ is an rms measurement done over one line cycle,
updated every half cycle.
VA,VC This measurement is provided for voltage and current on all
AFTER LPF1
phases plus the neutral current. All the half cycle rms
measurements are done over the same time interval and update
at the same time, as indicated by the RMSONERDY bit in the
ZXC_POS ZXA_POS ZXC_NEG ZXA_NEG
STATUS0 register. The results are stored in the AIRMSONE,
BIRMSONE, CIRMSONE, NIRMSONE, AVRMSONE,
BVRMSONE, and CVRMSONE registers.
15523-036
NORMAL PHASE SEQUENCE
SEQERR = 0 By default, the number of samples used in the calculation varies
Figure 36. 3-Wire Delta Normal Phase Sequence with measured line frequency. The LP_SEL bits in the ZX_LP_SEL
register select which line period measurement is used to set the
Write SEQ_CYC to indicate how many consecutive incorrect
number of samples used in the RMS½ measurement.
transitions must be observed before raising the SEQ_ERR
interrupt. It is recommended to set SEQ_CYC to 1. Figure 37 Alternatively, the user can set the number of samples used in
shows an installation error for 3-wire delta that results in a the calculation by setting the UPERIOD_SEL bit in CONFIG2,
detected phase sequence error. where the user configured USER_PERIOD register is used
instead of the selected line period measurement. For more
PHASE C PHASE A
information about USER_PERIOD and the line period
measurements, see the Line Period Calculation section.
VA, VB, VC
AFTER LPF1 The samples used for the RMS½ calculation can come from
before the high-pass filter or after the integrator, as selected in
the RMS_SRC_SEL bit in the CONFIG0 register.
ZXC_POS ZXC_NEG
ZXA_POS ZXA_NEG Because the high-pass filter has a significant settling time
associated with it, it is recommended to use the data from
before the high-pass filter for the fastest response time.
STATUS1.
SEQERR An offset correction register is provided for even better
performance with small input signal levels, xRMSONEOS.
The xRMSONE register reading with full-scale inputs is
15523-037
WRITE STATUS1.SEQERR = 1
STATUS1.SEQERR
SET TO 1
TO ACKNOWLEDGE THIS EVENT 52,702,092 (decimal).
AND CLEAR STATUS1.SEQERR
Figure 37. 3-wire Delta Phase Sequence Error (Wiring Error) The 10 cycle rms/12 cycle rms measurement is done over 10 cycles
on a 50 Hz network, or 12 cycles on a 60 Hz network.
Figure 38 shows that in an installation with the normal phase
sequence, a phase sequence error is generated if one of the An offset correction register is provided for even better
phase voltage drops below the ZXTHRSH. performance with small input signal levels, xRMS1012OS.
The xRMS1012 register reading with full scale inputs is
PHASE C PHASE A
52,702,092 (decimal).
VA,VB,VC
Table 18 shows the ½ cycle rms settling times for a 50 Hz signal.
AFTERLPF1 Table 19 shows the 10 cycle rms/12 cycle rms settling times for a
50 Hz signal.
ZXA_POS ZXA_NEG ZXA_POS ZXA_NEG ZXA_POS ZXA_NEG
ZXC_POS ZXC_NEG Table 18. ½ RMS Settling Time
½ RMS Settling Time,
STATUS1.
SEQERR Configuration FS = 99% (sec)
STATUS1.SEQERR
15523-038
SETTO1 WRITE STATUS1.SEQERR = 1

TO ACKNOWLEDGE THIS EVENT Table 19. 10 Cycle RMS/12 Cycle RMS Settling Time
AND CLEAR STATUS1.SEQERR
10/12 RMS Settling Time,
Figure 38. 3-Wire Delta Phase Sequence Error from a Phase Voltage
Dropping Below ZXTHRSH with SEQ_CYC = 1
Configuration FS = 99% (sec)
Dip/Swell Indication The OIPHASE[3:0] bits in the OISTATUS register indicate
Dip indicates if the voltage went below a specified threshold for a which current channels had RMS½ measurements greater than
user configured number of cycles. Conversely, swell indicates if the the threshold.
voltage went above a threshold for a specified number of cycles. If a phase is enabled, with the corresponding OC_EN bit set
Set the DIP_LVL register to correspond to the RMS½ value to and RMS½ current greater than the threshold, the OI status is
trigger the dip event, according to this equation: set and the RMS½ value is stored in the corresponding OIx
register. If a phase is disabled, or an overcurrent event does not
DIP_LVL = xVRMSONE × 2−5
occur on that phase, the OIx register keeps the last value.
Configure the number of cycles to observe the RMS½ value
Peak Detection
over in the DIP_CYC register.
The ADE9000 records the peak value measured on the current
The RMS½ voltages on Phase A, Phase B, and Phase C is and voltage channels, from the xI_PCF and xV_PCF waveforms.
compared to the DIP_LVL over the specified DIP_CYC. If the The PEAKSEL[2:0] bits in the CONFIG3 register allow the user
RMS½ voltage is low for the specified number of DIP_CYC, the to select which phases to monitor. Set PEAKSEL[2] to monitor
dip event has occurred on that phase and the corresponding Phase C, PEAKSEL[1] for Phase B, and PEAKSEL[0] for Phase A.
DIPA, DIPB, and DIPC bits are set in the STATUS1 register. Set PEAKSEL[2:0] = 111 (binary) to monitor all three phases.
The dip event can be configured to generate an interrupt on the
IRQ1 pin The IPEAK register stores the peak current value in
IPEAKVAL[23:0] and indicates which phase(s) currents
The dip event can be configured to generate an event on the reached the value in the IPPHASE[2:0] bits. IPEAKVAL is equal
CF4/EVENT/DREADY pin, if the corresponding bits are set in to xI_PCF/25.
the EVENT_MASK register. This allows the user to precisely
IPPHASE[2] indicates that Phase C had the peak value,
time the duration of a dip or swell, using the CF4/EVENT/
IPPHASE[1] indicates Phase B, and IPPHASE[0] indicates
DREADY pin in combination with a timer on an external Phase A.
microcontroller.
Similarly, VPEAK stores the peak voltage value in
The minimum RMS½ value measured during the dip is stored VPEAKVAL[23:0]. VPEAKVAL is equal to xV_PCF/25.
in the corresponding DIPA, DIPB, and DIPC registers.
VPPHASE[2] indicates if Phase C had the peak voltage value,
Similarly, the swell indication has a SWELL_LVL register to set VPPHASE[1] indicates Phase B, and VPPHASE[0] indicates
the swell threshold, according to this equation: Phase A.
SWELL_LVL = xVRMSONE × 2−5 When the user reads the IPEAK register, its value is reset. The
There is also a SWELL_CYC register. The maximum RMS½ same is true for reading VPEAK.
voltage value measured during the swell is stored in the Power Factor
corresponding SWELLA, SWELLB, and SWELLC registers.
The total active power and total apparent power are
If the DIP_SWELL_IRQ_MODE bit is set to 0 in the
accumulated over 1.024 sec. Then, the power factor is calculated
CONFIG1 register, an interrupt is generated every DIP_CYC/
on each phase according to this equation:
SWELL_CYC cycles. If DIP_SWELL_IRQ_MODE is set to 1,
one interrupt is generated when dip/swell mode is entered and AWATT accumulated over 1.024 sec
APF =
another interrupt is generated on exit. The mode is changed AVA accumulated over 1.024 sec
after DIP_CYC cycles. Note that if DIP_CYC/SWELL_CYC = 1,
an extra interrupt is generated on exit of the dip/swell condition, The sign of the APF calculation follows the sign of AWATT.
and the dip/swell value, DIPx/SWELLx, is updated at that time, To figure out what quadrant the energy is in, look at the sign of
which exceeds the DIP_LVL/SWELL_LVL value. the total or fundamental reactive energy in that phase along
Overcurrent Indication with the sign of the xPF or xWATT value, as indicated in the
data sheet. Quadrant I and Quadrant III have capacitive power
Overcurrent indication monitors the RMS½ current factors, and Quadrant II and Quadrant IV have inductive power
measurements. If a RMS½ current is greater than the user factors. Note that for most applications, the watts are received
configured OILVL, the overcurrent threshold, this is indicated (imported) from the grid, and therefore the watt and VAR stay
in the OI bit in the STATUS1 register. within Quadrant I and Quadrant IV.
OILVL = xIRMSONE × 2−5
The OC_EN[3:0] bits in the CONFIG3 register select which
phases to monitor for overcurrent events.
VAR
270° LAGGING
A THD calculation is available on the IA, IB, IC, VA, VB, and VC
WATT (–) WATT (+) channels in the AITHD, BITHD, CITHD, AVTHD, BVTHD, and
VAR (–) VAR (–)
QUADRANT III QUADRANT IV CVTHD registers, respectively. Note that a THD measurement is
INDUCTIVE: CAPACITIVE: not available on the IN channel.
CURRENT LAGS CURRENT LEADS
VOLTAGE
TEMPERATURE
VOLTAGE
θ1 = –30° PF1 = 0.866 CAP

The ADE9000 includes a temperature measurement unit that
WATT
V uses a temperature sensor in conjunction with a 12-bit
θ2 = 60° PF2 = 0.5 IND
successive approximation register (SAR) ADC.
CAPACITIVE:
CURRENT LEADS INDUCTIVE: TEMP AVERAGE
CURRENT LAGS SENSOR 12-BIT SAR TSENS_RESULT
15523-040
VOLTAGE I (1,256,512,1024
VOLTAGE
WATT (–) WATT (+)
VAR (+) VAR (+)
QUADRANT II QUADRANT I
90° LAGGING Figure 40. Temperature Measurement Block Diagram
15523-039
WATT(+) INDICATES POWER RECEIVED (IMPORTED FROM GRID) Enable the temperature sensor by setting the TEMP_EN bit in
WATT(–) INDICATES POWER DELIVERED (EXPORTED TO GRID)
the TEMP_CFG register. TEMP_TIME[1:0] allows 1, 256, 512,
Figure 39. Watt and VAR Sign for Capacitive and Inductive Loads
or 1024 temperature readings to be averaged, producing a result
The power factor results is stored in 5.27 format. The highest power after 1.25 ms to 1.3 sec. A temperature acquisition cycle is
factor value is 0x07FF_FFFF, which corresponds to a power factor started by setting the TEMP_START bit in the TEMP_CFG
of 1. A power factor of −1 is stored as 0xF800_0000. To determine register. The result is available in the TEMP_RSLT register. The
the power factor from the xPF register value, use this equation: TEMP_START bit is self clearing. Set the TEMP_START bit to
Power Factor = APF × 2−27 obtain a new reading. Set the TEMP_RDY bit in the MASK0
register to receive an interrupt when a new temperature
Total Harmonic Distortion
measurement is available.
Total harmonic distortion (THD) is calculated once per second
The temperature reading offset and gain is measured during
using total and fundamental rms values, as shown in this
production test and stored in the TEMP_TRIM register. To
equation:
convert the temperature readings in TEMP_RSLT into a
AIRMS 2 − AIFRMS 2 temperature in degrees Celsius, use this equation:
AITHD =
AIFRMS 2 Temperature (°C) = TEMP_RSLT × (−TEMP_GAIN/65536) +
The THD calculation is stored in signed 5.27 format. The (TEMP_OFFSET/32)
highest THD value is 0x2000_0000, which corresponds to a
THD of 400%. To obtain the THD value as a percentage, use
this equation:
%THD on Current Channel A = AITHD × 2−27 × 100%
ACCESSING ON-CHIP DATA

SPI PROTOCOL OVERVIEW SS
The ADE9000 has a SPI-compatible interface, consisting of four

SCLK
pins: SCLK, MOSI, MISO, and SS. The ADE9000 is always a SPI
slave; it never initiates SPI communication. The SPI interface is MOSI
15 0
CMD_HDR = 0x6078
compatible with 16-bit and 32-bit read/write operations. See the
Register Information section for information about the length MISO
31 0 15 0
of each register. BURST_EN = 0

ADDRESS 0x500 TO
AIRMS AT 0x607 32 BITS CRC, 16 BITS
ADDRESS 0x6FF 31 0 31 0
Figure 41 shows the connection between the ADE9000 SPI and MISO
15523-042
BURST_EN = 1, AIRMS AT 0x607 32 BITS BIRMS AT 0x608 32 BITS
a master device that contains a SPI interface. ADDRESS 0x500 TO
ADDRESS 0x6FF
ADE9000 SPI MASTER Figure 42. SPI Read Protocol Example—CRC or Next Data can Follow
MOSI MOSI
The default state of the MOSI pin depends on the master SPI
device. Here, it is assumed to be high (Logic 1).
MISO MISO
SS
SCLK SCK
15523-041
SS CS SCLK
Figure 41. Connecting the ADE9000 Slave SPI Port to a Master SPI Device
CMD_HDR = 0x00B0 AVGAIN AT 0x00B
The SS pin is the chip select input. It is used to start the SPI
communication with the ADE9000.
15523-043
There are three parts to the ADE9000 SPI protocol: first a 16-bit
Figure 43. SPI Write Protocol Example
command is sent, which indicates whether a read or write
operation is to be performed and which register to access. This The maximum serial clock frequency supported by this
command is followed by the 16-bit or 32-bit data to be written, interface is 20 MHz.
in the case of a SPI write, or the data read from the register, in The SPI read/write operation starts with a 16-bit command
the case of a SPI read operation. Finally, in the case of a SPI read (CMD_HDR), which contains the following information:
operation, a cyclic redundancy check (CRC) of the register data
follows, unless the address is in a region that supports burst • CMD_HDR[15:4], the 12 most significant bits of the
reading, in which case the data from the next register follows command header, contains the address of the register
(see the SPI Burst Read section for more information). (ADDR[11:0]) to be read or written.
• CMD_HDR[3] is the bit that specifies if the current
The SS input must stay low for the whole SPI transaction. operation is read/write. Set this bit to 1 for read and 0 for
Bringing SS high during a data transfer operation aborts the write.
transfer. A new transfer can be initiated by returning the SS • CMD_HDR[2:0] are bits that are required for internal chip
logic input low. It is not recommended to tie SS to ground timing and can be 1s or 0s. Note that these bits are read
because the high to low transition on SS starts the ADE9000 SPI back as 000 in the LAST_CMD register.
transaction.
Figure 44 shows the information contained in the command
Data shifts into the device at the MOSI logic input on the falling header.
edge of SCLK, and the device samples the input data on the ADDRESS DON’T CARE
rising edge of SCLK. Data shifts out of the ADE9000 at the TO BE ACCESSED BITS
MISO logic output on the falling edge of SCLK and must be 15 3 2 0
sampled by the master device on the rising edge of SCLK. The ADDR[11:0] R/W xxx[2:0]
most significant bit of the word is shifted in and out first.

15523-044
MISO has an internal weak pull-up of 100 kΩ, making the default READ = 1
WRITE = 0
state of the MISO pin high. It is possible to share the SPI bus with Figure 44. Command Header, CMD_HDR [15:0]
multiple devices, including multiple ADE9000 devices, if desired.
The ADE9000 is compatible with the following microcontroller
SPI port clock polarity and phase settings: CPOL = 0 and
CPHA = 0 (typically Mode 0), or CPOL = 1 and CPHA = 1
(typically Mode 3).
SPI WRITE the ADE9000 stops driving MISO and enables a 100 kΩ weak
A write operation using the SPI interface of the ADE9000 is pull-up. It is recommended to have the SCLK line idle high.
initiated when the SS pin goes low and the ADE9000 receives a An example of what happens when reading the AVGAIN register,
16-bit command header (CMD_HDR) with CMD_HDR[3] Address 0x00B, when BURST_EN = 0 and 1 is shown in Figure 45.
equal to 0. SS
The 16-bit or 32-bit data to be written follows the command

header, with the most significant bit first. SCLK
After the last bit of data has been clocked out, the master must 0
MOSI CMD_HDR = 0x00B8
bring the SS line high to release the SPI bus. It is recommended
to have the SCLK line idle high. 0 15 0
MISO BURST_EN = 0 AVGAIN AT 0x00B CRC, 16 BITS
SPI READ ADDRESS 0x000 TO
ADDRESS 0x6FF 0 31 0
A read operation using the SPI interface of the ADE9000 is
15523-045
MISO BURST_EN = 1, AVGAIN AT 0x00B AVGAIN AT 0x00B
ADDRESS 0x000 TO
initiated when the SS pin goes low and the ADE9000 receives a ADDRESS 0x6FF
16-bit command header (CMD_HDR) with CMD_HDR[3] Figure 45. SPI Read Protocol Example where the Following Data is the CRC
or the Initial Data is Repeated
equal to 1.
The 16-bit or 32-bit data from the register follows the command SPI BURST READ
header, with the most significant bit first. SPI burst read allows multiple registers to be read after sending
The CRC of the register data is appended if one CMD_HDR. After the register data has been clocked out,
the ADE9000 auto-increments the address and starts clocking
• BURST_EN = 0 and the address is within the range of out the data from the next register address.
0x000 to 0x6FF.
SPI burst read access is available on registers with addresses
• BURST_EN = 0 and the address is in the waveform buffer,
ranging from 0x500 0x6FF and in the waveform buffer, with
0x800 to 0xFFF, and BURST_CHAN is equal to 1111 (binary).
Address 0x800 to Address 0xFFF. SPI burst read is not available
The ADE9000 provides a SPI burst read functionality: instead on other register addresses. A SPI burst read operation occurs
of sending the CRC, the following data is from the next address for the options in Table 20 where next address is shown.
if the following conditions apply (see the SPI Burst Read section
To enable burst read functionality on the registers from 0x500
for more information):
to 0x6FF, set the BURST_EN bit in the CONFIG1 register to 1.
• BURST_EN = 1, and the address is within the range of The waveform buffer burst read functionality is enabled by
0x500 to 0x63C or 0x680 to 0x6BC. default and is managed by the BURST_CHAN[3:0] bits of the
• The address is within the range of 0x800 to 0xFFF, and WFB_CFG register. If these bits are set to 1111 (binary), the
BURST_CHAN is not equal to 1111 (binary). burst read functionality of the waveform buffer is disabled. For
If none of these cases apply, and extra clocks are sent, the further details on burst read operation of waveform buffer
original read data is resent. contents, see the Burst Read Waveform Buffer Samples from SPI
section.
Table 20 summarizes which data is sent after the data from the
register addressed in the CMD_HDR; it varies based on the A burst read operation using the SPI interface of the ADE9000
address being accessed and the BURST_EN selection. is initiated when the SS pin goes low and the ADE9000 receives a
16-bit command header (CMD_HDR) with CMD_HDR[3]
Table 20. Data Clocked Out After Addressed Data, in SPI equal to 1, which meets the criteria in Table 20 where next
Read Operation address is shown.
Address BURST_EN = 0 BURST_EN = 1
Following the command header, ADE9000 sends the register
0x000 to 0x4FF CRC Same data is resent
data for the register addressed in the command. After the last
0x500 to 0x6FF CRC Next address
bit of the first register value is received, the ADE9000 auto-
0x800 to 0xFFF If BURST_CHAN = If BURST_CHAN =
increments the address and starts clocking out the data from the
(Waveform Buffer) 1111, CRC; 1111, same data is
otherwise, next resent; otherwise, next next register address. If the starting address is in the range of
address address Address 0x500 to Address 0x516 and the SPI is clocked beyond
Address 0x516, the address is auto-incremented until it reaches
The SS line can be brought high before clocking out the CRC if
Address 0x5FF and then wraps back to the initial address. If the
this information is not needed in the application.
initial address is in the Address 0x600 to Address 0x63C or
After the last bit of data, or CRC, has been clocked out, the Address 0x680 to Address 0x6BC range and the SPI is clocked
master must bring the SS line high to release the SPI bus. Then beyond Address 0x63C or Address 0x6BC, the address wraps
back to the initial address. This process continues until the
master sets the SS line high. Then, the ADE9000 stops driving
MISO and enables a 100 kΩ weak pull-up. It is recommended to
have the SCLK line idle high. An example of a SPI burst read g0 g1 g2 g3 g15
operation is shown in Figure 42, when BURST_EN = 1. For FB

b0 b2 b 15
other examples, see the Burst Read Waveform Buffer Samples 1
LFSR
from SPI section.
15523-048
a31, a30, ..., a2, a1, a0
SPI PROTOCOL CRC
Figure 48. LFSR Generator Used for CRC_SPI Calculation
The ADE9000 SPI port calculates a CRC of the data sent out on
its MOSI pin so that the integrity of the data received by the Figure 48 shows how the LFSR works. The MISO 32-bit data
master can be checked. The CRC of the data sent out on the forms the [a31, a30,…, a0] bits used by the LFSR. Bit a0 is Bit 24 of
MOSI pin during the last register read is offered in a 16-bit the first MISO 32-bit data to enter the LFSR, and the last data to
register, CRC_SPI, and can be appended to the SPI read data as enter the LFSR, Bit a31, corresponds to Bit 7 transmitted on MISO.
part of the SPI transaction. The formulas that govern the LFSR are as follows.
The CRC_SPI register value is appended to the 16-/32-bit data bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that
read from the register addressed in the CMD_HDR for the cases form the CRC. Bit b0 is the least significant bit, and Bit b15 is the
in Table 20 where CRC is written (see the SPI Read section for most significant bit.
more information). gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating
The CRC result can always be read from the CRC_SPI register polynomial defined by the CRC-16-CCITT algorithm as
directly. follows:
There is no CRC checking as part of the SPI write register G(x) = x16 + x12 + x5 + 1 (3)
protocol. To ensure the data integrity of the SPI write operation, g0 = g5 = g12 = 1 (4)
read the register back to verify that the value has been written to
All other gi coefficients are equal to 0.
the ADE9000 correctly.
FB(j) = aj − 1 XOR b15(j − 1) (5)
ADE9000 CRC Algorithm
b0(j) = FB(j) AND g0 (6)
The CRC algorithm implemented within the ADE9000 is based
on the CRC-16-CCITT algorithm. The data output on MISO is bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, …, 15 (7)
introduced into a linear feedback shift register (LFSR)-based Equation 5, Equation 6, and Equation 7 must be repeated for j =
generator one byte at a time, most significant byte first without bit 1, 2, …, 32. The value written into the CRC_SPI register contains
reversal, as shown in Figure 46 and Figure 47. The 16-bit result Bit bi(32), i = 0, 1, …, 15.
is written in the CRC_SPI register.
A similar process is followed for 16-bit data; see Figure 47 for
MISO 32-BIT DATA
information about how the bits are ordered into the LFSR.
31 24 23 16 15
ADDITIONAL COMMUNICATION VERIFICATION
REGISTERS
15 16 23 24 31
LFSR The ADE9000 includes three registers that allow SPI operations to
GENERATOR
15523-046
a31 a0 be verified. The LAST_CMD (Address 0x4A3), LAST_DATA_16

(Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers
Figure 46. CRC Calculation of 32-Bit SPI Data record the received CMD_HDR and last read/transmitted data.
MISO 16-BIT DATA The LAST_DATA_16 register contains the last data read or written
15 8 7 0 during the last 16-bit transaction, and the LAST_DATA_32 register
holds the data read or written during the last 32-bit transaction.
0 7 8 15
The LAST_CMD register is updated after the CMD_HDR is
LFSR
+ GENERATOR received. If a command to read the LAST_CMD, LAST_DATA_16,
15523-047
a15 a0
or LAST_DATA_32 registers is received, these three registers
Figure 47. CRC Calculation of 16-Bit SPI Data
are not updated. Note that LAST_CMD[2:0] always reads back
as 000.
During a SPI read operation, the LAST_DATA_16 and The order in which the registers are calculated is given in Table 21,
LAST_DATA_32 registers are updated within two master clocks with the lowest register introduced first. Note that 32-byte registers
after the CMD_HDR has been received. If a command to read have four bytes introduced into the LFSR, and 16-byte registers
the LAST_CMD, LAST_DATA_16, or LAST_DATA_32 registers have two bytes introduced into the LFSR.
is received, these three registers are not updated.
Table 21. Order of Registers Included in Configuration
Note that the LAST_DATA_16 and LAST_DATA_32 registers Register CRC
are not updated after a SPI burst read operation; these are the Register Addresses Register Length (Bits)
cases in Table 20 where next address is written.
0x01 to 0x18 32
On a write operation, LAST_DATA_16 and LAST_DATA_32 0x21 to 0x38 32
are not updated until all 16 bits or 32 bits of the write data have 0x41 to 0x58 32
been received. Note that on a write register operation, the 0x60 to 0x73 32
addressed register is not written until all 16 bits or 32 bits are 0x409 32
received, depending on the length of the register. 0x40F 32
Note that when the LAST_CMD, LAST_DATA_16, and LAST_ 0x420 to 0x422 32
DATA_32 registers are read, their values remain unchanged. 0x424 32
0x470 to 0x475 32
CRC OF CONFIGURATION REGISTERS 0x480 to 0x481 16
The configuration register CRC feature in the ADE9000 monitors 0x490 to 0x497 16
many register values. It also optionally includes 15 registers that 0x499 16
are individually selectable in the CRC_OPTEN register. 0x4AF to 0x4B2 16
This feature runs as a background task; it takes 10.8 ms to 0x425 32
calculate the configuration register CRC. The result is stored in 0x4B8 to 0x4B9 16
the CRC_RSLT register. If any of the monitored registers change 0x47D 32
value, the CRC_RSLT changes as well, and the CRC_CHG bit in 0x478 to 0x479 32
the STATUS 1 register is set; this can also be configured to 0x4EF 16
generate an interrupt on IRQ1. 0x4BA 16
0x47E 32
After configuring the ADE9000 and writing the required registers 0x00 32
to calibrate the measurements (such as xIGAIN or xVGAIN, for 0x20 32
example), the configuration register CRC calculation can be
0x40 32
started by writing the FORCE_CRC_UPDATE bit in the
0x4B6 16
CRC_FORCE register. When the calculation is complete, the
0x4BF 16
CRC_DONE bit is set in the STATUS1 register.
0x4B5 16
The method used for calculating the configuration register
CRC is also based on the CRC-16-CCITT algorithm. The most
significant byte of each register is introduced into the LFSR first,
without bit reversal.
WAVEFORM BUFFER
The ADE9000 has a waveform buffer comprised of 2048, 32-bit Table 23. 24-Bit Sinc4 and Sinc4 + IIR LPF Data
memory locations with addresses from 0x800 to 0xFFF. This
Bits[31:28] Bits[27:4] Bits[3:0]
memory can be filled with samples from the sinc4 or sinc4 + IIR
SE ADC_DATA[23:0] 0000
LPF, current and voltage waveform samples processed by the
digital signal processor or resampled waveforms.
Table 22 indicates the WFB_SRC selection for each fixed data
Resampled waveforms make it easy to perform harmonic analysis rate waveform source. Each fixed data rate sample is 32-bits;
in an external processor, which can use the 16-bit, 128 points per however, the data format varies between the three sources, as
line cycle samples directly in a FFT, without having to perform shown in Table 22. When the waveform buffer is enabled, the
any windowing functions or changing the FFT coefficients data from all seven channels is stored into the buffer. One
function of line period. sample set consists of one sample per channel, seven samples
The data in the waveform buffer can come from four locations total, which are taken at the same point in time.
in the signal chain: Figure 49 shows how the fixed data rate samples are stored into
 Sinc4 outputs, xI_SINC_DAT, xV_SINC_DAT provided at the buffer. Every sample set is separated in the memory from
32 ksps update rate the adjacent one by the use of spare cells, which do not contain
 Sinc4 + IIR LPF output, xI_LPF_DAT, xV_LPF_DAT any sample data, as shown in Figure 49. In this way, every eighth
provided at 8 ksps update rate 32-bit memory location in the buffer is reserved as a spare cell.
 Current and voltage channel waveforms processed by the If the seventh channel is disabled, with the WF_IN_EN bit in
DSP (xI_PCF, xV_PCF) provided at 8 ksps update rate the WFB_CFG register equal to 0, the IN sample locations are
treated as spare cells as well.
 Resampled waveforms with 128 points per line cycle
processed by the DSP; data rate varies with line period 0 xFFF
IN
Filling and accessing of the waveform buffer depends on which VC
type of data is being filled in the buffer. The waveforms with a IC
fixed data rate, 32 ksps or 8 ksps, are referred to as fixed data

rate waveforms. Refer to the corresponding section to
understand what modes and access are available for resampled
waveforms vs. fixed data rate waveforms.
The waveform buffer samples can be accessed using the SPI
burst read functionality so that multiple samples can be read
0x807
using only one SPI command header (see the Burst Read
0x806 IN
Waveform Buffer Samples from SPI section).
0x805 VC
FIXED DATA RATE WAVEFORMS 0x804 IC
0x803 VB
Fixed data rate waveforms from the signal chain can be stored
0x802 IB
into the waveform buffer from the places shown in Table 22.
0x801 VA
Table 22. Fixed Data Rate Waveform Sources 0x800 IA

31 0
WFB_CFG. Data 32-Bit Data
IN, IF WFB_CFG.WF_IN_EN = 1
Source WF_SRC Rate Format
15523-049
SPARE CELL, IF WFB_CFG.WF_IN_EN = 0

Sinc4 Outputs 0 32 ksps 24 bits, shifted left SPARE CELL
by 4 bits and sign Figure 49. Fixed Data Rate Waveform Sample Storage
extended to 32 bits
Sinc4 + IIR LPF 2 8 ksps 24 bits, shifted left There are 256 (2048/8) sample sets that can be stored in the
Output by 4 bits and sign buffer. In the ADE9000, the sinc4 outputs at 32 ksps, so the
extended to 32 bits buffer can contain (256/32000) = 8 ms of data from the sinc4.
Waveforms 3 8 ksps 5.27 format The sinc4 + IIR LPF samples and DSP processed xI_PCF and
Processed by xV_PCF waveform samples are filled at 8 kHz, and the buffer
the DSP (xI_PCF, can contain 32 ms (256/8000) of this data.
xV_PCF)
When used with fixed data rate samples, the waveform buffer is
The 24-bit sinc4 and sinc4 + IIR LPF data is stored as 32-bit in divided into 16 pages, Page 0 to Page 15. Each page contains
the waveform buffer by shifting by left by 4 bits and sign 128, 32-bit memory locations. Figure 50 illustrates this
extending, as shown in Table 23. arrangement.
0xFFF
The following are the waveform buffer actions that can be
PAGE 15
0xF80
associated with an event when the buffer is filling continuously:
0xF7F
PAGE 14  Stop filling on trigger
0xF00  Center capture around trigger
0xEFF
 Save event address and keep filling
Stop when Buffer is Full Mode
Stop when buffer is full mode is enabled when WF_CAP_SEL = 1
and the WF_MODE[1:0] bits are equal to 00 in the WFB_CFG
register. Set the WF_CAP_EN bit in the WFB_CFG register to
0x9FF start filling the buffer from Address 0x800.
PAGE 3
0x980 When the Address Location 0xFFF in Page 15 is written, the
0x97F
filling operation stops. To receive an indication when the buffer
PAGE 2
0x900 is full, which corresponds to Page 15 being full, set Bit 15 of the
0x8FF
WFB_PG_IRQEN register prior to starting the capture. Then,
PAGE 1
0x880 the PAGE_FULL bit in STATUS0 is set when the buffer is full.
0x87F
This PAGE_FULL status change can be enabled to generate an
15523-050
PAGE 0
interrupt on IRQ0 as well.
0x800
Figure 50. Waveform Buffer Page Arrangement—for Fixed Data Rate To perform the next filling operation, disable the waveform
Samples Only buffer by clearing the WF_CAP_EN bit of the WFB_CFG register
Waveform Buffer Filling Indication—Fixed Data Rate to 0, and enable it again by setting the same bit to 1.
Samples Continuous Fill Mode
The WFB_PG_IRQEN register allows the user to monitor if Continuous fill mode is enabled when WF_CAP_SEL = 1 and
specific pages have been filled, with one bit managing a page of WF_MODE[1:0] in the WFB_CONFIG register is equal to 1, 2,
the buffer: Bit 0 manages Page 0, Bit 1 manages Page 1, and so or 3. Write the WF_CAP_EN bit in the WFB_CONFIG register
on. For example, if Bit 0 and Bit 3 of WFB_PQ_IRQEN are set, to start filling the buffer from Address 0x800.
the user receives an indication when the last address of Page 0,
In this mode, the waveform buffer is filled continuously. When
0x87F, has been written (meaning that Page 0 is full), and when
the entire buffer is filled up to Address Location 0xFFF, the filling
the last address of Page 3, 0x9FF, has been written (meaning
continues from Address Location 0x800 in a circular fashion.
that Page 3 is full). The PAGE_FULL bit of the STATUS0
register is set to 1 when a page enabled in the WFB_PG_IRQEN In this mode, it is important to monitor the filling status of the
register has been filled. The user can enable an interrupt to buffer using the WFB_PG_IRQEN register in conjunction with
occur on IRQ0 when the PAGE_FULL bit is set by setting the the PAGE_FULL bit in the STATUS0 register and the
PAGE_FULL bit in the STATUS0 register. WFB_LAST_PAGE bits in the WFB_TRG_STAT register, as
described in the Waveform Buffer Filling Indication—Fixed
The WFB_LAST_PAGE bits in the WFB_TRG_STAT register
Data Rate Samples section. If the data is not read out of the
indicate which page was filled last when filling with fixed data
buffer soon enough, it is overwritten.
rate samples.
To stop the waveform buffer capture, read the WFB_LAST_
FIXED DATA RATE WAVEFORMS FILLING AND PAGE register, so that the page that contains the most recent
TRIGGER-BASED MODES valid data is known, and then clear the WF_CAP_EN bit in the
The waveform buffer offers different filling modes to be used WFB_CONFIG register to 0.
with fixed data rate samples: To restart the filling operation, disable the waveform buffer by
 Stop when buffer is full clearing the WF_CAP_EN bit of the WFB_CONFIG register if not
 Continuous filling already cleared, and then enable it again by setting this bit to 1.
The ADE9000 allows a selection of events to trigger waveform There are two variations on the continuous fill mode that stop
buffer captures, and there is an option to store the current filling the waveform buffer based on a trigger event: stop filling
waveform buffer address during an event, to allow the user to on trigger mode, and center capture around trigger mode.
synchronize the event with the waveform samples. These modes are selected when WF_MODE[1:0] = 1 and 2,
respectively (see the Stop Filling on Trigger section and the
Center Capture Around Trigger section for more information).
Stop Filling on Trigger 4. Start the capture by writing WF_CAP_EN = 1.
When WF_CAP_SEL = 1 and WF_MODE[1:0] is equal to 1, 5. Wait for the buffer to be filled (indicated by when the
stop filling on trigger mode is selected. Use this mode to PAGE_FULL interrupt occurs or LAST_PAGE = 15).
analyze the ADC samples leading up to an event of interest. 6. When the buffer is filled, enable the desired waveform
buffer events in the WFB_TRG_CFG register and set the
In this mode, the waveform buffer is filled continuously. When WFB_TRIG_IRQ bit in the STATUS0 to generate an
the entire buffer is filled up to Address Location 0xFFF, the interrupt when the event has occurred and the waveform
filling continues from Address Location 0x800 in a circular buffer has stopped filling.
fashion. The events listed in Table 24 are classified as trigger 7. When WFB_TRIG_IRQ occurs, read the WFB_TRIG_ADDR
events. Upon receiving an enabled trigger event, the ADE9000 register to obtain the address of the trigger event, which is
stops filling the waveform buffer. within a sample or two of when the event occurred and is
The events listed in Table 24 can be enabled as waveform buffer the last filled address.
triggers, in the WFB_TRG_CFG register.
Waveform buffer values are retained when the waveform buffer
Table 24. Waveform Buffer Trigger Events in the is disabled by clearing the WF_CAP_EN bit in the WFB_CFG
WFB_TRG_CFG Register register; however, LAST_PAGE and WFB_TRIG_ADDR are
Bit No. Bit Name Description reset when that bit is cleared. Read the LAST_PAGE and
10 TRIG_FORCE Set this bit to trigger an event to stop WFB_TRIG_ADDR registers prior to writing WF_CAP_EN = 0.
the waveform buffer filling The trigger events given in Table 24 must be enabled or disabled
9 ZXCOMB ZXCOMB event prior to enabling the waveform buffer by writing to the
8 ZXVC ZX event in Phase C voltage WFB_TRG_CFG register.
7 ZXVB ZX event in Phase B voltage
Then, to perform the next filling operation in the stop filling
6 ZXVA ZX event in Phase A voltage
on trigger mode, disable the waveform buffer by clearing the
5 ZXIC ZX event in Phase C current
WF_CAP_EN bit of the WFB_CFG register, and then enable it
4 ZXIB ZX event in Phase B current
again by setting the same bit to 1. Note that if the TRIG_FORCE
3 ZXIA ZX event in Phase A current
bit was set to force a trigger, it must be cleared in the
2 OI Overcurrent event
WFB_TRG_CFG register prior to starting the next capture
1 SWELL Swell event
(before writing WF_CAP_EN = 1).
0 DIP Dip event
Center Capture Around Trigger
The trigger events in WFB_TRG_CFG[10:0] correspond to
interrupt events within the ADE9000, with the exception of the The center capture around trigger mode is enabled when
TRIG_FORCE bit. The user can set the TRIG_FORCE bit, WF_CAP_SEL = 1 and WF_MODE[1:0] = 2, and is similar to
WFB_TRG_CFG[10], to stop the filling the waveform buffer in the stop on trigger mode, except that the waveform buffer does
this mode. not stop filling after the trigger event. Even after the occurrence
of the trigger event, the filling of the buffer continues to take
When one of the events configured in WFB_TRG_CFG occurs,
place for the next 1024, 32-bit memory locations before
the filling of the buffer stops and the WFB_TRIG bit is set in
stopping. It is recommended to use this mode to analyze
the STATUS0 register, which can be configured to generate an
samples before and after an event. See the Stop Filling on
interrupt on the IRQ0 pin. The address of the IN waveform of
Trigger section for more information about trigger events.
the last sample set is stored in the WFB_TRIG_ADDR bits of
the WFB_TRG_STAT register. Because the filling stops when Note that in center trigger mode, the WFB_TRIG bit in the
the event occurs, any sample sets with addresses greater than STATUS0 register is set when the enabled trigger event occurs,
the WFB_TRIG_ADDR value contain old data. and the WFB_TRG_IRQ bit in the STATUS0 register is set
when the 1024 additional memory locations have been filled
To ensure that a buffer’s worth of samples has been captured and the waveform buffer filling stops. Both of these status bits
before the event, follow this sequence: can be configured to generate an interrupt on the IRQ0 pin.
1. Select stop capture on trigger mode: WF_CAP_SEL = 1, Calculate the last filled address using WFB_TRIG_ADDR:
WF_MODE = 1.
If (WFB_TRIG_ADDR+1024>0xFFF,
2. Disable all trigger events by writing WFB_TRG_CFG = 0.
Last Filled Address = WFB_TRIG_ADDR-1024;
3. Make sure that the buffer has been filled one time by enabling
an interrupt to occur on IRQ0 when the last page is filled, Else
by setting only Bit 15 in the WFB_PQ_IRQEN register and Last Filled Address = WFB_TRIG_ADDR+1024;
enabling the PAGE_FULL bit in the STATUS0 register.
Alternatively, the LAST_PAGE register can be read instead
of using the interrupt.
To ensure that a buffer’s worth of samples has been captured 0 xFFF IN
before the event, follow this sequence: VC IC

VB IB
1. Select center capture on trigger mode: WF_CAP_SEL = 1, VA IA
WF_MODE = 2.
2. Disable all trigger events by writing WFB_TRG_CFG = 0.
3. Make sure that at least half of the buffer has been filled by
enabling an interrupt to occur on IRQ0 when Page 7 is filled,
by setting only Bit 7 in the WFB_PQ_IRQEN register and
enabling the PAGE_FULL bit in the STATUS0 register.
Alternatively, the LAST_PAGE register can be read instead IN
of using the interrupt. VC IC
4. Start the capture by writing WF_CAP_EN = 1. VB IB
5. Wait for the buffer to be filled (indicated by when the VA IA

IN
PAGE_FULL interrupt occurs or LAST_PAGE = 15).
0x802 VC IC
6. When the buffer is filled, enable the desired waveform
0x801 VB IB
buffer events in the WFB_TRG_CFG register and set the
0x800 VA IA
WFB_TRIG_IRQ bit in the STATUS0 register to generate
31 15 0
an interrupt when the event has occurred and the
IN, IF WF_IN_EN = 1
15523-051
waveform buffer has stopped filling. SPARECELL, IF WF_IN_EN = 0
7. When WFB_TRIG_IRQ occurs, read the SPARE CELL
WFB_TRIG_ADDR register to obtain the address of the Figure 51. Resampled Waveform Sample Storage
trigger event, which is within a sample or two of when the The waveform buffer contains 2048, 32-bit memory locations
event occurred. The last filled address is 1024 samples later. and can hold 512 (2048/4) sets of samples in coherent fill mode.
Save Event Address and Keep Filling In the ADE9000, the buffer is filled with 128 resampled points
per line cycle, which implies that the buffer can hold four line
To record the waveform buffer address when a trigger event cycles’ worth of data at any instant in time(128 × 4 = 512). With
occurs, while still filling the buffer, select WF_MODE = 3 for a 50 Hz line frequency, the buffer contains 80 ms worth of
continuous filling. When a trigger event that is enabled in the resampled data.
WFB_TRG_CFG register occurs, the WFB_TRIG bit in the
STATUS0 register is set, which can be configured to generate an To start filling the waveform buffer with resampled waveforms,
interrupt on the IRQ0 pin. Read the WFB_TRIG_ADDR bits in first clear the WF_CAP_EN bit to disable the waveform buffer.
Then clear the WF_CAP_SEL bit in the WFB_CFG register to
the WFB_TRIG_STAT register to obtain the waveform buffer
select the resampled data to be stored in the waveform buffer.
address for the event. Only the first enabled trigger address is
Finally, set the WF_CAP_EN bit to start the resampling process.
stored; any later trigger events are ignored.
The waveform buffer starts filling from its first address location,
RESAMPLED WAVEFORMS 0x800. When the waveform buffer is full, the COH_WFB_FULL
When resampling is enabled, the data from all seven channels is bit of STATUS 0 goes high, which can be enabled to generate an
calculated and stored into the buffer. One sample set consists of interrupt on IRQ0. Note that this is the only status bit available
one sample per channel, seven samples total, which are from the for the resampled waveforms. The filling of the waveform buffer
same point in time. Each resampled waveforms sample is 16-bits stops.
wide. To obtain a new set of resampled data, first clear the
Figure 51 shows how the resampled waveforms are stored into WF_CAP_EN bit in the WFB_CFG register to 0 and then set
the buffer. Every sample set is separated in memory from the the bit back to 1.
adjacent one by the use of spare cells, as shown in Figure 51. The time taken to fill the buffer depends on the line frequency.
These spare cells do not contain any sample data. There is one The waveform buffer values are retained even when the
16-bit spare cell at the end of every fourth consecutive 32-bit waveform buffer is disabled by clearing the WF_CAP_EN bit
memory location. If the neutral current channel is disabled, the in the WFB_CFG register.
16-bit location that stores IN samples also act as spare cells.
CONFIGURING THE WAVEFORM BUFFER Table 25. Waveform Buffer Burst Read
The waveform source (sinc4, sinc4 + IIR, xI_PCF/xV_PCF, or BURST_CHAN[3:0] Channels to Burst
resampled), type of capture (continuous, single capture, or stop 0000 (default) All channels
on trigger), and fill mode (continuous, one time, or based on 0001 IA and VA
trigger) must be configured in the WFB_CFG register. To 0010 IB and VB
perform this configuration, first disabled the waveform buffer 0011 IC and VC
by writing WF_CAP_EN = 0. Then write the WF_SRC, 1000 IA
WF_CAP_SEL, and WF_MODE bits in the WFB_CFG register. 1001 VA
1010 IB
When the WF_CAP_EN bit is set, the capture is initiated based
1011 VB
on whichever mode is selected by the WF_CAP_SEL and
1100 IC
WF_MODE bits in the WFB_CFG register.
1101 VC
For example, if WF_CAP_SEL = 0, resampled waveforms are 1110 IN if WF_IN_EN = 1 in the WFB_CFG register
stored into the buffer. If WF_CAP_SEL = 1, fixed data rate 1111 Single address read (SPI burst mode is
samples are stored into the buffer, and the WF_MODE bits disabled)
indicate whether the buffer is filled continuously or only one The same BURST_CHAN options are available for both fixed
time, and if trigger events affect the buffer filling. All of these data rate samples and resampled data.
bits must be configured before writing the WF_CAP_EN bit in
the WFB_CFG register. The waveform buffer sample that is read out depends on the
selection in BURST_CHAN and on whether the stored data is
When the waveform buffer is disabled by clearing the fixed data rate data or resampled data.
WF_CAP_EN bit, the waveform buffer data remains valid;
however, the LAST_ADDR and WFB_TRIG_ADDR registers If BURST_CHAN is not equal to 1111 and fixed data rate data
are reset. is stored in the waveform buffer, when WF_CAP_SEL = 1, the
three least significant bits of the address are masked out when
To start a new waveform capture, disable the waveform buffer determining which sample set to read out.
by writing WF_CAP_EN = 0. Then configure the
WF_CAP_SEL and WF_MODE bits as desired by writing to the If BURST_CHAN is not equal to 1111 and resampled data is
WFB_CFG register. Finally, set the WF_CAP_EN bit in the stored in the waveform buffer, when WF_CAP_SEL = 0, the
WFB_CFG register to start the capture. Do not change the two least significant bits of the address are masked out when
WF_CAP_SEL or WF_MODE bits while the WF_CAP_EN bit determining which sample set to read out.
is set. If BURST_CHAN is equal to 1111, whichever address was
written in the CMD_HDR is read out.
BURST READ WAVEFORM BUFFER SAMPLES
FROM SPI These cases are summarized in Table 26.
The waveform buffer contents can be read using SPI burst read Table 26. SPI Address Interpretation when Reading from
mode. SPI burst read mode allows samples of data to be read Waveform Buffer
while only sending one SPI command header. The transfer of Address of Sample Address of Sample
data continues as long as the SS line is kept low and SCLK Set (BURST_CHAN Set (BURST_CHAN
clocks arrive at the ADE9000 SCLK pin. Capture Type ≠ 1111) = 1111)
To make it easier to read out the desired data using the SPI Fixed Data Rate ADDR[11:3] ADDR[11:0]
Samples
burst read functionality, the user can indicate which channels of (WF_CAP_SEL = 1)
data to read out of the waveform buffer by using the Resampled Data ADDR[11:2] ADDR[11:0]
BURST_CHAN bits in the WFB_CFG register, as shown in (WF_CAP_SEL = 0)
Table 25.
Example 1: Fixed Data Rate Data, Seven Channel Samples Example 3: Fixed Data Rate Data, Single Address Read
Mode
WFB_CAP_SEL = 1, WF_IN_EN = 1, and BURST_CHAN = 0000
in the WFB_CFG register indicates that there is fixed data rate WFB_CAP_SEL = 1 and BURST_CHAN = 1111 in the
data in the waveform buffer and the user wants to read out WFB_CFG register indicates that there is fixed data rate data in
samples from all seven channels. A command is sent to read the waveform buffer and the user wants to read out one single
Address 0x801, which is interpreted as a read to the sample set address. A command is sent to read Address 0x801, which is
starting at Address 0x800. The first 32 SPI clocks return IA from interpreted as a read to Address 0x801. VA waveform from
Address 0x800, followed by VA from Address 0x801, and so on, Address 0x801 is transferred, followed by the CRC if
until IN from Address 0x806. Then the sample set auto-increments BURST_EN = 0. If BURST_EN = 1, the VA waveform data from
and the next data is IA from Address 0x808, followed by VA. Address 0x801 is repeated again. This example is shown in
This example is shown in Figure 52. The default state of the Figure 54. The default state of the MOSI pin depends on the
MOSI pin depends on the master SPI device; in Figure 52, it is master SPI device; in Figure 54, it is assumed to be high
assumed to be high (Logic 1). (Logic 1). The transfer of data continues as long as the CS line is
kept low and SCLK clocks arrive at the ADE9000 SCLK pin.
Example2: Resampled Data, Phase C (I and V samples)
Example 4: Resampled Data, Single Address Read Mode
WFB_CAP_SEL = 0 and BURST_CHAN = 0011 in the
WFB_CFG register indicates that there is resampled data in the WFB_CAP_SEL = 0 and BURST_CHAN = 1111 in the
waveform buffer and the user wants to read out IC and VC WFB_CFG register indicates that there is resampled data in the
samples. A command is sent to read Address 0x801, which is waveform buffer and the user wants to read out one single
interpreted as a read to the sample set starting at Address 0x800. address. A command is sent to read Address 0x801, which is
VC waveform from Address 0x802 is first transferred, followed by interpreted as a read to Address 0x801. The first 16 SPI clocks
IC from Address 0x802. Then the sample set auto-increments return the VA waveform from Address 0x801, followed by the
and the next data is VC from Address 0x806, followed by IC IA waveform from Address 0x801, and finally the CRC if
from the same address, then VC from Address 0x80A and IC BURST_EN = 0. If BURST_EN = 1, the VA and IA waveform
from Address 0x80A, and so on (see Figure 53). The default data from Address 0x801 is repeated again (see Figure 55).
state of the MOSI pin depends on the master SPI device; in
Figure 53, it is assumed to be high (Logic 1).
SS
SCLK
MOSI
CMD_HDR = 0x8018
15523-052
MISO
IA AT 0x800, 32 BITS VA AT 0x801, 32 BITS IB AT 0x802,32 BITS VB AT 0x803, 32 BITS IN AT 0x806, 32 BITS IA AT 0x808, 32 BITS
Figure 52. Waveform Buffer SPI Burst Read of Fixed Data Rate Samples, with BURST_CHAN = 0, to Read Out All Channels
SS
SCLK
MOSI CMD_HDR = 0x8018

15523-053
MISO VC AT 0x802, 16 BITS IC AT 0x802, 16 BITS VC AT 0x806, 16 BITS IC AT 0x806, 16 BITS
Figure 53. Waveform Buffer SPI Burst Read of Resampled Data, with BURST_CHAN = 0011, to Read out IC and VC Data
SS
SCLK
15 0
MOSI
CMD_HDR = 0x8018
31 0 15 0
MISO
BURST_EN = 0 VA AT 0x801, 32 BITS CRC, 16 BITS
ADDRESS 0x800 TO 0xFFF
BURST_CHAN = 1111
31 0 31 0
MISO
15523-054
BURST_EN = 1 VA AT 0x801, 32 BITS VA AT 0x801, 32 BITS
BURST_CHAN = 1111
Figure 54. Waveform Buffer SPI Single Address Read of Fixed Rate Data with BURST_CHAN = 1111
SS
SCLK
15 0
MOSI
CMD_HDR = 0x8018
15 0 15 0 15 0
MISO
BURST_EN = 0 VA AT 0x801 IA AT 0x801 CRC, 16 BITS
BURST_CHAN = 1111
15 0 15 0 15 0 15
MISO
15523-055
BURST_EN = 1 VA AT 0x801 IA AT 0x801 VA AT 0x801 IA AT 0x801
BURST_CHAN = 1111
Figure 55. Waveform Buffer SPI Single Address Read of Resampled Data with BURST_CHAN = 1111
SPI CRC when Reading Waveform Buffer SPI Last Data Register when Reading Waveform Buffer
When reading fixed data rate samples, with WF_CAP_SEL = 1, If BURST_CHAN = 1111, the LAST_DATA_32 register is
data read out of the waveform buffer has a CRC calculated, updated after reading a sample in the waveform buffer with the
which is stored into the CRC_SPI register and can be read back value of that 32-bit waveform buffer location.
after the waveform buffer burst read. Note that the LAST_DATA_32 register is not updated when
When reading a single address of waveform buffer data, the reading the waveform buffer samples if BURST_CHAN is not
CRC_SPI is calculated and appended after the 32-bit data, as equal to 1111.
shown in Figure 54.
Note that when reading resampled data out of the waveform
buffer, when WF_CAP_SEL = 0, the SPI_CRC _RSLT register is
not updated. Read the waveform buffer a second time to check
the integrity of the SPI read data.
INTERRUPTS/EVENT
The ADE9000 has three pins, IRQ0, IRQ1, and CF4/EVENT/ There is an option to combine all the interrupts onto a single
DREADY, which can be used as interrupts to the host processor. interrupt pin, IRQ1, instead of using two pins, IRQ0 and IRQ1.
The IRQ0 and IRQ1 pins go low when an enabled interrupt To activate this option, set the IRQ0_ON_IRQ1 bit in the
occurs and stay low until the event is acknowledged by setting CONFIG1 register. Note that the IRQ0 pin still indicates the
the corresponding status bit in the STATUS0 and STATUS1 enabled IRQ0 events while in this mode, and IRQ1 indicates
registers, respectively. The EVENT function, which is both IRQ1 and IRQ0 events.
multiplexed with the CF4 and DREADY options on the The meaning of each individual interrupt source is provided in
CF4/EVENT/DREADY pin, tracks the state of the enabled
the related data sheet section; refer to these sections in the
signals and goes low and high with these internal signals. The ADE9000 data sheet for more information.
EVENT function is useful for measuring the duration of events,
such as dips or swells, externally.
EVENT
The EVENT function is multiplexed with CF4 and DREADY on
INTERRUPTS (IRQ0 AND IRQ1)
the CF4/EVENT/DREADY pin. To enable the EVENT function
The IRQ0 and IRQ1 pins are managed by 32-bit interrupt mask to be output on this pin, write CF4_CFG = 10 in the CONFIG1
registers, MASK0 and MASK1, respectively. Every event that register.
can generate an interrupt has a corresponding bit in the MASK0
There are 16 signals that can be incorporated into the EVENT
or MASK1 register and the STATUS0 or STATUS1 register.
pin and are selected in the EVENT_MASK register. All of these
To enable an interrupt, set the corresponding bit in the events sources are maskable and disabled by default.
MASK0 or MASK1 register to 1. To disable an interrupt, the
corresponding bit in the MASK0 or MASK1 register must be The logic level of the EVENT output is solely dependent on the
cleared to 0. enabled events; it cannot be changed by the user. If any of the 16
events are enabled by setting their corresponding mask bit to 1
The STATUS0 and STATUS1 registers indicate if an event that
in the EVENT_MASK register, the EVENT pin goes low
can generate an interrupt has occurred. If the corresponding bit
whenever one of the enabled events occurs and stays low until
in the MASK0 or MASK1 register is set, an interrupt is generated
all the enabled signals have gone high. Then, the EVENT pin
on the corresponding IRQ0 or IRQ1 pin, and the pin goes low.
goes high. Note that the status sources used to generate the
To determine the source of the interrupt, read the EVENT are not latched; if one event source is selected, the
corresponding STATUS0 or STATUS1 register and identify EVENT pin tracks the status of that source.
which enabled bits are set to 1. To acknowledge the event and
clear bits in the STATUSx register, write to the STATUSx STATUS BITS IN ADDITIONAL REGISTERS
register with the desired bit positions set to 1. Then the Several interrupts are used in conjunction with other status
corresponding IRQ0 or IRQ1 pin goes high. registers.
For example, if a zero-crossing occurs on the Phase A voltage Overcurrent
input and the ZXVA bit is set in the MASK1 register, the IRQ1 The OI bit in the MASK1 register works in conjunction with the
pin goes low, indicating that an enabled event has occurred. To OIPHASE status bits in the OISTATUS register.
acknowledge the event, write a 1 to the ZXVA bit in the
No Load
STATUS1 register, and then the IRQ1 pin goes low. The ZXVA
STATUS1 bit is set regardless of whether the ZXVA bit is The VAFNOLOAD, RFNOLOAD, AFNOLOAD, VANLOAD,
enabled in MASK1. RNLOAD, and ANLOAD bits in the MASK1 register work in
conjunction with additional status bits in the PHNOLOAD register.
There are a few interrupts that are nonmaskable, meaning that
they are generated even if the corresponding bit in the MASKx The following bits in the MASK0 register work with the status
register is 0. These nonmaskable interrupts include RSTDONE bits in the PHSIGN register: REVAPx, REVRPx, and REVPSUMx.
and ERROR0. Read the additional registers to obtain more information when
the corresponding bits are set in the STATUSx register.
APPLYING THE ADE9000 TO DIFFERENT METERING CONFIGURATIONS

The voltage and current waveforms of a polyphase system are 270° LAGGING
defined in the following equations:

VCN
v a (t ) = 2 sin(ωt ) VAN
v b (t ) = 2 sin(ωt − 120  ) IC
180° 0°
v c (t ) = 2 sin(ωt + 120 )
 IA
C
IB
ia (t ) = 2 sin(ωt − θ) A
VBN
ib (t ) = 2 sin(ωt − θ − 120 )
15523-058

N
B 90° LAGGING
ic (t ) = 2 sin(ωt − θ + 120 ) 
Figure 58. 4-Wire Delta Service Vector Diagram
270° LAGGING
To understand how these signals relate to each other, create a
phasor diagram following a convention using lagging phase
angles. Figure 56 shows a common polyphase metering
configuration, the 4-wire wye, with va, vb, and vc defined in the
previous equations. Phase B lags Phase A by 120°, and Phase C
180° 0°
lags Phase A by 240°. Currents are shown at a power factor of 1,
PF = 1, where θ = 0 in the ia, ib, and ic expressions (shown
previously), and the current is in phase with the voltage.
A
270° LAGGING
15523-059
N
B 90° LAGGING
VCN Figure 59. 3-Wire Residential 1PH Service Vector Diagram
IC 270° LAGGING
IA VAN
180° 0°
C
IB
A VBN
N 180° 0°
15523-056
B 90° LAGGING
Figure 56. 4-Wire Wye Service Vector Diagram
The following figures show common metering configurations:

3-wire delta, 4-wire delta, and 3-wire residential and network. N
A 90° LAGGING
The ADE9000 can also measure multiple single-phase circuits.

15523-060
270° LAGGING B
Figure 60. 3-Wire Network Meter Vector Diagram
The phasor diagrams help to understand how the voltages and

VAC VBA
currents are related in time. Figure 61 shows the 4-wire wye voltage
IC
phase sequence in time, corresponding to the Figure 56 phasor
180°
IB
0° diagram and the equations for va, vb, and vc provided previously.
IA
C
PHASE A PHASE B PHASEC
VAN VBN VCN
A
15523-057
90° LAGGING
B
15523-061
Figure 57. 3-Wire Delta Service Vector Diagram
Figure 61. 4-Wire Wye, Voltage Phase Sequence in Time
NON-BLONDEL COMPLIANT METERS IEC meter forms are all Blondel compliant. ANSI has some
Blondel’s theorem states that there must be n − 1 measuring meter forms that are not Blondel compliant, meaning that there
elements in a meter, where n is the number of the wires of the are fewer than n − 1 elements, so that in a 4-wire wye or 4-wire
electric system. In this way, a Blondel compliant 4-wire wye or delta, two voltage and three currents are measured. The
4-wire delta measures three voltages and three currents. In a ADE9000 has provisions to deal with non-Blondel compliant
3-wire delta service, at least two voltages and two currents must meter forms. Use the VCONSEL[2:0] bits in the ACCMODE
be measured to be Blondel compliant. register to select what calculation to use for VB based on the VA
and VC signals.
Table 27. Non-Blondel Compliant Meter Forms

Service Type Non-Blondel Compliant ANSI Meter Form VCONSEL[2:0] VB Calculation
4-Wire Wye, 2 Voltages, 3 Currents 6S, 7S, 14S, 29S, 36S, 46S, 76S 010 VB = −VA − VC
4-Wire Delta, 2 Voltages, 3 Currents 8S, 15S, 24S 011 VB = −VA
APPLYING THE ADE9000 TO A 4-WIRE WYE PHASE A
220V 0°
SERVICE
VAP
For the highest level of performance when measuring a 4-wire PHASE B
wye service, connect the neutral to ground, as shown in 220V –120°
Figure 62. For this configuration, VCONSEL[2:0] = 000. VBP

PHASE A PHASE C
220V 0° 220V 120°
VAP VCP
PHASE B
220V –120°
NEUTRAL
VBP
VAN
PHASE C
220V 120°
VCP VBN
NEUTRAL
VCN
VAN
AGND DGND
VBN
NEUTRAL ATTENUATION
NETWORK

VCN 220V 0° VBN 220V –120° VCN 220V 120°
VCONSEL = 000
VA, VB, VC VA 0.353V 0° VB 0.353V –120° VC 0.353V 120°
AGND DGND
15523-063
VCONSEL = 000 VAN 220V 0° VBN 220V –120° VCN 220V 120°
Figure 63. 4-Wire Wye, Series Impedance on the Neutral
Phase sequence error detection is performed based on the

expected ABC sequence; see the Phase Sequence Error
15523-062
Detection section for more information.

Figure 62. 4-Wire Wye, Neutral Connected to Ground To obtain the overall power consumed by the system (active,
Alternatively, a series impedance can be used on the neutral, as reactive, and apparent), add the contribution from the Phase A,
shown in Figure 63, which can be advantageous if an isolated Phase B, and Phase C accumulations.
power supply is used. Note that this configuration has poor
performance if the phase voltages are not balanced. For more
information, refer to the AN-1334. For this configuration,
VCONSEL[2:0] = 000.
APPLYING THE ADE9000 TO A 3-WIRE DELTA To use the same PCB for both 4-wire wye and 3-wire delta
SERVICE circuits, another option is to wire Phase B to the neutral
terminal of the meter, keeping the same circuit as used in
For the highest level of performance when measuring a 3-wire
Figure 62 or Figure 63. Note that VCONSEL[2:0] must be set to
delta service, connect Phase B to ground, as shown in Figure 64.
001 if it is desired to obtain the VAC rms value, which is
For this configuration, write VCONSEL[2:0] = 00. Then VB =
calculated in the BVRMS register, and to use the correct phase
VA − VC, and the ADE9000 calculates the VAC potential in the
sequence detection method for the 3-wire delta configuration.
BVRMS register. To calculate the current flowing through IB
To calculate the current flowing through IB from the IA and IC
from the IA and IC measurements, set ICONSEL = 1 so that
measurements, set ICONSEL = 1 so that IB = −IA − IC.
IB = −IA − IC.
PHASE A Alternatively, a series impedance can be used on Phase B, as
220V 0°
shown in Figure 66. This configuration can be advantageous if
VAP
an isolated power supply is used; however, the readings are
PHASE B inaccurate in this configuration if the phase voltages are not
220V –120°
balanced. Use VCONSEL[2:0] = 100 with this configuration so
VBP that VA = VA − VB, VB = VA − VC, and VC = VC − VB. To
PHASE C
220V 120° calculate the current flowing through IB from the IA and IC
measurements, set ICONSEL = 1 so that IB = −IA − IC.
VCP
PHASE A
220V 0°
VAP
VAN PHASE B
220V –120°
VBP
VBN
220V 120°
VCP
VCN
AGND DGND
VCONSEL = 001 VAN

VA, VB, VC
VBA 220V 3 30°
VBC 220V 3 90°
VC 0.353V 90° VA 0.353V 30°
VAC 220V 3 150°
VB 0.353V 150° VBN
VCN
15523-064
AGND DGND
Figure 64. 3-Wire Delta, Phase B Connected to Ground VCONSEL[2:0] = 100

CALCULATED VA, VB, VC
Note that for this 3-wire delta, Phase B connected to ground VBC 220V 3 90°
VBA 220V 3 30°
0.353V 30°
configuration, the phasor diagram of the VA, VC, and VB VC 0.353V 90°
VAC 220V 3 150°
waveforms inside the ADE9000 IC, shown in Figure 65, is VB 0.353V 150°
shifted compared to the service diagram shown in Figure 57.

270° LAGGING
15523-066
CV_PCF
Figure 66. 3-Wire Delta, Series Impedance on Phase B and VCONSEL = 100
CI_PCF
AV_PCF The phasor diagram of the VA, VB, and VC waveforms
180° 0° computed inside the ADE9000 for the 3-wire delta with series
AI_PCF
BI_PCF impedance on Phase B and VCONSEL = 100 matches the one
BV_PCF shown in Figure 65.
VCONSEL = 1
Phase sequence error detection is performed with the
expectation that the VC waveform leads VA; see the Phase
15523-065
90° LAGGING Sequence Error Detection section for more information.

Figure 65. Phasor Diagram of xV_PCF and xI_PCF Waveforms Inside the IC
with 3-Wire Delta with Phase B as Ground and VCONSEL = 001
In a Blondel compliant 3-wire delta meter, only the overall APPLYING THE ADE9000 TO A NON-BLONDEL
power consumed by the system is meaningful; the individual COMPLIANT 4-WIRE DELTA SERVICE
phase powers are not meaningful because a line current is
To use the ADE9000 in a non-Blondel compliant 4-wire delta
multiplied by a line to line voltage. To obtain the overall power
service (such as for ANSI meter forms 8S, 15S, and 24S), the
consumed by the system (active, reactive, and apparent), add
Phase A and Phase C voltages are measured and the Phase B
the contribution from Phase A and Phase C.
voltage is calculated, VB = −VA. All three phase currents are
APPLYING THE ADE9000 TO A NON-BLONDEL measured. For this configuration, write VCONSEL[2:0] = 011
COMPLIANT 4-WIRE WYE SERVICE and connect as shown in Figure 68.
To use the ADE9000 in a non-Blondel compliant 4-wire wye PHASE A
220V 30°
service (such as for ANSI meter forms 6S, 7S, 14S, 29S, 36S, 46S,
and 76S), the Phase A and Phase C voltages are measured and VAP
PHASE B
the Phase B voltage is calculated, VB = −VA − VC. All three 220V –150°
phase currents are measured. For this configuration, write
VCONSEL[2:0] = 010 and connect as shown in Figure 67. VBP
PHASE A 220V 120°

220V 0°
VCP
VAP
PHASE B
220V –120°
NEUTRAL
VAN
VBP
PHASE C
220V 120°
VBN
VCP
VCN
NEUTRAL
VAN
AGND DGND
VBN
VCONSEL = 011 VAN 220V 30° VBN 220V –150° VCN 220V 120°
VCN
AGND DGND
15523-068
VCONSEL = 010 VAN 220V 0° VBN 220V –120° VCN 220V 120° Figure 68. Non-Blondel Compliant 3-Wire Delta
The phasor diagram follows Figure 58. Phase sequence error

detection is performed based on the expected ABC sequence;
see the Phase Sequence Error Detection section for more
information.
15523-067
To obtain the total power (active, reactive, and apparent), add

Figure 67. Non-Blondel Compliant 4-Wire Wye
the contribution from Phase A, Phase B, and Phase C.
The phasor diagram follows Figure 56. Phase sequence error
ADE9000 SERVICE TYPE SUMMARY
detection is performed based on the expected ABC sequence;
see the Phase Sequence Error Detection section for more To summarize, the ADE9000 can be used in many different
information. configurations to measure 4-wire wye, 4-wire delta, and 3-wire
delta installations. Table 28 summarizes which VCONSEL[2:0]
To obtain the total power (active, reactive, and apparent), add and ICONSEL settings to use for each configuration.
the contribution from Phase A, Phase B, and Phase C.
Table 28. Service Type and VCONSEL, ICONSEL Setting Summary
ADE9000 Number of Number of
Ground Voltage Sensors Current Sensors
Service Type Reference Figure for Reference Required VCONSEL[2:0] Required ICONSEL
4-Wire Wye Neutral Figure 62 3 000 3 0
4-Wire Wye Isolated Figure 63 3 000 3 0
3-Wire Delta Phase B Figure 64; Figure 62 2 001; 2 0: IB has current sensor
with Phase B tied to VB = VA − VC 1: IB = IA − IC
neutral
3-Wire Delta Isolated Figure 63 with 2 001; 2 0: IB has current sensor
Phase B tied to VB = VA − VC 1: IB = −IA − IC
neutral
3-Wire Delta Isolated Figure 66 2 100; 2 0: IB has current sensor
VA = VA − VB; 1: IB = −IA − IC
VB = VA − VC;
VC = VC − VB
4-Wire Delta Neutral Figure 62 (note that 3 000 3 0
VA and VB phasor
diagram follows
Figure 58)
4-Wire Wye, Neutral Figure 67 2 010; 3 0
Non-Blondel VB = −VA − VC
Compliant
4-Wire Delta, Neutral Figure 68 2 011; 2 0: IB has current sensor
Non-Blondel VB = −VA 1: IB = −IA − IC
Compliant
3-Wire 1PH Neutral Not applicable 1 to 2 000 1 to 2 0
3-Wire Neutral Not applicable 2 000 2 0
Network
Multiple 1PH Neutral Not applicable 3 000 3 0
Circuits
QUICK START
This section describes how to set up the ADE9000 for a 3-phase, 10. If energy is monitored using energy registers, configure the
4-wire wye measurement. Figure 62 shows the typical hardware following registers:
connection for a 3-phase, 4-wire wye configuration.
a. Configure the WATTACC and VARACC bits in the
1. Wait for the RSTDONE interrupt, indicated by the IRQ pin ACCMODE register to select amongst available
going low. accumulation modes (for example: signed, absolute,
2. Configure PSM0 normal power mode by setting the positive, or negative accumulation mode). The default
PM1 pin and the PM0 pin to low. accumulation mode is signed.
3. Configure PGA gain on current and voltage channels using b. Configure the NOLOAD_TMR bits in the EP_CFG
the PGA_GAIN gain register. The default gain on all register and set the ACT_NL_LVL, REACT_NL_LVL,
channels is 1. and APP_NL_LVL level registers to detect no load and
4. Configure the HPFDIS bits in the CONFIG0 register to prevent energy accumulation of noise.
enable/disable the high-pass filter. The high-pass filter is c. Configure the EGY_TMR_MODE bit in the EP_CFG
enabled by default. It is recommended to keep the high- register to select sample (EGY_TMR_MODE = 0) or
pass filter enabled. Set the desired corner frequency for line cycle (EGY_TMR_MODE = 1) accumulation. Set
HPF using the HPF_CRN bits in the CONFIG2 register. the desired samples or half line cycles in the
The default value for HPF_CRN is 6 (1.25 Hz). EGY_TIME register.
5. If Rogowski coils are used as current sensors, enable the d. Configure the EGY_LD_ACCUM bit in the EP_CFG
digital integrator using the INTEN and INITEN bits in the register to add the internal energy register to user energy
CONFIG0 register. Disable the integrator when using register on EGYRDY (EGY_LD_ACCUM = 0), or to
current transformers. The digital integrators are disabled overwrite the user energy register with the internal
by default. energy register value (EGY_LD_ACCUM = 1).
a. If an integrator is enabled, set the DICOEFF register e. Configure the RD_RST_EN bit in the EP_CFG
to 0xFFFFE000. register to enable reset of user energy registers on read
6. Configure the expected fundamental frequency using the (RD_RST_EN = 1), or to disable reset of user energy
SELFREQ bit (50 Hz: SELFREQ = 0, 60 Hz: SELFREQ = 1) registers on read (RD_RST_EN = 0).
in the ACCMODE register, and program the nominal voltage
11. The ADE9000 can provide interrupts for a variety of events
in the VLEVEL register for fundamental calculations.
on the IRQ0 and IRQ1 pins. The MASK0 or MASK1 and
VLEVEL = X × 1,144,084, where X is the dynamic range
that the nominal signal is at with respect to full scale. STATUS0 or STATUS1 registers manage the respective
7. Configure the zero-crossing source for ZX detection. If interrupt pins.
ZX_SRC_SEL = 1 in the CONFIG0 register, data before the 12. See the Power Quality Measurements section to configure
HPF, integrator, and phase compensation is used. If the power quality parameters.
ZX_SRC_SEL = 0, data after the HPF, integrator, and phase 13. See the Waveform Buffer section to configure and use the
compensation is used. It is recommended to have waveform buffer.
ZX_SRC_SEL = 0. 14. Enable the DSP by setting the RUN register = 1, and enable
8. Set VCONSEL = 000 in the ACCMODE register for a energy accumulation by setting the EGY_PWR_EN bit in
3-phase, 4-wire wye configuration. the EP_CFG register = 1.
9. If energy is monitored using the CF outputs, configure the 15. Note that calibration is performed once at typical operating
following registers. Skip this section if the CF outputs are conditions. When the calibration values are computed,
not used. write the constants to registers before enabling the DSP.
16. To prevent any changes to the ADE9000 configuration,
a. Configure the CFxSEL bits in the CFMODE register enable write protection by writing 0x3C64 to the
to select the energy type to monitor. WR_LOCK register.
b. Configure the TERMSELx bits in the COMPMODE
register to select the phases to include in the CF
calculation.
c. Program xTHR to 0x00100000.
d. Compute and program the corresponding CFxDEN
register based on the desired impulses per kilowatt-hour.
e. Configure the CF pulse width using the CF_LCFG
register.
CALIBRATION
The following section describes calibrating the ADE9000 using Therefore, the following gain must be applied to reach the
register readings. The expected register values at full scale are expected value:
used as the reference. AIRMSEXPECTED 4,801,488
GAIN = = = 0.907
Table 29. Full-Scale ADC Codes AIRMSMEASURED 5,294,441
Parameter Full-Scale Codes (Decimal) The AIGAIN register is calculated as follows:
Total and Fundamental IRMS and 52,702,092
AIGAIN = (GAIN − 1) × 227 = −12,482,248 = 0xFF418938
VRMS
Total and Fundamental WATT, 20,694,066 To calibrate AIRMSOS offset register, apply a small current
VAR, and VA typically at 5000:1 or less dynamic range. In this example, the
Fast RMS½ 52,702,092 offset calibration current is 20 mA.
10 Cycle RMS/12 Cycle RMS 52,702,092
After applying offset calibration current, the AIRMS register
Resampled Data 18,196
reading is 70,431.
SYSTEM PARAMETERS The expected AIRMS register reading is
The system is calibrated at nominal operating voltage and current IcalibrationFSP × Full-Scale RMS Codes
using an accurate source. The accuracy of the calibration is less = 0.0002 × 52,702,092 = 10,540.
than or equal to the accuracy of the source. The example shows The AIRMSOS register is calculated as
the calibration for Channel A. The calculations are similar for
AIRMSEXPECTED 2 − AIRMSMEASURED 2
Channel B and Channel C. AIRMSOS =
215
• VNOMINAL = 220 V rms 2
10,540 − 70,431 2
• INOMINAL = 10 A rms = = − 147,992 = 0xFFFDBDE8

215
• Line frequency = 50 Hz
Follow similar steps to obtain the AVGAIN and AVRMSOS
• Current transformer ratio = 3000:1
calibration constants.
• Burden resistor = 20 Ω
• Voltage Divider R1 = 990 kΩ PHASE CALIBRATION
• R2 = 1 kΩ APHCAL0 is the phase calibration register for Channel A.
The current transfer function is 20/3000 = 0.0067 V rms/A rms. To calculate APHCAL0, apply a nominal current and voltage at
a lagging 0.5 power factor such that the active and reactive
The voltage transfer function is 1/(900 + 1) = 0.001 V rms/A rms. energy registers are positive. In this example, the energy
The input at the current ADC pins is 0.0067 × 10 = 0.067 V rms. registers are configured such that EP_CFG = 0x0011 and
The input at the voltage ADC pins is 0.001 × 220 = 0.22 V rms. EGY_TIME = 7999 (1 sec accumulation).
The ADC full-scale voltage at gain = 1 is 0.707 V rms. Read the AWATTHR_HI and AVARHR_HI registers.
The nominal current as a percentage of full scale is Phase Error (ϕ)

IFSP = 0.067/0.707 = 9.47%.  AWATTHR _ HI × sin(60 ) − AVARHR _ HI × cos(60 ) 
= − tan −1  
 AWATTHR _ HI × cos(60 ) + AVARHR _ HI × sin(60 ) 
The nominal voltage as a percentage of full scale is  
VFSP = 0.220/0.707 = 31.1%.  10356 × sin(60 ) − 17585 × cos(60 ) 
= − tan −1   = − 0.49°
RMS CALIBRATION  10356 cos(60 ) + 17585 × sin(60 ) 
 
AIGAIN and AVGAIN are the respective current and voltage Therefore, the phase calibration register is
calibration registers for Channel A.
 sin(ϕ − ω) + sin ω  27
With the nominal voltage and current inputs, read the AIRMS APHCAL0 =  ×2
 sin(2 × ω − ϕ) 
and AVRMS registers. It is recommended to read the rms values  
at zero-crossings for 1 sec and average them for better accuracy.  sin(RADIAN(−0.49) − 0.039) + sin(0.039)  27
= ×2
For this example, the AIRMS register reading is 5,294,441.  sin(2 × 0.039 − RADIAN (−0.49) 
 
The expected AIRMS register reading is = − 13265997 = 0xFF3593B3
IFSP × full-scale rms codes = 0.0947 × 52,702,092 = 4,801,488 APHCAL0 = 0xFF3593B3

Follow similar steps to obtain the BPHCAL0 and CPHCAL0
calibration constants.
POWER CALIBRATION CONVERSION CONSTANTS
APGAIN is the gain calibration register for Phase A. The active, Conversion constants are used to convert ADE9000 register
reactive, and apparent powers in each phase have a common readings into physical parameters. When the device is calibrated
gain register and individual offset calibration registers. to the full-scale ADC codes given in Table 29, the conversion
1. Apply the nominal voltage and current at power factor = 1. constants for the example system are calculated as follows:
2. EP_CFG = 0x0011 and EGY_TIME = 7999 (1 sec μArms 
Current Conversion Constant  
accumulation).  LSB 
3. Read the AWATTHR_HI register. Inominal × 106
4. The APGAIN register value is obtained as follows: =
I FSP × Full−scale RMS codes
APGAIN =
10 × 106
AWATTHR _ HI EXPECTED − AWATTHR _ HI MEASURED =
×2 27
0.0947 × 52,702,092
AWATTHR _ HI MEASURED
= 2.0036 μArms/LSB
AWATTHR_HIEXPECTED
μVrms 
= IFSP × VFSP × Full-Scale Power Codes × Voltage Conversion Constant  
Accumulation Time × 8000 × 2−13  LSB 
= 0.0947 × 0.311 × 20,694,066 × 1 sec × 8000 × 2−13 Vnominal × 106
=
= 595,191 VFSP × Full−scale RMS codes
Let AWATTHR_HIMEASURED = 580,000: 220 × 106
=
595,191 − 580,000 0.311 × 52,702,092
APGAIN = × 2 27 = 3515347 = 0x35A3D3 = 13.4225 μVrms/LSB
580,000
Like the rms offset calibration, the power offset calibration is  mWATT/mVAR/mVA 
Power Conversion Constant  
performed with a small current at 5000:1 or less dynamic range.  LSB 
In this example, the offset calibration current is 20 mA and the Inominal × Vnominal × 10 3
voltage is 220 V. =
I FSP × VFSP × Full−scale RMS codes
1. Apply a nominal voltage and offset calibration current at 10 × 220 × 103
power factor = 1. =
0.0947 × 0.311 × 20,694,066
2. EP_CFG = 0x0013 and EGY_TIME = 1000 (10 sec
= 3.6097 (mWATT/mVAR/mVA)/LSB
accumulation).
3. Read the AWATTHR_HI register.  µWATTHr/µVARHr/µVAHr 
4. AWATTOS is calculated as Energy Conversion Constant  
 LSB 
6
AWATTOS = Inominal × Vnominal × 10
=
AWATTHR _ HI EXPECTED − AWATTHR _ HI MEASURED I FSP × VFSP × Full−scale RMS codes × 2 −13 × 3600
Accumulation Time × f DSP × 2 −13 10 × 220 × 106
=
AWATTHR_HIEXPECTED 0.0947 × 0.311 × 20,694,066 × 2 −13 × 3600
= IcalibrationFSP × VFSP × Full-Scale Power Codes × = 1.0268 (µWATTHr/µVARHr/µVAHr)/LSB
Accumulation Time × 8000 × 2−13 The physical parameters are obtained by multiplying the
= 0.0002 × 0.311 × 20,694,066 × 10 sec × 8000 × 2−13 register readings with the respective conversion constants.
= 12570
For example, if the AIRMS register reading is 10,540,400
12570 − 11,000 decimal codes,
AWATTOS = = 161 = 0xA1
10 × 8000 × 2 −13
Phase A rms current (A rms)
5. To compute AVAROS, apply a nominal voltage and offset = 2.0036 µA rms/LSB × 10,540,400
calibration current at power factor = 0. = 21.12 A rms
Follow similar steps to obtain BPGAIN, BWATTOS, BVAROS,
CPGAIN, CWATTOS, and CVAROS.
REGISTER INFORMATION
Table 30. Register Summary
Address Name Description Reset Access
0x000 AIGAIN Phase A current gain adjust. 0x00000000 R/W
0x001 AIGAIN0 Phase A multipoint gain correction factor. If multipoint gain and phase compensation 0x00000000 R/W
is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor,
AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude
and the MTTHR_Lx and MTTHR_Hx register values.
0x006 APHCAL0 Phase A multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation
is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the
APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms
amplitude and the MTTHR_Lx and MTTHR_Hx register values.
0x00A APHCAL4 Phase A multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
0x00B AVGAIN Phase A voltage gain adjust. 0x00000000 R/W
0x00C AIRMSOS Phase A current rms offset for the filter-based AIRMS calculation. 0x00000000 R/W
0x00D AVRMSOS Phase A voltage rms offset for the filter-based AVRMS calculation. 0x00000000 R/W
0x00E APGAIN Phase A power gain adjust for the AWATT, AVA, AVAR, AFWATT, AFVA, and AFVAR 0x00000000 R/W
calculations.
0x00F AWATTOS Phase A total active power offset correction for the AWATT calculation. 0x00000000 R/W
0x010 AVAROS Phase A total reactive power offset correction for the AVAR calculation. 0x00000000 R/W
0x011 AFWATTOS Phase A fundamental active power offset correction for the AFWATT calculation. 0x00000000 R/W
0x012 AFVAROS Phase A fundamental reactive power offset correction for the AFVAR calculation. 0x00000000 R/W
0x013 AIFRMSOS Phase A current rms offset for the fundamental current rms, AIFRMS calculation. 0x00000000 R/W
0x014 AVFRMSOS Phase A voltage rms offset for the fundamental voltage rms, AVFRMS calculation. 0x00000000 R/W
0x015 AVRMSONEOS Phase A voltage rms offset for the fast RMS½ AVRMSONE calculation. 0x00000000 R/W
0x016 AIRMSONEOS Phase A current rms offset for the fast RMS½ AIRMSONE calculation. 0x00000000 R/W
0x017 AVRMS1012OS Phase A voltage rms offset for the 10 cycle rms/12 cycle rms AVRMS1012 calculation. 0x00000000 R/W
0x018 AIRMS1012OS Phase A current rms offset for the 10 cycle rms/12 cycle rms AIRMS1012 calculation. 0x00000000 R/W
0x020 BIGAIN Phase B current gain adjust. 0x00000000 R/W
0x021 BIGAIN0 Phase B multipoint gain correction factor. If multipoint gain and phase compensation 0x00000000 R/W
BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude
0x026 BPHCAL0 Phase B multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation
BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms
0x02A BPHCAL4 Phase B multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
0x02B BVGAIN Phase B voltage gain adjust. 0x00000000 R/W
0x02C BIRMSOS Phase B current rms offset for the BIRMS calculation. 0x00000000 R/W
0x02D BVRMSOS Phase B voltage rms offset for the BVRMS calculation. 0x00000000 R/W
0x02E BPGAIN Phase B power gain adjust for the BWATT, BVA, BVAR, BFWATT, BFVA, and BFVAR 0x00000000 R/W
calculations.
0x02F BWATTOS Phase B total active power offset correction for the BWATT calculation. 0x00000000 R/W
0x030 BVAROS Phase B total reactive power offset correction for the BVAR calculation. 0x00000000 R/W
0x031 BFWATTOS Phase B fundamental active power offset correction for the BFWATT calculation. 0x00000000 R/W
0x032 BFVAROS Phase B fundamental reactive power offset correction for the BFVAR calculation. 0x00000000 R/W
0x033 BIFRMSOS Phase B current rms offset for the fundamental current rms BIFRMS calculation. 0x00000000 R/W
0x034 BVFRMSOS Phase B voltage rms offset for the fundamental voltage rms BVFRMS calculation. 0x00000000 R/W
0x035 BVRMSONEOS Phase B voltage rms offset for the fast RMS½ BVRMSONE calculation. 0x00000000 R/W
0x036 BIRMSONEOS Phase B current rms offset for the fast RMS½ BIRMSONE calculation. 0x00000000 R/W
0x037 BVRMS1012OS Phase B voltage rms offset for the 10 cycle rms/12 cycle rms BVRMS1012 calculation. 0x00000000 R/W
0x038 BIRMS1012OS Phase B current rms offset for the 10 cycle rms/12 cycle rms BVRMS1012 calculation. 0x00000000 R/W
0x040 CIGAIN Phase C current gain adjust. 0x00000000 R/W
0x041 CIGAIN0 Phase C multipoint gain correction factor. If multipoint gain and phase compensation 0x00000000 R/W
CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude
0x044 CIGAIN3 Phase C Multipoint gain correction factor. If multipoint gain and phase compensation 0x00000000 R/W
0x045 CIGAIN4 Phase C Multipoint gain correction factor. If multipoint gain and phase compensation 0x00000000 R/W
0x046 CPHCAL0 Phase C multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation
CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms
0x04A CPHCAL4 Phase C multipoint phase correction factor. If multipoint phase and gain calibration is 0x00000000 R/W
0x04B CVGAIN Phase C voltage gain adjust. 0x00000000 R/W
0x04C CIRMSOS Phase C current rms offset for the CIRMS calculation. 0x00000000 R/W
0x04D CVRMSOS Phase C voltage rms offset for the CVRMS calculation. 0x00000000 R/W
0x04E CPGAIN Phase C power gain adjust for the CWATT, CVA, CVAR, CFWATT, CFVA, and CFVAR 0x00000000 R/W
calculations.
0x04F CWATTOS Phase C total active power offset correction for the CWATT calculation. 0x00000000 R/W
0x050 CVAROS Phase C total reactive power offset correction for the CVAR calculation. 0x00000000 R/W
0x051 CFWATTOS Phase C fundamental active power offset correction for the CFWATT calculation. 0x00000000 R/W
0x052 CFVAROS Phase C fundamental reactive power offset correction for the CFVAR calculation. 0x00000000 R/W
0x053 CIFRMSOS Phase C current rms offset for the fundamental current rms CIFRMS calculation. 0x00000000 R/W
0x054 CVFRMSOS Phase C voltage rms offset for the fundamental voltage rms CVFRMS calculation. 0x00000000 R/W
0x055 CVRMSONEOS Phase C voltage rms offset for the fast RMS½ CVRMSONE calculation. 0x00000000 R/W
0x056 CIRMSONEOS Phase C current rms offset for the fast RMS½ CIRMSONE calculation. 0x00000000 R/W
0x057 CVRMS1012OS Phase C voltage rms offset for the 10 cycle rms/12 cycle rms CVRMS1012 calculation. 0x00000000 R/W
0x058 CIRMS1012OS Phase C current rms offset for the 10 cycle rms/12 cycle rms CIRMS1012 calculation. 0x00000000 R/W
0x060 CONFIG0 Configuration Register 0. 0x00000000 R/W
0x061 MTTHR_L0 Multipoint phase/gain threshold. If MTEN = 1 in the CONFIG0 register, the 0x00000000 R/W
MTGNTHR_Lx and MTGNTHR_Hx registers set up the ranges in which to apply
each set of corrections, allowing hysteresis. See the Multipoint Phase/Gain
Calibration section for more information.
0x062 MTTHR_L1 Multipoint phase/gain threshold. See MTTHR_L0 for more information. 0x00000000 R/W
0x066 MTTHR_H0 Multipoint phase/gain threshold. See MTTHR_L0 for more information. 0x00000000 R/W
0x06A MTTHR_H4 Multipoint phase/gain threshold. See MTTHR_L0 for more information. 0x00000000 R/W
0x06B NIRMSOS Neutral current rms offset for the NIRMS calculation. 0x00000000 R/W
0x06C ISUMRMSOS Offset correction for the ISUMRMS calculation based on the sum of IA + IB + IC ± IN. 0x00000000 R/W
0x06D NIGAIN Neutral current gain adjust. 0x00000000 R/W
0x06E NPHCAL Neutral current phase compensation. 0x00000000 R/W
0x06F NIRMSONEOS Neutral current rms offset for the fast RMS½ NIRMSONE calculation. 0x00000000 R/W
0x070 NIRMS1012OS Neutral current rms offset for the 10 cycle rms/12 cycle rms NIRMS1012 calculation. 0x00000000 R/W
0x071 VNOM Nominal phase voltage rms used in the computation of apparent power, xVA, 0x00000000 R/W
when the VNOMx_EN bit is set in the CONFIG0 register.
0x072 DICOEFF Value used in the digital integrator algorithm. If the integrator is turned on, with 0x00000000 R/W
INTEN or ININTEN equal to one in the CONFIG0 register, it is recommended to set
this value to 0xFFFFE000.
0x073 ISUMLVL Threshold to compare ISUMRMS against. Configure this register to receive a 0x00000000 R/W
MISMTCH indication in STATUS0 if ISUMRMS exceeds this threshold.
0x20A AI_PCF Instantaneous Phase A current channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x20B AV_PCF Instantaneous Phase A voltage channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x20C AIRMS Phase A filter-based current rms value, updates at 8 kSPS. 0x00000000 R
0x20D AVRMS Phase A filter-based voltage rms value, updates at 8 kSPS. 0x00000000 R
0x20E AIFRMS Phase A current fundamental rms, updates at 8 kSPS. 0x00000000 R
0x20F AVFRMS Phase A voltage fundamental RMS, updates at 8 kSPS. 0x00000000 R
0x210 AWATT Phase A low-pass filtered total active power, updated at 8 kSPS. 0x00000000 R
0x211 AVAR Phase A low-pass filtered total reactive power, updated at 8 kSPS. 0x00000000 R
0x212 AVA Phase A total apparent power, updated at 8 kSPS. 0x00000000 R
0x213 AFWATT Phase A fundamental active power, updated at 8 kSPS. 0x00000000 R
0x214 AFVAR Phase A fundamental reactive power, updated at 8 kSPS. 0x00000000 R
0x215 AFVA Phase A fundamental apparent power, updated at 8 kSPS. 0x00000000 R
0x216 APF Phase A power factor, updated every 1.024 sec. 0x00000000 R
0x217 AVTHD Phase A voltage THD, updated every 1.024 sec. 0x00000000 R
0x218 AITHD Phase A current THD, updated every 1.024 sec. 0x00000000 R
0x219 AIRMSONE Phase A current fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x21A AVRMSONE Phase A voltage fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x21B AIRMS1012 Phase A current fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if
SELFREQ = 1 for a 60 Hz network, in the ACCMODE register.
0x21C AVRMS1012 Phase A voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x21D AMTREGION If multipoint gain and phase compensation is enabled, with MTEN = 1 in the 0x0000000F R
CONFIG0 register, this register indicate which AIGAINx and APHCALx is currently
being used.
0x22A BI_PCF Instantaneous Phase B current channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x22B BV_PCF Instantaneous Phase B voltage channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x22C BIRMS Phase B filter-based current rms value, updates at 8 kSPS. 0x00000000 R
0x22D BVRMS Phase B filter-based voltage rms value, updates at 8 kSPS. 0x00000000 R
0x22E BIFRMS Phase B current fundamental rms, updates at 8 kSPS. 0x00000000 R
0x22F BVFRMS Phase B voltage fundamental rms, updates at 8 kSPS. 0x00000000 R
0x230 BWATT Phase B low-pass filtered total active power, updated at 8 kSPS. 0x00000000 R
0x231 BVAR Phase B low-pass filtered total reactive power, updated at 8 kSPS. 0x00000000 R
0x232 BVA Phase B total apparent power, updated at 8 kSPS. 0x00000000 R
0x233 BFWATT Phase B fundamental active power, updated at 8 kSPS. 0x00000000 R
0x234 BFVAR Phase B fundamental reactive power, updated at 8 kSPS. 0x00000000 R
0x235 BFVA Phase B fundamental apparent power, updated at 8 kSPS. 0x00000000 R
0x236 BPF Phase B power factor, updated every 1.024 sec. 0x00000000 R
0x237 BVTHD Phase B voltage THD, updated every 1.024 sec. 0x00000000 R
0x238 BITHD Phase B current THD, updated every 1.024 sec. 0x00000000 R
0x239 BIRMSONE Phase B current fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x23A BVRMSONE Phase B voltage fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x23B BIRMS1012 Phase B current fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x23C BVRMS1012 Phase B voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x23D BMTREGION If multipoint gain and phase compensation is enabled, with MTEN = 1 in the COFIG0 0x0000000F R
register, this register indicate which BIGAINx and BPHCALx is currently being used.
0x24A CI_PCF Instantaneous Phase C current channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x24B CV_PCF Instantaneous Phase C voltage channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x24C CIRMS Phase C filter-based current rms value, updates at 8 kSPS. 0x00000000 R
0x24D CVRMS Phase C filter-based voltage rms value, updates at 8 kSPS. 0x00000000 R
0x24E CIFRMS Phase C current fundamental rms, updates at 8 kSPS. 0x00000000 R
0x24F CVFRMS Phase C voltage fundamental rms, updates at 8 kSPS. 0x00000000 R
0x250 CWATT Phase C low-pass filtered total active power, updated at 8 kSPS. 0x00000000 R
0x251 CVAR Phase C low-pass filtered total reactive power, updated at 8 kSPS. 0x00000000 R
0x252 CVA Phase C total apparent power, updated at 8 kSPS. 0x00000000 R
0x253 CFWATT Phase C fundamental active power, updated at 8 kSPS. 0x00000000 R
0x254 CFVAR Phase C fundamental reactive power, updated at 8 kSPS. 0x00000000 R
0x255 CFVA Phase C fundamental apparent power, updated at 8 kSPS. 0x00000000 R
0x256 CPF Phase C power factor, updated every 1.024 sec. 0x00000000 R
0x257 CVTHD Phase C voltage THD, updated every 1.024 sec. 0x00000000 R
0x258 CITHD Phase C current total THD, updated every 1.024 sec. 0x00000000 R
0x259 CIRMSONE Phase C current fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x25A CVRMSONE Phase C voltage fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x25B CIRMS1012 Phase C current fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x25C CVRMS1012 Phase C voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x25D CMTREGION If multipoint gain and phase compensation is enabled, with MTEN = 1 in the 0x0000000F R
CONFIG0 register, these bits indicate which CIGAINx and CPHCALx is currently
being used.
0x265 NI_PCF Instantaneous neutral current channel waveform processed by the DSP at 8 kSPS. 0x00000000 R
0x266 NIRMS Neutral current filter-based rms value. 0x00000000 R
0x267 NIRMSONE Neutral current fast RMS½ calculation, one cycle rms updated every half cycle. 0x00000000 R
0x268 NIRMS1012 Neutral current fast 10 cycle rms/12 cycle rms calculation. The calculation is 0x00000000 R
0x269 ISUMRMS Filter-based rms based on the sum of IA + IB + IC ± IN. 0x00000000 R
0x26A VERSION2 This register indicates the version of the metrology algorithms after the user 0x0000000C R
writes run = 1 to start the measurements.
0x2E5 AWATT_ACC Phase A accumulated total active power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x2E6 AWATTHR_LO Phase A accumulated total active energy, LSB. Updated according to the settings 0x00000000 R
in the EP_CFG and EGY_TIME registers.
0x2E7 AWATTHR_HI Phase A accumulated total active energy, MSB. Updated according to the settings in 0x00000000 R
the EP_CFG and EGY_TIME registers.
0x2EF AVAR_ACC Phase A accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x2F0 AVARHR_LO Phase A accumulated total reactive energy, LSB. Updated according to the settings in 0x00000000 R
the EP_CFG and EGY_TIME registers.
0x2F1 AVARHR_HI Phase A accumulated total reactive energy, MSB. Updated according to the settings 0x00000000 R
0x2F9 AVA_ACC Phase A accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x2FA AVAHR_LO Phase A accumulated total apparent energy, LSB. Updated according to the settings 0x00000000 R
0x2FB AVAHR_HI Phase A accumulated total apparent energy, LSB. Updated according to the settings 0x00000000 R
0x303 AFWATT_ACC Phase A accumulated fundamental active power, updated after PWR_TIME 0x00000000 R
8 kSPS samples.
0x304 AFWATTHR_LO Phase A accumulated fundamental active energy, LSB. Updated according to the 0x00000000 R
settings in the EP_CFG and EGY_TIME registers.
0x305 AFWATTHR_HI Phase A accumulated fundamental active energy, MSB. Updated according to the 0x00000000 R
0x30D AFVAR_ACC Phase A accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x30E AFVARHR_LO Phase A accumulated fundamental reactive energy, LSB. Updated according to 0x00000000 R
the settings in the EP_CFG and EGY_TIME registers.
0x30F AFVARHR_HI Phase A accumulated fundamental reactive energy, MSB. Updated according to 0x00000000 R
0x317 AFVA_ACC Phase A accumulated fundamental apparent power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x318 AFVAHR_LO Phase A accumulated fundamental apparent energy, LSB. Updated according to 0x00000000 R
0x319 AFVAHR_HI Phase A accumulated fundamental apparent energy, MSB. Updated according to 0x00000000 R
0x321 BWATT_ACC Phase B accumulated total active power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x322 BWATTHR_LO Phase B accumulated total active energy, LSB. Updated according to the settings 0x00000000 R
0x323 BWATTHR_HI Phase B accumulated total active energy, MSB. Updated according to the settings 0x00000000 R
0x32B BVAR_ACC Phase B accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x32C BVARHR_LO Phase B accumulated total reactive energy, LSB. Updated according to the 0x00000000 R
0x32D BVARHR_HI Phase B accumulated total reactive energy, MSB. Updated according to the 0x00000000 R
0x335 BVA_ACC Phase B accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x336 BVAHR_LO Phase B accumulated total apparent energy, LSB. Updated according to the 0x00000000 R
0x337 BVAHR_HI Phase B accumulated total apparent energy, MSB. Updated according to the 0x00000000 R
0x33F BFWATT_ACC Phase B accumulated fundamental active power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x340 BFWATTHR_LO Phase B accumulated fundamental active energy, LSB. Updated according to the 0x00000000 R
0x341 BFWATTHR_HI Phase B accumulated fundamental active energy, MSB. Updated according to the 0x00000000 R
settings in EP_CFG and EGY_TIME registers.
0x349 BFVAR_ACC Phase B accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x34A BFVARHR_LO Phase B accumulated fundamental reactive energy, LSB. Updated according to 0x00000000 R
0x34B BFVARHR_HI Phase B accumulated fundamental reactive energy, MSB. Updated according to 0x00000000 R
0x353 BFVA_ACC Phase B accumulated fundamental apparent power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x354 BFVAHR_LO Phase B accumulated fundamental apparent energy, LSB. Updated according to 0x00000000 R
0x355 BFVAHR_HI Phase B accumulated fundamental apparent energy, MSB. Updated according to 0x00000000 R
0x35D CWATT_ACC Phase C accumulated total active power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x35E CWATTHR_LO Phase C accumulated total active energy, LSB. Updated according to the settings 0x00000000 R
0x35F CWATTHR_HI Phase C accumulated total active energy, MSB. Updated according to the settings 0x00000000 R
in the P_CFG and EGY_TIME registers.
0x367 CVAR_ACC Phase C accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x368 CVARHR_LO Phase C accumulated total reactive energy, LSB. Updated according to the 0x00000000 R
0x369 CVARHR_HI Phase C accumulated total reactive energy, MSB. Updated according to the 0x00000000 R
0x371 CVA_ACC Phase C accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. 0x00000000 R
0x372 CVAHR_LO Phase C accumulated total apparent energy, LSB. Updated according to the 0x00000000 R
0x373 CVAHR_HI Phase C accumulated total apparent energy, MSB. Updated according to the 0x00000000 R
0x37B CFWATT_ACC Phase C accumulated fundamental active power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x37C CFWATTHR_LO Phase C accumulated fundamental active energy, LSB. Updated according to the 0x00000000 R
0x37D CFWATTHR_HI Phase C accumulated fundamental active energy, MSB. Updated according to the 0x00000000 R
0x385 CFVAR_ACC Phase C accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS 0x00000000 R
samples.
0x386 CFVARHR_LO Phase C accumulated fundamental reactive energy, LSB. Updated according to 0x00000000 R
0x387 CFVARHR_HI Phase C accumulated fundamental reactive energy, MSB. Updated according to 0x00000000 R
0x38F CFVA_ACC Phase C accumulated fundamental apparent power, updated after PWR_TIME 0x00000000 R
8 kSPS samples.
0x390 CFVAHR_LO Phase C accumulated fundamental apparent energy, LSB. Updated according to 0x00000000 R
0x391 CFVAHR_HI Phase C accumulated fundamental apparent energy, MSB. Updated according to 0x00000000 R
0x397 PWATT_ACC Accumulated positive total active power, MSB, from AWATT, BWATT, and CWATT 0x00000000 R
registers, updated after PWR_TIME 8 kSPS samples.
0x39B NWATT_ACC Accumulated Negative total active power, MSB, from AWATT, BWATT, and CWATT 0x00000000 R
0x39F PVAR_ACC Accumulated positive total reactive power, MSB, from AVAR, BVAR, and CVAR 0x00000000 R
0x3A3 NVAR_ACC Accumulated Negative total reactive power, MSB, from AVAR, BVAR, and CVAR 0x00000000 R
0x400 IPEAK Current peak register. 0x00000000 R
0x401 VPEAK Voltage peak register. 0x00000000 R
0x402 STATUS0 Status Register 0. 0x00000000 R/W
0x403 STATUS1 Status Register 1. 0x00000000 R/W
0x404 EVENT_STATUS Event status register. 0x00000000 R
0x405 MASK0 Interrupt Enable Register 0. 0x00000000 R/W
0x406 MASK1 Interrupt Enable Register 1. 0x00000000 R/W
0x407 EVENT_MASK Event enable register. 0x00000000 R/W
0x409 OILVL Over current detection threshold level. 0x00FFFFFF R/W
0x40A OIA Phase A overcurrent RMS½ value. If a phase is enabled, with the OC_ENA bit set 0x00000000 R
in the CONFIG3 register and AIRMSONE greater than the OILVL threshold, this
value is updated.
0x40B OIB Phase B overcurrent RMS½ value. If a phase is enabled, with the OC_ENB bit set 0x00000000 R
in the CONFIG3 register and BIRMSONE greater than the OILVL threshold, this
value is updated.
0x40C OIC Phase C overcurrent RMS½ value. If a phase is enabled, with the OC_ENC bit set 0x00000000 R
in the CONFIG3 register and CIRMSONE greater than the OILVL threshold, this
value is updated.
0x40D OIN Neutral current overcurrent RMS½ value. If enabled, with the OC_ENN bit set in 0x00000000 R
the CONFIG3 register and NIRMSONE greater than the OILVL threshold, this value
is updated.
0x40E USER_PERIOD User configured line period value used for resampling, fast RMS½ and 10 cycle rms/ 0x00500000 R/W
12 cycle rms when the UPERIOD_SEL bit in the CONFIG2 register is set.
0x40F VLEVEL Register used in the algorithm that computes the fundamental active, reactive, 0x00045D45 R/W
and apparent powers as well as the fundamental IRMS and VRMS values.
0x410 DIP_LVL Voltage RMS½ dip detection threshold level. 0x00000000 R/W
0x411 DIPA Phase A voltage RMS½ value during a dip condition. 0x007FFFFF R
0x412 DIPB Phase B voltage RMS½ value during a dip condition. 0x007FFFFF R
0x413 DIPC Phase C voltage RMS½ value during a dip condition. 0x007FFFFF R
0x414 SWELL_LVL Voltage RMS½ swell detection threshold level. 0x00FFFFFF R/W
0x415 SWELLA Phase A voltage RMS½ value during a swell condition. 0x00000000 R
0x416 SWELLB Phase B voltage RMS½ value during a swell condition. 0x00000000 R
0x417 SWELLC Phase C voltage RMS½ value during a swell condition. 0x00000000 R
0x418 APERIOD Line period on Phase A voltage. 0x00A00000 R
0x419 BPERIOD Line period on Phase B voltage. 0x00A00000 R
0x41A CPERIOD Line period on Phase C voltage. 0x00A00000 R
0x41B COM_PERIOD Line period measurement on combined signal from Phase A, Phase B, and 0x00A00000 R
Phase C voltages.
0x41C ACT_NL_LVL No load threshold in the total and fundamental active power datapath. 0x0000FFFF R/W
0x41D REACT_NL_LVL No load threshold in the total and fundamental reactive power datapath. 0x0000FFFF R/W
0x41E APP_NL_LVL No load threshold in the total and fundamental apparent power datapath. 0x0000FFFF R/W
0x41F PHNOLOAD Phase no load register. 0x00000000 R
0x420 WTHR Sets the maximum output rate from the digital to frequency converter for the 0x0000FFFF R/W
total and fundamental active power for the CFx calibration pulse output. It is
recommended to write WTHR = 0x0010_0000.
0x421 VARTHR Sets the maximum output rate from the digital to frequency converter for the 0x0000FFFF R/W
total and fundamental reactive power for the CFx calibration pulse output. It is
recommended to write VARTHR = 0x0010_0000.
0x422 VATHR Sets the maximum output rate from the digital to frequency converter for the 0x0000FFFF R/W
total and fundamental apparent power for the CFx calibration pulse output. It is
recommended to write VATHR = 0x0010_0000.
0x423 LAST_DATA_32 This register holds the data read or written during the last 32-bit transaction on 0x00000000 R
the SPI port.
0x424 ADC_REDIRECT This register allows any ADC output to be redirected to any digital datapath. 0x001FFFFF R/W
0x425 CF_LCFG CFx calibration pulse width configuration register. 0x00000000 R/W
0x472 PART_ID This register identifies the IC. If the ADE9000_ID bit = 1, the IC is the ADE9000. 0x00100000 R
0x474 TEMP_TRIM Temperature sensor gain and offset, calculated during the manufacturing process. 0x00000000 R/W
0x480 RUN Write this register to 1 to start the measurements. 0x0000 R/W
0x481 CONFIG1 Configuration Register 1. 0x0000 R/W
0x482 ANGL_VA_VB Time between positive to negative zero-crossings on Phase A and Phase B voltages. 0x0000 R
0x483 ANGL_VB_VC Time between positive to negative zero-crossings on Phase B and Phase C voltages. 0x0000 R
0x484 ANGL_VA_VC Time between positive to negative zero-crossings on Phase A and Phase C voltages. 0x0000 R
0x485 ANGL_VA_IA Time between positive to negative zero-crossings on Phase A voltage and current. 0x0000 R
0x486 ANGL_VB_IB Time between positive to negative zero-crossings on Phase B voltage and current. 0x0000 R
0x487 ANGL_VC_IC Time between positive to negative zero-crossings on Phase C voltage and current. 0x0000 R
0x488 ANGL_IA_IB Time between positive to negative zero-crossings on Phase A and Phase B current. 0x0000 R
0x489 ANGL_IB_IC Time between positive to negative zero-crossings on Phase B and Phase C current. 0x0000 R
0x48A ANGL_IA_IC Time between positive to negative zero-crossings on Phase A and Phase C current. 0x0000 R
0x48B DIP_CYC Voltage RMS½ dip detection cycle configuration. 0xFFFF R/W
0x48C SWELL_CYC Voltage RMS½ swell detection cycle configuration. 0xFFFF R/W
0x48F OISTATUS Overcurrent status register. 0x0000 R
0x490 CFMODE CFx configuration register. 0x0000 R/W
0x491 COMPMODE Computation mode register. 0x0000 R/W
0x492 ACCMODE Accumulation mode register. 0x0000 R/W
0x493 CONFIG3 Configuration Register 3. 0xF000 R/W
0x494 CF1DEN CF1 denominator register. 0xFFFF R/W
0x498 ZXTOUT Zero-crossing timeout configuration register. 0xFFFF R/W
0x499 ZXTHRSH Voltage channel zero-crossing threshold register. 0x0009 R/W
0x49A ZX_LP_SEL This register selects which zero-crossing and which line period measurement are 0x001E R/W
used for other calculations.
0x49C SEQ_CYC Number of line cycles used for phase sequence detection. It is recommended to 0x00FF R/W
set this register to 1.
0x49D PHSIGN Power sign register. 0x0000 R
0x4A0 WFB_CFG Waveform buffer configuration register. 0x0000 R/W
0x4A1 WFB_PG_IRQEN This register enables interrupts to occur after specific pages of the waveform 0x0000 R/W
buffer are filled.
0x4A2 WFB_TRG_CFG This register enables events to trigger a capture in the waveform buffer. 0x0000 R/W
0x4A3 WFB_TRG_STAT This register indicates the last page that was filled in the waveform buffer and 0x0000 R/W
the location of trigger events.
0x4A4 CONFIG5 Configuration Register 5. 0x0063 R/W
0x4A8 CRC_RSLT This register holds the CRC of the configuration registers. 0x0000 R
0x4A9 CRC_SPI This register holds the 16-bit CRC of the data sent out on the MOSI pin during the 0x0000 R
last SPI register read.
0x4AC LAST_DATA_16 This register holds the data read or written during the last 16-bit transaction on 0x0000 R
the SPI port.
0x4AE LAST_CMD This register holds the address and read/write operation request (CMD_HDR) for 0x0000 R
the last transaction on the SPI port.
0x4AF CONFIG2 Configuration Register 2. 0x0C00 R/W
0x4B0 EP_CFG Energy and power accumulation configuration. 0x0000 R/W
0x4B1 PWR_TIME Power update time configuration. 0x00FF R/W
0x4B2 EGY_TIME Energy accumulation update time configuration. 0x00FF R/W
0x4B4 CRC_FORCE This register forces an update of the CRC of configuration registers. 0x0000 R/W
0x4B5 CRC_OPTEN This register selects which registers are optionally included in the configuration 0x0000 R/W
register CRC feature.
0x4B6 TEMP_CFG Temperature sensor configuration register. 0x0000 R/W
0x4B7 TEMP_RSLT Temperature measurement result. 0x0000 R
0x4B9 PGA_GAIN This register configures the PGA gain for each ADC. 0x0000 R/W
0x4BA CHNL_DIS ADC channel enable/disable. 0x0000 R/W
0x4BF WR_LOCK This register enables the configuration lock feature. 0x0000 R/W
0x4E0 VAR_DIS Enables/disables total reactive power calculation. 0x0000 R/W
0x4F0 RESERVED1 This register is reserved. 0x0000 R
0x4FE Version Version of ADE9000 IC. 0x0040 R
0x500 AI_SINC_DAT Current channel A ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x501 AV_SINC_DAT Voltage channel A ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x502 BI_SINC_DAT Current channel B ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x503 BV_SINC_DAT Voltage channel B ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x504 CI_SINC_DAT Current channel C ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x505 CV_SINC_DAT Voltage channel C ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x506 NI_SINC_DAT Neutral current channel ADC waveforms from the sinc4 output at 32 kSPS. 0x00000000 R
0x510 AI_LPF_DAT Current channel A ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x511 AV_LPF_DAT Voltage channel A ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x512 BI_LPF_DAT Current channel B ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x513 BV_LPF_DAT Voltage channel B ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x514 CI_LPF_DAT Current channel C ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x515 CV_LPF_DAT Voltage channel C ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x516 NI_LPF_DAT Neutral current channel ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. 0x00000000 R
0x600 AV_PCF_1 SPI burst read accessible. Registers organized functionally. See AV_PCF. 0x00000000 R/W
0x601 BV_PCF_1 SPI burst read accessible. Registers organized functionally. See BV_PCF. 0x00000000 R/W
0x602 CV_PCF_1 SPI burst read accessible. Registers organized functionally. See CV_PCF. 0x00000000 R/W
0x603 NI_PCF_1 SPI burst read accessible. Registers organized functionally. See NI_PCF. 0x00000000 R/W
0x604 AI_PCF_1 SPI burst read accessible. Registers organized functionally. See AI_PCF. 0x00000000 R/W
0x605 BI_PCF_1 SPI burst read accessible. Registers organized functionally. See BI_PCF. 0x00000000 R/W
0x606 CI_PCF_1 SPI burst read accessible. Registers organized functionally. See CI_PCF. 0x00000000 R/W
0x607 AIRMS_1 SPI burst read accessible. Registers organized functionally. See AIRMS. 0x00000000 R/W
0x608 BIRMS_1 SPI burst read accessible. Registers organized functionally. See BIRMS. 0x00000000 R/W
0x609 CIRMS_1 SPI burst read accessible. Registers organized functionally. See CIRMS. 0x00000000 R/W
0x60A AVRMS_1 SPI burst read accessible. Registers organized functionally. See AVRMS. 0x00000000 R/W
0x60B BVRMS_1 SPI burst read accessible. Registers organized functionally. See BVRMS. 0x00000000 R/W
0x60C CVRMS_1 SPI burst read accessible. Registers organized functionally. See CVRMS. 0x00000000 R/W
0x60D NIRMS_1 SPI burst read accessible. Registers organized functionally. See NIRMS. 0x00000000 R/W
0x60E AWATT_1 SPI burst read accessible. Registers organized functionally. See AWATT. 0x00000000 R/W
0x60F BWATT_1 SPI burst read accessible. Registers organized functionally. See BWATT. 0x00000000 R/W
0x610 CWATT_1 SPI burst read accessible. Registers organized functionally. See CWATT. 0x00000000 R/W
0x611 AVA_1 SPI burst read accessible. Registers organized functionally. See AVA. 0x00000000 R/W
0x612 BVA_1 SPI burst read accessible. Registers organized functionally. See BVA. 0x00000000 R/W
0x613 CVA_1 SPI burst read accessible. Registers organized functionally. See CVA. 0x00000000 R/W
0x614 AVAR_1 SPI burst read accessible. Registers organized functionally. See AVAR. 0x00000000 R/W
0x615 BVAR_1 SPI burst read accessible. Registers organized functionally. See BVAR. 0x00000000 R/W
0x616 CVAR_1 SPI burst read accessible. Registers organized functionally. See CVAR. 0x00000000 R/W
0x617 AFVAR_1 SPI burst read accessible. Registers organized functionally. See AFVAR. 0x00000000 R/W
0x618 BFVAR_1 SPI burst read accessible. Registers organized functionally. See BFVAR. 0x00000000 R/W
0x619 CFVAR_1 SPI burst read accessible. Registers organized functionally. See CFVAR. 0x00000000 R/W
0x61A APF_1 SPI burst read accessible. Registers organized functionally. See APF. 0x00000000 R/W
0x61B BPF_1 SPI burst read accessible. Registers organized functionally. See BPF. 0x00000000 R/W
0x61C CPF_1 SPI burst read accessible. Registers organized functionally. See CPF. 0x00000000 R/W
0x61D AVTHD_1 SPI burst read accessible. Registers organized functionally. See AVTHD. 0x00000000 R/W
0x61E BVTHD_1 SPI burst read accessible. Registers organized functionally. See BVTHD. 0x00000000 R/W
0x61F CVTHD_1 SPI burst read accessible. Registers organized functionally. See CVTHD. 0x00000000 R/W
0x620 AITHD_1 SPI burst read accessible. Registers organized functionally. See AITHD. 0x00000000 R/W
0x621 BITHD_1 SPI burst read accessible. Registers organized functionally. See BITHD. 0x00000000 R/W
0x622 CITHD_1 SPI burst read accessible. Registers organized functionally. See CITHD. 0x00000000 R/W
0x623 AFWATT_1 SPI burst read accessible. Registers organized functionally. See AFWATT. 0x00000000 R/W
0x624 BFWATT_1 SPI burst read accessible. Registers organized functionally. See BFWATT. 0x00000000 R/W
0x625 CFWATT_1 SPI burst read accessible. Registers organized functionally. See CFWATT. 0x00000000 R/W
0x626 AFVA_1 SPI burst read accessible. Registers organized functionally. See AFVA. 0x00000000 R/W
0x627 BFVA_1 SPI burst read accessible. Registers organized functionally. See BFVA. 0x00000000 R/W
0x628 CFVA_1 SPI burst read accessible. Registers organized functionally. See CFVA. 0x00000000 R/W
0x629 AFIRMS_1 SPI burst read accessible. Registers organized functionally. See AFIRMS. 0x00000000 R/W
0x62A BFIRMS_1 SPI burst read accessible. Registers organized functionally. See BFIRMS. 0x00000000 R/W
0x62B CFIRMS_1 SPI burst read accessible. Registers organized functionally. See CFIRMS. 0x00000000 R/W
0x62C AFVRMS_1 SPI burst read accessible. Registers organized functionally. See AFVRMS. 0x00000000 R/W
0x62D BFVRMS_1 SPI burst read accessible. Registers organized functionally. See BFVRMS. 0x00000000 R/W
0x62E CFVRMS_1 SPI burst read accessible. Registers organized functionally. See CFVRMS. 0x00000000 R/W
0x62F AIRMSONE_1 SPI burst read accessible. Registers organized functionally. See AIRMSONE. 0x00000000 R/W
0x630 BIRMSONE_1 SPI burst read accessible. Registers organized functionally. See BIRMSONE. 0x00000000 R/W
0x631 CIRMSONE_1 SPI burst read accessible. Registers organized functionally. See CIRMSONE. 0x00000000 R/W
0x632 AVRMSONE_1 SPI burst read accessible. Registers organized functionally. See AVRMSONE. 0x00000000 R/W
0x633 BVRMSONE_1 SPI burst read accessible. Registers organized functionally. See BVRMSONE. 0x00000000 R/W
0x634 CVRMSONE_1 SPI burst read accessible. Registers organized functionally. See CVRMSONE. 0x00000000 R/W
0x635 NIRMSONE_1 SPI burst read accessible. Registers organized functionally. See NIRMSONE. 0x00000000 R/W
0x636 AIRMS1012_1 SPI burst read accessible. Registers organized functionally. See AIRMS1012. 0x00000000 R/W
0x637 BIRMS1012_1 SPI burst read accessible. Registers organized functionally. See BIRMS1012. 0x00000000 R/W
0x638 CIRMS1012_1 SPI burst read accessible. Registers organized functionally. See CIRMS1012. 0x00000000 R/W
0x639 AVRMS1012_1 SPI burst read accessible. Registers organized functionally. See AVRMS1012. 0x00000000 R/W
0x63A BVRMS1012_1 SPI burst read accessible. Registers organized functionally. See BVRMS1012. 0x00000000 R/W
0x63B CVRMS1012_1 SPI burst read accessible. Registers organized functionally. See CVRMS1012. 0x00000000 R/W
0x63C NIRMS1012_1 SPI burst read accessible. Registers organized functionally. See NIRMS1012. 0x00000000 R/W
0x680 AV_PCF_2 SPI burst read accessible. Registers organized by phase. See AV_PCF. 0x00000000 R/W
0x681 AI_PCF_2 SPI burst read accessible. Registers organized by phase. See AI_PCF. 0x00000000 R/W
0x682 AIRMS_2 SPI burst read accessible. Registers organized by phase. See AIRMS. 0x00000000 R/W
0x683 AVRMS_2 SPI burst read accessible. Registers organized by phase. See AVRMS. 0x00000000 R/W
0x684 AWATT_2 SPI burst read accessible. Registers organized by phase. See AWATT. 0x00000000 R/W
0x685 AVA_2 SPI burst read accessible. Registers organized by phase. See AVA. 0x00000000 R/W
0x686 AVAR_2 SPI burst read accessible. Registers organized by phase. See AVAR. 0x00000000 R/W
0x687 AFVAR_2 SPI burst read accessible. Registers organized by phase. See AFVAR. 0x00000000 R/W
0x688 APF_2 SPI burst read accessible. Registers organized by phase. See APF. 0x00000000 R/W
0x689 AVTHD_2 SPI burst read accessible. Registers organized by phase. See AVTHD. 0x00000000 R/W
0x68A AITHD_2 SPI burst read accessible. Registers organized by phase. See AITHD. 0x00000000 R/W
0x68B AFWATT_2 SPI burst read accessible. Registers organized by phase. See AFWATT. 0x00000000 R/W
0x68C AFVA_2 SPI burst read accessible. Registers organized by phase. See AFVA. 0x00000000 R/W
0x68D AFIRMS_2 SPI burst read accessible. Registers organized by phase. See AFIRMS. 0x00000000 R/W
0x68E AFVRMS_2 SPI burst read accessible. Registers organized by phase. See AFVRMS. 0x00000000 R/W
0x68F AIRMSONE_2 SPI burst read accessible. Registers organized by phase. See AIRMSONE. 0x00000000 R/W
0x690 AVRMSONE_2 SPI burst read accessible. Registers organized by phase. See AVRMSONE. 0x00000000 R/W
0x691 AIRMS1012_2 SPI burst read accessible. Registers organized by phase. See AIRMS1012. 0x00000000 R/W
0x692 AVRMS1012_2 SPI burst read accessible. Registers organized by phase. See AVRMS1012. 0x00000000 R/W
0x693 BV_PCF_2 SPI burst read accessible. Registers organized by phase. See BV_PCF. 0x00000000 R/W
0x694 BI_PCF_2 SPI burst read accessible. Registers organized by phase. See BI_PCF. 0x00000000 R/W
0x695 BIRMS_2 SPI burst read accessible. Registers organized by phase. See BIRMS. 0x00000000 R/W
0x696 BVRMS_2 SPI burst read accessible. Registers organized by phase. See BVRMS. 0x00000000 R/W
0x697 BWATT_2 SPI burst read accessible. Registers organized by phase. See BWATT. 0x00000000 R/W
0x698 BVA_2 SPI burst read accessible. Registers organized by phase. See BVA. 0x00000000 R/W
0x699 BVAR_2 SPI burst read accessible. Registers organized by phase. See BVAR. 0x00000000 R/W
0x69A BFVAR_2 SPI burst read accessible. Registers organized by phase. See BFVAR. 0x00000000 R/W
0x69B BPF_2 SPI burst read accessible. Registers organized by phase. See BPF. 0x00000000 R/W
0x69C BVTHD_2 SPI burst read accessible. Registers organized by phase. See BVTHD. 0x00000000 R/W
0x69D BITHD_2 SPI burst read accessible. Registers organized by phase. See BITHD. 0x00000000 R/W
0x69E BFWATT_2 SPI burst read accessible. Registers organized by phase. See BFWATT. 0x00000000 R/W
0x69F BFVA_2 SPI burst read accessible. Registers organized by phase. See BFVA. 0x00000000 R/W
0x6A0 BFIRMS_2 SPI burst read accessible. Registers organized by phase. See BFIRMS. 0x00000000 R/W
0x6A1 BFVRMS_2 SPI burst read accessible. Registers organized by phase. See BFVRMS. 0x00000000 R/W
0x6A2 BIRMSONE_2 SPI burst read accessible. Registers organized by phase. See BIRMSONE. 0x00000000 R/W
0x6A3 BVRMSONE_2 SPI burst read accessible. Registers organized by phase. See BVRMSONE. 0x00000000 R/W
0x6A4 BIRMS1012_2 SPI burst read accessible. Registers organized by phase. See BIRMS1012. 0x00000000 R/W
0x6A5 BVRMS1012_2 SPI burst read accessible. Registers organized by phase. See BVRMS1012. 0x00000000 R/W
0x6A6 CV_PCF_2 SPI burst read accessible. Registers organized by phase. See CV_PCF. 0x00000000 R/W
0x6A7 CI_PCF_2 SPI burst read accessible. Registers organized by phase. See CI_PCF. 0x00000000 R/W
0x6A8 CIRMS_2 SPI burst read accessible. Registers organized by phase. See CIRMS. 0x00000000 R/W
0x6A9 CVRMS_2 SPI burst read accessible. Registers organized by phase. See CVRMS. 0x00000000 R/W
0x6AA CWATT_2 SPI burst read accessible. Registers organized by phase. See CWATT. 0x00000000 R/W
0x6AB CVA_2 SPI burst read accessible. Registers organized by phase. See CVA. 0x00000000 R/W
0x6AC CVAR_2 SPI burst read accessible. Registers organized by phase. See CVAR. 0x00000000 R/W
0x6AD CFVAR_2 SPI burst read accessible. Registers organized by phase. See CFVAR. 0x00000000 R/W
0x6AE CPF_2 SPI burst read accessible. Registers organized by phase. See CPF. 0x00000000 R/W
0x6AF CVTHD_2 SPI burst read accessible. Registers organized by phase. See CVTHD. 0x00000000 R/W
0x6B0 CITHD_2 SPI burst read accessible. Registers organized by phase. See CITHD. 0x00000000 R/W
0x6B1 CFWATT_2 SPI burst read accessible. Registers organized by phase. See CFWATT. 0x00000000 R/W
0x6B2 CFVA_2 SPI burst read accessible. Registers organized by phase. See CFVA. 0x00000000 R/W
0x6B3 CFIRMS_2 SPI burst read accessible. Registers organized by phase. See CFIRMS. 0x00000000 R/W
0x6B4 CFVRMS_2 SPI burst read accessible. Registers organized by phase. See CFVRMS. 0x00000000 R/W
0x6B5 CIRMSONE_2 SPI burst read accessible. Registers organized by phase. See CIRMSONE. 0x00000000 R/W
0x6B6 CVRMSONE_2 SPI burst read accessible. Registers organized by phase. See CVRMSONE. 0x00000000 R/W
0x6B7 CIRMS1012_2 SPI burst read accessible. Registers organized by phase. See CIRMS1012. 0x00000000 R/W
0x6B8 CVRMS1012_2 SPI burst read accessible. Registers organized by phase. See CVRMS1012. 0x00000000 R/W
0x6B9 NI_PCF_2 SPI burst read accessible. Registers organized by phase. See NI_PCF. 0x00000000 R/W
0x6BA NIRMS_2 SPI burst read accessible. Registers organized by phase. See NIRMS. 0x00000000 R/W
0x6BB NIRMSONE_2 SPI burst read accessible. Registers organized by phase. See NIRMSONE. 0x00000000 R/W
0x6BC NIRMS1012_2 SPI burst read accessible. Registers organized by phase. See NIRMS1012. 0x00000000 R/W
REGISTER DETAILS
Table 31 details the registers of the ADE9000 that have bit fields. Additional registers listed in Table 30 do not have bit fields.
Table 31. Register Details

Addr. Name Bits Bit Name Settings Description Reset Access
0x060 CONFIG0 [31:14] RESERVED Reserved. 0x0 R
13 DISRPLPF Set this bit to disable the low-pass filter in the 0x0 R/W
total reactive power datapath.
12 DISAPLPF Set this bit to disable the low-pass filter in the 0x0 R/W
total active power datapath.
11 ININTEN Set this bit to enable the digital integrator in the 0x0 R/W
neutral current channel.
10 VNOMC_EN Set this bit to use the nominal phase voltage 0x0 R/W
rms, VNOM, in the computation of Phase C total
apparent power, CVA.
9 VNOMB_EN Set this bit to use the nominal phase voltage 0x0 R/W
rms, VNOM, in the computation of Phase B total
apparent power, BVA.
8 VNOMA_EN Set this bit to use the nominal phase voltage 0x0 R/W
rms, VNOM, in the computation of Phase A total
apparent power, AVA.
7 RMS_SRC_SEL This bit selects which samples are used for the 0x0 R/W
RMS½ and 10 cycle rms/12 cycle rms calculation.
0 xI_PCF waveforms, after the high-pass filter and
integrator.
1 ADC samples, before the high-pass filter and
integrator.
6 ZX_SRC_SEL This bit selects whether data going into the zero- 0x0 R/W
crossing detection circuit comes before the
high-pass filter, integrator, and phase
compensation or afterwards.
0 After the high-pass filter, integrator, and phase
compensation.
1 Before the high-pass filter, integrator, and phase
compensation.
5 INTEN Set this bit to enable the integrators in the phase 0x0 R/W
current channels. The neutral current channel
integrator is managed by the ININTEN bit in the
CONFIG0 register.
4 MTEN Set this bit to enable multipoint phase and gain 0x0 R/W
compensation. If enabled, an additional gain
factor, xIGAIN0 through xIGAIN5, is applied to
the current channel based on the xIRMS current
rms amplitude and the MTTHR_Lx and
MTTHR_Hx register values.
3 HPFDIS Set this bit to disable high-pass filters in all the 0x0 R/W
voltage and current channels.
2 RESERVED Reserved. 0x0 R
[1:0] ISUM_CFG ISUM calculation configuration. 0x0 R/W
00 ISUM = AI_PCF + BI_PCF + CI_PCF (for
approximated neutral current rms calculation).
01 ISUM = AI_PCF + BI_PCF + CI_PCF + NI_PCF (to
determine mismatch between neutral and
phase currents).
10 ISUM = AI_PCF + BI_PCF + CI_PCF − NI_PCF (to
determine mismatch between neutral and
phase currents).
11 ISUM = AI_PCF + BI_PCF + CI_PCF (for
approximated neutral current rms calculation).
0x21D AMTREGION [31:4] RESERVED Reserved. 0x0 R
[3:0] AREGION If multipoint gain and phase compensation is 0xF R
enabled, with MTEN = 1 in the CONFIG0 register,
these bits indicate which AIGAINx and APHCALx
is currently being used
0000 AIGAIN0, APHCAL0.
1111 This feature is disabled because MTEN = 0 in the
CONFIG0 register.
0x23D BMTREGION [31:4] RESERVED Reserved. 0x0 R
[3:0] BREGION If multipoint gain and phase compensation is 0xF R
these bits indicate which BIGAINx and BPHCALx
is currently being used.
0000 BIGAIN0, BPHCAL0.
CONFIG0 register.
0x25D CMTREGION [31:4] RESERVED Reserved. 0x0 R
[3:0] CREGION If multipoint gain and phase compensation is 0xF R
these bits indicate which CIGAINx and CPHCALx
is currently being used.
0000 CIGAIN0, CPHCAL0.
CONFIG0 register.
0x400 IPEAK [31:27] RESERVED Reserved. 0x0 R
[26:24] IPPHASE These bits indicate which phases generate the 0x0 R
IPEAKVAL value. Note that the PEAKSEL, Bits[4:2]
in the CONFIG3 register determine which current
channel to monitor the peak value on. When
IPPHASE, Bit 0 is set to 1, Phase A current is
generated by the IPEAKVAL, Bits[23:0] value.
Similarly, IPPHASE, Bit 1 indicates that the Phase B
and IPPHASE, Bit 2 indicates that the Phase C
current generated the peak value.
[23:0] IPEAKVAL The IPEAK register stores the absolute value of 0x0 R
the peak current. IPEAK is equal to xI_PCF/25.
0x401 VPEAK [31:27] RESERVED Reserved. 0x0 R
[26:24] VPPHASE These bits indicate which phase(s) generate the 0x0 R
VPEAKVAL value. Note that the PEAKSEL,
Bits[4:2] in the CONFIG3 register determine which
voltage channels to monitor the peak value on.
When VPPHASE, Bit 0 is 1, the Phase A voltage
generated the VPEAKVAL, Bits[23:0] value.
Similarly, VPPHASE, Bit 1 indicates Phase B and
VPPHASE, Bit 2 indicates that the Phase C
voltage generated the peak value.
[23:0] VPEAKVAL The VPEAK register stores the absolute value of 0x0 R
the peak voltage. VPEAK is equal to xV_PCF/25.
0x402 STATUS0 [31:26] RESERVED Reserved. 0x0 R
25 TEMP_RDY This bit goes high to indicate when a new 0x0 R/W1
temperature measurement is available.
24 MISMTCH This bit is set to indicate a change in the 0x0 R/W1
relationship between ISUMRMS and ISUMLVL.
23 COH_WFB_FULL This bit is set when the waveform buffer is full 0x0 R/W1
with resampled data, which is selected when
WF_CAP_SEL = 0 in the WFB_CFG register.
22 WFB_TRIG This bit is set when one of the events configured 0x0 R/W1
in WFB_TRIG_CFG occurs.
21 THD_PF_RDY This bit goes high to indicate when the THD and 0x0 R/W1
power factor measurements update, every
1.024 sec.
20 RMS1012RDY This bit is set when the 10 cycle rms/12 cycle rms 0x0 R/W1
values update.
19 RMSONERDY This bit is set when the fast RMS½ values update. 0x0 R/W1
18 PWRRDY This bit is set when the power values in the 0x0 R/W1
xWATT_ACC, xVA_ACC, xVAR_ACC, xFWATT_ACC,
xFVA_ACC, and xFVAR_ACC registers update,
after PWR_TIME 8 kSPS samples.
17 PAGE_FULL This bit is set when a page enabled in the 0x0 R/W1
WFB_PG_IRQEN register is filled with fixed data
rate samples, when WF_CAP_SEL bit in the
WFB_CFG register is equal to zero.
16 WFB_TRIG_IRQ This bit is set when the waveform buffer stops 0x0 R/W1
filling after an event configured in WFB_TRIG_CFG
occurs. This happens with fixed data rate samples
only, when WF_CAP_SEL bit in the WFB_CFG
register is equal to zero.
15 DREADY This bit is set when new waveform samples are 0x0 R/W1
ready. The update rate depends on the data
selected in the WF_SRC bits in the WFB_CFG
register.
14 CF4 This bit is set when a CF4 pulse is issued, when 0x0 R/W1
the CF4 pin goes from a high to low state.
10 REVPSUM4 This bit is set to indicate if the CF4 polarity 0x0 R/W1
changed sign. For example, if the last CF4 pulse
was positive reactive energy and the next CF4
pulse is negative reactive energy, the REVPSUM4
bit is set. This bit is updated when a CF4 pulse is
output, when the CF4 pin goes from high to low.
changed sign. See REVPSUM4.
6 REVRPC This bit indicates if the Phase C total or 0x0 R/W1
fundamental reactive power has changed sign.
The PWR_SIGN_SEL bit in the EP_CFG register
selects whether total or fundamental reactive
power is monitored. This bit is updated when the
power values in the xVAR_ACC and xFVAR_ACC
registers update, after PWR_TIME 8 kSPS samples.
5 REVRPB This bit indicates if the Phase B total or 0x0 R/W1
See REVRPC.
4 REVRPA This bit indicates if the Phase A total or 0x0 R/W1
See REVRPC.
3 REVAPC This bit indicates if the Phase C total or 0x0 R/W1
fundamental active power has changed sign.
The PWR_SIGN_SEL bit in the EP_CFG register
selects whether total or fundamental active power
is monitored. This bit is updated when the power
values in the xWATT_ACC and xFWATT_ACC
registers update, after PWR_TIME 8 kSPS samples.
2 REVAPB This bit indicates if the Phase B total or 0x0 R/W1
See REVAPC.
1 REVAPA This bit indicates if the Phase A total or 0x0 R/W1
See REVAPC.
0 EGYRDY This bit is set when the power values in the 0x0 R/W1
xWATTHR xVAHR, xVARHR, xFVARHR, xFWATTHR,
xFVAHR registers update, after EGY_TIME 8 kSPS
samples or line cycles, depending on the
EGY_TMR_MODE bit in the EP_CFG register.
0x403 STATUS1 31 ERROR3 This bit indicates an error and generates a non- 0x0 R/W1
maskable interrupt. Issue a software or hardware
reset to clear this error.
30 ERROR2 This bit indicates that an error was detected and 0x0 R/W1
corrected. No action is required.
29 ERROR1 This bit indicates an error and generates a non- 0x0 R
28 ERROR0 This bit indicates an error and generates a non- 0x0 R
27 CRC_DONE This bit is set to indicate when the configuration 0x0 R/W1
register CRC calculation is complete, after initiated
by writing the FORCE_CRC_UPDATE bit in the
CRC_FORCE register.
26 CRC_CHG This bit is set if any of the registers monitored by 0x0 R/W1
the configuration register CRC change value. The
CRC_RSLT register holds the new configuration
register CRC value.
25 DIPC This bit is set to indicates Phase C voltage 0x0 R/W1
entered or exited a dip condition.
24 DIPB This bit is set to indicates Phase B voltage 0x0 R/W1
23 DIPA This bit is set to indicates Phase A voltage 0x0 R/W1
22 SWELLC This bit is set to indicates Phase C voltage 0x0 R/W1
entered or exited a swell condition.
21 SWELLB This bit is set to indicates Phase B voltage 0x0 R/W1
20 SWELLA This bit it set to indicates Phase A voltage 0x0 R/W1
18 SEQERR This bit is set to indicate a phase sequence error 0x0 R/W1
on the Phase voltage zero-crossings.
17 OI This bit is set to indicate that an overcurrent 0x0 R/W1
event occurred on one of the phases indicated
in the OISTATUS register.
16 RSTDONE This bit is set to indicate that the IC finished its 0x0 R/W1
power-up sequence after a reset or after
changing between PSM3 operating mode to
PSM0, which indicates that the user can
configure the IC via the SPI port.
15 ZXIC When this bit is set to 1, it indicates a zero- 0x0 R/W1
crossing is detected on Phase C current.
14 ZXIB When this bit is set to 1, it indicates a zero- 0x0 R/W1
crossing is detected on Phase B current.
13 ZXIA When this bit is set to 1, it indicates a zero- 0x0 R/W1
crossing is detected on Phase A current.
12 ZXCOMB When this bit is set, it indicates a zero-crossing is 0x0 R/W1
detected on the combined signal from VA, VB,
and VC.
11 ZXVC When this bit is set, it indicates a zero-crossing is 0x0 R/W1
detected on the Phase C voltage channel.
10 ZXVB When this bit is set, it indicates a zero-crossing is 0x0 R/W1
detected on the Phase B voltage channel.
9 ZXVA When this bit is set, it indicates a zero-crossing is 0x0 R/W1
detected on the Phase A voltage channel.
8 ZXTOVC This bit is set to indicate a zero-crossing timeout 0x0 R/W1
on Phase C. This means that a zero-crossing on
the Phase C voltage is missing.
7 ZXTOVB This bit is set to indicate a zero-crossing timeout 0x0 R/W1
on Phase B. This means that a zero-crossing on
the Phase B voltage is missing.
6 ZXTOVA This bit is set to indicate a zero-crossing timeout 0x0 R/W1
on Phase A. This means that a zero-crossing on
the Phase A voltage is missing.
5 VAFNOLOAD This bit is set when one or more phase 0x0 R/W1
fundamental apparent energy enters or exits
the no load condition. The phase is indicated
in the PHNOLOAD register.
4 RFNOLOAD This bit is set when one or more phase 0x0 R/W1
fundamental reactive energy enters or exits the
no load condition. The phase is indicated in the
PHNOLOAD register.
3 AFNOLOAD This bit is set when one or more phase 0x0 R/W1
fundamental active energy enters or exits the no
load condition. The phase is indicated in the
PHNOLOAD register.
2 VANLOAD This bit is set when one or more phase total 0x0 R/W1
apparent energy enters or exits the no load
condition. The phase is indicated in the
PHNOLOAD register.
1 RNLOAD This bit is set when one or more phase total 0x0 R/W1
reactive energy enters or exits the no load
PHNOLOAD register.
0 ANLOAD This bit is set when one or more phase total 0x0 R/W1
active energy enters or exits the no load
PHNOLOAD register.
0x404 EVENT_STATUS [31:17] RESERVED Reserved. 0x0 R
16 DREADY This bit changes from a zero to a one when new 0x0 R
waveform samples are ready. The update rate
depends on the data selected in the WF_SRC
bits in the WFB_CFG register.
15 VAFNOLOAD This bit is set when the fundamental apparent 0x0 R
energy accumulations in all phases are out of no
load. This bit goes to zero when one or more
phases of total apparent energy accumulation
goes into no load.
14 RFNOLOAD This bit is set when the fundamental reactive 0x0 R
phases of fundamental reactive energy
accumulation goes into no load.
13 AFNOLOAD This bit is set when the fundamental active 0x0 R
phases of fundamental active energy
12 VANLOAD This bit is set when the total apparent energy 0x0 R
accumulations in all phases are out of no load.
This bit goes to zero when one or more phases
of total apparent energy accumulation goes into
no load.
11 RNLOAD This bit is set when the total reactive energy 0x0 R
of total reactive energy accumulation goes into
no load.
10 ANLOAD This bit is set when the total active energy 0x0 R
of total active energy accumulation goes into no
load.
9 REVPSUM4 This bit indicates the sign of the last CF4 pulse. A 0x0 R
zero indicates that the pulse was from negative
energy and a one indicates that the energy was
positive. This bit is updated when a CF4 pulse is
5 SWELLC This bit is equal to one when the Phase C 0x0 R
voltage is in the swell condition and is zero
when it is not in a swell condition.
4 SWELLB This bit is equal to one when the Phase B voltage 0x0 R
is in the swell condition and is zero when it is not
in a swell condition.
3 SWELLA This bit is equal to one when the Phase A 0x0 R
voltage is in the swell condition and is zero
when it is not in a swell condition.
2 DIPC This bit is equal to one when the Phase C 0x0 R
voltage is in the dip condition and is zero when
it is not in a dip condition.
1 DIPB This bit is equal to one when the Phase B voltage 0x0 R
is in the dip condition and is zero when it is not
in a dip condition
0 DIPA This bit is equal to one when the Phase A 0x0 R
voltage is in the dip condition and is zero when
it is not in a dip condition.
0x405 MASK0 [31:26] RESERVED Reserved. 0x0 R
25 TEMP_RDY_MASK Set this bit to enable an interrupt when a new 0x0 R/W
temperature measurement is available.
24 MISMTCH Set this bit to enable an interrupt when there is a 0x0 R/W
change in the relationship between ISUMRMS
and ISUMLVL.
23 COH_WFB_FULL Set this bit to enable an interrupt when the 0x0 R/W
waveform buffer is full with resampled data,
which is selected when WF_CAP_SEL = 0 in the
WFB_CFG register.
22 WFB_TRIG Set this bit to enable an interrupt when one of 0x0 R/W
the events configured in WFB_TRIG_CFG occurs.
21 THD_PF_RDY Set this bit to enable an interrupt when the THD 0x0 R/W
and power factor measurements are updated,
every 1.024 sec.
20 RMS1012RDY Set this bit to enable an interrupt when the 0x0 R/W
10 cycle rms/12 cycle rms values are updated.
19 RMSONERDY Set this bit to enable an interrupt when the fast 0x0 R/W
RMS½ values are updated.
18 PWRRDY Set this bit to enable an interrupt when the 0x0 R/W
power values in the xWATT_ACC, xVA_ACC,
xVAR_ACC, xFWATT_ACC, xFVA_ACC, and
xFVAR_ACC registers update, after PWR_TIME
8 kSPS samples.
17 PAGE_FULL Set this bit to enable an interrupt when a page 0x0 R/W
enabled in the WFB_PG_IRQEN register is filled.
16 WFB_TRIG_IRQ Set this bit to enable an interrupt when This bit 0x0 R/W
is set when the waveform buffer has stopped filling
after an event configured in WFB_TRIG_CFG occurs.
15 DREADY Set this bit to enable an interrupt when new 0x0 R/W
waveform samples are ready. The update rate
depends on the data selected in the WF_SRC bits in
the WFB_CFG register.
14 CF4 Set this bit to enable an interrupt when the CF4 0x0 R/W
pulse is issued, when the CF4 pin goes from a
high to low state.
high to low state.
high to low state.
high to low state.
10 REVPSUM4 Set this bit to enable an interrupt when the CF4 0x0 R/W
polarity changed sign.
6 REVRPC Set this bit to enable an interrupt when the 0x0 R/W
Phase C total or fundamental reactive power has
changed sign.
5 REVRPB Set this bit to enable an interrupt when the 0x0 R/W
Phase C total or fundamental reactive power has
changed sign.
4 REVRPA Set this bit to enable an interrupt when the 0x0 R/W
Phase A total or fundamental reactive power has
changed sign.
3 REVAPC Set this bit to enable an interrupt when the 0x0 R/W
Phase C total or fundamental active power has
changed sign.
2 REVAPB Set this bit to enable an interrupt when the 0x0 R/W
Phase B total or fundamental active power has
changed sign.
1 REVAPA Set this bit to enable an interrupt when the 0x0 R/W
Phase A total or fundamental active power has
changed sign.
0 EGYRDY Set this bit to enable an interrupt when the 0x0 R/W
power values in the xWATTHR, xVAHR xVARHR
xFWATTHR, xFVAHR, and xFVARHR registers
update, after EGY_TIME 8 kSPS samples or line
cycles, depending on the EGY_TMR_MODE bit in
the EP_CFG register.
0x406 MASK1 31 ERROR3 Set this bit to enable an interrupt if ERROR3 occurs. 0x0 R/W
Issue a software reset or hardware reset to clear
this error.
30 ERROR2 Set this bit to enable an interrupt if ERROR2 occurs. 0x0 R/W
29 ERROR1 This interrupt is not maskable. Issue a software 0x0 R/W
reset or hardware reset to clear this error.
28 ERROR0 This interrupt is not maskable. Issue a software 0x0 R/W
reset or hardware reset to clear this error.
27 CRC_DONE Set this bit to enable an interrupt when the 0x0 R/W
configuration register CRC calculation is complete,
after initiated by writing the FORCE_CRC_UPDATE
bit in the CRC_FORCE register.
26 CRC_CHG Set this bit to enable an interrupt if any of the 0x0 R/W
registers monitored by the configuration register
CRC change value. The CRC_RSLT register holds
the new configuration register CRC value.
25 DIPC Set this bit to enable an interrupt when the 0x0 R/W
Phase C voltage enters a dip condition
24 DIPB Set this bit to enable an interrupt when the 0x0 R/W
Phase B voltage enters a dip condition.
23 DIPA Set this bit to enable an interrupt when the 0x0 R/W
Phase A voltage enters a dip condition.
22 SWELLC Set this bit to enable an interrupt when the 0x0 R/W
Phase C voltage enters a swell condition.
21 SWELLB Set this bit to enable an interrupt when the 0x0 R/W
Phase B voltage enters a swell condition.
20 SWELLA Set this bit to enable an interrupt when the 0x0 R/W
Phase A voltage enters a swell condition.
18 SEQERR Set this bit to enable an interrupt when on a 0x0 R/W
phase sequence error on the phase voltage
zero-crossings.
17 OI Set this bit to enable an interrupt when one of 0x0 R/W
the currents enabled in the OC_EN bits in the
CONFIG3 register enters an overcurrent condition.
15 ZXIC Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase C current
channel.
14 ZXIB Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase B current
channel.
13 ZXIA Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase A current
channel.
12 ZXCOMB Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the combined signal
from VA, VB, and VC.
11 ZXVC Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase C voltage
channel.
10 ZXVB Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase B voltage
channel.
9 ZXVA Set this bit to enable an interrupt when a zero- 0x0 R/W
crossing is detected on the Phase A voltage
channel.
8 ZXTOVC Set this bit to enable an interrupt when there is a 0x0 R/W
zero-crossing timeout on Phase C. This means
that a zero-crossing on the Phase C voltage is
missing.
7 ZXTOVB Set this bit to enable an interrupt when there is a 0x0 R/W
zero-crossing timeout on Phase B. This means
that a zero-crossing on the Phase B voltage is
missing.
6 ZXTOVA Set this bit to enable an interrupt when there is a 0x0 R/W
zero-crossing timeout on Phase A. This means
that a zero-crossing on the Phase A voltage is
missing.
5 VAFNOLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase fundamental apparent energy
enters or exits the no load condition.
4 RFNOLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase total reactive energy enters or exits
the no load condition.
3 AFNOLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase fundamental active energy enters or
exits the no load condition.
2 VANLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase total apparent energy enters or exits
1 RNLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase total reactive energy enters or exits
0 ANLOAD Set this bit to enable an interrupt when one or 0x0 R/W
more phase total active energy enters or exits
0x407 EVENT_MASK [31:17] RESERVED Reserved. 0x0 R
16 DREADY Set this bit to enable the EVENT pin to go low 0x0 R/W
when new waveform samples are ready. The
update rate depends on the data selected in
the WF_SRC bits in the WFB_CFG register.
15 VAFNOLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of fundamental
apparent energy accumulation goes into no load.
14 RFNOLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of fundamental
reactive energy accumulation goes into no load.
13 AFNOLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of fundamental active
energy accumulation goes into no load.
12 VANLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of total apparent
11 RNLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of total reactive
10 ANLOAD Set this bit to enable the EVENT pin to go low 0x0 R/W
when one or more phases of total active energy
9 REVPSUM4 Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate if the last CF4 pulse was from negative
energy. This bit is updated when a CF4 pulse is
5 SWELLCEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase C voltage is in a swell
condition.
4 SWELLBEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase B voltage is in a swell
condition.
3 SWELLAEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase A voltage is in a swell
condition.
2 DIPCEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase C voltage is in a dip
condition.
1 DIPBEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase B voltage is in a dip
condition.
0 DIPAEN Set this bit to enable the EVENT pin to go low to 0x0 R/W
indicate that the Phase A voltage is in a dip
condition.
0x409 OILVL [31:24] RESERVED Reserved. 0x0 R
[23:0] OILVL_VAL Over current detection threshold level. 0xFFFFFF R/W
0x40A OIA [31:24] RESERVED Reserved. 0x0 R
[23:0] OI_VAL Phase A overcurrent RMS½ value. If a phase is 0x0 R
enabled, with the OC_ENA bit set in the CONFIG3
register and AIRMSONE greater than the OILVL
threshold, this value is updated.
0x40B OIB [31:24] RESERVED Reserved. 0x0 R
[23:0] OIB_VAL Phase B overcurrent RMS½ value. If a phase is 0x0 R
enabled, with the OC_ENB bit set in the CONFIG3
register and BIRMSONE greater than the OILVL
0x40C OIC [31:24] RESERVED Reserved. 0x0 R
[23:0] OIC_VAL Phase C overcurrent RMS½ value. If a phase is 0x0 R
enabled, with the OC_ENC bit set in the CONFIG3
register and CIRMSONE greater than the OILVL
0x40D OIN [31:24] RESERVED Reserved. 0x0 R
[23:0] OIN_VAL Neutral current overcurrent RMS½ value. If 0x0 R
enabled, with the OC_ENN bit set in the CONFIG3
register and NIRMSONE greater than the OILVL
0x40F VLEVEL [31:24] RESERVED Reserved. 0x0 R
[23:0] VLEVEL_VAL Register used in the algorithm that computes 0x45D45 R/W
the fundamental active, reactive, and apparent
powers, as well as the fundamental IRMS and VRMS
values.
0x410 DIP_LVL [31:24] RESERVED Reserved. 0x0 R
[23:0] DIPLVL Voltage RMS½ dip detection threshold level. 0x0 R/W
0x411 DIPA [31:24] RESERVED Reserved. 0x0 R
[23:0] DIPA_VAL Phase A voltage RMS½ value during a dip 0x7FFFFF R
condition.
0x412 DIPB [31:24] RESERVED Reserved. 0x0 R
[23:0] DIPB_VAL Phase B voltage RMS½ value during a dip 0x7FFFFF R
condition.
0x413 DIPC [31:24] RESERVED Reserved. 0x0 R
[23:0] DIPC_VAL Phase C voltage RMS½ value during a dip 0x7FFFFF R
condition.
0x414 SWELL_LVL [31:24] RESERVED Reserved. 0x0 R
[23:0] SWELLLVL Voltage RMS½ swell detection threshold level. 0xFFFFFF R/W
0x415 SWELLA [31:24] RESERVED Reserved. 0x0 R
[23:0] SWELLA_VAL Phase A voltage RMS½ value during a swell 0x0 R
condition.
0x416 SWELLB [31:24] RESERVED Reserved. 0x0 R
[23:0] SWELLB_VAL Phase B voltage RMS½ value during a swell 0x0 R
condition.
0x417 SWELLC [31:24] RESERVED Reserved. 0x0 R
[23:0] SWELLC_VAL Phase C voltage RMS½ value during a swell 0x0 R
condition.
0x41F PHNOLOAD [31:18] RESERVED Reserved. 0x0 R
17 CFVANL This bit is set if the Phase C fundamental 0x0 R
apparent energy is in no load.
16 CFVARNL This bit is set if the Phase C fundamental reactive 0x0 R
energy is in no load.
15 CFWATTNL This bit is set if the Phase C fundamental active 0x0 R
14 CVANL This bit is set if the Phase C total apparent 0x0 R
13 CVARNL This bit is set if the Phase B total reactive energy 0x0 R
is in no load.
12 CWATTNL This bit is set if the Phase C total active energy is 0x0 R
in no load.
11 BFVANL This bit is set if the Phase B fundamental 0x0 R
10 BFVARNL This bit is set if the Phase B fundamental reactive 0x0 R
9 BFWATTNL This bit is set if the Phase B fundamental active 0x0 R
8 BVANL This bit is set if the Phase B total apparent 0x0 R
7 BVARNL This bit is set if the Phase B total reactive energy 0x0 R
is in no load.
6 BWATTNL This bit is set if the Phase B total active energy is 0x0 R
in no load.
5 AFVANL This bit is set if the Phase A fundamental 0x0 R
4 AFVARNL This bit is set if the Phase A fundamental reactive 0x0 R
3 AFWATTNL This bit is set if the Phase A fundamental active 0x0 R
2 AVANL This bit is set if the Phase A total apparent 0x0 R
1 AVARNL This bit is set if the Phase A total reactive energy 0x0 R
is in no load.
0 AWATTNL This bit is set if the Phase A total active energy is 0x0 R
in no load.
0x424 ADC_REDIRECT [31:21] RESERVED Reserved. 0x0 R
[20:18] VC_DIN VC channel data can be selected from all channels. 0x7 R/W
The bit descriptions for 000b through 110b match
VC_DIN. When the value is equal to 111b, then
000 IA ADC data.
001 IB ADC data.
010 IC ADC data.
011 IN ADC data.
100 VA ADC data.
101 VB ADC data.
110 VC ADC data.
111 VC ADC data.
[17:15] VB_DIN VB channel data can be selected from all channels. 0x7 R/W
111 VB ADC data.
[14:12] VA_DIN VA channel data can be selected from all channels. 0x7 R/W
111 VA ADC data.
[11:9] IN_DIN IN channel data can be selected from all channels. 0x7 R/W
111 IN ADC data.
[8:6] IC_DIN IC channel data can be selected from all channels. 0x7 R/W
111 IC ADC data.
[5:3] IB_DIN IB channel data can be selected from all channels. 0x7 R/W
111 IB ADC data.
[2:0] IA_DIN IA channel data can be selected from all channels. 0x7 R/W
111 IA ADC data.
0x425 CF_LCFG [31:23] RESERVED Reserved. 0x0 R
22 CF4_LT If this bit is set, the CF4 pulse width is determined 0x0 R/W
by the CF_LTMR register value. If this bit is equal
to zero, then the active low pulse width is set at
80 ms for frequencies lower than 6.25 Hz.
to zero, the active low pulse width is set at 80 ms
for frequencies lower than 6.25 Hz.
[18:0] CF_LTMR If the CFx_LT bit in the CF_LCFG register is set, 0x0 R/W
this value determines the active low pulse width
of the CFx pulse.
0x472 PART_ID [31:21] RESERVED Reserved. 0x0 R
20 ADE9000_ID This bit is set to identify an ADE9000 IC. 0x1 R
[19:0] RESERVED Reserved. 0x0 R
0x474 TEMP_TRIM [31:16] TEMP_OFFSET Offset of temperature sensor, calculated during 0x0 R/W
the manufacturing process.
[15:0] TEMP_GAIN Gain of temperature sensor, calculated during 0x0 R/W
the manufacturing process.
0x481 CONFIG1 15 EXT_REF Set this bit if using an external voltage reference. 0x0 R/W
12 IRQ0_ON_IRQ1 Set this bit to combine all the interrupts onto a 0x0 R/W
single interrupt pin, IRQ1, instead of using two
pins, IRQ0 and IRQ1. Note that the IRQ0 pin still
indicates the enabled IRQ0 events while in this
mode and the IRQ1pin indicates both IRQ1 and
IRQ0 events.
11 BURST_EN Set this bit to enable burst read functionality on 0x0 R/W
the registers from Address 0x500 to Address 0x63C
or Address 0x680 to Address 0x6BC. Note that this
bit disables the CRC being appended to SPI
register reads.
10 DIP_SWELL_IRQ_MODE Set interrupt mode for dip/swell. 0x0 R/W
0 Receive continuous interrupts after every
DIP_CYC/SWELL_CYC cycles.
1 Receive one interrupt when entering dip/swell
mode and another interrupt when exiting
dip/swell mode.
[9:8] PWR_SETTLE These bits configure the time for the power and 0x0 R/W
filter-based rms measurements to settle before
starting the power, energy, and CF accumulations.
0: 64 ms.
1: 128 ms.
2: 256 ms.
3: 0 ms.
5 CF_ACC_CLR Set this bit to clear the accumulation in the digital 0x0 W
to frequency converter and the CFDEN counter.
Note that this bit automatically clears itself.
[3:2] CF4_CFG These bits select which function to output on 0x0 R/W
the CF4 pin.
00 CF4, from digital to frequency converter.
10 EVENT.
11 DREADY.
1 CF3_CFG This bit selects which function to output on the 0x0 R/W
CF3 pin.
1 Zero-crossing output selected by the ZX_SEL bits
in the ZX_LP_SEL register.
0 SWRST Set this bit to initiate a software reset. Note that 0x0 W1
this bit is self clearing.
0x48F OISTATUS [15:4] RESERVED Reserved. 0x0 R
[3:0] OIPHASE OIPHASE, Bit 0 indicates Phase A is above OILVL. 0x0 R
OIPHASE, Bit 1 indicates Phase B is above OILVL.
OIPHASE, Bit 2 indicates Phase C is above OILVL.
OIPHASE, Bit 3 indicates Phase N is above OILVL.
0x490 CFMODE 15 CF4DIS CF4 output disable. Set this bit to disable the 0x0 R/W
CF4 output and bring the pin high. Note that
when this bit is set, the CFx bit in STATUS0 is not
set when a CF pulse is accumulated in the digital
to frequency converter.
14 CF3DIS CF3 output disable. See CF4DIS. 0x0 R/W
13 CF2DIS CF2 output disable. See CF4DIS. 0x0 R/W
12 CF1DIS CF1 output disable. See CF4DIS 0x0 R/W
[11:9] CF4SEL Type of energy output on the CF4 pin. Configure 0x0 R/W
TERMSEL4 in the COMPMODE register to select
which phases are included.
000 Total active power.
001 Total reactive power.
010 Total apparent power.
011 Fundamental active power.
100 Fundamental reactive power.
101 Fundamental apparent power.
[8:6] CF3SEL Selects type of energy output on CF3 pin. See 0x0 R/W
CF4SEL.
CF4SEL.
CF4SEL.
0x491 COMPMODE [15:12] RESERVED Reserved. 0x0 R
[11:9] TERMSEL4 Phases to include in CF4 pulse output. Set 0x0 R/W
TERMSEL4, Bit 2 to 1 to include Phase C in the
CF4 pulse output. Similarly, set TERMSEL4, Bit 1 to
include Phase B, and TERMSEL4, Bit 0 for Phase A.
[8:6] TERMSEL3 Phases to include in CF3 pulse output. See 0x0 R/W
TERMSEL4.
TERMSEL4.
TERMSEL4.
0x492 ACCMODE [15:9] RESERVED Reserved. 0x0 R
8 SELFREQ Use this bit to configure the IC for a 50 Hz or 0x0 R/W
60 Hz system. This setting is used in the
fundamental power measurements and to set the
default line period used for VRMS½, 10 cycle rms/
12 cycle rms and resampling calculations if a
zero-crossing is not present.
0 50 Hz.
1 60 Hz.
7 ICONSEL Set this bit to calculate the current flowing 0x0 R/W
through IB from the IA and IC measurements. If
this bit is set, IB = −IA − IC.
[6:4] VCONSEL 3-wire and 4-wire hardware configuration 0x0 R/W
selection.
000 4-wire wye.
001 3-wire delta. VB' = VA − VC.
010 4-wire wye, nonBlondel compliant. VB' = −VA − VC.
011 4-wire delta, nonBlondel compliant. VB' = −VA.
100 3-wire delta. VA' = VA − VB; VB' = VA − VC; VC' =
VC − VB.
[3:2] VARACC Total and fundamental reactive power accumula- 0x0 R/W
tion mode for energy registers and CFx pulses.
00 Signed accumulation mode.
01 Absolute value accumulation mode.
10 Positive accumulation mode.
11 Negative accumulation mode.
[1:0] WATTACC Total and fundamental active power accumulation 0x0 R/W
mode for energy registers and CFx pulses. See
VARACC.
0x493 CONFIG3 [15:12] OC_EN Overcurrent detection enable. OC_EN[3:0] bits 0xF R/W
can all be set to 1 simultaneously to allow
overcurrent detection on all three phases and/or
neutral simultaneously.
Bit 12. When OC_EN[3] is set to 1, Phase A is
selected for the overcurrent detection.
Bit 13. When OC_EN[2] is set to 1, Phase B is
Bit 14. When OC_EN[1] is set to 1, Phase C is
Bit 15. When OC_EN[0] is set to 1, the neutral line
is selected for the overcurrent detection.
[4:2] PEAKSEL Set this bit to select which phase(s) to monitor 0x0 R/W
peak voltages and currents on. Write 1 to PEAKSEL,
Bit 0 to enable Phase A peak detection. Similarly,
PEAKSEL, Bit 1 enables Phase B peak detection, and
PEAKSEL, Bit 2 enables Phase C peak detection.
0x49A ZX_LP_SEL [15:5] RESERVED Reserved. 0x0 R
[4:3] LP_SEL Selects line period measurement used for 0x3 R/W
VRMS½ cycle, 10 cycle rms/12 cycle rms, and
resampling.
00 APERIOD, line period measurement from Phase A
voltage.
01 BPERIOD, line period measurement from Phase B
voltage.
10 CPERIOD, line period measurement from Phase C
voltage.
11 COM_PERIOD, line period measurement on
combined signal from VA, VB, and VC.
[2:1] ZX_SEL Selects the zero-crossing signal, which can be 0x3 R/W
routed to the CF3/ZX output pin and used for
line cycle energy accumulation.
00 ZXVA, Phase A voltage zero-crossing signal.
01 ZXVB, Phase B voltage zero-crossing signal.
10 ZXVC, Phase C voltage zero-crossing signal.
11 ZXCOMB, zero-crossing on combined signal
from VA, VB, and VC.
0x49D PHSIGN [15:10] RESERVED Reserved. 0x0 R
9 SUM4SIGN Sign of the sum of the powers included in the 0x0 R
CF4 datapath. The CF4 energy is positive if this
bit is clear and negative if this bit is set.
5 CVARSIGN Phase C reactive power sign bit. The PWR_SIGN_ 0x0 R
SEL bit in the EP_CFG selects whether this feature
monitors total or fundamental reactive power.
4 CWSIGN Phase C active power sign bit. The PWR_SIGN_SEL 0x0 R
bit in the EP_CFG selects whether this feature
monitors total or fundamental active power.
3 BVARSIGN Phase B reactive power sign bit. The PWR_SIGN_ 0x0 R
2 BWSIGN Phase B active power sign bit. The PWR_SIGN_SEL 0x0 R
1 AVARSIGN Phase A reactive power sign bit. The PWR_SIGN_ 0x0 R
0 AWSIGN Phase A active power sign bit. The PWR_SIGN_SEL 0x0 R
0x4A0 WFB_CFG [15:13] RESERVED Reserved. 0x0 R
12 WF_IN_EN This setting determines whether the IN waveform 0x0 R/W
samples are read out of the waveform buffer
through the SPI.
0 IN waveform samples are not read out of
waveform buffer through the SPI.
1 IN waveform samples are read out of waveform
buffer through the SPI.
[9:8] WF_SRC Waveform buffer source and DREADY (data 0x0 R/W
ready update rate) selection.
00 Sinc4 output at 32 kSPS.
01 Reserved.
10 Sinc4 + IIR LPF output at 8 kSPS.
11 Current and voltage channel waveform samples,
processed by the DSP (xI_PCF, xV_PCF) at 8 kSPS.
[7:6] WF_MODE Fixed data rate waveforms filling and trigger 0x0 R/W
based modes.
00 Stop when waveform buffer is full.
01 Continuous fill—stop only on enabled trigger
events.
10 Continuous filling—center capture around
enabled trigger events.
11 Continuous fill—save event address of enabled
trigger events.
5 WF_CAP_SEL This bit selects whether the waveform buffer is 0x0 R/W
filled with resampled data or fixed data rate
data, selected in the WF_CAP_SEL bits.
0 Resampled data.
1 Fixed data rate data.
4 WF_CAP_EN When this bit is set, a waveform capture is started. 0x0 R/W
0 The waveform capture is disabled. The waveform
buffer contents are maintained.
1 The waveform capture is started, according to
the type of capture in WF_CAP_SEL and the
WF_SRC bits when this bit goes from a 0 to a 1.
[3:0] BURST_CHAN Selects which data to read out of the waveform 0x0 R/W
buffer through SPI.
0000 All channels.
0001 IA and VA.
0010 IB and VB.
0011 IC and VC.
1000 IA.
1001 VA.
1010 IB.
1011 VB.
1100 IC.
1101 VC.
1110 IN if WF_IN_EN = 1 in the WFB_CFG register.
1111 Single address read (SPI burst read mode is
disabled).
0x4A2 WFB_TRG_CFG [15:11] RESERVED Reserved. 0x0 R
10 TRIG_FORCE Set this bit to trigger an event to stop the 0x0 R/W
waveform buffer filling.
9 ZXCOMB Zero-crossing on combined signal from VA, VB, 0x0 R/W
and VC.
8 ZXVC Phase C voltage zero-crossing. 0x0 R/W
7 ZXVB Phase B voltage zero-crossing. 0x0 R/W
6 ZXVA Phase A voltage zero-crossing. 0x0 R/W
5 ZXIC Phase C current zero-crossing. 0x0 R/W
4 ZXIB Phase B current zero-crossing. 0x0 R/W
3 ZXIA Phase A current zero-crossing. 0x0 R/W
2 OI Over current event in any phase. 0x0 R/W
1 SWELL Swell event in any phase. 0x0 R/W
0 DIP Dip event in any phase. 0x0 R/W
0x4A3 WFB_TRG_STAT [15:12] WFB_LAST_PAGE These bits indicate which page of the waveform 0x0 R/W
buffer was filled last, when filling with fixed rate
data samples.
[10:0] WFB_TRIG_ADDR These bits hold the address of the last sample 0x0 R
put into the waveform buffer after a trigger
event occurred, which is within a sample or two
of when the actual trigger event occurred.
0x4AF CONFIG2 [15:13] RESERVED Reserved. 0x0 R
12 UPERIOD_SEL Set this bit to use a user configured line period, 0x0 R/W
in USER_PERIOD, for the VRMS½, 10 cycle rms/
12 cycle rms and resampling calculation. If this
bit is clear, the phase voltage line period selected
by the LP_SEL[1:0] bits in the ZX_LP_SEL register
is used.
[11:9] HPF_CRN High-pass filter corner (f3dB) enabled when the 0x6 R/W
HPFDIS bit in the CONFIG0 register is equal to zero.
000 77.39 Hz.
001 39.275 Hz.
010 19.79 Hz.
011 9.935 Hz.
100 4.98 Hz.
101 2.495 Hz.
110 1.25 Hz.
111 0.625 Hz.
0x4B0 EP_CFG [15:13] NOLOAD_TMR This register configures how many 8 kSPS 0x0 R/W
samples to evaluate the no load condition over.
000 64 samples.
001 128 samples.
010 256 samples.
011 512 samples.
100 1024 samples.
101 2048 samples.
110 4096 samples.
111 Disable no load threshold.
7 PWR_SIGN_SEL[1] Selects whether the REVRPx bit follows the sign 0x0 R/W
of the total or fundamental reactive power.
0 Total reactive power.
1 Fundamental reactive power.
6 PWR_SIGN_SEL[0] Selects whether the REVAPx bit follows the sign 0x0 R/W
of the total or fundamental active power.
1 Fundamental active power.
5 RD_RST_EN Set this bit to enable the energy register read 0x0 R/W
with reset feature. If this bit is set, when one of
the xWATTHR, xVAHR, xVARH, xFWATTHR,
xFVAHR, and xFVARHR register is read, it is reset
and begins accumulating energy from zero.
4 EGY_LD_ACCUM If this bit is equal to zero, the internal energy 0x0 R/W
register is added to the user accessible energy
register. If the bit is set, the internal energy
register overwrites the user accessible energy
register when the EGYRDY event occurs.
1 EGY_TMR_MODE This bit determines whether energy is 0x0 R/W
accumulated based on the number of 8 kSPS
samples or zero-crossing events configured in
the EGY_TIME register.
0 Accumulate energy based on 8 kSPS samples.
1 Accumulate energy based on the zero-crossing
selected by the ZX_SEL bits in the ZX_LP_SEL
register.
0 EGY_PWR_EN Set this bit to enable the energy and power 0x0 R/W
accumulator, when the run bit is also set.
0x4B4 CRC_FORCE [15:1] RESERVED Reserved. 0x0 R
0 FORCE_CRC_UPDATE Write this bit to force the configuration register 0x0 R/W
CRC calculation to start. When the calculation is
complete, the CRC_DONE bit is set in the
STATUS1 register.
0x4B5 CRC_OPTEN 15 CRC_WFB_TRG_CFG_EN Set this bit to include the WFB_TRG_CFG register 0x0 R/W
in the configuration register CRC calculation.
14 CRC_WFB_PG_IRQEN Set this bit to include the WFB_PG_IRQEN register 0x0 R/W
13 CRC_WFB_CFG_EN Set this bit to include the WFB_CFG register in 0x0 R/W
the configuration register CRC calculation.
12 CRC_SEQ_CYC_EN Set this bit to include the SEQ_CYC register in 0x0 R/W
11 CRC_ZXLPSEL_EN Set this bit to include the ZX_LP_SEL register in 0x0 R/W
10 CRC_ZXTOUT_EN Set this bit to include the CRC_ZXTOUT_EN register 0x0 R/W
9 CRC_APP_NL_LVL_EN Set this bit to include the APP_NL_LVL register in 0x0 R/W
8 CRC_REACT_NL_LVL_EN Set this bit to include the REACT_NL_LVL register in 0x0 R/W
7 CRC_ACT_NL_LVL_EN Set this bit to include the ACT_NL_LVL register in 0x0 R/W
6 CRC_SWELL_CYC_EN Set this bit to include the SWELL_CYC register in 0x0 R/W
5 CRC_SWELL_LVL_EN Set this bit to include the SWELL_LVL register in 0x0 R/W
4 CRC_DIP_CYC_EN Set this bit to include the DIP_CYC register in the 0x0 R/W
configuration register CRC calculation.
3 CRC_DIP_LVL_EN Set this bit to include the DIP_LVL register in the 0x0 R/W
2 CRC_EVENT_MASK_EN Set this bit to include the EVENT_MASK register 0x0 R/W
1 CRC_MASK1_EN Set this bit to include the MASK1 register in the 0x0 R/W
0 CRC_MASK0_EN Set this bit to include the MASK0 register in the 0x0 R/W
0x4B6 TEMP_CFG [15:4] RESERVED Reserved. 0x0 R
3 TEMP_START Set this bit to request a temperature sensor 0x0 W1
reading. The new temperature reading is
available in 1.25 ms, indicated by the TEMP_RDY
bit in the STATUS0 register. Note that this bit is
self clearing.
2 TEMP_EN Set this bit to enable the temperature sensor. 0x0 R/W
[1:0] TEMP_TIME Select the number of temperature readings to 0x0 R/W
average.
0 1 sample. New temperature measurement every
1.25 ms.
1 256 samples. New temperature measurement
every 320 ms.
every 640 ms.
every 1.3 sec.
0x4B7 TEMP_RSLT [15:12] RESERVED Reserved. 0x0 R
[11:0] TEMP_RESULT 12-bit temperature sensor result. 0x0 R
0x4B9 PGA_GAIN [15:14] RESERVED Reserved. 0x0 R
[13:12] VC_GAIN PGA gain for voltage Channel C ADC. 0x0 R/W
00 Gain = 1.
01 Gain = 2.
10 Gain = 4.
11 Gain = 4.
[11:10] VB_GAIN PGA gain for Voltage Channel B ADC. See VC_GAIN. 0x0 R/W
[9:8] VA_GAIN PGA gain for Voltage Channel A ADC. See VC_GAIN. 0x0 R/W
[7:6] IN_GAIN PGA gain for neutral current channel ADC. See 0x0 R/W
VC_GAIN.
[5:4] IC_GAIN PGA gain for Current Channel C ADC. See VC_GAIN. 0x0 R/W
[3:2] IB_GAIN PGA gain for Voltage Channel B ADC. See VC_GAIN. 0x0 R/W
[1:0] IA_GAIN PGA gain for Current Channel A ADC. See VC_GAIN. 0x0 R/W
0x4BA CHNL_DIS [15:7] RESERVED Reserved. 0x0 R
6 VC_DISADC Set this bit to one to disable the ADC. 0x0 R/W
5 VB_DISADC Set this bit to one to disable the ADC. 0x0 R/W
4 VA_DISADC Set this bit to one to disable the ADC. 0x0 R/W
3 IN_DISADC Set this bit to one to disable the ADC. 0x0 R/W
2 IC_DISADC Set this bit to one to disable the ADC. 0x0 R/W
1 IB_DISADC Set this bit to one to disable the ADC. 0x0 R/W
0 IA_DISADC Set this bit to one to disable the ADC. 0x0 R/W
0x4E0 VAR_DIS [15:1] RESERVED Reserved. 0x0 R
0 VARDIS Set this bit to disable the total VAR calculation. 0x0 R/W
This bit must be set before writing the run bit for
proper operation.
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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ADE9000 Technical Reference Manual

Functionality and Features of the ADE9000 High Performance, Multiphase Energy

PGA ADC CLKOUT

GND OR RESAMPLED DATA)

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

Internal RF Immunity Filter ....................................................... 4 Resampled Waveforms .............................................................. 39

Modes of Operation ..................................................................... 4 Configuring the Waveform Buffer ........................................... 40

Voltage Reference ......................................................................... 5 Interrupts/EVENT ......................................................................... 43

Crystal Oscillator/External Clock .................................................. 6 Interrupts (IRQ0 and IRQ1) ..................................................... 43

Power Management .......................................................................... 7 EVENT......................................................................................... 43

Reset ............................................................................................... 8 Non-Blondel Compliant Meters ............................................... 45

Measurements ................................................................................... 9 Applying the ADE9000 to a 3-Wire Delta Service ................. 47

ANALOG-TO-DIGITAL CONVERTER (ADC)

reference. Each ADC contains a programmable gain amplifier

to those obtained when sensing the mains voltage signal through

• |IxP − IxN| ≤ +1 V peak, |VxP − VxN| ≤ +1 V peak CHANNEL (x_PCF) WAVEFORM

with an input of ±1 V. With a gain of 1, this full-scale output 0

corresponds to a differential antiphase input of 0.707 V rms,

produced with an input of 0.353 V rms, as shown in Figure 3. At

Write the x_GAIN bits in the PGA_GAIN register to configure

information at a decimated rate of 32 kHz or 8 kHz.

2.048MHz 32kHz 8kHz

22nF 22nF 15523-007

CRYSTAL OSCILLATOR/EXTERNAL CLOCK

To select the appropriate capacitance value for the ceramic

1.3 TO 1.5V VREF

0.5ms 20ms ~26ms

Figure 9. ADE9000 Power-On Sequence for PSM0

Table 4. Power Modes (PSM0 and PSM3)

Name Description Rate REFERENCE

IB Calculation Using ICONSEL It is recommended to leave the high-pass filter enabled to

Table 6. HPF Corner Gain with 50 Hz Input Signal

–89.86 xPHCALx =  ×2

DELAY I Figure 15. Multipoint Phase and Gain Calibration

other, with the ISUM_CFG[1:0] equal to 00 or 11, ISUMRMS is

0.353 V rms. Then, with a nominal 240 V, the input signal is at

ADE9000 PER PHASE AWATTHR

AWATT_ACC INTERNAL POWER ACCUMULATOR VALUE

accumulated in the internal accumulator overflows in 13.3 sec ZXVC

Energy and Phase Selection where:

It can be desirable to clear out a partial CF accumulation, for AWATT +

PHASE A ACTIVE POWER

CLEARED AFTER USER WRITES STATUS0

POWER UP DATE INTERVAL

Figure 28. Combined Zero-Crossing Detection

ZX_SRC_SEL ZX INDICATION IN STATUS1

xx_PCF ANGLE MEASUREMENT

Table 17. Zero-Crossing Use in Other Functions

The time between the zero-crossing on Phase A and Phase B is

8738132 (decimal). ANGL_VA_VC

ZXC ZXB ZXA

which results in ANGLx_I2I and ANGLx_V2I readings that are

4-Wire Wye and 4-Wire Delta

NORMAL PHASE SEQUENCE VCONSEL[2:0] = 001.

SETTO1 WRITE STATUS1.SEQERR = 1

θ1 = –30° PF1 = 0.866 CAP

ACCESSING ON-CHIP DATA

The ADE9000 has a SPI-compatible interface, consisting of four

of each register. BURST_EN = 0