Inter FET CTC-036

JFET SPICE Modeling

The primary focus of SPICE modeling at InterFET is SPICE2 parameters which can be
easily used with most industry SPICE simulators. The core reference for this material is
“Semiconductor Device Modeling with SPICE” second addition, by Giuseppe Massobrio and
Paolo Antognetti.

Fundamental SPICE2 JFET Parameters

Symbol Abbreviation Default Value Definition
𝑉𝑇0 VTO -2 Threshold Voltage
𝛽 BETA 100u Transconductance Parameter
𝜆 LAMBDA 0 Channel-Length Modulation Parameter
𝑟𝐷 RD 0 Drain Parasitic Resistance
𝑟𝑆 RS 0 Source Parasitic Resistance
𝐶𝐺𝐷 CGD 0 Initial Gate to Drain Capacitance
𝐶𝐺𝑆 CGS 0 Initial Gate to Source Capacitance
𝜑0 PB 1 Gate-Junction Potential
𝐹𝐶 FC 500m Forward-Bias Capacitance Coefficient
𝐼𝑆 IS 10f Gate Saturation Current Parameter
𝑎𝐹 AF 0 Flicker Noise Exponent on Drain Current
𝑘𝐹 KF 1 Flicker Noise Coefficient on Drain Current

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DC Model
The DC model parameters (𝑉𝑇0 , 𝛽, and 𝜆) are the most crucial set of parameters needed to
generate a SPICE model of a JFET. These values are expressed in SPICE2 when performing ‘Id-Vds’ or ‘Id-
Vgs’ sweeps. The SPICE2 implementation of the JFET static model uses the Shichman-Hodges polynomial
models to depict the Cutoff, Ohmic, and Saturation regions of JFETs as separate piecewise equations,
shown in equation 1.

0 (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 0 (𝑍𝑒𝑟𝑜)

𝐼𝐷 = {𝛽𝑉𝐷𝑆 (2(𝑉𝐺𝑆 − 𝑉𝑇0 ) − 𝑉𝐷𝑆 )(1 + 𝜆𝑉𝐷𝑆 ) 0 ≤ 𝑉𝐷𝑆 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) (𝑂ℎ𝑚𝑖𝑐)
𝛽(𝑉𝐺𝑆 − 𝑉𝑇0 )2 (1 + 𝜆𝑉𝐷𝑆 ) 0 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 𝑉𝐷𝑆 (𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛)

Equation 1, SPICE equation for Drain current.

These parameters are also used to compute the Transconductance (𝑔𝑚 ) and the Drain to Source
Conductance (𝑔𝐷𝑆 ) as piecewise functions like equation 1, as shown in equations 2 and 3.

0 (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 0 (𝑍𝑒𝑟𝑜)

𝑔𝑚 = { 2𝛽𝑉𝐷𝑆 (1 + 𝜆𝑉𝐷𝑆 ) 0 ≤ 𝑉𝐷𝑆 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) (𝑂ℎ𝑚𝑖𝑐)
2𝛽(1 + 𝜆𝑉𝐷𝑆 )(𝑉𝐺𝑆 − 𝑉𝑇0 ) 0 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 𝑉𝐷𝑆 (𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛)

Equation 2, SPICE equation for Transconductance.

0 (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 0 (𝑍𝑒𝑟𝑜)
𝑔𝐷𝑆 = {2𝛽(1 + 2𝜆𝑉𝐷𝑆 )(𝑉𝐺𝑆 − 𝑉𝑇0 ) − 𝛽𝑉𝐷𝑆 (2 + 3𝜆𝑉𝐷𝑆 ) 0 ≤ 𝑉𝐷𝑆 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) (𝑂ℎ𝑚𝑖𝑐)
2
𝜆𝛽(𝑉𝐺𝑆 − 𝑉𝑇0 ) 0 < (𝑉𝐺𝑆 − 𝑉𝑇0 ) ≤ 𝑉𝐷𝑆 (𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛)

Equation 3, SPICE equations for Drain to Source Conductance.

Calculating these parameters for a JFET requires at least one full ‘Id-Vds’ sweep for that given
part and is somewhat easy if 𝑟𝐷 and 𝑟𝑆 are assumed to be negligible. 𝑉𝑇0 and 𝛽 can be computed
simultaneously by taking either an ‘Id-Vgs’ or an ‘Id-Vds’ sweep, taking the square-root of the drain
current, and performing a linear regression from the √𝐼𝐷𝑆𝑆 to some point on the sweep where the curve
is still linear. The slope is equal to √𝛽, and the x-intercept is 𝑉𝑇𝑂 . Figure 12 the method for calculating
the values, as well as highlighting the difference between 𝑉𝑇0 and 𝑉𝐺𝑆 (𝑂𝐹𝐹).

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Figure 1, Using an ‘Id-Vgs’ sweep (N0132SL) to find a linear regression for obtaining VTO and
BETA.
Computing 𝜆 is a little different and requires 𝑉𝑇0 and 𝛽 to be calculated first. Once 𝑉𝑇0 and 𝛽 are
known, take an ‘Id-Vds’ sweep, remove all data points with abs(𝑉𝐷𝑆 ) less than abs(𝑉𝐺𝑆 (𝑂𝐹𝐹)). I usually
remove all points with abs(𝑉𝐷𝑆 ) below ~1.2 ∙ abs(𝑉𝐺𝑆 (𝑂𝐹𝐹)) to ensure all remnants from the “knee” of
the sweep are removed. Then perform Equation 4 to obtain 𝜆.

𝐼𝐷 (𝑉𝐷𝑆 , 𝑉𝐺𝑆 ) 1
𝜆 = mean ( 2
− )
𝛽𝑉𝐷𝑆 (𝑉𝐺𝑆 − 𝑉𝑇𝑂 ) 𝑉𝐷𝑆

Equation 4, Equation for finding LAMBDA.

As a final step, you can tune 𝛽 to align the SPICE curves to the real data as desired. A fast way of
doing this is by recomputing the saturation region 𝐼𝐷 using the SPICE parameters and dividing the results
by the real data, averaging the result, and multiplying that by the original 𝛽 to obtain a new 𝛽. For
example:

𝛽𝑂𝑙𝑑 (𝑉𝐺𝑆 − 𝑉𝑇𝑂 )2 (1 + 𝜆𝑉𝐷𝑆 )

𝛽𝑁𝑒𝑤 = 𝛽𝑂𝑙𝑑 for abs(𝑉𝐷𝑆 ) > 1.2 ∙ abs(𝑉𝐺𝑆 (𝑂𝐹𝐹))
𝐼𝐷 (𝑉𝐷𝑆 , 𝑉𝐺𝑆 )

Equation 5, Equation for calibrating BETA.

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Figure 2, An ‘Id-Vds’ sweep (N0001SH) overlayed with a SPICE Model.

It should be noted that due to the simple nature of the SPICE2 JFET DC parameters, getting a
great match won’t always be possible, and sometimes the models will be poor.

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Voltage Dependent Capacitors

SPICE2 handles capacitance as two components, Gate to Source Capacitance (𝐶𝐺𝑆 ) and Gate to
Drain Capacitance (𝐶𝐺𝐷 ). The parameters used for this are the measured nonbiased 𝐶𝐺𝑆 and 𝐶𝐺𝐷
capacitance values, as well as the Gate-Junction Potential (𝜑0 ) and the Forward-Bias Capacitance
Coefficient (𝐹𝐶 ). Equations 4 and 5 are for calculating the voltage-dependent capacitances as performed
in SPICE2.

𝑉𝐺𝑆 −𝑚
𝐶𝐺𝑆𝑖 (1 − ) 𝑉𝐺𝑆 ≤ (𝐹𝐶 ∙ 𝜑0 ) (𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒)
𝜑0
𝐶𝐺𝑆 =
𝐶𝐺𝑆𝑖 𝑚𝑉𝐺𝑆
1+𝑚
((1 − 𝐹𝐶 )(1 + 𝑚) − ) 𝑉𝐺𝑆 > (𝐹𝐶 ∙ 𝜑0 ) (𝐿𝑖𝑛𝑒𝑎𝑟 𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒)
{(1 − 𝐹𝐶 ) 𝜑0

Equation 6, SPICE equation for Gate to Source Capacitance.

𝑉𝐺𝐷 −𝑚
𝐶𝐺𝐷𝑖 (1 − ) 𝑉𝐺𝐷 ≤ (𝐹𝐶 ∙ 𝜑0 ) (𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒)
𝜑0
𝐶𝐺𝐷 =
𝐶𝐺𝐷𝑖 𝑚𝑉𝐺𝐷
1+𝑚
((1 − 𝐹𝐶 )(1 + 𝑚) − ) 𝑉𝐺𝐷 > (𝐹𝐶 ∙ 𝜑0 ) (𝐿𝑖𝑛𝑒𝑎𝑟 𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒)
{(1 − 𝐹𝐶 ) 𝜑0

Equation 7, SPICE equation for Gate to Drain Capacitance.

The nonbiased 𝐶𝐺𝑆 and 𝐶𝐺𝐷 capacitances aren’t necessarily always equal but can be treated as
such in most cases. The nonbiased ratings for a JFET can be obtained by measuring the Reverse Transfer
Capacitance (𝐶𝑟𝑆𝑆 ) at 𝑉𝐺𝑆 = 0 and 𝑉𝐷𝑆 = 0, shown in Equation 6.

𝐶𝑖 = 𝐶𝐺𝑆𝑖 = 𝐶𝐺𝐷𝑖 = 𝐶𝑟𝑆𝑆 (𝑉𝐺𝑆 = 0, 𝑉𝐷𝑆 = 0)

Equation 8, Relation between Initial Capacitances and the Reverse Transfer Capacitance.
The Gate-Junction Potential (𝜑0 ) of a given JFET can be computed with Equation 7 when applied
to a sweep of 𝐶𝑟𝑆𝑆 data as taken in the ohmic and saturation regions of the JFET.

𝑉𝐺𝑆 − 𝑉𝐷𝑆
𝜑0 = MEAN 2
𝐶𝑖
1−( )
( 𝐶𝑟𝑆𝑆 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 ) )
Equation 9, Equation to solve for the Gate-Junction Potential.

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Gate Leakage
JFET Gate Leakage is modeled in SPICE2 similarly to that of ideal PN-Junction diodes, which
additionally carries into how JFETs equivalent diodes are modeled in SPICE2. There is only one SPICE
parameter involved in this calculation, being the Gate Saturation Current Parameter 𝐼𝑆 (not to be
confused with the JFET Source Current). There is also the leakage conductance SPICE value 𝐺𝑀𝑖𝑛 that can
be modified separately, but unfortunately that impacts all models that utilize 𝐺𝑀𝑖𝑛 in that given
simulation, including other JFETs and diodes. The default value of 𝐺𝑀𝑖𝑛 in SPICE2 is 10−12 Siemens.

The leakage (and overall diode behavior) is modeled as two diodes, Gate to Drain and Gate to
Source. The equations for the currents traveling through the diodes is shown in Equations 8-9. When a
JFET is configured as a two-terminal diode, either of these equations can be used if the equation is
𝑘𝐵
doubled and 𝑉𝐺𝐷 or 𝑉𝐺𝑆 are treated as 𝑉𝐷 (the voltage applied to the diode). Note that =
𝑞
8.617333 ∙ 10−5 𝑒𝑉/°𝐾.
𝑘𝐵 𝑇
−𝐼𝑆 + 𝑉𝐺𝐷 𝐺𝑀𝑖𝑛 𝑉𝐺𝐷 ≤ −5 (𝐿𝑖𝑛𝑒𝑎𝑟 𝐿𝑒𝑎𝑘𝑎𝑔𝑒)
𝑞
𝐼𝐺𝐷 = 𝑘 𝑇 −1
𝑉𝐺𝐷 ( 𝐵 ) 𝑘𝐵 𝑇
𝐼𝑆 (𝑒 𝑞 − 1) + 𝑉𝐺𝐷 𝐺𝑀𝑖𝑛 𝑉𝐺𝐷 > −5 (𝐸𝑥𝑝𝑜𝑛𝑒𝑛𝑡𝑖𝑎𝑙 𝐿𝑒𝑎𝑘𝑎𝑔𝑒)
{ 𝑞

Equation 10, SPICE equation for the Gate to Drain Leakage Current.
𝑘𝐵 𝑇
−𝐼𝑆 + 𝑉𝐺𝑆 𝐺𝑀𝑖𝑛 𝑉𝐺𝑆 ≤ −5 (𝐿𝑖𝑛𝑒𝑎𝑟 𝐿𝑒𝑎𝑘𝑎𝑔𝑒)
𝑞
𝐼𝐺𝑆 = 𝑘 𝑇 −1
𝑉𝐺𝑆 ( 𝐵 ) 𝑘𝐵 𝑇
𝐼𝑆 (𝑒 𝑞 − 1) + 𝑉𝐺𝑆 𝐺𝑀𝑖𝑛 𝑉𝐺𝑆 > −5 (𝐸𝑥𝑝𝑜𝑛𝑒𝑛𝑡𝑖𝑎𝑙 𝐿𝑒𝑎𝑘𝑎𝑔𝑒)
{ 𝑞

Equation 11, SPICE equation for the Gate to Source Leakage Current.
Since the Forward-Bias Voltage (𝑉𝐹𝐵 ) of the diodes isn’t directly controllable, a compromise may
have to be made between choosing an accurate gate leakage current and accurate 𝑉𝐹𝐵 . Additionally, it
should be noted that the diode breakdown voltage and current is not included in the JFET diode model.
Figure 14 shows a diode characteristic of an example JFET using the SPICE2 equations using an N-channel
J109.

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Figure 3, An ‘Ig-Vgs’ sweep (N0450SL) showing the JFET diode behavior in SPICE2.
The 𝐼𝑆 parameter can be computed alongside 𝐺𝑀𝑖𝑛 (default 𝐺𝑀𝑖𝑛 = 10−12 Siemens) or be
computed independently. By shorting the Source and Drain pins of the FET and reverse biased the FET, a
reverse-bias diode characteristic will be formed, and can be used in the following equations for
computation:

For the 𝐼𝑆 parameter:

𝐼𝑆 = 𝑉𝐷 𝐺𝑀𝑖𝑛 − 𝐼𝐺 (𝑉𝐷 )
Equation 12, Equation for computing Gate Saturation Current Parameter.
For both the 𝐼𝑆 and 𝐺𝑀𝑖𝑛 parameters, a full reverse-bias sweep will be needed, and to perform a linear
regression to obtain a slope (𝑚𝑔 ) and an intercept (𝑏𝑔 ):

𝐼𝑆 = −𝑏𝑔 𝐺𝑀𝑖𝑛 = 𝑚𝑔

Equation 13, Equation for computing Gate Saturation Current Parameter and the Leakage
Conductance.

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Parasitic Resistances
All real JFETs exhibit parasitic resistances to varying extents, because of bond wires,
semiconductor resistances, lead resistances, etc.. Working with parasitic resistances is tricky, because the
parasitic resistances are not possible to model with a single equation and instead need to be simulated.

Figure 4, A JFET model showing parasitic resistances externally. Schematic produced using
LTSpice.
Even though the parasitic resistances are typically less than 10 Ohms, the impact of these
resistances can be significant, especially on parts with higher 𝐼𝐷𝑆𝑆 . Figures 16-18 show the impact of
parasitic resistances on a high-current JFET, note the impact of 𝑟𝐷 on the observed knee position and the
impact of 𝑟𝑆 on 𝐼𝐷𝑆𝑆 . There may be a way of determining the parasitic resistances if 𝑟𝐷 ≈ 𝑟𝑆 that involves
performing a few ‘Vgs-Id’ sweep that includes a slightly positive 𝑉𝐺𝑆 to counteract the effect of 𝑟𝑆 .

It should be noted that the parasitic resistances impact the large signal, small signal, and noise
behavior of a JFET in SPICE2. As a result, modeling the parasitic resistances with precision and accuracy is
a critical task.

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Figure 5, A comparative simulation of an IF3601 with no parasitic resistance (green) and with
a 1 Ohm drain resistance (red). Simulated using LTSpice.

Figure 6, A comparative simulation of an IF3601 with no parasitic resistance (green) and with
a 1 Ohm source resistance (red). Simulated using LTSpice.

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Figure 7, A comparative simulation of an IF3601 with no parasitic resistance (green) and with
1 Ohm drain and source resistances (red). Simulated using LTSpice.

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Noise Equations and Approximations

JFET noise in SPICE is modeled as current sources in parallel to the channel and the drain and
source parasitic resistances, with an equivalent noise model shown below:

Figure 8, An equivalent small-signal model for depicting SPICE2 JFET noise current sources.
The names of each of the current sources shown depict their noise component, excluding the
current source labeled “Channel,” which is a non-noise current source for depicting the small-signal
current traveling through the JFET. Then the question becomes, what are Flicker, Shot, and Johnson
noise? It is worth noting that 𝑘𝐵 = 1.380649 ∙ 10−23 𝐽/°𝐾 in this section.

Flicker noise is a noise contribution with the cause not fully understood, acting on the device
channel. It is the only noise contribution with SPICE parameters exclusively for this function, 𝐴𝐹 and 𝐾𝐹 .
This noise source is impacted by the drain current and decays inversely with frequency, because of this, it
is most prominent in lower frequencies [2].

𝐾𝐹 𝐼𝐷 𝐴𝐹
𝑁𝐹𝑙𝑖𝑐𝑘𝑒𝑟 (𝐴2 ) = ∆𝑓
𝑓

Equation 14, SPICE equation for the Channel Flicker Noise contribution.
Shot noise (also known as Poisson) noise is another contribution induced on the device channel.
This component is caused by the discrete and chaotic behavior of moving electrical charges. This noise
source is impacted by the junction temperature and the transconductance of the device at any given
time. This component is present and uniform across all frequencies [2].

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8𝑘𝐵 𝑇𝑔𝑚
𝑁𝑆ℎ𝑜𝑡 (𝐴2 ) = ∆𝑓
3
Equation 15, SPICE equations for the Channel Flicker and Shot Noise contributions.
Johnson (also known as Thermal) noise is the noise contribution introduced by the two parasitic
resistances 𝑟𝐷 and 𝑟𝑆 . The magnitude of the current noise is linearly impacted by the junction
temperature (in Kelvin). Equation 13 contains the constants needed for this section, and Equation 14
contains the equations for the drain and source thermal noise sources. This component is also present
and uniform across all frequencies [2].

4𝑘𝐵 𝑇 4𝑘𝐵 𝑇
𝑁𝐷𝑟𝑎𝑖𝑛−𝑇ℎ𝑒𝑟𝑚𝑎𝑙 (𝐴2 ) = ∆𝑓 𝑁𝑆𝑜𝑢𝑟𝑐𝑒−𝑇ℎ𝑒𝑟𝑚𝑎𝑙 (𝐴2 ) = ∆𝑓
𝑟𝐷 𝑟𝑆

Equation 16, SPICE equations for the Thermal Noise contributions of the Parasitic Resistances.
All the noise current sources occur in parallel to some form of a resistance, as a result, they can
be expressed as Thevenin-Norton Equivalent voltage sources. It is critical to note that the Shot and
Flicker noise components share a parallel resistance, and as a result can be added together.

So, once the values for all the noise components at any given temperature, drain current, and
transconductance have been determined, how can that be converted to Input Referred Voltage Noise?
First, here’s a sample circuit for computing the noise. Output-Referred Noise is noise occurring at the
drain, and Input-Referred Noise is the noise occurring at the gate.

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Figure 9, A simple circuit for measuring Voltage or Current Noise in LTSpice. Schematic
produced using LTSpice.
To compute the noise at different nodes, we need to convert all the current noise sources into the
Output-Referred Current Noise:

𝑁𝐷𝑟𝑎𝑖𝑛−𝑇ℎ𝑒𝑟𝑚𝑎𝑙 𝑟𝐷 + 𝑁𝑆𝑜𝑢𝑟𝑐𝑒−𝑇ℎ𝑒𝑟𝑚𝑎𝑙 𝑟𝑆 + (𝑁𝐹𝑙𝑖𝑐𝑘𝑒𝑟 + 𝑁𝑆ℎ𝑜𝑡 )𝑅𝐷𝑆

𝑁𝑂𝑅−𝐼 (𝐴) ≈ √
𝑅𝐷𝑆 + 𝑟𝐷 + 𝑟𝑆

Equation 17, Approximate equation for the SPICE Output-Referred Current Noise.
After doing that, we can then calculate the Output or Input-Referred Voltage Noise:
𝑉 𝑉 𝑁𝑂𝑅−𝑉
𝑁𝑂𝑅−𝑉 ( ) ≈ 𝑁𝑂𝑅−𝐼 𝑅𝐷𝐸 → 𝑁𝐼𝑅−𝑉 ( )≈
√𝐻𝑧 √𝐻𝑧 𝑔𝑚 𝑅𝐷𝐸

Equation 18, Approximate equations for the SPICE Output and Input-Referred Voltage Noise.
To calculate the SPICE parameters needed for accurate noise behavior, you first need to take the
measured noise (input-referred) and convert it into output-referred current noise.

𝑁𝑂𝑅−𝐼 (𝐴) = 𝑔𝑚 𝑁𝐼𝑅−𝑉

Equation 19, Approximate equations for the SPICE Output and Input-Referred Voltage Noise.

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Then since the thermal noises and the shot noise can be calculated, compute those and remove
them from the total current noise.

𝑁𝑂𝑅−𝐼 2 (𝑅𝐷𝑆 + 𝑟𝐷 + 𝑟𝑆 ) − (𝑟𝐷 𝑁𝑇ℎ𝑒𝑟𝑚𝑎𝑙−𝐷𝐶𝑎𝑙𝑐 + 𝑟𝑆 𝑁𝑇ℎ𝑒𝑟𝑚𝑎𝑙−𝑆𝐶𝑎𝑙𝑐 + 𝑅𝐷𝑆 𝑁𝑆ℎ𝑜𝑡−𝐶𝑎𝑙𝑐 )

𝑁𝐹𝑙𝑖𝑐𝑘𝑒𝑟−𝐶𝑎𝑙𝑐 =
𝑅𝐷𝑆

Equation 20, Approximate equations for the SPICE Output and Input-Referred Voltage Noise.
Then compute the following values (𝑥𝑉 and 𝑦𝑉 ) and perform a linear regression on them,
obtaining the slope (𝑚) and y-intercept (𝑏).
𝑥𝑉 = 𝑙𝑛(𝐼𝐷 ) 𝑦𝑉 = 𝑙𝑛(𝑁𝐹𝑙𝑖𝑐𝑘𝑒𝑟−𝐶𝑎𝑙𝑐 (𝐼𝐷 , 𝑓) ∙ 𝑓)
𝑎𝐹 = median(𝑚) 𝑘𝐹 = median(𝑒 𝑏 )

Equation 21, Equations for estimating the AF and KF SPICE parameters.

The results should be somewhat accurate given that the correct 𝐼𝐷 , 𝑔𝑚 , and 𝑇 are used for each
noise sweep.

IF1320 Input-Referred Noise Sweep

3.5E-09

3E-09
Voltage Noise (nV/rHz)

2.5E-09 Real @ 4.75E-01 mA

Real @ 9.00E-01 mA
2E-09 Real @ 1.90E+00 mA
SPICE @ 4.75E-01 mA
1.5E-09 SPICE @ 9.00E-01 mA
SPICE @ 1.90E+00 mA
1E-09

5E-10

0
10 100 1000 10000
Frequency (Hz)

Figure 10, An Input-Referred Voltage Noise Sweep with overlayed SPICE model.

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 Inter FET CTC-036

Citations
[1] G. Massobrio and P. Antognetti, Semiconductor Device Modeling with Spice. McGraw-
Hill, 2009.
[2] R. Keim, What Is Electrical Noise and Where Does It Come From?. All About Circuits,
2018.

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 Inter FET CTC-036
Equation 1, SPICE equation for Drain current.............................................................................................. 2
Equation 2, SPICE equation for Transconductance. ..................................................................................... 2
Equation 3, SPICE equations for Drain to Source Conductance. ................................................................. 2
Equation 4, Equation for finding LAMBDA. ................................................................................................. 3
Equation 5, Equation for calibrating BETA. .................................................................................................. 3
Equation 6, SPICE equation for Gate to Source Capacitance. ..................................................................... 5
Equation 7, SPICE equation for Gate to Drain Capacitance......................................................................... 5
Equation 8, Relation between Initial Capacitances and the Reverse Transfer Capacitance. ..................... 5
Equation 9, Equation to solve for the Gate-Junction Potential................................................................... 5
Equation 10, SPICE equation for the Gate to Drain Leakage Current. ........................................................ 6
Equation 11, SPICE equation for the Gate to Source Leakage Current. ...................................................... 6
Equation 12, Equation for computing Gate Saturation Current Parameter. ............................................... 7
Equation 13, Equation for computing Gate Saturation Current Parameter and Leakage Conductance. ... 7
Equation 14, SPICE equation for the Channel Flicker Noise contribution. ............................................... 11
Equation 15, SPICE equations for the Channel Flicker and Shot Noise contributions. ............................ 12
Equation 16, SPICE equations for the Thermal Noise contributions of the Parasitic Resistances. .......... 12
Equation 17, Approximate equation for the SPICE Output-Referred Current Noise. ............................... 13
Equation 18, Approximate equations for the SPICE Output and Input-Referred Voltage Noise. ............ 13
Equation 19, Approximate equations for the SPICE Output and Input-Referred Voltage Noise. ............ 13
Equation 20, Approximate equations for the SPICE Output and Input-Referred Voltage Noise. ............ 14
Equation 21, Equations for estimating the AF and KF SPICE parameters. ................................................ 14

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