DJM 900 Nexus

ORDER NO.
RRV4170
DJM-900NXS
DJ MIXER
DJM-900NXS
NOTE: The model name of this product is DJM-900nexus.
THIS MANUAL IS APPLICABLE TO THE FOLLOWING MODEL(S) AND TYPE(S).

Model Type Power Requirement Remarks
DJM-900NXS SYXJ8 AC 220 V to 240 V
DJM-900NXS UXJCB AC 120 V

DJM-900NXS LXJ AC 110 V to 120 V or 220 V to 240 V
DJM-900NXS KXJ5 AC 220 V
DJM-900NXS XJCN5 AC 220 V to 240 V
For details, refer to "Important Check Points for good servicing".
PIONEER CORPORATION 1-1, Shin-ogura, Saiwai-ku, Kawasaki-shi, Kanagawa 212-0031, Japan

PIONEER ELECTRONICS (USA) INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A.
PIONEER EUROPE NV Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 253 Alexandra Road, #04-01, Singapore 159936
PIONEER CORPORATION 2011
K-IZV APR. 2011 Printed in Japan
1 2 3 4
SAFETY INFORMATION
This service manual is intended for qualified service technicians; it is not meant for the casual do-it-
yourselfer. Qualified technicians have the necessary test equipment and tools, and have been trained
to properly and safely repair complex products such as those covered by this manual.
Improperly performed repairs can adversely affect the safety and reliability of the product and may
void the warranty. If you are not qualified to perform the repair of this product properly and safely, you
should not risk trying to do so and refer the repair to a qualified service technician.
WARNING
B This product may contain a chemical known to the State of California to cause cancer, or birth defects or other reproductive
harm.
Health & Safety Code Section 25249.6 - Proposition 65
(FOR USA MODEL ONLY)

ANY MEASUREMENTS NOT WITHIN THE LIMITS
1. SAFETY PRECAUTIONS
OUTLINED ABOVE ARE INDICATIVE OF A POTENTIAL
The following check should be performed for the
SHOCK HAZARD AND MUST BE CORRECTED BEFORE
continued protection of the customer and service
RETURNING THE APPLIANCE TO THE CUSTOMER.
technician.
C LEAKAGE CURRENT CHECK
Measure leakage current to a known earth ground 2. PRODUCT SAFETY NOTICE
(water pipe, conduit, etc.) by connecting a leakage Many electrical and mechanical parts in the appliance
current tester such as Simpson Model 229-2 or have special safety related characteristics. These are
equivalent between the earth ground and all exposed often not evident from visual inspection nor the protection
metal parts of the appliance (input/output terminals, afforded by them necessarily can be obtained by using
screwheads, metal overlays, control shaft, etc.). Plug replacement components rated for voltage, wattage, etc.
the AC line cord of the appliance directly into a 120 V Replacement parts which have these special safety
AC 60 Hz outlet and turn the AC power switch on. Any characteristics are identified in this Service Manual.
current measured must not exceed 0.5 mA. Electrical components having such features are
identified by marking with a > on the schematics and on
D
the parts list in this Service Manual.
Reading should The use of a substitute replacement component which
Leakage not be above does not have the same safety characteristics as the
Device current 0.5 mA
under tester PIONEER recommended replacement one, shown in the
test parts list in this Service Manual, may create shock, fire,
Test all or other hazards.
exposed metal
surfaces Product Safety is continuously under review and new
instructions are issued from time to time. For the latest
information, always consult the current PIONEER Service
Also test with Manual. A subscription to, or additional copies of,
plug reversed Earth PIONEER Service Manual may be obtained at a nominal
E (Using AC adapter ground
plug as required) charge from PIONEER.
AC Leakage Test
2 DJM-900NXS
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A
[Important Check Points for Good Servicing]
In this manual, procedures that must be performed during repairs are marked with the below symbol.
Please be sure to confirm and follow these procedures.
1. Product safety
Please conform to product regulations (such as safety and radiation regulations), and maintain a safe servicing environment by
following the safety instructions described in this manual.
1 Use specified parts for repair.
Use genuine parts. Be sure to use important parts for safety.
2 Do not perform modifications without proper instructions.

B
Please follow the specified safety methods when modification(addition/change of parts) is required due to interferences such as
radio/TV interference and foreign noise.
3 Make sure the soldering of repaired locations is properly performed.
When you solder while repairing, please be sure that there are no cold solder and other debris.
Soldering should be finished with the proper quantity. (Refer to the example)
4 Make sure the screws are tightly fastened.
Please be sure that all screws are fastened, and that there are no loose screws.
5 Make sure each connectors are correctly inserted.
Please be sure that all connectors are inserted, and that there are no imperfect insertion.
C
6 Make sure the wiring cables are set to their original state.
Please replace the wiring and cables to the original state after repairs.
In addition, be sure that there are no pinched wires, etc.
7 Make sure screws and soldering scraps do not remain inside the product.
Please check that neither solder debris nor screws remain inside the product.
8 There should be no semi-broken wires, scratches, melting, etc. on the coating of the power cord.
Damaged power cords may lead to fire accidents, so please be sure that there are no damages.
If you find a damaged power cord, please exchange it with a suitable one.
9 There should be no spark traces or similar marks on the power plug.

D
When spark traces or similar marks are found on the power supply plug, please check the connection and advise on secure
connections and suitable usage. Please exchange the power cord if necessary.
a Safe environment should be secured during servicing.
When you perform repairs, please pay attention to static electricity, furniture, household articles, etc. in order to prevent injuries.
Please pay attention to your surroundings and repair safely.
2. Adjustments
To keep the original performance of the products, optimum adjustments and confirmation of characteristics within specification.
Adjustments should be performed in accordance with the procedures/instructions described in this manual.
3. Lubricants, Glues, and Replacement parts E
Use grease and adhesives that are equal to the specified substance.
Make sure the proper amount is applied.
4. Cleaning
For parts that require cleaning, such as optical pickups, tape deck heads, lenses and mirrors used in projection monitors, proper
cleaning should be performed to restore their performances.
5. Shipping mode and Shipping screws

To protect products from damages or failures during transit, the shipping mode should be set or the shipping screws should be F
installed before shipment. Please be sure to follow this method especially if it is specified in this manual.
DJM-900NXS 3
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CONTENTS
SAFETY INFORMATION ..........................................................................................................................................................2
1. SERVICE PRECAUTIONS ....................................................................................................................................................6
A 1.1 NOTES ON SOLDERING ...............................................................................................................................................6
1.2 NOTES ON REPLACING ................................................................................................................................................6
1.3 SERVICE NOTICE ..........................................................................................................................................................6
1.4 ON MODIFICATION OF THE VOLTAGE-MONITORING CIRCUITS...............................................................................7
2. SPECIFICATIONS .................................................................................................................................................................9
2.1 SPECIFICATIONS...........................................................................................................................................................9
2.2 PANEL FACILITIES .......................................................................................................................................................10
3. BASIC ITEMS FOR SERVICE.............................................................................................................................................13
3.1 CHECK POINTS AFTER SERVICING..........................................................................................................................13
3.2 JIGS LIST......................................................................................................................................................................13
3.3 PCB LOCATIONS .........................................................................................................................................................14
4. BLOCK DIAGRAM...............................................................................................................................................................16
B 4.1 OVERALL WIRING DIAGRAM......................................................................................................................................16
4.2 AUDIO SYSTEM BLOCK DIAGRAM ............................................................................................................................18
4.3 DSP BLOCK DIAGRAM ................................................................................................................................................20
4.4 POWER BLOCK DIAGRAM..........................................................................................................................................22
5. DIAGNOSIS.........................................................................................................................................................................24
5.1 POWER ON SEQUENCE .............................................................................................................................................24
5.2 TROUBLESHOOTING ..................................................................................................................................................26
5.3 INFORMATION ON POWER DIAGNOSTICS ...............................................................................................................40
5.4 VOLTAGE MONITORING CIRCUIT ..............................................................................................................................41
5.5 ABOUT THE PROTECTOR ..........................................................................................................................................43
5.6 DIAGNOSIS OF V+34D ................................................................................................................................................44
5.7 ERROR INDICATIONS..................................................................................................................................................45
C
5.8 CONNECTION CHECK WITH EACH INTERFACE ......................................................................................................46
6. SERVICE MODE .................................................................................................................................................................47
6.1 TEST MODE .................................................................................................................................................................47
6.2 ABOUT THE DEVICE ...................................................................................................................................................64
7. DISASSEMBLY....................................................................................................................................................................65
8. EACH SETTING AND ADJUSTMENT ................................................................................................................................75
8.1 NECESSARY ITEMS TO BE NOTED ...........................................................................................................................75
8.2 UPDATING OF THE FIRMWARE..................................................................................................................................75
8.3 HOW TO CONFIRM THE DVS......................................................................................................................................81
8.4 USER SETABLE ITEMS ...............................................................................................................................................85
8.5 SHEET FOR CONFIRMATION OF THE USER SETTING ...........................................................................................86
D
9. EXPLODED VIEWS AND PARTS LIST ...............................................................................................................................88
9.1 PACKING SECTION......................................................................................................................................................88
9.2 EXTERIOR SECION .....................................................................................................................................................90
9.3 BOTTOM SECTION ......................................................................................................................................................92
9.4 CONTROL PANEL SECTION (1/2) ...............................................................................................................................94
9.5 CONTROL PANEL SECTION (2/2) ...............................................................................................................................96
10. SCHEMATIC DIAGRAM ....................................................................................................................................................98
10.1 INPUT ASSY (1/11) ....................................................................................................................................................98
10.2 INPUT ASSY (2/11) ..................................................................................................................................................100
10.3 INPUT ASSY (3/11) ..................................................................................................................................................102
10.4 INPUT ASSY (4/11) ..................................................................................................................................................104
10.5 INPUT ASSY (5/11) ..................................................................................................................................................106
E
10.6 INPUT ASSY (6/11) ..................................................................................................................................................108
10.7 INPUT ASSY (7/11) ..................................................................................................................................................110
10.8 INPUT ASSY (8/11) ..................................................................................................................................................112
10.9 INPUT ASSY (9/11) ..................................................................................................................................................114
10.10 INPUT ASSY (10/11) ..............................................................................................................................................116
10.11 INPUT ASSY (11/11) ..............................................................................................................................................118
10.12 MIC1 and TRM1 to TRM4 ASSYS ..........................................................................................................................120
10.13 MAIN ASSY (1/21) ..................................................................................................................................................122
10.14 MAIN ASSY (2/21) ..................................................................................................................................................124
10.15 MAIN ASSY (3/21) ..................................................................................................................................................126
10.16 MAIN ASSY (4/21) ..................................................................................................................................................128
F 10.17 MAIN ASSY (5/21) ..................................................................................................................................................130
10.18 MAIN ASSY (6/21) ..................................................................................................................................................132
10.19 MAIN ASSY (7/21) ..................................................................................................................................................134
10.20 MAIN ASSY (8/21) ..................................................................................................................................................136
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10.21 MAIN ASSY (9/21).................................................................................................................................................. 138

10.22 MAIN ASSY (10/21)................................................................................................................................................ 140
10.23 MAIN ASSY (11/21)................................................................................................................................................ 142 A
10.24 MAIN ASSY (12/21)................................................................................................................................................ 144
10.25 MAIN ASSY (13/21)................................................................................................................................................ 146
10.26 MAIN ASSY (14/21)................................................................................................................................................ 148
10.27 MAIN ASSY (15/21)................................................................................................................................................ 150
10.28 MAIN ASSY (16/21)................................................................................................................................................ 152
10.29 MAIN ASSY (17/21)................................................................................................................................................ 154
10.30 MAIN ASSY (18/21)................................................................................................................................................ 156
10.31 MAIN ASSY (19/21)................................................................................................................................................ 158
10.32 MAIN ASSY (20/21)................................................................................................................................................ 160
10.33 MAIN ASSY (21/21)................................................................................................................................................ 162
10.34 USBI and HPJK ASSYS ......................................................................................................................................... 164
B
10.35 SEND ASSY ........................................................................................................................................................... 166
10.36 PNLA ASSY (1/2) ................................................................................................................................................... 168
10.37 PNLA ASSY (2/2) ................................................................................................................................................... 170
10.38 CDCB and FAD1 to FAD4 ASSYS.......................................................................................................................... 172
10.39 PNLB and FADC ASSYS ........................................................................................................................................ 174
10.40 POWER SUPPLY and AC SW ASSYS ................................................................................................................... 176
10.41 WAVEFORMS......................................................................................................................................................... 178
11. PCB CONNECTION DIAGRAM ...................................................................................................................................... 190
11.1 INPUT ASSY ............................................................................................................................................................ 190
11.2 MIC1 and TRM1 to TRM4 ASSYS............................................................................................................................ 194
11.3 MAIN ASSY .............................................................................................................................................................. 196
11.4 USBI, HPJK and SEND ASSYS ............................................................................................................................... 202 C
11.5 PNLA ASSY.............................................................................................................................................................. 204
11.6 CDCB and FAD1 to FAD4 ASSYS............................................................................................................................ 208
11.7 PNLB and FADC ASSYS .......................................................................................................................................... 210
11.8 POWER SUPPLY and AC SW ASSYS ..................................................................................................................... 214
12. PCB PARTS LIST ............................................................................................................................................................ 215
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1. SERVICE PRECAUTIONS
1.1 NOTES ON SOLDERING
A • For environmental protection, lead-free solder is used on the printed circuit boards mounted in this unit.
Be sure to use lead-free solder and a soldering iron that can meet specifications for use with lead-free solders for repairs
accompanied by reworking of soldering.
• Compared with conventional eutectic solders, lead-free solders have higher melting points, by approximately 40 ºC.
Therefore, for lead-free soldering, the tip temperature of a soldering iron must be set to around 373 ºC in general, although
the temperature depends on the heat capacity of the PC board on which reworking is required and the weight of the tip of
the soldering iron.
Do NOT use a soldering iron whose tip temperature cannot be controlled.
Compared with eutectic solders, lead-free solders have higher bond strengths but slower wetting times and higher melting
B
temperatures (hard to melt/easy to harden).
The following lead-free solders are available as service parts:

• Parts numbers of lead-free solder:
GYP1006 1.0 in dia.
GYP1007 0.6 in dia.
GYP1008 0.3 in dia.
1.2 NOTES ON REPLACING

C The part listed below is difficult to replace as a discrete component part.
When the part listed in the table is defective, replace whole Assy.
Parts that is Diffcult to Replace
Assy Name PCB Assy Part No.
Ref No. Function Part No. Remarks
IC1406 12V → 1.2V DC/DC converter BD9326EFJ IC with heat-pad
IC1407 12V → 3.3V DC/DC converter BD9326EFJ IC with heat-pad
IC501 ETHER UCOM R5S76700B200BG BGA
IC1801 USB UCOM ADSP-BF524BBCZ-3A BGA
IC2214 FPGA XC3S50A-4FTG256C BGA
MAIN Assy DWX3190
IC701 DSP D810K013BZKB400 BGA
Q3405 Transistor 2SD1760F5 (R) Transistor with heat-pad
Q3406 Transistor 2SB1184F5 (R) Transistor with heat-pad
D Q3407 Transistor 2SD1760F5 (R) Transistor with heat-pad
Q3408 Transistor 2SB1184F5 (R) Transistor with heat-pad
CDCB Assy DWX3191 IC3601 CDC SENSOR AD7147ACPZ500RL7 IC with heat-pad
1.3 SERVICE NOTICE

VOLTAGE MONITORING
This unit always monitors for power failure and will shut itself off immediately after an error is detected.
A power failure is indicated with flashing of the LFO FORM LED (Intervals: 250 ms [Lit 125 ms/Unlit 125 ms]).
All the LEDs other than LFO FORM will be unlit, and all the switches and VRs will be disabled.
E Repair the unit according to the diagnostic procedures described in “5.4 Information on Power Diagnostics.”
CONFIRMATION OF USER-SETTING
This product has user- and club-setting data. Be sure to confirm those data before starting repair, although changing them
may not have a large effect. Use the Check Sheet in “8.5,” to which you can transcribe the settings, as required.
The settings are stored in Flash ROM (IC502) on the Main Assy.
To display the [USER SETUP] screen, hold [ON/OFF (UTILITY)] pressed for at least 1 sec.
To display the [CLUB SETUP] screen, press [POWER] (ON) while holding [ON/OFF (UTILITY)] pressed.
FLASH ROM ON THE MAIN Assy

Never replace the Flash ROM (IC502) on the MAIN Assy during servicing.
F If the FLASH ROM is assumed to be defective, replace the whole MAIN Assy.
This FLASH ROM contains data that can only be written in at the factory.
An IEEE 802.3-based MAC address specific to this unit has been written.
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1.4 ON MODIFICATION OF THE VOLTAGE-MONITORING CIRCUITS
The voltage-monitoring circuits have been modified because of a malfunction found during mass-production of the products. A
Note that the measures taken for the products may differ by the timing of the production.
• Malfunction: A shutdown may occur when certain headphones are used with this product.
• Cause: Malfunction of the voltage-monitoring circuits
• Modifications: 1 Removal of the ±9-V monitoring circuit
2 Removal (short-circuiting) of the power-drop resistors (R1205, R1206)
1 ±9-V monitoring circuit 2 Power-drop resistors (R1205, R1206)
V+9HP V+5A
STBY
STBY D1205 V+9HP
R1220
HP Block NM
R1217
V+15A_HP V+9HP
R1214
3.3k
HN1A01FU(YGR) V+9HP_UNREG
(D)
IC1201 A side
12k
Drop Resister
(F)
STBY C1216 KIA7809API C1218 D1203

Q1203 NM P1211 R1206 0.33u/50 0.1u/16 RB501V-40
OUT
(1/2) 1 2 1
IN
A side 15 2W GND 3
B
1000p/50
1 6 NM
C1206
C1270
100u/25
C1221
4
47u/16
A side R1219 ! 2 B side
CH
R1228
Q1203
R1215
V+5A 5 0
2 1k 3 (2/2)
39k
(F)
R1218
12k
(D)
STBY
R1216
1 GNDA_HP
D1206
10k
KN1202 NM
CKF1089-A V-9HP_UNREG
V-9HP
IC1202
STBY Drop Resister KIA7909PI A Side
D1202
V-9HP V-9HP P1212 R1205 OUT RB501V-40
IN
1 2 2W 2 GND 3
C1220
15
CCG1254
NM
47u/16
1000p/50
C1217
C1219
1
C1271
100u/25
B Side
C1213
C1269
1u/16
D1204 !
22u/16
CH
R1229
NM
1SS301 0
STBY
GNDA_HP GNDA_HP V-9HP
Timing of the production:

(1) All units with serial numbers beginning with KA or KB, and some units with serial C
numbers beginning with KC or KD

(2) Some units with serial numbers beginning with KC, KD, or KF (planned), and all units
with serial numbers beginning with KE
(3) Some units with serial numbers beginning with KF, and all units with serial numbers
beginning with on and after KG (planned)
(1) All units with serial numbers beginning with KA or KB, and some units with serial numbers beginning with KC or KD
1 Removal of the chip diode [D1204].
V+9HP V+5A
STBY
R1220
R1217
D
R1214
3.3k
HN1A01FU(YGR)
(D)
12k
(F)
Q1203 NM
(1/2)
A side
1 6 A side 4
R1219
Q1203
MAIN ASSY
R1215
V+5A 5
2 1k 3 (2/2)
39k
(F)
R1218
12k
(D)
R1216
10k
V-9HP
V-9HP Remove D1204.
Remove D1204.
D1204
1SS301
D1204
2 Soldering of a lead wire or a piece of wire to R1205

and R1206. R1206 R1205
E
STBY
D1205 V+9HP
HP Block NM
V+9HP
V+9HP_UNREG IC1201 A side
STBY Drop Resister C1216 KIA7809API C1218 D1203
P1211 R1206 0.33u/50
IN OUT
0.1u/16 RB501V-40
1. Soldering of a lead wire (or a piece
1 2 1 GND 3
15 2W of wire) to the resistor
1000p/50
NM
C1270
C1221
47u/16
! 2 B side
CH
R1228
0
R1206 R1205
STBY
GNDA_HP
D1206
NM
V-9HP_UNREG
V-9HP
IC1202
STBY Drop Resister KIA7909PI A Side
D1202
P1212 R1205 RB501V-40
OUT
IN
1 2 2W 2 GND 3
C1220
15
CCG1254
NM
47u/16
1000p/50
C1217
C1219
1
C1271
B Side
C1269
1u/16
! F
22u/16
CH
R1229
NM
2. Securing the lead wires (pieces of wire) to

0
STBY
the resistors with adhesive
Silicone adhesive used: GYA1011
GNDA_HP V-9HP
DJM-900NXS 7
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A (2) Some units with serial numbers beginning with KC, KD, or KF (planned), and all units with serial numbers
beginning with KE
1 Not mounting the ±9-V monitoring-circuit block.
STBY
V+9HP V+5A The following parts are not mounted:
STBY D1204
R1220 Q1203
R1217
R1214
NM
Q1203
(D) R1214
NM
(F)
(1/2) NM
NM
1 6
R1215
A side A side R1219 4
Q1203
R1216
R1215
5
V+5A 2 NM (2/2) R1217
(F)
NM
3
R1218
NM
R1218
NM
(D)
R1216
B R1219
NM
V-9HP V-9HP
D1204
NM
2 Mounting pieces of wire [DDC1022] instead of the resistors [R1205, R1206].
These parts are described as JP1205 and JP1206 in the circuit diagrams.
However, JP1205 and JP1206 are not printed on the board.
DDC1022-A
(3) Some units with serial numbers beginning with KF, and all units with serial numbers beginning
with on and after KG (planned)
1 Not mounting the ±9-V monitoring-circuit block. (This measure is the same as (2).)
2 Patterns on the board are to be modified so that R1205 and R1206 are short-circuited.
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2. SPECIFICATIONS
2.1 SPECIFICATIONS
General Input / Output terminals A
Power requirements........................AC 220 V to 240 V, 50 Hz/ 60 Hz PHONO input terminal
(SYXJ8, XJCN5) RCA pin jack........................................................................2 sets
AC 120 V, 60 Hz (UXJCB) CD/ LINE input terminal
AC 110 V to 120 V or 220 V to 240 V, 50 Hz/ 60 Hz (LXJ) RCA pin jacks......................................................................4 sets
AC 220 V, 60 Hz (KXJ5) LINE input terminal
Power consumption.....................41 W (SYXJ8, LXJ, KXJ5, XJCN5) RCA pin jack........................................................................2 sets
42 W (UXJJCB) MIC1 input terminal
Power consumption (standby)...................................................0.4 W XLR connector/ phone jack (Ø 6.3 mm)................................1 set
MIC2 input terminal
Main unit weight.........................................................7.1 kg (15.7 lb) Phone jack (Ø 6.3 mm).........................................................1 set
Max. dimensions............331 mm (W) × 107.9 mm (H) × 409 mm (D) RETURN Input terminals
(13 in. (W) × 4.2 in. (H) × 16.1 in. (D)) Phone jack (Ø 6.3 mm).........................................................1 set
Tolerable operating temperature...............................+5 °C to +35 °C DIGITAL IN coaxial input terminal
B
(+41 °F to +95 °F) RCA pin jacks......................................................................4 sets
Tolerable operating humidity..............5 % to 85 % (no condensation) MASTER output terminal
XLR connector......................................................................1 set
Audio Section RCA pin jack........................................................................1 sets
Sampling rate ........................................................................ 96 kHz BOOTH output terminal
A/ D, D/ A converter............................................................... .24 bits Phone jack (Ø 6.3 mm).........................................................1 set
Frequency characteristic REC OUT output terminal
CD/ LINE.............................................................20 Hz to 20 kHz RCA pin jack........................................................................1 sets
S/ N ratio (rated output) SEND output terminal
PHONO...............................................................................88 dB Phone jack (Ø 6.3 mm).........................................................1 set
CD/ LINE...........................................................................105 dB DIGITAL MASTER OUT coaxial output terminal
MIC1, MIC2.........................................................................84 dB RCA pin jack........................................................................1 sets
Total harmonic distortion (CD/ LINE — MASTER1)............ 0.005 % MIDI OUT terminal
Standard input level / Input impedance 5P DIN...................................................................................1 set C
PHONO...............................................................–52 dBu/ 47 kΩ PHONES output terminal
CD/ LINE.............................................................–12 dBu/ 47 kΩ Stereo phone jack (Ø 6.3 mm)..............................................1 set
MIC1......................................................................–52 dBu/ 8 kΩ USB terminal
MIC2....................................................................–52 dBu/ 12 kΩ B type....................................................................................1 set
RETURN..............................................................–12 dBu/ 47 kΩ LINK terminal
Standard output level / Load impedance / Output impedance LAN terminal (100Base-TX)..................................................1 set
MASTER1.......................................+8 dBu/ 10 kΩ/ 5 Ω or lower
MASTER2......................................+2 dBu/ 10 kΩ/ 22 Ω or lower • The specifications and design of this product are subject to
REC OUT.......................................–8 dBu/ 10 kΩ/ 22 Ω or lower change without notice.
BOOTH..........................................+8 dBu/ 10 kΩ/ 1 kΩ or lower
SEND...........................................–12 dBu/ 10 kΩ/ 1 kΩ or lower
PHONES........................................+8.5 dBu/ 32 Ω/ 1 Ω or lower
Rated output level / Load impedance D
MASTER1............................................................+26 dBu/ 10 kΩ
MASTER2............................................................+22 dBu/ 10 kΩ
Crosstalk (LINE).......................................................................82 dB
Channel equalizer characteristic
HI..........................................................–26 dB to +6 dB (13 kHz)
MID.........................................................–26 dB to +6 dB (1 kHz)
LOW........................................................–26 dB to +6 dB (70 Hz)
Microphone equalizer characteristic
HI........................................................–12 dB to +12 dB (10 kHz)
LOW....................................................–12 dB to +12 dB (100 Hz)
E
Accessories
• CD-ROM
(DXX2619)
• USB cable
(DDE1128)
• Power cord
(SYXJ8: ADG7062, UXJCB: DDG1108, LXJ: ADG7062,
KXJ5: XDG3066, /XJCN5: ADG7105)
• Operating instructions
(SYXJ8: DRB1533, UXJCB: DRB1542, LXJ: DRB1543,
KXJ5: DRB1545, /XJCN5: DRB1544)
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2.2 PANEL FACILITIES
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3. BASIC ITEMS FOR SERVICE

3.1 CHECK POINTS AFTER SERVICING
A
Items to be checked after servicing / DJM
To keep the product quality after servicing, confirm recommended check points shown below.
No. Procedures Check points
The firmware version must be the latest one.
1 Check the firmware version in Test mode.
If it is not the latest one, be sure to update it.
Confirm whether the customer complain has been solved.
2 If the customer complain occurs with the specific source, such as The customer complain must not be reappeared.
Mic, each Input, Fader, Equalizer, and Trim, input that specific Audio and operations must be normal.
source for checking.
Check the analog audio input
3
(Check the MIC1, MIC2 and RETURN.) (Make the analog Audio and operations must be normal. B
connections with CDJ player, analog player and MIC.)
Check the analog audio output (MASTER1, 2, REC, BOOTH and
4 Audio and operations must be normal.
SEND.) (Make the analog connection with CDJ player.)
Check the digital audio input/output
5 Audio for each channel and operations must be normal.
(Make the dgital connection with CDJ player.)
6 Check DVS. Make sure that PC applications function properly and that the
audio signals and operations of each channel are normal.
7 Check the headphones output. There must be no errors, such as noise, in the audio output.
Check playback, using the fader function. (Select the fader
8 function then check operations of each channel with audio signals There must be no errors in audio output and operations of each
via the DSP.) channel.
Check the connection of each interface. C
9 USB B The device must be properly recognized by the PC.

LINK The LAN must be properly connected in Test mode.
Make sure that all buttons and controls on the main unit
10 Check the buttons and controls.
function properly.
11 Check operations of the X-PAD. Touch the X-PAD in Test mode and check that it operates properly.
12 Check the FL displays and LEDs. Check that all the FL displays and LEDs light in Test mode.
13 Check the user settings. They must be returned to those set before repair.
14 Check the appearance of the product. No scratches or dirt on its appearance after receiving it for service.
See the table below for the items to be checked regarding audio.
D
Item to be checked regarding audio
Distortion
Noise
Volume too low
Volume too high
Volume fluctuating
Sound interrupted
3.2 JIGS LIST

Jigs List
Jig Name Part No. Purpose of use / Remarks
USB cable GGP1193 for PC connection, accessory
Lubricants and Glues List

F
Name Part No. Remarks

Lubricating oil GYA1001 Refer to "9.4 CONTROL PANEL SECTION (1/2)".
DJM-900NXS 13
5 6 7 8
1 2 3 4
3.3 PCB LOCATIONS
A
TRM1 ASSY C D TRM2 ASSY
USBI ASSY H E TRM3 ASSY
L CDCB ASSY K PNLA ASSY MIC1 ASSY B F TRM4 ASSY
• Bottom view
T ACSW
ASSY
B J SEND
ASSY
A INPUT
ASSY
C PNLB Q
ASSY
FADC R
ASSY
G MAIN ASSY S POWER SUPPLY
FAD1 ASSY M P FAD4 ASSY ASSY
I HPJK ASSY
FAD2 ASSY N O FAD3 ASSY
NOTES: - Parts marked by “NSP” are generally unavailable because they are not in our Master Spare Parts List.
- The > mark found on some component parts indicates the importance of the safety factor of the part.
Therefore, when replacing, be sure to use parts of identical designation.
Mark No. Description Part No. Mark No. Description Part No.
E LIST OF ASSEMBLIES
NSP 1..MOTHER ASSY DWM2418 NSP 1..SUB ASSY DWM2420
2..MAIN ASSY DWX3190 2..ACSW ASSY DWR1490
2..CDCB ASSY DWX3191 2..PNLB ASSY DWX3197
2..USBI ASSY DWX3192 2..FAD1 ASSY DWX3198
2..FAD2 ASSY DWX3199
NSP 1..AUDIO ASSY DWM2419
2..INPUT ASSY DWX3193 2..FAD3 ASSY DWX3200
2..SEND ASSY DWX3195 2..FAD4 ASSY DWX3201
2..TRM1 ASSY DWX3203 2..FADC ASSY DWX3202
2..TRM2 ASSY DWX3204 2..MIC1 ASSY DWX3207
2..HPJK ASSY DWX3208
2..TRM3 ASSY DWX3205
2..TRM4 ASSY DWX3206 1..PNLA ASSY DWX3196
F
> 1..POWER SUPPLY ASSY DWR1492
14 DJM-900NXS
1 2 3 4
5 6 7 8
DJM-900NXS 15
5 6 7 8
1 2 3 4
4. BLOCK DIAGRAM
4.1 OVERALL WIRING DIAGRAM
A
- When ordering service parts, be sure to refer to "EXPLODED VIEWS
and PARTS LIST" or "PCB PARTS LIST". MIDI MIC2 CH1
JA6202 JA6201 JA4201
- The > mark found on some component parts indicates the importance DKN1188-A DKN1614-A DKB1083-A
of the safety factor of the part. L

R
- : The power supply is shown with the marked box.
PHONO
CD/LINE
K K 1/2, K 2/2 MIC1 ASSY

(DWX3207)
TRM1 ASSY
(DWX3203)
PNLA ASSY CN6601 L CDCB ASSY
B
(DWX3196)
VKN1243-A
12 GNDD
11 RBC_LED
11
12 (DWX3191) B C
10 VR_TRIM1
10 V+3R3
9 V+3R3REF
10
MIC1_COLD
MIC1_COLD
11 GNDREF
9 GNDD 9
MIC1_HOT
MIC1_HOT
8 RBC_SI 8
7 RBC_SO
2 GNDA
4 GNDA
6 GNDA
8 GNDA
7 R_out
7
MIC1
3 L_out
5 R_in
6 GNDD
1 L_in
GNDA
GNDA
6
5 RBC_SCK 5
12
10
JA9001
CKS3533-A
XKP3076-A
4 GNDD 4
11
7
5
1
DKB1108-A
3 RBC_CS 3
2 RBC_INT CN3601
CN8201
CN9001
2
6
5
4
3
2
1
10
2
4
6
8
1 GNDD 1 VKN1416-A-TBB
11
1
3
5
7
9
6
2
5
1
6P 11P B to B
DDD1582-A 11 RBC_LED
5 RBC_SCK
BtoB
2 RBC_INT
CKS3561-A
7 RBC_SO
3 RBC_CS
XKP3065-A
10 V+3R3
8 RBC_SI
12 GNDD
10
2
4
8
12P FFC
CN6201
9 GNDD
6 GNDD
4 GNDD
1 GNDD
11
1
3
5
7
9
5
3
CN4201
L=52mm P=1.0mm
9 V+3R3D_REFA
11 GNDD_REFA
MIC1_COLD
MIC1_COLD
MIC1_HOT
MIC1_HOT
10 VR-TRIM1
GNDA
GNDA
7 R_out1
3 L_out1
2 GNDA
4 GNDA
6 GNDA
8 GNDA
5 R_in1
1 L_in1
PF03PP-B12 PF03PP2B07 PF03PP6B07 PF03PP4B12
6
5
4
3
2
1
1 V+3R3D_REFA
3 V+3R3D_REFA
1 V+3R3D_REFA
3 V+3R3D_REFA
L= 125mm L= 75mm L= 75mm L= 125mm

3 GNDD_REFA
1 GNDD_REFA
3 GNDD_REFA
1 GNDD_REFA
2 VR_FADER1
2 2 VR_FADER2
2 2 VR_FADER3
2 2 VR_FADER4
WHITE RED BLUE YELLOW
36 CH1 SEL(Time code)

A A 1/11- A 11/11
KM200NA3R
KM200NA3E
KM200NA3
KM200NA3Y
CN6610
CN6611
CN6612
CN6609
38 CH1_DATA
39 MIC_DATA
2
40 MIDI TXD
1
3
1
C
INPUT ASSY (DWX3193)
37 GNDD
KM200NA3Y
KM200NA3R
CN7401
CN7601
KM200NA3
KM200NA3E
CN7801
CN7201
2
2
3
1
39
37
CN4002
1 V+3R3REF2
3 V+3R3REF2
1 V+3R3REF2
3 V+3R3REF2
40
38
3 GNDREF2
1 GNDREF2
3 GNDREF2
1 GNDREF2
VKN1811-A
2 VR_FD1
2 VR_FD2
2 VR_FD3
2 VR_FD4
DIGITAL
IN OUT LAN
JA101 JA2401 JA1501
M N O P DKB1110-A
L
DKB1089-A VKN2023-A
FAD1 ASSY FAD2 ASSY FAD3 ASSY FAD4 ASSY CN6602

52492-3120
CN1001
9604S-31C
R
(DWX3198) (DWX3199) (DWX3200) (DWX3201) 31 V+5D_LED

30 GNDD_LED
29 V+5D_LED
28 GNDD_LED
30
28
31
29
1
3
2
4
1 V+5D_LED
2 GNDD_LED
3 V+5D_LED
4 GNDD_LED
27 V+12STB 5 V+12STB
26 STANDBY_LED 27 5
26 6 6 STANDBY_LED
25 STBY_KEY 7 STBY_KEY
25 7
24 MVR_MUTE 24 8 8 MVR_MUTE
23 CROSS_FADER 23 9 9 CROSSS_FADER
CN6603 22 EFX_ON/OFF 22 10 10 EFX_ON/OFF
52492-3120 21 GNDD 21 11 11 GNDD
31
31 EFFECT_ON/OFF 20 V+3R3D
19 GNDD
20
19
DDD1551-A 13
12 12 V+3R3D
13 GNDD
D 30
29
30 CROSS_FADER
29 ENC1_1
28 ENC1_0
18 V+34D
17 GNDD
18
17 15
14 14 V+34D
15 GNDD
5 CH1 SEL(Time code)

28 16 SUB_CPU_RESET 16 16 16 SUB_CPU_RESET
27
27 EFX_CH_SEL
26 GNDD_REFA_PA 15 SUB_CTRL 15 31P FFC 17 17 SUB_CTRL
26 25 V+3R3_REFA_PA 14 SUB_INT 14 18 18 SUB_INT
25 13 GNDD 13 19 19 GNDD
24 LED_MTX_SEL7A
24
23 23 LED_MTX_SEL6A 12 FPGA_CLK
11 GNDD
12
11 L=222mm P=1.25mm 21
20 20 FPGA_CLK
22 LED_MTX_SEL5A 21 GNDD
22 10 22
3 CH1_DATA
2 MIC_DATA
21 LED_OUT16 10 FPGA_TX_DAT 23 22 FPGA_TX_DAT
1 MIDI TXD
21 9 FPGA_RX_DAT 9
20 20 LED_OUT15 8 24 23 FPGA_RX_DAT
19 GNDD_LED 8 FPGA_SIGNAL 24 FPGA_SIGNAL
19 7 25
4 GNDD
18 KEY_IN7 7 GNDD 25 GNDD JA3801
18 6 V+3R3D_REFA 6 26
26 V+3R3D_REFA
DDD1553-A 16
17
15
17 KEY_IN6
16 KEY_IN5
15 KEY_IN4
5 VR_FADER1
4 GNDD_REFA
4
5
3
27
29
28 27 VR_FADER1
28 GND_REFA V+5VBUS
DKN1237-A
31P FFC 14 14 KEY_MTX_SEL5 3 VR_FADER2

2 VR_FADER3
2 30 29 VR_FADER2 D+USB
D-USB
13 1 31 30 VR_FADER3
GNDD
GNDD
3
13 KEY_MTX_SEL4
1 VR_FADER4
P=1.25mm 12 12 KEY_MTX_SEL3 31 VR_FADER4
2
4
11 11 KEY_MTX_SEL2
L=301mm 10
9
10 KEY_MTX_SEL1
9 GNDD
5
4
3
2
1
8
7
8 BOOTH_LEV EL
4 2 CN3801
7 HP_MIX
6 6 HP_LEVEL 5 3 1 KM200NA5L
5 5 LEVEL/DEPTH
4
3 4 GNDD_REFB
REVERSE 2 3 V+3R3_REFB
H USBI
1 2 GNDD
1 GNDD
(DWX
DDA1041-A
L=225mm PH
E
Q PNLB ASSY
31 EFFECT_ON/OFF 31
30 CROSS_FADER 30
29 ENC1_1 29 CN1802
28 ENC1_0 28
27 EFX_CH_SEL 2 4 AKM1276-A-TBB
27 1 3 5
26 GNDD_REFA_PA 26
25 V+3R3_REFA_PA 25
(DWX3197)
V+5VBUS
24 LED_MTX_SEL7 24
D+USB
23
D-USB
23 LED_MTX_SEL6
GNDD
GNDD
22 LED_MTX_SEL5 22
21 LED_OUT16 21
20 LED_OUT15 20
19 GNDD_LED 19
1
2
3
4
5
18 KEY_IN7 18
17 KEY_IN6 17
16 KEY_IN5 16
HPJK ASSY
R FADC ASSY
15
I
15 KEY_IN4
14
14 KEY_MTX_SEL5 13
13 KEY_MTX_SEL4 12
12 KEY_MTX_SEL3 11
11 KEY_MTX_SEL2 10
(DWX3202) (DWX3208)
G G 1/
10 KEY_MTX_SEL1 9
9 GNDD 8
8 BOOTH_LEV EL 7
7 HP_MIX 6
6 HP_LEVEL 5
5 LEVEL/DEPTH 4
4 GNDD_REFB 3
3 V+3R3_REFB 2
2 GNDD 1
1 GNDD
CN7001
9604S-31C
CN7002
KM200NA3
CN8001
KM200NA3L
MAIN ASS
3 V+3R3_REFA_2 3 1 1 GNDD_REFA_2
2 VR_CFD 2 2 2 VR_CFD JA9201
1 GNDD_REFA_2 1 3 3 V+3R3_REFA_2
DKN1622-A 4 HP_R 4 4 4 HP_R
3 GNDHP_O 3 3 3 GNDHP_O
2 GNDHP_O 2 2 2 GNDHP_O
F 1 HP_L 1 1 1 HP_L
PF03PP-B07 PHONES CN9201

KM200NA4L
CN3401
AKM1275-A-TBB
L= 75mm
PF04PP-S12
L=125mm
16 DJM-900NXS
1 2 3 4
1 GNDD 5 V+5VBUS
1
01
2 GNDD 4 D+USB
2
L
R
3 D-USB 3 D-USB
C2
3
4 2
4
4 D+USB 2 GNDD
614-A
5 3 1
5
5 V+5VBUS 1 GNDD
GITAL
JA2401
CN4201
1/11
CN8201
XKP3065-A
XKP3076-A
DKB1089-A
CN1802
OUT
1 L_in1 1 1 1 L_in
JA3801
CN3801
2 GNDA 2 2 2 GNDA
3 L_out1 3 3 3 L_out
DKN1237-A
C
4 GNDA 4 4 4 GNDA
WX3193)
KM200NA5L
5 R_in1 5 5 5 R_in
AKM1276-A-TBB
JA4201
6 GNDA 6 6 6 GNDA
JA1501
CD/LINE
L=225mm PH
7 R_out1 7 7 7 R_out
CH1
CN4002
VKN1811-A
8 8
11P B to B
8 GNDA 8 GNDA
DKB1083-A
LAN
DDA1041-A
1 MIDI TXD 40 MIDI TXD
VKN2023-A
9 V+3R3D_REFA 9 9 9 V+3R3REF
1 2 MIC_DATA 40 39 MIC_DATA 10 VR-TRIM1 10 10 10 VR_TRIM1
2 3 CH1_DATA 39 38 CH1_DATA 11 GNDD_REFA 11 11 11 GNDREF
L
R
PHONO
3 4 GNDD 38 37 GNDD
H USBI
4 5 CH1_SEL(Time code) 37 36 CH1_SEL(Time code)
5 6 CH1_SEL 36 35 CH1_SEL
6 7 CH1_TRIM 35 34 CH1_TRIM
7 8 GNDD 34 33 GNDD
8 9 CH2_DATA 33 32 CH2_DATA
9 10 GNDD 32 31 GNDD
31 CN4601 CN8401
10 11 CH2_SEL(Time code) 30 CH2_SEL(Time code)
11 12 CH2_SEL 30 29 CH2_SEL XKP3065-A XKP3076-A
JA4601
13 28 1 L_in2 1 1 1 L_in
14 GNDD 27 GNDD
CD/LINE
2 GNDA
ASSY
5
27 2 2 2 GNDA
5
14
CH2
15 MCLK 26 MCLK
(DWX3192)
15 26 3 L_out2
D
16 GNDD 25 GNDD 3 3 3 L_out
DKB1083-A
16 25 4 GNDA 4 4 4 GNDA
17 17 BCLK 24 24 BCLK
5 R_in2 5 5 5 R_in
LINE
18 GNDD 23 23 GNDD
18 6 GNDA 6 6 6 GNDA
19 LRCLK 22 LRCLK
L
19 22 7 R_out2 7 7
R
20 GNDD 21 GNDD 7 R_out

21 8 8
11P B to B
20 8 GNDA 8 GNDA
DDD1550-A
21 AD/DA_RESET 20 20 AD/DA_RESET 9
21 9 V+3R3D_REFA 9 9 V+3R3REF
22 22 GNDD_REFA 19 19 GNDD_REFA 10 10
10 VR-TRIM2
CN1002
23 GNDD_REFA 18 18 GNDD_REFA 10 VR_TRIM2
23 11 GNDD_REFA 11 11 11 GNDREF
24 24 V+3R3DRERA 17 17 V+3R3DRERA
25 25 V+3R3DRERA 16 16 V+3R3DRERA
26 26 GNDD 15 15 GNDD
G G 1/21- G 21/21
27 CH3_DATA 14 14 CH3_DATA
VKN2050- -TBB
27
28 28 GNDD 13 13 GNDD
40P FFC L=90mm P=0.5mm

JA5001
29 29 CH3_SEL(Time code) 12 12 CH3_SEL(Time code)

CD/LINE
11
CH3
30 30 CH3_SEL 11 CH3_SEL
DKB1083-A
32 9 CN5001 CN8601
MAIN ASSY (DWX3190)

32 GNDD 9 GNDD
8
LINE
33 33 CH4_DATA 8 CH4_DATA XKP3065-A XKP3076-A

34 34 GNDD 7 7 GNDD
L
7 V+5A
1 V+5D
6 1 L_in3 1 L_in
R
35
9 V-15A
1 1
2 GNDD
4 GNDD
35 CH4_SEL(Time code) 6 CH4_SEL(Time code)
3 V+12D
36 5 2 GNDA 2 GNDA
11 V+15A
36 CH4_SEL 5 CH4_SEL 2 2
5 V+3R3D
4
7
6
5
4
3
2
1
37 3 L_out3 3 3 3 L_out
E
6 GNDA_IN
8 GNDA_IN
37 CH4_TRIM 3 4 CH4_TRIM
10 GNDA_IN
38 38 GNDD 3 GNDD 4 GNDA 4 4 4 GNDA
39 2 5 R_in3 5 5 5 R_in
39 RETURN_DATA 2 RETURN_DATA
1
3
5
7
9
1
11
40 6 GNDA 6 6 6 GNDA
CN1203
40 RETRUN_IN 1 RETRUN_IN
2
4
6
8
7 R_out3 7 7 7 R_out
10
GNDD
GNDD
RESET
8 8
11P B to B
8 GNDA 8 GNDA
JA5401
9 V+3R3D_REFA 9 9 9 V+3R3REF
AKM1282-A-TBB
6
5
4
3
2
1
10 VR-TRIM3 10 10 10 VR_TRIM3
+12V STBY
CD/LINE
11 GNDD_REFA 11 11 11 GNDREF
CH4
STBY Control
DKB1083-A
1 1 V+5D
+12V Switched
+12V Switched
2 GNDD
+5VA
2
-15VA
GNDA
GNDA
+15VA
3 3 V+12D
Digital power supply

4 4 GNDD
Analog power supply

L
R
7
5
3
1
5
3
VMUTE 1
5
PHONO
5 V+3R3D
CN1202
6
4
2
6
4
2
6 GNDA_IN
CN1201
6
WHITE
AKM1277-A-TBB
AKM1278-A-TBB
7 7 V+5A
8 8 GNDA_IN
9 9 V-15A CN5401 CN8801
10 10 GNDA_IN
11 XKP3065-A XKP3076-A
11 V+15A
1 L_in4
1 1 1 L_in
JA5801
2 GNDA
7
5
3
1
5
3
1
2 2 2 GNDA
3 R_in4
8
6
4
2
6
4
2
6
3 3 3 L_out
6
4 GNDA
JA3201
L
4 4 4 GNDA
P2
XKB3066-A
6
5
4
3
2
1
5 L_out4
7
6
5
4
3
2
1
5 5
P3
5 R_in
L/MONO
6 GNDA 6 6 6 GNDA
RED
7 R_out4 7 7
L=75mm PH
CN4003
7 R_out
8 GNDA 8 8
11P B to B
8 GNDA
+5VA
-15VA
GNDA
GNDA
9 V+3R3D_REFA 9 9
+15VA
GNDD
GNDD
9 V+3R3REF
L=225mm
VMUTE
RESET
L=225mm
10 VR-TRIM4 10 10
PF11PP-D07
RETURN
10 VR_TRIM4
JA5802
11 GNDD_REFA 11 11
R
R
11 GNDREF
KM200NA11L
+12V STBY
JA3202
BOOTH
STBY Control
DKN1614-A
DKP3901-A
+12V Switched
+12V Switched
(DWX3203) (DWX3204) (DWX3205) (DWX3206)
PF06EP-S22
TRM1 ASSY TRM2 ASSY TRM3 ASSY TRM4 ASSY
JA3001
DKN1622-A DKN1622-A DKB1083-A
L
R
4 GND_PO
1 GND_PO
6 V+5A_SE
12 BCK_SE
3 V-15A_SE
9 GNDA_SE
8 GNDA_SE
5 GNDA_SE
JA2802
19 GNDD_O
17 GNDD_O
15 GNDD_O
13 GNDD_O
11 GNDD_O
2 V+15A_SE
L
10 MCLK_SE
7 MUTE_OUT
REC
16 LRCK_OUT
18 RESET_OUT
DKB1093-A
DJM-900NXS
14 ADAT_SEND_OUT
UXJCB/JXJ
8
6
4
2
MASTER2
18
16
14
12
10
R
19
9
7
5
3
1
17
15
13
11
JA2801
MASTER1
CN1003
AKM7077-A
DKB1093-A
S
19P
AC INLET ASSY
BRIDGE CONNECTOR
UXJCB DDG1108-A
DKP3927-A
AC POWER CORD
7
7
8
6
4
2
18
16
14
12
10
19
9
7
5
3
1
17
15
13
11
J
CN6401
AKP7199-A
JA6401
4 GND_PO
1 GND_PO
6 V+5A_SE
12 BCK_SE
:DKP3762-B
3 V-15A_SE
9 GNDA_SE
8 GNDA_SE
5 GNDA_SE
19 GNDD_O
17 GNDD_O
15 GNDD_O
13 GNDD_O
11 GNDD_O
2 V+15A_SE
10 MCLK_SE
7 MUTE_OUT
DKN1614-A
16 LRCK_OUT
T
L/MONO
18 RESET_OUT
SEND
14 ADAT_SEND_OUT
KXJ5:XDG3066-B
XJCN5:ADG7105-B
R
JA6402
AC INLET ASSY
(DWR1492)
SYXJ8/LOXJ:ADG7062-A
SYXJ8/LOXJ/XJCN5/KXJ5
DKN1614-A
AC POWER CORD
(DWR1490)
ACSW ASSY
P1
(DWX3195)
SEND ASSY
!
!
WHITE
LIVE
N
N
POWER SUPPLY ASSY

!
NEUTRAL
!
!
BROWN
8
8
JP9401
DKP3799-A
CN9401
2-178496-4
!
!
L
N
L=150mm
17
F
E
B
A
D
C
F
E
B
A
D
C
18
Analog Audio
Digital Audio
1
1
MUTE signal
Control Signal
POWER
L CDCB ASSY
X-PAD SENSOR IC CSI(SPI)
IC3601
FL K
(Touch Panel) SUB ucom
AD7147ACPZ500RL7
IC6601 PNLA ASSY
DYW1800- /J LED
(UPD78F1162AGF) (MATRIX)
KEY MATRIX CSI(SPI)
KEY_IN0-7
Q PNLB ASSY
RESET_OUT
2
2
VR MATRIX RESET IC
G
VR_IN1-6 IC2010
S-80927CNMC-G8X MAIN ASSY
FAD1 Assy
MAIN CPU
VR_FADER1 IC2011
Channel 1 Fader
DYW1799- /J POWER SUPPLY Assy
VR_FADER2 FAD2 Assy (UPD78F1166AGF)
Channel 2 Fader CSI(SPI)
VR_FADER3 FAD3 Assy
Channel 3 Fader
CKIO 80MHz S
VR_FADER4 FAD4 Assy
BUS
BUS
BUS
BUS
BUS
Channel 4 Fader
4.2 AUDIO SYSTEM BLOCK DIAGRAM
SH_BUS POWER
CROSS_FADEFADC Assy
SUPPLY ASSY
MCPU_BUS
Cross Fader FLASH (64M) SDRAM (128M)
DJM-900NXS
IC502 IC503 FPGA
EFFECT_ON/OFF
EFFECT_ON/OFF DYW1798- /J MD56V72160B-6TAZ
RESET
IC2214
CSI(SPI) DIT_SI/SO/SCK
ETHER PHY FLASH (4M)

Ether IC1603
SDRAM (256M) XC3S50A-4FTG256C
differential 100Ω BUS
100base RTL8201EL-VC-GR IC703 IC702
3
Descrete
3
ETHER UCOM DYW1797- /J MD56V82160-6TAZ

Mute circuit
A INPUT ASSY IC501
BUS
BUS
R5S76700B200BG
BUS
MIDI_TXD
MIDI ECLKOUT 98.304MHz
DSP_BUS
BUS
B MIC1 ASSY
IC6201
MIC 1 (mono) NJM4580MD
IC6203 ADAT_LANIN MVR_MUTE(MASTER TRIM)
NJM4580MD
MIC 2 (mono) ADC(single)

IC6204 ADAT_MIC_A
IC4202 AK5358AET
CPU_MUTE
RY4201
NJM4580MD IC4404
MUTE_OUT
VSR1008
TRIM1 Assy NJM4580MD
IC4402
LINE NJM4580MD CH1_L IC4408
ADC(differntial) IC2404
TC7WH157FK
DIT
4
4
PHONO IC4406 SRC
Channel 1
CS5381-KZ ADAT_DOUT CS8421-CZ IC2405 DIGITAL OUT
IC4201 CH1_R
NJM4580MD IC4401 ADAT_CH1_ AK4114VQ
RNB4580F IC4405
IC4602 Time Code NJM4580MD ADC(single)
NJM4580MD RY4601 IC4403
IC4804 AK5358AET
VSR1008 TRIM2 Assy NJM4580MD
LINE IC4802
NJM4580MD CH2_L IC3405 IC3406 RY3401 I HPJK ASSY
ADC(differntial) IC4808 NJM4580MD NJM4580MD VSR1008
CD IC4806 TC7WH157FK DAC(differential) HEAD
Channel 2
CH2_R CS5381-KZ IC3404
IC4601 ADAT_HP PHONES
NJM4580MD IC4801 AK4382AVT
RNB4580F IC4805 ADAT_CH2_ (TRS)
NJM4580MD RY5001 IC4803
IC5204 AK5358AET
LINE IC5202
NJM4580MD CH3_L
CD IC5206 TC7WH157FK
Channel 3
LINE IC4802
NJM4580MD CH2_L IC3405 IC3406 RY3401 I HPJK ASSY
ADC(differntial) IC4808 NJM4580MD NJM4580MD VSR1008
CD IC4806 TC7WH157FK DAC(differential) HEAD
Channe
CH2_R CS5381-KZ IC3404
IC4601 ADAT_HP PHONES
NJM4580MD IC4801 AK4382AVT
RNB4580F IC4805 ADAT_CH2_ (TRS)
NJM4580MD RY5001 IC4803
IC5204 AK5358AET
LINE IC5202
NJM4580MD CH3_L
CD IC5206 TC7WH157FK
Channel 3
CS5381-KZ
IC5001 CH3_R
IC5201
NJM4580MD RNB4580F RY2801
IC5205 ADAT_CH3_ IC2803 IC2806
Time Code NJM4580MD ADC(single) NJM4580MD NJM4580D VSR1008
IC5402 IC5203
NJM4580MD RY5401 IC5604 AK5358AET
5
TRIM4 Assy DAC(differential)
5
LINE VSR1008 NJM4580MD
IC5602 ADAT_MASTER IC2802 MASTER 1
NJM4580MD CH4_L IC5608 AK4390EF
ADC(differntial) TC7WH157FK
PHONO IC5606 IC2804 IC2805
Channel 4
CS5381-KZ NJM4580MD NJM4580MD RY2802
IC5401 CH4_R VSR1008
IC5601 ADAT_CH4_
NJM4580MD RNB4580F IC5605
Time Code NJM4580MD ADC(single) DSP
IC5603 MASTER 2
AK5358AET IC701 IC3002 IC3004
IC5801
RNB4580F NJM4580D NJM4580MD
D810K013BZKB400-K
ADC(single) IC3003
RETURN IC5802 RNB4580F
ADAT_RETURN DAC(single)
(TS) AK5358AET ADAT_REC IC3001 REC
AK4387ET
IC3202 IC3203
NJM4580MD NJM4580MD
IC110 ADAT_DIR1
DIR DAC(differential)
DIGITAL CH1 DIR9001PW ADAT_BO IC3201
BOOTH
AK4382AVT (TRS)
IC202 ADAT_DIR2
DIR IC3205 IC3204
DIGITAL CH2 DIR9001PW NJM4580MD NJM4580MD
MIDITXD_USB
UART
6
6
MIDITXD_USB IC302 ADAT_DIR3 IC6402
DIR RNB4580F
DIGITAL CH3 DIR9001PW DAC(single) SEND
IC6401 (TS)
ADAT_SEND AK4382AVT
DIR IC402 ADAT_DIR4
DIGITAL CH4 DIR9001PW J SEND ASSY
TC74LCX157FK
TC74LCX157FK IC112 IC114
IC111 IC113 ADAT_USB1 SRC
ADAT_UDOUT1
ADAT_USBIN1
CS8421-CZ
ADAT_DIR1 SRC ADAT_UDIN1
CS8421-CZ
IC204 IC206
ADAT_USBIN2 IC203 IC205 ADAT_USB2 SRC
ADAT_UDOUT2
SRC CS8421-CZ
ADAT_DIR2 ADAT_UDIN2
USBI ASSY CS8421-CZ
DJM-900NXS
H IC304 IC306
ADAT_USBIN3 IC303 IC305 ADAT_USB3 ADAT_UDOUT3
USB B SRC
USB Ucom SRC CS8421-CZ
USB differential 90Ω ADAT_DIR3
CS8421-CZ ADAT_UDIN3
CH1-4 IC1801 IC406
ADAT_USBIN4 IC404
IC403 IC405 ADAT_USB4 ADAT_UDOUT4
ADSP-BF524BBCZ-3A-K SRC
7
ADAT_DIR4
7
SRC CS8421-CZ
CS8421-CZ ADAT_UDIN4
USB_S_CLK 75MHz
SDRAM (64M)
IC1802 BUS
IS42S16400F-6TL
8
8
19
F
E
B
A
D
C
1 2 3 4
4.3 DSP BLOCK DIAGRAM
20 DJM-900NXS
1 2 3 4
5 6 7 8
DJM-900NXS 21
5 6 7 8
1 2 3 4
4.4 POWER BLOCK DIAGRAM
L V+3R3
B C
GNDD MIC1 ASSY TRI
CDCB ASSY
M V+3R3D_REFA
GNDD_REFA
FAD1 ASSY
B
GNDA
N V+3R3D_REFA
GNDD_REFA
K PNLA ASSY
FAD2 ASSY
V+3R3D_REFA
O GNDD_REFA
FAD3 ASSY
V+3R3D_REFA
P GNDD_REFA
FAD4 ASSY
C
V+3R3_REFA
V+3R3D_REFA
V+3R3_REFB
GNDD_REFA
GNDD_REFB
GNDD_REFA
GNDD_LED
V+5D_LED
V+12STB
V+3R3D
V+34D
GNDD
GNDD
V+3R3D_REFA
GNDD_REFA
D R Q PNLB ASSY
FADC ASSY
V+2R5D IC1402 V+3R3D V+3R3D
V+5VBUS
H GNDD
USB
UCOM
V+5D_LED
V+5D
USBI ASSY
E V+1R2D
I GNDHP
V+34D
Tr SW
Q1409
V+34D_1
HPJK ASSY
22 DJM-900NXS
1 2 3 4
5 6 7 8
C D E F
C1 ASSY TRIM1 ASSY TRIM2 ASSY TRIM3 ASSY TRIM4 ASSY
V+3R3D_REFA
V+3R3D_REFA
V+3R3D_REFA
V+3R3D_REFA
GNDD_REFA
GNDD_REFA
GNDD_REFA
GNDD_REFA
B
GNDA
GNDA
GNDA
GNDA
J
SEND ASSY
T
ACSW
A INPUT ASSY ASSY
NEUTRAL
C
LIVE
V+3R3D_REFA
GNDD_REFA
GND_PO
V+3R3D
GNDD
GNDA
GNDA
V+15A
V+15A
V-15A
V-15A
V+5A
V+5A
V+12D
GNDD
V+5D
VMUTE
ICP GNDA
P1207
+5VA
G MAIN ASSY
ICP
P1208
D
OUTPUT
ICP
P1210
+15VA S
D V+3R3D IC1407
V+12D
CIRCUIT -15VA POWER
ICP
P1209 SUPPLY
V+5D V+12D
ASSY
IC1405
V+5D_LED V+9HP V+15A_HP
IC1201
HP CIRCUIT
V-9HP V-15A_HP
V+12D IC1202
V+1R2D IC1406 GNDD E
V+12D ICP +12V Switched
P1204
Tr SW V+34D_1 V+12D
Q1409 IC1401 V+3R3E V+12E +12V STBY
MAIN_CPU IC1404
V+12STB
DJM-900NXS 23
5 6 7 8
1 2 3 4
5. DIAGNOSIS
5.1 POWER ON SEQUENCE
A
Sequece Diagram
SUB UCOM USB UCOM MAIN CPU FPGA ETHER UCOM DSP
Program start
MUTE setting ON
Reset Reset
Starting power supply to the peripheral ICs
NEC_B_CTRL setting to HIGH

Inhibiting SUB UCOM from
accessing FPGA
Canceling reset Canceling reset
B
Program start First boot start
Second boot RAM transfer
Entering main loop Second boot start
Starting power supply to FL Reset
Reset
Reset
FPGA_xPGM setting to LOW
SH_CTRL setting to LOW

C Inhibiting MAIN CPU from
accessing FPGA
Canceling reset of DSP Flash

Canceling reset
FPGA_xPGM setting to HIGH Program start

Starting FPGA configuration
FPGA_xINIT standby HIGH
FPGA_xPGM setting to HIGH

Accepting FPGA configuration
Loading data into FPGA
FPGA_DONE standby HIGH

D FPGA_DONE setting to HIGH
Completion of FPGA
configuration DSP_CTRL setting to HIGH
Notifying of starting FPGA
Canceling reset clock supply
ETHER UCOM-DSP:
Standby for handshake request
DPRAM validation
Obtaining FPGA version
ETHER UCOM-DSP:
Handshake request
ETHER UCOM-DSP: Standby for

response to handshake request
DSP version setting

E
ETHER UCOM-DSP:
Handshake request and response
ETHER UCOM-DSP:
Standby for handshake response
ETHER UCOM-DSP:
Handshake response
Canceling reset of SUBIC
Canceling reset of PHY

ETHER UCOM-MAIN CPU:
Handshake request
24 DJM-900NXS
1 2 3 4
5 6 7 8
A
A
SH_CTRL setting to HIGH

Inhibiting and cancelling
MAIN_CPU from accessing
FPGA
ETHER UCOM-MAIN CPU: ETHER UCOM-MAIN CPU:
Standby for handshake request Standby for handshake response
MAIN CPU version setting

ETHER UCOM-MAIN CPU:
Handshake response
MAIN CPU-SUB UCOM:

Standby for handshake indication MAIN CPU-SUB UCOM:
Standby for handshake indication
MAIN CPU-SUB UCOM: B

Handshake request
Standby for SUB UCOM version setting
MAIN CPU-SUB UCOM:

Standby for handshake response
NEC_B_CTRL setting to LOW
MAIN CPU-SUB UCOM: Inhibiting and cancelling

Handshake response SUB UCOM from accessing FPGA
Notifying of submicrocomputer
version Notifying of SUB UCOM version
Notifying of KEY data (every 2 ms)

Standby for notification of operation mode
Obtaining KEY data
Operation mode judgment

Notifying of operation mode
C
Process for the specific operation mode

Branching Update mode
Branching
Branching
USB UCOM reset cancel indication
USB_REQ standby LOW

Canceling reset
Bootstrap loader start

Loading of USB UCOM firmware
Program start Main program RAM transfer
Multitasking start Standby for USB UCOM version setting
Process for main communication start D

USB_REQ setting to LOW
Permission for USB function start
Permission for USB function start Standby for USB function start response
Completion of USB function start
USB function activation

USB UCOM version request
Standby for USB UCOM version response
Notifying of USB UCOM version

USB UCOM version setting
Standby for notification of setup data setting Loading of setup data E

Setup data setting
Notifying of setup data setting
SRC reset cancel Main program RAM transfer Updater RAM

transfer
Notifying of completion of
normal DSP startup
Updater start
Initialization process of main microcomputer Program start
Entering main loop Multitasking start
Completion of ETHER UCOM initialization

Notification of completion of
ETHER UCOM initialization
F
MUTE setting OFF
DJM-900NXS 25
5 6 7 8
1 2 3 4
5.2 TROUBLESHOOTING
A
Contents
[0] Prior Confirmation
[0-1] Checking Internal Cables
[1] Failure in Startup
[1-1] The unit dose not turn on, and the LED of the LFO FORM (WAKE UP) button does not flash.
[1-2] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) button flashes once.
[1-3] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes three times.
[1-4] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes five times.
[1-5] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes six times.
[1-6] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes seven times.
[1-7] The unit does not turn on, and the LED flashes endlessly.
[2] AUDIO INPUT
B
[2-1] No signal is input to the CD/LINE, PHONO connectors.
[2-2] No signal is input to the DIGITAL connector.
[2-3] No signal is input to the MIC1/MIC2 connectors.
[2-4] No signal is input to the RETURN connector.
[3] AUDIO OUTPUT
[3-1] No signal is output from the MASTER1/MASTER2 connectors.
[3-2] No signal is output from the REC connector.
[3-3] No signal is output from the BOOTH connector.
[3-4] No signal is output from the SEND connector.
[3-5] No signal is output from the PHONES connector.
[3-6] No signal is output from the DIGITAL MASTER OUT connector.
[4] DVS
C
[4-1] No analog timecode signal input to the mixer.
[4-2] No signal is input to and output from the USB 1 to 4 connectors.
[5] FL
[5-1] The FL does not light.
[6] X-PAD
[6-1] Pressing on the JOG dial not be detected.
[6-2] The X-PAD LEDs not light.
[7] LAN
[7-1] No LAN communication.
D *Point to be checked – Assys are classified with prefix.

[1-**] MAIN Assy
[2-**] INPUT Assy
[3-**] SEND Assy
[4-**] PNLA Assy
[5-**] HPJK Assy
[6-**] POER SUPPLY Assy
E
[0] Prior Confirmation
[0-1] Checking Internal Cables
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
Disconnection, Check that all the cables are securely 4.1 OVERALL
breakage, or connected. Securely connect the cables. If a cable is
1 Relevant part CONNECTION
loose connection Check that there is no breakage in the broken, replace it.
DIAGRAM
of internal cables cables.
26 DJM-900NXS
1 2 3 4
5 6 7 8
[1] Failure in Startup A
[1-1] The unit dose not turn on, and the LED of the LFO FORM (WAKE UP) button does not flash.
A V+12STBY power failure or MAIN_CPU (IC2011) startup error may be suspected.
MAIN Assy • If the V+12STBY power cannot be confirmed, go to [2].
1 Power failure Check for the V+12STBY power.
CN1202-1pin 1-1 • If the V+12STBY power can be confirmed, go to [3].
• If the V+12STBY power can be confirmed,

4.3 POWER
Power failure POWER SUPPLY the wire DKP3901 may be defective. Replace it. BLOCK DIAGRAM
2 Wire defect P3-1pin 5-1 Check for the V+12STBY power. • If the V+12STBY power cannot be confirmed,
the POWER SUPPLY Assy may be defective. 5.3
Replace it. INFORMATION ON
POWER
• If the V+3R3E power can be confirmed, go to [4]. DIAGNOSTICS B
MAIN Assy • If the V+3R3E power cannot be confirmed, the 3.3V
3 Power failure Check for the V+3R3E power.
IC1404-4pin 1-3 REGULATOR (IC1404) block may be defective.
Check for the status of soldering and replace it.
• If an output signal can be confirmed, go to [5].

RESET signal MAIN Assy • If an output signal cannot be confirmed, the 10.41 WAVEFORMS
4 Check for the CPU_RESET signal.
error R2023 1-39 RESET IC (IC2010) block may be defective. MAIN ASSY 1-39
• If an output signal cannot be confirmed, the

20 MHz CLK MAIN Assy 10.41 WAVEFORMS
5 Check for the 20M_CLK signal. crystal (X2001) block may be defective.
error R2019 1-40 MAIN ASSY 1-40
MAIN_CPU If the symptom persists after the above The MAIN CPU (IC2011) may be defective.
6 MAIN Assy —
defective corrections. Replace it. C
[1-2] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) button flashes once.
Communication error between the MAIN_CPU (IC2011) and DSP (IC701).
[POWER] [POWER] [POWER]
MAIN Assy 4.3 POWER
V+3R3D_DSP If an error is detected, check for the power supply
[POWER] BLOCK DIAGRAM
V+1R2D_DSP source on the power supply block diagram, and
DSP (IC701) L702 1-55 5.3
V+1R2D_DPLL repair it if it has an error. INFORMATION ON
does not start. L701 1-56
V+3R3D_DSP_MEM [RESET] POWER
L703 1-57
[RESET] If the signal level is not High, check for the signal DIAGNOSTICS
1 Devices R782 1-58
DSP_RESET supply source of the RESET signal, and repair it if [RESET]
• DSP (IC701) [RESET] 10.41 WAVEFORMS
Check that the signal level of DFLASH_RST it has an error.
• FLASH (IC703) R671 1-26 is High. [CLK] MAIN ASSY
• SDRAM (IC702) R674 1-27 [CLK] If no signal is input, check for the signal supply
1-26 1-27 D
[CLK] [CLK]
Check if the 24 MHz clock is input to source of the CLK signal and repair it if it has an 10.41 WAVEFORMS
R896 1-59
24.5M_CLK_DSP. error. MAIN ASSY 1-59
[1-3] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes three times.
Communication error between MAIN_CPU (IC2011) and ETHER_ICOM (IC501).
[POWER] Check that power at each point [POWER] [POWER]
ETHER_UCOM MAIN Assy is normal. If an error is detected, check for the power supply 4.3 POWER
(IC501) does not[POWER] V+1R2D_LAN source on the power supply block diagram, and BLOCK DIAGRAM
L502 1-23 V+3R3D_LAN repair it if it has an error. 5.3
start.
L501 1-24 V+1R2D_LAN_PLL [RESET] INFORMATION ON
L503 1-25 V+3R3D_LAN_MEM POWER
Devices If the signal level is not High, check for the signal DIAGNOSTICS
1
• ETHER UCOM R613 1-22 [RESET] supply source of the RESET signal, and repair it if [RESET] E
(IC501) [RESET] Check that the signal level of SUB_SH_ it has an error. 10.41 WAVEFORMS
RESET is High.
• FLASH (IC502) R673 [CLK]
1-43 MAIN ASSY 1-43
[CLK] If no signal is input, check for the signal supply
• SDRAM (IC503) [CLK] [CLK]
R2020 1-41 Check if the 20 MHz clock is input to 20M_ source of the CLK signal and repair it if it has an 10.41 WAVEFORMS
CLK_SH. error. MAIN ASSY 1-41
[POWER] [POWER]
MAIN Assy V+3R3D_FPGA [POWER] 4.3 POWER
[POWER] V+1R2D_FPGA If an error is detected, check for the power supply BLOCK DIAGRAM
R2239 1-50 V+3R3D_FPGA_AUX source on the power supply block diagram, and 5.3
FPGA (IC2214) INFORMATION ON
R2268 1-51 [RESET] repair it if it has an error.
configuration is POWER
R2280 1-52 Check that the signal level of SH_FPGA_ [RESET]
not completed. DIAGNOSTICS
[RESET] RST_X is High. If the signal level is not High, check for the signal [RESET]
2 supply source of the RESET signal, and repair it if
R717 1-30 [CLK] 10.41 WAVEFORMS
Devices
[CLK] Check if the 20 MHz clock is input to 24M_ it has an error. MAIN ASSY 1-30
• FPGA (IC2214) [CLK]
R2304 1-53 CLK_FPGA. [CLK]
• FLASH (IC502) 10.41 WAVEFORMS
[Communication line] [Communication line] If no signal is input, check for the signal supply F
R2335 1-54 source of the CLK signal and repair it if it has an MAIN ASSY 1-53
Check that the signal level of SH_FPGA_ [Communication line]
DONE is High. error. 10.41 WAVEFORMS
MAIN ASSY 1-54
DJM-900NXS 27
5 6 7 8
1 2 3 4
A
MAIN Assy 4.3 POWER
V+3R3D_DSP If an error is detected, check for the power supply
[POWER] BLOCK DIAGRAM
V+1R2D_DSP source on the power supply block diagram, and
DSP (IC701) L702 1-55 5.3
V+1R2D_DPLL repair it if it has an error. INFORMATION ON
does not start. L701 1-56
V+3R3D_DSP_MEM [RESET] POWER
L703 1-57
[RESET] If the signal level is not High, check for the signal DIAGNOSTICS
3 Devices R782 1-58
DSP_RESET supply source of the RESET signal, and repair it if [RESET]
• DSP (IC701) [RESET]
Check that the signal level of DFLASH_RST it has an error. 10.41 WAVEFORMS
• FLASH (IC703) R671 1-26 MAIN ASSY
is High. [CLK]
• SDRAM (IC702) R674 1-27 1-26 1-27
[CLK] If no signal is input, check for the signal supply
[CLK] [CLK]
Check if the 24 MHz clock is input to source of the CLK signal and repair it if it has an
R896 1-59 10.41 WAVEFORMS
24.5M_CLK_DSP. error. MAIN ASSY 1-59
B
[1-4] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes five times.
Communication error between MAIN_CPU (IC2011) and SUB_UCOM (IC6601).
[POWER] [POWER]
[POWER] If an error is detected, check for the power supply 4.3 POWER
V+3R3D_PA source on the power supply block diagram, and BLOCK DIAGRAM
SUB_UCOM PNLB Assy
[RESET] repair it if it has an error. 5.3
(IC6601) does [POWER]
Check that the signal level of SUB_CPU_ [RESET] INFORMATION ON
not start. R6615 4-19
1 RESET is High. If the signal level is not High, check for the signal POWER
[RESET] DIAGNOSTICS
[CLK] supply source of the RESET signal, and repair it if
Devices R6611 4-17 [RESET]
Check if the 20 MHz clock is input. it has an error.
• SUB_UCOM [CLK] 10.41 WAVEFORMS
As the drive circuit is in an IC, a normal [CLK]
(IC6601) X6601 4-18 PNLB ASSY 4-17
waveform check cannot be performed. If no signal is input, check for the signal supply [CLK]
C Simply check whether or not it oscillates. source of the CLK signal and repair it if it has an 10.41 WAVEFORMS
error. PNLB ASSY 4-18
[1-5] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes six times.
Communication error between MAIN_CPU (IC2011) and USB_UCOM (IC1801).
USB_UCOM MAIN Assy If an error is detected, check for the power supply 4.3 POWER
V+1R2D_USB
(IC1801) does [POWER] source on the power supply block diagram, and BLOCK DIAGRAM
V+3R3D_USB
not start. L1802 1-31 repair it if it has an error. 5.3
V+3R3D_USB_MEM INFORMATION ON
L1801 1-32 [RESET]
V+2R5D_USB_PLL POWER
1 Devices R1806 1-33 If the signal level is not High, check for the signal
[RESET] DIAGNOSTICS
• USB_UCOM R1817 1-34 supply source of the RESET signal, and repair it if
Check that the signal level of USB_RESET [RESET]
(IC1801) [RESET] it has an error. 10.41 WAVEFORMS
D is High.
• SDRAM C1831 1-36 [CLK] MAIN ASSY 1-36
[CLK]
(IC1802) [CLK] If no signal is input, check for the signal supply [CLK]
Check if the 24 MHz clock is input to
R2304 1-35 source of the CLK signal and repair it if it has an 10.41 WAVEFORMS
24M_CLK_USB.
error. MAIN ASSY 1-35
[1-6] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes seven times.
Communication error between MAIN_CPU (IC2011) and DIT (IC2405).
[POWER] [POWER]
[POWER] If an error is detected, check for the power supply 4.3 POWER
Check for the voltage of the V+3R3D_DIT source on the power supply block diagram, and BLOCK DIAGRAM
MAIN Assy
power. repair it if it has an error. 5.3
[POWER] INFORMATION ON
R2425 1-73 [RESET]
E Power [RESET] If the signal level is not High, check for the signal POWER
1 [RESET] DIAGNOSTICS
Signal line Check that the signal level of DIT_RESET supply source of the RESET signal, and repair it if
C2411 1-69 [RESET]
is High. it has an error.
[CLK] 10.41 WAVEFORMS
[CLK] MAIN ASSY 1-69
R2409 1-68
[CLK] If no signal is input, check for the signal supply [CLK]
Check that 24M CLK is input. source of the CLK signal and repair it if it has an 10.41 WAVEFORMS
error. MAIN ASSY 1-68
MAIN Assy If the symptom persists after the above DIT (IC2405) may be defective.
2 Defective part —
DIT (IC2405) corrections. Replace it.
[1-7] The unit does not turn on, and the LED flashes endlessly.
The unit is shut down in error by the Power Monitoring Circuit.
F No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
See "5.4 VOLTAGE Check for power at each point, following 5.4 VOLTAGE MONI-
1 Power failure Repair the defective parts.
MONITORING CIRCUIT.” “5.4 VOLTAGE MONITORING CIRCUIT.” TORING CIRCUIT
28 DJM-900NXS
1 2 3 4
5 6 7 8
A
[2] AUDIO INPUT
[2-1] No signal is input to the CD/LINE, PHONO connectors.
DIGITAL, CD/LINE,
Prior Confirm on the screen that the selector Operating
PHONO, LINE, USB
Confirmation is set properly. instructions
*/* selector/TRIM
INPUT Assy • If it is low, go to [2].
IC4408/IC4808/
Loose connection IC5208/IC5608 [Checking the Audio Timecode select block] • If it is high, check for loose connection with the MAIN
Assy, improper part-mounting status for communica- 10.41 WAVEFORMS
1 /defective parts Check that the TC_SEL* signal level is Low.
6 pin tion, or imporper mounting status of the MAIN CPU. INPUT ASSY 2-32
Representative If no problem is still found, the MAIN CPU (IC201)
CH1 2-32 may be defective. Replace it.
INPUT Assy B
IC4406(CH1)
IC4806(CH2) [Checking the ADC block] If no audio signal is input to ADC, a problem in
IC5206(CH3) 10.41 WAVEFORMS an analog circuit at a previous stage may be 10.41 WAVEFORMS
Loose connection
2 IC5606(CH4) INPUT ASSY 2-32 suspected. INPUT ASSY
/defective parts
16, 17, 20, 21 pin Check for an audio signal at the input • If no audio signal is input, go to [5]. 2-20 2-21
Representative connector of ADC. • If an audio signal is input, go to [3].
CH1_R- 2-20
/CH1_R+ 2-21
INPUT Assy
IC4406(CH1)
IC4806(CH2) • If the RESET signal level is L, go to [9].
Loose connection 10.41 WAVEFORMS
3 IC5206(CH3) Check for the RESET signal of ADC. • If the RESET signal level is H, go to [4].
/defective parts INPUT ASSY 2-22
IC5606(CH4) - 1 pin
Representative CH1
2-22 C
INPUT Assy
IC4406(CH1)
IC4806(CH2)
IC5206(CH3)
10.41 WAVEFORMS
Loose connection IC5606(CH4) 10.41 WAVEFORMS • If no CLK signal is input, go to [11].
4 LRCK: 3 pin INPUT ASSY 2-32 • If the CLK signal is input, ADC must be INPUT ASSY
/defective parts
Representative 2-23 Check for the CLK signal of ADC. improperly soldered or defective. 2-23 2-24 2-25
BCLK: 4 pin
Representative 2-24
MCLK: 5 pin
Representative 2-25
INPUT Assy
IC4402(CH1)
IC4802(CH2)
IC5202(CH3) D
Loose connection IC5602(CH4) [Checking an Intermediate Buffer block] • If a singal is input but not output, this block 10.41 WAVEFORMS
5 /defective parts Input: 2, 3, 5, 6 pin INPUT ASSY
Check for the signal input to and output must be improperly soldered or defective.
Representative CH1 from the Intermediate Buffer block. • If no signal is input, go to [6]. 2-18 2-19
2-18 after TRIM
Output: 1, 7 pin
Representative CH1
R 2-19
INPUT Assy
CN4201(CH1)
CN4601(CH2)
• If a signal is interrupted at the periphery of
Loose connection CN5001(CH3) [Checking the TRIM] TRIM, check for the mounting status or 10.41 WAVEFORMS
6 CN5401(CH4) Check for an audio signal at the periphery
/defective parts soldering status of TRIM. If no problem is found, INPUT ASSY
1 pin, 3 pin, 5 pin,
of TRIM. replace the TRIM Assy. 2-17 2-18
7 pin
Representative CH1 • If there is no signal before TRIM, go to [7].
E
R 2-17 2-18
INPUT Assy
IC4201(CH1 PHONO)
IC4202(CH1 LINE)
IC4601(CH2 CD)
IC4602(CH2 LINE) [Checking the Input Buffer block] • If no singal is output, this block must be
Loose connection IC5001(CH3 CD) 10.41 WAVEFORMS
7 Check if an audio signal is output from the improperly soldered or defective.
/defective parts IC5002(CH3 LINE) INPUT ASSY 2-16
operation amplifier. • If an audio signal is output, go to [8].
IC5401(CH4 PHONO)
IC5402(CH4 CD)
1 pin, 7 pin
Representative CH1
LINE R 2-16
DJM-900NXS 29
5 6 7 8
1 2 3 4
A
• If a LINE_SEL* signal is not output properly,
INPUT Assy/ [Checking the RELAY block] check for loose connection with the MAIN Assy,
MAIN Assy Check for the LINE_SEL* signal. improper part mounting status for communication,
Loose connection If the input selector is set to PHONO, or improper mounting of the MAIN CPU.
8 LINE_SEL* 10.41 WAVEFORMS
/defective parts the LINE_SEL* signal level is H. If there is no problem, the MAIN CPU (IC2011) INPUT ASSY 2-14
Representative If the input selector is set to CD/LINE, may be defective. Replace it.
LINE_SEL1 the LINE_SEL* signal level is L. • If a LINE_SEL* signal is output properly, this
2-14
block must be improperly soldered or defective.
INPUT Assy
IC4009/IC4010 • If the signal level at Pin 2 is H and that at Pin 4 is 10.41 WAVEFORMS
Loose connection 2 pin, 4 pin [Checking the RESET signal path] L, IC4009/IC4010 must be soldered impropely or INPUT ASSY
9 /defective parts Representative Check for the RESET signal. defective. 2-9 2-8
RESET_IN 2-9 • If the signal level at Pin 2 is L, go to [10].
B RESET_IN1 2-8
INPUT Assy • If the signal level at Pin 2 is L, go to [12].

IC4005 2 pin, 3 pin • If the signal level at Pin 3 is not normal, check for 10.41 WAVEFORMS
Loose connection [Checking the RESET signal path] INPUT ASSY
10 AD/DA_RESET 2-7 BCLK in [13].
/defective parts Check for the RESET signal.
BCLK 2-12 • If the signal level at Pin 2 is H and that at Pin 3 is 2-7 2-12
normal, IC4005 is soldered improperly or defective.
INPUT Assy
LRCLK: IC4002/IC4006
BCLK: IC4003/IC4007
MCLK: IC4004/IC4008 • If the signal level at Pin 2 is normal and Pin 4 has
2 pin, 4 pin no signal, IC4002/IC4006/IC4003/IC4007/IC4004 10.41 WAVEFORMS
10.41 WAVEFORMS INPUT ASSY
Loose connection Representative [Checking the CLK signal path]
11 LRCLK_IN_2 2-6 INPUT ASSY 2-6 2-13 2-3
/defective parts Check for the LRCLK, BCLK, and MCLK
LRCLK 2-13 2-18 2-19 2-12 2-2 2-11
signals. /IC4008 must be improperly soldered or defective.
BCLK_IN_2 2-3
C BCLK 2-12 • If the signal at Pin 2 is not normal, go to [13].
MCLK_IN_2 2-2
MCLK 2-11
Loose connection MAIN Assy [Checking the RESET signal path] If no problem is found, ETHER UCOM (IC501) 10.41 WAVEFORMS
12 MAIN ASSY 1-28
/defective parts R709 1-28 Check for the RESET signal. must be improperly soldered or defective.
MAIN Assy
LRCLK: IC2206 2,4 pin • If the signal at Pin 2 is normal and Pin 4 has no 10.41 WAVEFORMS
signal, IC2206/IC2209/IC2210 must be improperly
Loose connection 1-44 1-49 [Checking the CLK signal path] MAIN ASSY
13 BCLK: IC2209 2,4 pin Check for the LRCLK, BCLK, and MCLK soldered or defective. 1-44 1-49
/defective parts
1-45 1-48 signals. • If the signal at Pin 2 is not normal, FPGA (IC2214) 1-45 1-48
MCLK: IC2210 2,4 pin must be improperly soldered or defective. 1-46 1-47
1-46 1-47
D [2-2] No signal is input to the DIGITAL connector.

DIGITAL, CD/LINE,
Prior Confirm on the screen that the selector
PHONO, LINE, USB
Confirmation is set properly.
*/* selector/TRIM
MAIN Assy
IC101(CH1)
Loose connection IC201(CH2) If any of the signals is not input, IC101(CH1)
10.41 WAVEFORMS
1 IC301(CH3) Check if a signal is input to DIGITAL /IC201(CH2)/IC301(CH3)/IC401(CH4) may be
/defective parts MAIN ASSY 1-6
IC401(CH4) -5 pin properly. defective.
Representative
CH1_SPDIF 1-6
MAIN Assy
IC110(CH1)
E
IC202(CH2)
Loose connection • If it is H, go to [3]. 10.41 WAVEFORMS
IC302(CH3) Check that the RESET signal level of the
2 /defective parts • If it is L and IC504 has no problem, ETHER MAIN ASSY 1-11
IC402(CH4) -21 pin DIR is High.
UCOM (IC501) must be improperly soldered or
Representative
defective.
DIR_RESET
1-11
MAIN Assy
IC110(CH1)
IC202(CH2)
IC302(CH3)
IC402(CH4) • If a signal is output, go to [4]. 10.41 WAVEFORMS
Loose connection • LRCKO: 10 pin Check for the LRCKO, BCKO, SCKO, • If any of the signals is not output, IC110(CH1) MAIN ASSY
3 /defective parts 1-8 1-9
• BCKO: 11 pin DOUT signal output from DIR. /IC202(CH2)/IC302(CH3)/IC402(CH4) may be
• SCKO: 4 pin improperly soldered or defective. 1-7 1-10
• DOUT: 12 pin
F Representative
1-8 1-9 1-7 1-10
30 DJM-900NXS
1 2 3 4
5 6 7 8
A
MAIN Assy
IC111(CH1)
IC203(CH2)
Loose connection IC303(CH3) Check for the digital audio signal at 10.41 WAVEFORMS
4 • If there is a signal, go to [6].
MAIN ASSY 1-16
/defective parts IC403(CH4) -9 pin DIGI/USB SW. • If there is no signal, go to [5].
Representative
ADATIN_SRC1
1-16
MAIN Assy
IC111(CH1)
• If it is L, but no signal is output, IC111(CH1)
IC203(CH2) Check that the DIGI_SEL* signal level is Low. /IC203(CH2)/IC303(CH3)/IC403(CH4) must be 10.41 WAVEFORMS
Loose connection IC303(CH3) IC111(CH1)/IC203(CH2)/IC303(CH3)/
5 improperly soldered or defective. MAIN ASSY 1-12
/defective parts IC403(CH4) -9 pin
IC403(CH4) 1 pin • If it is not L, MAIN CUP: IC2011 must be B
Representative
improperly soldered or defective.
DIGI_SEL1
1-12
MAIN Assy
UDIN1
UDIN2 • If a signal is outout, DSP (IC701) must be 10.41 WAVEFORMS
Loose connection UDIN3
6 Check for the output signal at SRC. improperly soldered or defective. MAIN ASSY 1-17
/defective parts UDIN4 • If a signal I not output, go to [7].
Test land
Representative 1-17
MAIN Assy
IC113(CH1)
• If it is L, Ether UCOM (IC501) must be
Loose connection IC205(CH2) Check that the CH*SRC_RESET signal
10.41 WAVEFORMS
7 IC305(CH3) improperly soldered or defective. MAIN ASSY 1-13
/defective parts level is High. • If it is H, go to [8]. C
IC405(CH4)
5 pin
Representative 1-13
MAIN Assy • If there is no CLK signal, IC111(CH1)/IC203

IC113(CH1) (CH2)/IC303(CH3)/IC403(CH4) must be
Loose connection IC205(CH2) Check for the CLK signal (ILRCK, ISCLK) improperly soldered or defective. 10.41 WAVEFORMS
8 IC305(CH3) • If there is a CLK signal, IC113(CH1)/IC205 MAIN ASSY
/defective parts
IC405(CH4) -7, 8 pin at SRC. (CH2)/IC305(CH3)/IC405(CH4) must be 1-14 1-15
Representative improperly soldered or defective.
1-14 1-15
[2-3] No signal is input to the MIC1/MIC2 connectors.

OFF, ON, TALK D
Prior Confirm on the screen that the selector
Confirmation OVER switch is set properly.
If no audio signal is input to the ADC, a problem
INPUT Assy
Loose connection IC6204 in an analog circuit at a previous stage may be 10.41 WAVEFORMS
Check for an audio signal at the input
1 /defective parts suspected. INPUT ASSY
MIC1: 2 pin 2-41 connector of the ADC.
• If no signal is input, go to [2]. 2-41 2-44
MIC2: 1 pin 2-44 • If a signal is input, go to [3].
• If a signal is interrupted at the periphery of the
INPUT Assy TRIM, VR6202/VR6201 must be improperly 10.41 WAVEFORMS
Loose connection VR6202 Check for an audio signal at the periphery soldered or defective.
2 2-39 2-40 INPUT ASSY
/defective parts of the TRIM. • If there is no signal before the TRIM, the MIC1 2-39 2-40
VR6201 2-42 2-43
/MIC2 AMP block must be improperly soldered 2-42 2-43
or defective.
Loose connection INPUT Assy • If the signal level is L, go to [5]. 10.41 WAVEFORMS
3 /defective parts Check for the RESET signal of the ADC. • If the signal level is H, go to [4].
IC6204 13 pin 2-45 INPUT ASSY 2-45 E
INPUT Assy
LRCK: IC6204 10.41 WAVEFORMS
10pi 2-48 • If there is no CLK signal, go to [7]. INPUT ASSY
Loose connection Check for the CLK signal of the ADC.
4 BCLK: IC6204 • If there is a CLK signal but no signal is output 2-48
/defective parts • LRCK • BCLK • MCLK
12 pin 2-46 from the ADC, the ADC must be improperly 2-46
MCLK: IC6204 soldered or defective. 2-47
11 pin 2-47
• If the signal level at Pin 2 is H and that at Pin 4
Loose connection INPUT Assy is L, IC4010 must be improperly soldered or
10.41 WAVEFORMS
5 /defective parts IC4010 2 pin 2-9 Check for the RESET signal. INPUT ASSY
4 pin 2-10 defective.
2-9 2-10
• If the signal level at Pin 2 is L, go to [6].
• If the signal level at Pin 2 is L, go to [8].
Loose connection INPUT Assy • If the signal level at Pin 3 is not normal, check
10.41 WAVEFORMS
6 /defective parts IC4005 2 pin, 3 pin Check for the RESET signal. for BCLK in [7]. F
INPUT ASSY
• lf a signal at Pin 2 is H and that at Pin 3 is
2-7 2-12 2-7 2-12
normal, IC4005 must be improperly soldered
or defective.
DJM-900NXS 31
5 6 7 8
1 2 3 4
A
INPUT Assy
• LRCK: IC4006 10.41 WAVEFORMS
• If the signal at Pin 2 is normal and Pin 4 has
Loose connection 2 pin 2-11 , 4 pin 2-2 INPUT ASSY
Check for the LRCLK, BCLK, and MCLK no signal, IC4006/IC4007/IC4008 must be
7 • BCLK: IC4007 2-11 2-2
/defective parts signals. improperly soldered or defective.
2 pin 2-12 , 4 pin 2-4
• If the signal at Pin 2 is not normal, go to [9]. 2-12 2-4
• MCLK: IC4008
2-13 2-6
2 pin 2-13 , 4 pin 2-6
• If no problem with the signal is found, check for

Loose connection MAIN Assy [Checking the RESET signal path] the cable connection with the MAIN Assy and
8 the parts mounted along the communication line. 10.41 WAVEFORMS
/defective parts R709 1-28 Check for the RESET signal. MAIN ASSY 1-28
• If no problem is found, ETHER UCOM (IC501)
may be improperly soldered.
B MAIN Assy
LRCLK: IC2206 • If the signal at Pin 2 is normal and Pin 4 has no 10.41 WAVEFORMS
2, 4 pin 1-44 1-49 [Checking the CLK signal path] signal, IC2206/IC2209/IC2210 must be improperly MAIN ASSY
Loose connection
9 BCLK: IC2209 Check for the LRCLK, BCLK, and MCLK soldered or defective. 1-44 1-49
/defective parts 2, 4 pin 1-45 1-48 signals. • If a signal at Pin 2 is not normal, FPGA (IC2214) 1-45 1-48
MCLK: IC2210 must be improperly soldered or defective. 1-46 1-47
2, 4 pin 1-46 1-47
[2-4] No signal is input to the RETURN connector.

DELAY, ECHO,
SPIRAL, REVERB,
TRANS, FILTER,
FLANGER, PHASER,
C ROBOT, MELODIC, • Check that the type for BEAT EFFECT is
Prior
SLIP ROLL, ROLL, set to SND/RTN.
Confirmation
REV ROLL, SND/RTN • Check that the BEAT EFFECT is set to ON.
(MIDI LFO) SW
/EFFECT ON/OFF
button
Loose connection INPUT Assy • If it is L, JA5801 must be improperly soldered

10.41 WAVEFORMS
1 /defective parts CN4002 1 pin Check that the RETURN IN signal level is H. or defective.
INPUT ASSY 2-15
2-15 • If it is H, go to [2].
If no audio signal is input to the ADC, a problem
INPUT Assy in an analog circuit at a previous stage may be
IC5802 1 pin 2-34 , Check for an audio signal at the input suspected.
2 /defective parts INPUT ASSY
2 pin 2-33 connector of the ADC. • If no singal is input, the Input Buffer block must
2-34
be improperly soldered or defective.
2-33
• If a signal is input, go to [3].
D
Loose connection INPUT Assy • If the signal level is L, go to [5]. 10.41 WAVEFORMS
3 /defective parts IC5802 13 pin 2-35 Check for the RESET signal of the ADC.
• If the signal level is H, go to [4]. INPUT ASSY 2-35
INPUT Assy
• LRCK: IC5802
• If there is no signal, go to [7]. 10.41 WAVEFORMS
10 pin 2-38
Loose connection Check for the CLK signal of the ADC. • If there is a CLK signal but no signal is output INPUT ASSY
4 • BCLK: IC5802
/defective parts from the ADC, the ADC must be improperly 2-38
12 pin 2-36 LRCK, BCLK, MCLK
• MCLK: IC5802 soldered or defective. 2-36
11 pin 2-37 2-37
INPUT Assy
• If a signal at Pin 2 is H and that at Pin 4 is L, 10.41 WAVEFORMS
Loose connection IC4009 2 pin 2-9 ,
5 Check for Pins 2 and 4 of IC4009. IC4009 must be improperly soldered or defective. INPUT ASSY
/defective parts 4 pin 2-8
• If the singal level at Pin 2 is L, go to [6]. 2-9 2-8
E RESET_IN1
• If the singal level at Pin 2 is L, go to [8].
INPUT Assy • If a signal at Pin 3 is not normal, check for BCLK
6 IC4005 2 pin, 3 pin Check for Pins 2 and 3 of IC4005. in [7].
/defective parts INPUT ASSY
2-7 2-12 • If the signal level at Pin 2 is H and that at Pin 3 is
2-7 2-12
normal, IC4005 must be improperly soldered or
defective.
INPUT Assy
• LRCK: IC4002 10.41 WAVEFORMS
2 pin 2-11 , 4 pin 2-1 • If a signal at Pin 2 is normal and Pin 4 has no INPUT ASSY
Loose connection • BCLK: IC4003 signal, IC4002/IC4003/IC4004 must be 2-11 2-1
7 /defective parts 2 pin 2-12 , 4 pin 2-3 Check for the LRCLK, BCLK, and MCLK improperly soldered or defective.
signals. 2-12 2-3
• MCLK: IC4004 • If a signal at Pin 2 is not normal, go to [9].
2-13 2-5
2 pin 2-13 , 4 pin 2-5
F • If no problem with the signal is found, check for

the cable connection with the MAIN Assy and
Loose connection MAIN Assy [Checking the RESET signal path] 10.41 WAVEFORMS
8 the parts mounted along the communication line.
/defective parts R709 1-28 Check for the RESET signal. MAIN ASSY 1-28
• If no problem is found, ETHER UCOM (IC501)
may be improperly soldered.
32 DJM-900NXS
1 2 3 4
5 6 7 8
A
MAIN Assy
LRCLK: IC2206 • If the signal at Pin 2 is normal and Pin 4 has no 10.41 WAVEFORMS
Loose connection 2,4 pin 1-44 1-49 [Checking the CLK signal path] signal, IC2206/IC2209/IC2210 must be improperly MAIN ASSY
9 /defective parts BCLK: IC2209 Check for the LRCLK, BCLK, and MCLK soldered or defective. 1-44 1-49
2,4 pin 1-45 1-48 signals. • If a signal at Pin 2 is not normal, FPGA (IC2214) 1-45 1-48
MCLK: IC2210 must be improperly soldered or defective. 1-46 1-47
2,4 pin 1-46 1-47
[3] AUDIO OUTPUT

[3-1] No signal is output from the MASTER1/MASTER2 connectors.
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference B
• If neither MASTER 1 nor 2 connector outputs, go to [2].
Prior MASTER1 / Identify the connector(s) that do(es) not
1 • If only the MASTER 1 connector does not output, go to [11].
Confirmation MASTER2 output signals.
• If only the MASTER2 connector does not output, go to [13].
MAIN Assy
IC2802-10,11,20, • If a signal is output from the DAC output (Pins 10, 10.41 WAVEFORMS
21 pin 11, 20, and 21 of IC2802) but no signal is output MAIN ASSY
Loose connection 1-92 1-93 [Checking the Shaping Noise Filter] from Pins 1 and 7 of IC2803/IC2804, the Shaping
1-92 1-93
2 1-90 1-91 Check for the DAC differential audio signal Noise Filter block must be improperly soldered or
/defective parts 1-90 1-91
IC2803 1,7 pin output. defective.
1-94 1-95
1-94 1-95 • If no signal is output from the DAC output (Pins
1-96 1-97
/IC2804-1,7 pin 10, 11, 20, and 21 of IC2802), go to [3].
1-96 1-97
• If no signal is output, the DSP(IC701) must be

Loose connection MAIN Assy Check that a signal is output from the improperly soldered or defective. 10.41 WAVEFORMS C
3 /defective parts IC2802-29 pin 1-89 ADAT_MASTER_OUT. • If a signal is output, go to [4]. MAIN ASSY 1-89
• If it is H, failure of the PNLA may be suspected.

Loose connection MAIN Assy Check that the MVR_MUTE_OUT signal Check for the MASTER LEVEL operation in test 10.41 WAVEFORMS
4 /defective parts IC2802-1 pin 1-84 level is Low. mode. MAIN ASSY 1-84
• If it is L, go to [5].
Loose connection MAIN Assy Check that the RESET_OUT signal level is • If it is H, go to [8]. 10.41 WAVEFORMS
5
/defective parts IC2802-27 pin 1-85 High. • If it is L, go to [6]. MAIN ASSY 1-85
MAIN Assy • If a signal level at Pin 2 is H and that at Pin 4 is L, 10.41 WAVEFORMS
Loose connection
6 IC2601-2,4 pin Check for the RESET_OUT signal. IC2601 must be improperly soldered or defective. MAIN ASSY
/defective parts
1-78 1-82 • If the singal level at Pin 2 is L, go to [7]. 1-78 1-82
Loose connection MAIN Assy Check for the mounting status of the RESET • If no problem is found, ETHER UCOM (IC501) 10.41 WAVEFORMS
7 R709 1-28
/defective parts signal line R709. must be improperly soldered or defective. MAIN ASSY 1-28 D
MAIN Assy
IC2802 • If [3], [4], [5], and [8] are normal but a signal is
not output from the DAC (Pins 10, 11, 20, and 10.41 WAVEFORMS
Loose connection LRCLK 30 pin Check for the CLK signal of IC2802.
8 21 of IC2802), IC2802 must be improperly MAIN ASSY
/defective parts BCLK 28 pin LRCK, BCLK, MCLK soldered or defective. 1-88 1-87 1-86
MCLK 24 pin
• If no CLK signal is found, go to [9].
1-88 1-87 1-86
MAIN Assy
LRCK: IC2604 10.41 WAVEFORMS
Check for Pins 2 and 4 of • If the signal at Pin 2 is normal and Pin 4 has no
2,4 pin 1-77 1-81 MAIN ASSY
Loose connection LRCK: IC2604 signal, IC2604/IC2603/IC2602 must be
9 BCLK: IC2603 1-77 1-81
/defective parts BCLK: IC2603 improperly soldered or defective.
2,4 pin 1-76 1-80 1-76 1-80
MCLK: IC2602 • If a signal at Pin 2 is not normal, go to [10].
MCLK: IC2602 1-75 1-79
2,4 pin 1-75 1-79
E
MAIN Assy
LRCK: IC2205 • If the signal at Pin 2 is normal and Pin 4 has no 10.41 WAVEFORMS
2,4 pin 1-49 1-44 Check for Pins 2 and 4 of signal, IC2205/IC2207/IC2208 must be improperly
Loose connection LRCK: IC2205 MAIN ASSY
10 BCLK: IC2207 soldered or defective. 1-49 1-44
/defective parts BCLK: IC2207
2,4 pin 1-48 1-45 • If a signal at Pin 2 is not normal, FPGA (IC2214) 1-48 1-45
MCLK: IC2208 must be improperly soldered or defective.
MCLK: IC2208 1-47 1-46
2,4 pin 1-47 1-46
MAIN Assy
IC2806-1,7 pin • If no signal is output, IC2806/IC2805 must be 10.41 WAVEFORMS
Loose connection MAIN ASSY
11 /defective parts 1-98 1-99 Check for the Balanced Output AMP. improperly soldered or defective.
• If a signal is output, go to [12]. 1-98 1-99
IC2805-1,7 pin
1-100 1-101 1-100 1-101
• If it is H, Q2836/Q2837 must be improperly

Loose connection soldered or defective. If a CPU_MUTE_OUT
MAIN Assy Check that the MUTE_M1 (test land) signal 10.41 WAVEFORMS F
12 /defective parts signal is not output properly, go to [13].
MUTE_M1 1-102 level is Low. MAIN ASSY 1-102
• If it is L, RY2801/RY2802 must be improperly
soldered or defective.
DJM-900NXS 33
5 6 7 8
1 2 3 4
A
• If it is H, IC2011 must be improperly soldered
Loose connection MAIN Assy Check that the signal level at Pin 86 of or defective. 10.41 WAVEFORMS
13 /defective parts IC2011 86 pin 1-38 CPU_MUTE: MAIN_CPU (IC2011) is Low. • If it is L, Q2001/R2014/R2608 must be improperly MAIN ASSY 1-38
• If it is L, Q3007/Q3008 must be improperly
[No audio output from the MASTER2] soldered or defective.
14
Loose connection MAIN Assy
Check that the MUTE_OUT signal level is • If it is H, Q2601/Q2602/Q2603 must be improperly 10.41 WAVEFORMS
/defective parts MUTE_O 1-83
Low. soldered or defective. If the CPU_MUTE signal is MAIN ASSY 1-83
not supplied properly, go to [13].
• If no singal is found, the Bal -> Unbal AMP block

[No audio output from the MASTER2] must be improperly soldered or defective. 10.41 WAVEFORMS
15 Check the signal at the MASTER2_L/ • If there is a singal but no final output signal, the MAIN ASSY
/defective parts 1-108 1-109 MASTER2_R (test land). Output AMP block must be improperly soldered 1-108 1-109
B
or defective.
[3-2] No signal is output from the REC connector.

Loose connection MAIN Assy Check that the MUTE_OUT signal level is • If it is H, Q2601/Q2602/Q2603 must be improperly 10.41 WAVEFORMS
1 /defective parts MUTE_O 1-83 Low. soldered or defective. If the CPU_MUTE signal MAIN ASSY 1-83
level is not L, go to [13] of [3-1] No signal is
output from the MASTER1/MASTER2 connectors.
MAIN Assy
C AOUTL_REC
• If a signal is interrupted at the periphery of 10.41 WAVEFORMS
AOUTR_REC
Loose connection Check the audio signals input to and output IC3003, IC3003 or peripheral parts must be MAIN ASSY
2 REC_L
/defective parts from IC3003. improperly soldered or defective. 1-110 1-111
REC_R
• If no signal is input to IC3003, go to [3]. 1-112 1-113
1-110 1-111
1-112 1-113
Loose connection • If no signal is found, DSP(IC701) must be

MAIN Assy Check that a signal is supplied to the 10.41 WAVEFORMS
3 improperly soldered or defective.
/defective parts IC3001 3 pin 1-105 ADAT_REC_OUT. MAIN ASSY 1-105
• If a signal is found, go to [4].
Loose connection Check that the RESET_OUT signal level • If it is H, go to [5].

MAIN Assy 10.41 WAVEFORMS
4 /defective parts is High. • If it is L, go to [6] of [3-1] No signal is output from
IC3001 5 pin 1-107 MAIN ASSY 1-107
the MASTER1/MASTER2 connectors.
MAIN Assy
IC3001 If [3], [4], and [5] are normal but a singal is not 10.41 WAVEFORMS
D output from the DAC (Pins 10 and 11 of IC3001),
Loose connection LRCK: 4 pin MAIN ASSY
5 BCLK: 2 pin Check for the CLK signal of the IC3001. IC3001 must be improperly soldered or defective. 1-106 1-104
/defective parts • If a CLK signal is not found, go to [9] of [3-1] No
MCLK: 1 pin 1-103
signal is output from the MASTER1/MASTER2
1-106 1-104 1-103
connectors.
[3-3] No signal is output from the BOOTH connector.

• If it is L, Q3205/Q3206/Q3207/Q3208 must be
improperly soldered or defective.
Loose connection MAIN Assy Check that the MUTE_OUT signal level is • If it is H, Q2601/Q2602/Q2603 must be improperly 10.41 WAVEFORMS
E 1 Low. soldered or defective. If the CPU_MUTE signal
/defective parts MUTE_O 1-83 MAIN ASSY 1-83
level is not L, go to [13] of [3-1] No signal is
MAIN Assy
IC3203 10.41 WAVEFORMS
1-123 1-124
• If a signal is interrupted at the periphery of MAIN ASSY
Loose connection Check the audio signals input to and output IC3203/IC3204, IC3203/IC3204 or peripheral 1-123 1-124
2 1-127 1-128
/defective parts from IC3203/IC3204. parts must be improperly soldered or defective. 1-127 1-128
IC3204
• If no signal is input to IC3203/IC3204, go to [3]. 1-125 1-126
1-125 1-126 1-129 1-130
1-129 1-130
34 DJM-900NXS
1 2 3 4
5 6 7 8
A
MAIN Assy
10.41 WAVEFORMS
IC3202
• If a signal is interrupted at the periphery of MAIN ASSY
1-119 1-120
Loose connection Check the audio signals input to and output 1-119 1-120
3 1-123 1-124 IC3202/IC3205, IC3202/IC3205 or peripheral
/defective parts from IC3202/IC3205. parts must be improperly soldered or defective. 1-123 1-124
IC3205 1-121 1-122
1-121 1-122 • If no signal is input to IC3202/IC3205, go to [4].
1-125 1-126
1-125 1-126
Loose connection MAIN Assy • If no signal is found, DSP(IC701) must be 10.41 WAVEFORMS
4 Check that a signal is supplied to the
/defective parts improperly soldered or defective. MAIN ASSY 1-116
IC3201-3 pin 1-116 ADAT_BOOTH_OUT.
Loose connection MAIN Assy • If a signal level is High, go to [6] of [3-1] No 10.41 WAVEFORMS B
Check that the RESET_OUT signal level
5 /defective parts is High. signal is output from the MASTER1/MASTER2 MAIN ASSY 1-118
IC3201-5 pin 1-118
connectors.
• If a CLK signal is not found, go to [9] of [3-1] No
Loose connection IC3201 Check for the CLK signal of the IC3001. MAIN ASSY
6 LRCK: 4 pin 1-117 signal is output from the MASTER1/MASTER2 1-117
/defective parts LRCK, BCLK, MCLK connectors.
BCLK: 2 pin 1-115 1-115
MCLK: 1 pin 1-114 1-114
[3-4] No signal is output from the SEND connector.

Loose connection MAIN Assy CN1003/ Check the connection status of CN1003/
1 C
/defective parts SEND Assy CN6401 CN6401.
MAIN Assy / soldered or defective.
Loose connection SEND Assy Check that the MUTE_OUT signal level is • If it is H, Q2601/Q2602/Q2603 must be improperly 10.41 WAVEFORMS
2 /defective parts MUTE_OUT soldered or defective. If the CPU_MUTE signal
Low. MAIN ASSY 1-83
MUTE_O 1-83 level is not L, go to [13] of [3-1] No signal is
SEND Assy • If a signal is interrupted at the periphery of 10.41 WAVEFORMS

Loose connection Check the audio signals input to and output IC6402, IC6402 or peripheral parts must be SEND ASSY
3 IC6402
/defective parts from IC6402. improperly soldered or defective. 3-6 3-7
3-6 3-7 3-8 3-9
• If no signal is input to IC6402, go to [4]. 3-8 3-9
• If no signal is found, DSP(IC701) must be 10.41 WAVEFORMS

Loose connection SEND Assy Check that a signal is supplied to the
4 improperly soldered or defective. SEND ASSY 3-4
/defective parts IC6401-3 pin 3-4 ADAT_SEND_OUT.
D
• If it is H, go to [6].
Loose connection SEND Assy Check that the RESET_OUT signal level • If it is L, check for R709. If no problem is found,
5 /defective parts IC6401 5 pin is High. ETHER UCOM (IC501) must be improperly
SEND Assy
Loose connection LRCK: 4 pin 3-3 • If a CLK signal is not found, go to [9] of [3-1] No 10.41 WAVEFORMS
6 Check for the CLK signal of the IC6401. SEND ASSY
/defective parts BCLK: 2 pin 3-2 signal is output from the MASTER1/MASTER2
connectors. 3-3 3-2 3-1
MCLK: 1 pin 3-1
[3-5] No signal is output from the PHONES connector.

1 Loose connection MAIN Assy / Check for the connection between the Correct any power connections.
/defective parts HPJK Assy MAIN Assy and HPJK Assy. E
HPJK Assy • If a signal is found, the HPJK ASSY or wires are 10.41 WAVEFORMS
Loose connection Check for the signals at Pins 1 and 4 of
2 CN9201-1 pin,4 pin defective. Replace them. HPJK ASSY
/defective parts CN9201.
5-1 5-2 • If no signal is found, go to [3]. 5-1 5-2

Loose connection RY3401-3 pin,8 pin Check for the signals at Pins 3 and 8 of • If a signal is found, go to [3].
3 MAIN ASSY
/defective parts RY3401. • If no signal is found, go to [5].
1-144 1-145 1-144 1-145
• If it is H, Q3409 must be improperly soldered or

defective.
MAIN Assy
Loose connection Check that the CPU_MUTE signal level is • If the CPU_MUTE signal is not supplied properly, 10.41 WAVEFORMS
4 CPU_MUTE 1-38
/defective parts High. go to [13] of [3-1] No signal is output from the MAIN ASSY 1-38
MASTER1/MASTER2 connectors.
• If no problem is found, RY3401 must be
improperly soldered or defective. F
DJM-900NXS 35
5 6 7 8
1 2 3 4
A
MAIN Assy
IC3406 • If a signal is interrupted at the periphery of 10.41 WAVEFORMS
Loose connection HP_L1/HP_L2 Check the audio signals input to and output IC3406, IC3406 or peripheral parts must be MAIN ASSY
5 /defective parts 1-140 1-142 improperly soldered or defective. 1-140 1-142
from IC3406.
HP_R1/HP_R2 • If no signal is input to IC3406, go to [6]. 1-141 1-143
1-141 1-143
MAIN Assy
IC3405 10.41 WAVEFORMS
• If a signal is interrupted at the periphery of
Loose connection HP_L+/L-/L1 MAIN ASSY
6 Check the audio signals input to and output IC3405, IC3405 or peripheral parts must be
1-136 1-137 1-140
/defective parts 1-136 1-137 1-140 from IC3405. improperly soldered or defective.
1-139 1-138 1-141
HP_R+/R-/R1 • If no signal is input to IC3405, go to [7].
1-139 1-138 1-141
B Loose connection • If no signal is found, DSP(IC701) must be

MAIN Assy Check that a signal is supplied to the 10.41 WAVEFORMS
7 /defective parts improperly soldered or defective.
IC3404-3 pin 1-131 ADAT_HP. MAIN ASSY 1-131
• If it is H, go to [9].
Loose connection MAIN Assy Check that the DIR_ADC_DAC_RESET • If it is L, check for R709. If no problem is found, 10.41 WAVEFORMS
8 /defective parts IC3404-5 pin 1-132 signal level is High. ETHER UCOM (IC501) must be improperly MAIN ASSY 1-132
MAIN Assy
LRCK: IC3201-4 pin 10.41 WAVEFORMS
Loose connection 1-135 • If a CLK signal is not found, go to [9] of [3-1] No MAIN ASSY
9 /defective parts BCLK: IC3201-2 pin Check for the CLK signal of the IC3404. signal is output from the MASTER1/MASTER2 1-135
1-134 connectors. 1-134
MCLK: IC3201-1 pin 1-133
1-133
C
[3-6] No signal is output from the DIGITAL MASTER OUT connector.
• If a signal is output, parts between IC2405 and
1
Check for the signal at Pin 16 of DIT JA2401 must be improperly soldered or defective. 10.41 WAVEFORMS
/defective parts IC2405-16 pin 1-74 (IC2405). MAIN ASSY 1-74
• If no signal is output, go to [2].
• If Pin 31 of DIT_RESET is not High, check for

R710. If no problem is found, Ether UCOM (IC501)
must be improperly soldered or defective.
MAIN Assy
DIT_RESET: 31 pin Check for input signal at each points of IC2405. • If the signals at Pin 24 of LRCK, Pin 26 of BCLK,
1-69
and Pin 28 of DAUX are not normal, go to [3].
• A signal level at Pin 31 of the DIT_RESET
LRCK_DOUT: 24 pin 10.41 WAVEFORMS
must be High. • If the signal at Pin 30 of XTI is not normal and no
D Loose connection 1-71 MAIN ASSY
• LRCK_DOUT: 24 pin problem is found on IC2403, FPGA (IC2214) must
2 BCLK_DOUT: 26 pin 1-69 1-71
/defective parts • BCLK_DOUT: 26 pin be improperly soldered or defective.
1-72 • DAUX: 28 pin 1-72 1-70
DAUX: 28 pin • XTI: 30 pin • If signals at Pin 33 of the DIT_TXD, Pin 34 of the 1-68 1-65
XTI: 30 pin • DIT_TXD: 33 pin DIT_SCK, and Pin 35 of the DITD_CS are not 1-66 1-67
DIT_TXD: 33 pin 1-65 • DIT_SCK: 34 pin normal, MAIN UCOM (IC2011) must be improperly
DIT_SCK: 34 pin 1-66 • DITD_CS: 35 pin soldered or defective.
DITD_CS: 35 pin 1-67
• If both are normal and no signal is detected at Pin
16 of IC2405, IC2405 must be improperly soldered
or defective.
• If Pin 5 of DOUT_SRC_RESET is not High, check
for R708. If no problem is found, Ether UCOM
(IC501) must be improperly soldered or defective.
E • If the signals at Pin 7 of the LRCK and Pin 8 of the

MAIN Assy SCLK are not normal but no problem is found on
DOUT_SRC_RESET: IC2401/IC2402, FPGA (IC2214) must be
Check for input signal at each points of DOUT
5 pin 1-63 SRC (IC2404). improperly soldered or defective.
SRC_LRCK: 7 pin
• If no signal is found at Pin 9 of the ADAT_DOUT, 10.41 WAVEFORMS
1-61 • A signal level at Pin 5 of the DOUT_SRC_
DSP (IC701) must be improperly soldered or MAIN ASSY
Loose connection SRC_BCLK: 8 pin RESET must be High. 1-63 1-61
3 1-62 • SRC_LRCK: 7 pin defective.
/defective parts 1-62 1-60
ADAT_DOUT: 9 pin • SRC_BCLK: 8 pin
• If the signal at Pin 15 of the MS_SEL is not 1-64
1-60 • ADAT_DOUT: 9 pin
MS_SEL: 15 pin • MS_SEL: 15 pin normal and Q2403/Q2402/Q2401 do not function
properly, they must be improperly soldered or
1-64
defective. If the DOUT_MS_SEL signal is not
supplied properly, check for R711. If no problem is
found, Ether UCOM (IC501) must be improperly
F
• If both are normal and no signal is output from
IC2404, IC2404 must be improperly soldered or
defective.
36 DJM-900NXS
1 2 3 4
5 6 7 8
A
[4] DVS
[4-1] No analog timecode signal input to the mixer
• Check that the selector is set to USB*/*.
• Check that the DJM-900 nexus utility of the
DIGITAL, CD/LINE, connected PC is set properly.
Prior PHONO, LINE, USB • Check that the timecode (control) CD is Operating
0
Confirmation */* selector/PC connected to the CD connector and the instructions
settings timecode (control) record is connected to
the PHONO connector.
• Check for the connections of CN1802/CN3801. • Correct any poor connections.

MAIN Assy • Check that the voltage at Pin 5 (V+5VBUS) of • If the voltage at Pin 5 (V+5VBUS) of CN1802 is
Loose connection
1 V+5VBUS 1-37 CN1802 is about 5 V (4.75 to 5.25) using a PC not about 5 V (4.75 to 5.25), replace the USBI B
/defective parts
/ USBI Assy connected. Assy.
INPUT Assy [Checking the Audio Timecode select block] • If it is not H, MAIN CUP (IC2011) must be
Loose connection Check that the TC_SEL* signal level (Pin 6 10.41 WAVEFORMS
2 TC_SEL* 2-32 / improperly soldered or defective.
/defective parts of IC4408/IC4808/IC5208/IC5608) is H. INPUT ASSY 2-32
MAIN Assy • If it is H, go to [3].
INPUT Assy • If no signal is input, go to [4].

Loose connection Check that a signal is input at Pin 2 of 10.41 WAVEFORMS
3 CH*_ADAT_TIME • If a signal is input, IC4408/IC4808/IC5208/
/defective parts IC4408/IC4808/IC5208/IC5608. INPUT ASSY 2-27
2-27 IC5608 must be improperly soldered or defective.
[Checking a Timecode ADC block] If no audio signal is input to the ADC, a problem
INPUT Assy
Check that a singal is input to the input in an analog circuit at a previous stage may be
Loose connection Representative 10.41 WAVEFORMS
4 connector of the Timecode ADC. suspected.
/defective parts CH1_TIME_R INPUT ASSY 2-26
IC4403(CH1)/IC4803(CH2)/IC5203(CH3) • If no signal is input, go to [4].
2-26 /IC5603(CH4) 1 pin, 2 pin • If a signal is input, go to [5].
INPUT Assy [Checking an Timecode Buffer block] C
Before TRIM/ Check for a signal at the periphery of the If a signal is interrupted at the periphery of the
5 CH*_TIME_ Timecode Buffer. Timecode Buffer, this block must be improperly
/defective parts INPUT ASSY 2-26
L/CH*_TIME_R IC4401(CH1)/IC4801(CH2)/IC5201(CH3) soldered or defective.
2-26 /IC5601(CH4)
If a signal level at Pin 13 of the RESET_IN* is
not H, go to [9] of [2-1] No signal is input to the
[Checking a Timecode ADC block] CD/LINE, PHONO connectors.
INPUT Assy Check for signals at IC4403(CH1)/IC4803
Representative (CH2)/IC5203(CH3)/IC5603(CH4). • LRCK: 10 pin 10.41 WAVEFORMS
Loose connection CH1_RESET • MCLK: 11 pin INPUT ASSY
6 /defective parts :13 pin 2-28 A signal level at Pin 13 of the RESET_IN* • BCLK: 12 pin 2-28
LRCK: 10 pin 2-31 should be H. If no signal is input, go to [11] of [2-1] No signal 2-31
• LRCK: 10 pin is input to CD/LINE, PHONO connectors.
MCLK: 11 pin 2-30 2-30
BCLK: 12 pin 2-29 • MCLK: 11 pin 2-29
• BCLK: 12 pin • If both are normal and there is no signal at Pin D
9, IC4403(CH1)/IC4803(CH2)/IC5203(CH3)/
IC5603(CH4) must be improperly soldered or
defective.
[4-2] No signal is input to and output from the USB 1 to 4 connectors.

DIGITAL, CD/LINE,
Prior PHONO, LINE, USB • Check that the selector is set to USB*/*.
Operating
0 • Check that the DJM-900 nexus utility of the
Confirmation */* selector/PC instructions
connected PC is set properly.
settings
• Check for the connections of CN1802/CN3801. • Correct any poor connections.
Loose connection MAIN Assy /
• Check that the voltage at Pin 5 (V+5VBUS) of • If the voltage at Pin 5 (V+5VBUS) of CN1802 is E
1 /defective parts V+5VBUS 1-37 CN1802 is about 5 V (4.75 to 5.25) using a PC not about 5 V (4.75 to 5.25), replace the USBI
USBI Assy connected. Assy.
DJM-900NXS 37
5 6 7 8
1 2 3 4
A [5] Indicator (FL/LED) not lit

SUB UCOM (IC6601) controls the FL/LED.
MAIN_CPU controls only LFO FORM (WAKE UP) button LED and EFFECT ON/OFF button LED.
[5-1] The FL does not light.
Driver power to the FL is supplied within the MAIN Assy.
PNLA Assy
V6601
24 pin 4-12
1 pin 4-10
25 pin 4-9 If no loose connection is detected with the FL of
the PNLA Assy but power voltage is not detected, 4.3 POWER
Check for the voltage of the FL (V+3R3D_ check the mounting status of the DC-DC converter BLOCK DIAGRAM
1 Power failure MAIN Assy 5.3 INFORMATION
B PA/V+5D_LED_PA/V+34D_PA). IC and peripheral parts for each voltage point of
IC1407 V+3R3D ON POWER
Block 1-2 the MAIN Assy.
DIAGNOSTICS
IC1405 V+5D If an error is detected, repair the defective parts.
Block 1-5
IC1401 V+34D
Block 1-4
If the voltage is outside the normal range, a bias
Filament PNLA Assy circuit error of the FL may be suspected.
2 voltage error Voltage between pins Check that the FL filament voltage is Check the mounting status of Q6601, Q6602, and —
of the FL 1 to 32 of V6601 2.3 V ± 20%. peripheral parts. If there is no problem, Q6601 or
4-11 Q6602 may be defective. Replace them.
PNLA Assy Check for the output signal of the FL communication
line and the cable connection status in the PNLA Assy. If no signal is output, check for the mounting
V6601
• FL_SCK status of SUB UCOM (IC6601). 10.41 WAVEFORMS
22 pin 4-14
3 Signal errors • FL_TXD If there is no problem, the port may be defective. PNLA ASSY
C 21 pin 4-13
• FL_LAT Replace it. 4-14 4-13
23 pin 4-15
• FL_BK If soldering is improper, resolder it. 4-15 4-16
24 pin 4-16
If the symptom persists after the above FL may be defective.

4 Defective FL PNLA Assy —
corrections. Replace it.
[6] X-PAD
SUB UCOM (IC6601) controls the X-PAD.
[6-1] Pressing on the JOG dial not be detected
D Check for loose connection on the signal
Loose PNLA Assy If any connection on the power or signal line is
1 line from the power source and SUB UCOM
connection CDCB Assy improper, correct it.
(IC6601) to the touch sensor IC (IC3601).
PNLA Assy Check for input and output signals of the communi- 4.3 POWER
CN6601 cation line of the touch sensor IC in the PNLA Assy BLOCK DIAGRAM
10 pin 4-2 when power is supplied and the unit is turned on. If there is no signal when the unit is turned on, 5.3 INFORMATION
5 pin 4-5 • V+3R3 (power) check the mounting status of SUB UCOM ON POWER
2 Signal errors 8 pin 4-3 • RBC_SCK (IC6601). DIAGNOSTICS
7 pin 4-4 • RBC_SI If there is no problem, the port may be defective. 10.41 WAVEFORMS
3 pin 4-6 • RBC_SO Replace it. PNLA ASSY
2 pin 4-7 • RBC_CS 4-5 4-3 4-4
• RBC_INT 4-6 4-7
PNLA Assy Check that the input and output signals of the
If there are no input or output signals, the touch
Touch sensor IC (the same points touch sensor IC communication line in the PNLA —
3 sensor IC (IC3601) may be defective. As this
defective checked in No.2) Assy with the X-PAD touched in normal operation.
E part cannot be replaced, replace the Assy.
(the same points checked in No.2)
[6-2] The X-PAD LEDs not light

4.3 POWER
PNLA Assy
Loose BLOCK DIAGRAM
CN6602 Check for drive voltage of V+12_STB of the If any connection on the power line is improper,
1 connection 5.3 INFORMATION
27 pin 4-8 LED. correct it. ON POWER
/MAIN Assy DIAGNOSTICS
If the touch sensor functions normally but no
PNLA Assy 10.41 WAVEFORMS
signal is output, check the mounting status of
IC6601 Check if the LED drive signal is output from PNLA ASSY
2 Signal errors the periphery of Q6651 to Q6654. If there is no
79 pin 4-21 SUB uCOM (IC6601 Pins 79 and 80). 4-21
problem, SUB UCOM (IC6601) port may be
80 pin 4-20 4-20
defective. Replace it.
F
PNLA Assy Check for the voltage (2.7–4.2 V) at both If no voltage is detected, the LED may be
3 Defective LED CN6601 electrodes of the LED. defective. Replace it.
11⇔12 pin 4-1
38 DJM-900NXS
1 2 3 4
5 6 7 8
A
[7] LAN
[7-1] No LAN communication
• If all show normal status, go to [2].
• If LAN is NG, go to [3].
Perform the Mode 12:Device Test in Test If MACAd, IPAdd, and Subn are abnormal, data
1 — — mode, and check if normal status is displayed stored in the Flash (IC502) for the ETHER UCOM
may be damaged. Replace the entire MAIN Assy. 6.1 TEST MODE
for LAN, MACAd, IPAdd, and Subn.
Note: The Flash (IC502) DYW1798 for the
ETHER UCOM is not a service part for MAC
address administration. Replace it with the MAIN
Assy.
B
Error between the
2 LAN connectors Check that the status of TRANS (T1601),
MAIN Assy 1-18 Repair the defective parts. —
(JA1601) and ETHER Filters (F1601, F1602), etc.
-PHY (IC1603)
4.3 POWER
Error between ETHER-PHY (IC1603) and BLOCK DIAGRAM
MAIN Assy
ETHER Ucom (IC501) may be suspected. 5.3 INFORMATION
[POWER]
[POWER] ON POWER
L1601 1-20
• Power V+3R3D DIAGNOSTICS
• Part defective [CLK] Repair the defective parts.
3 [CLK] [CLK]
• Signal error R1629 1-21
• 25M CLK * (25M_CLK_PHY) 10.41 WAVEFORMS
[Communication line]
[Communication line] MAIN ASSY 1-21
1-19
[Communication line]
Representative R1631 • Check for the MII BUS line.
10.41 WAVEFORMS
MAIN ASSY 1-19 C
If the symptom persists after the above ETHER-PHY (IC1603) may be defective.
4 Part defective MAIN Assy —
corrections. Replace it.
DJM-900NXS 39
5 6 7 8
1 2 3 4
5.3 INFORMATION ON POWER DIAGNOSTICS
A
G MAIN ASSY
Observing Normal Voltage Possible defective point when Standby State
Name Remarks Level
Point a voltage error is generated (Power SW ON)
1 VMUTE 14.3-19.9 MUTE CIRCUIT(Q2603etc) OFF
V+18VMUTE
2 14.3-19.9 MUTE CIRCUIT(Q2603etc) OFF
(V+18VMUTE_*)
V+15A OUTPUT CIRCUIT(MAIN ASSY),
3 14.2-15.8 OFF
(V+15A_*) INPUT CIRCUIT(INPUT ASSY)
V-15A OUTPUT CIRCUIT(MAIN ASSY),
4 -15.8 - -14.3 OFF
(V-15A_*) INPUT CIRCUIT(INPUT ASSY)
V+5A OUTPUT CIRCUIT(MAIN ASSY),
5 4.7-5.3 OFF
B (V+5A_*) INPUT CIRCUIT(INPUT ASSY)
6 +12V Switched Before the ICP 11.3-12.7 ALL DIGITAL CIRCUIT OFF
V+12D
7 After the ICP 11.3-12.7 ALL DIGITAL CIRCUIT OFF
(V+12D_*)
V+12STBY MAIN_CPU(IC2011),
8 11.3-12.7 RESET IC(IC2010) ON
(V+12E)
9 V+9HP 8.55-9.45 HP CIRCUIT OFF
10 V-9HP -9.4 - -8.6 HP CIRCUIT OFF
V+3R3E MAIN_CPU(IC2011),
11 (V+3R3E_*) 3.15-3.45 ON
RESET IC(IC2010)
V+5D
12 (V+5D_*) 4.8-5.3 FL.,LED,MIDI,DIGITAL OUT OFF
C V+3R3D
13 (V+3R3D_*) 3.15-3.45 ALL DIGITAL CIRCUIT OFF
V+1R2D FPGA(IC2214),DSP(IC701),Ether
14 (V+1R2D_*) 1.1-1.27 OFF
UCOM(IC501),USB UCOM(IC1801)
V+2R5D
15 (V+2R5D_*) 2.37-2.62 SRC,USB UCOM(IC1801) OFF
16 V+34D_1 Before the TrSW 31-36 FL. OFF

17 V+34D After the TrSW 31-36 FL. OFF
18 V+5VBUS Power of the connected PC 4.75-5.25 USB communication failure ON
A INPUT ASSY
19 V+15A After the ICP 14.2-15.8 INPUT CIRCUIT OFF
D
20 V-15A After the ICP -15.8 - -14.3 INPUT CIRCUIT OFF
21 V+5A 4.7-5.3 INPUT CIRCUIT OFF
INPUT CIRCUIT RELAY(RY4201,
22 V+12D After the ICP 11.3-12.7 OFF
4601,5001,5401)
23 V+5D 4.8-5.3 MIDI OUT OFF
24 V+3R3D 3.15-3.45 DIGITAL CIRCUIT OFF
J SEND ASSY
25 V+15A_SE After the ICP 14.2-15.8 SEND OUTPUT CIRCUIT OFF
26 V-15A_SE After the ICP -15.8 - -14.3 SEND OUTPUT CIRCUIT OFF
27 V+5A_SE 4.7-5.3 SEND_DAC(IC6401) OFF
E
K PNLA ASSY
28 V+5D_LED 4.8-5.3 FL.,LED, OFF
29 V+12STB 11.3-12.7 LED(X-PAD,LFO FORM) ON
30 V+3R3D 3.15-3.45 FL.,SUB UCOM(IC6601) OFF
31 V+34D 31-36 FL. OFF
32 V+3R3D_REFA 3.15-3.45 CH1-4 FADER,CROSS FADER OFF
Q PNLB ASSY
33 V+3R3D_REFA 3.15-3.45 CROSS FADER OFF
F L CDCB ASSY
34 V+3R3 3.15-3.45 CDC SENSOR(IC3601) OFF
ex)V+5A_* • • • • • V+5A_BO,V+5A_HP,V+5A_M1 etc • • •
40 DJM-900NXS
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5 6 7 8
5.4 VOLTAGE MONITORING CIRCUIT
A
Voltage-Monitoring Circuit
This unit monitors the voltages of the main power-supply ICs, using the VDET signal.
The VDET signal level is middle (+1.08 V to +1.32 V) during normal operations. When the level becomes outside the middle
level, as shown in the table below, an error is informed to the MAIN CPU (IC2011).
Product behavior when an error is generated

Upon reception of the VDET signal that informs of power failure, the MAIN CPU sets the P-CON signal to Low and stops the
switching-system output from SW power.
MAIN ASSY
VMUTE V+34D
V+12D V+12D B
V+15A V+5D Monitoring Voltage
V-15A V+3R3D
monitoring
V+5A V+2R5D
V+1R2D circuit
The MAIN_CPU controls V+15A
power output. V-15A
POWER SUPPLY ASSY
V+5A
VDET
H: Abnormal
Mid: Normal
L: Abnormal
PNLA ASSY
H: SW power is output.
P-CON L: SW power output is stopped.
STBY_LED
MAIN_CPU LFO FORM LED C
D6624 (RED)
(IC2011)
V+12E V+3R3E Flashing when
IC1404 an error occurs
Always output during power-on
The MAIN CPU also informs of power failure with flashing of the LFO FORM button, by sending the STBY_LED signal:
Flashing intervals: 250 ms (lit for 125 ms/unlit for 125 ms)
As the switching-system output is stopped, the indications other than the LFO FORM button are unlit and all the switches
and VRs are disabled. D
Schematic diagram of the voltage monitoring section
G MAIN ASSY
Analog voltage abnormality detect circuit
V+15A_1 V+5A V+12D

LTA124EUB
STBY
HN1A01FU(YGR)
Q1206
R1210
R1207
R1202
10k
(F)
11k
(F)
HN1A01FU(YGR) NM
Q 1 2 0 1 (1/2) VADET
A side 1 6 4 3:2C
LTC124EUB
R1209 R1222
To Power Block
Q1201
R1203
5
Q1205
V+5A 2 A side VADET

(2/2)
1k 0
20k
R1221
3
(F)
R1208
10k
22k
(F)
F
R1204
Low value Hi value

10k
V+5A 4.28V 5.61V

V-15A_1
V-15A_1 9.94V
GNDD GNDD V+9HP 8.23V
D1201 V-9HP -5.96V -11.82V
1SS301
V+15A 13.38V 16.74V
V-15A -11.83V -18.57V
DJM-900NXS 41
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1 2 3 4
A
Table 1: List of voltage values for power monitoring and statuses of the voltage comparator transistors
Statuses of voltage comparator transistors
VDET
State Power Voltage Q1410 Q1410 Q1402 Q1402 Q1201 Q1201 Q1203 Q1203 Voltage
Q1404 Q1405 Q1406 Q1205 Q1206 Q1407
(1/2) (2/2) (1/2) (2/2) (1/2) (2/2) (1/2) (2/2)
In normal
operation OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Mid
V+34D < 25.58V ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF Hi
V+12D < 10.4V OFF ON OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF Hi
> 13.24V OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF OFF OFF Hi
V+5D < 4.33V OFF OFF ON OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF Hi
> 5.82V OFF ON OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF HI
B
V+3R3D < 2.85V OFF OFF OFF ON OFF ON ON OFF OFF OFF OFF OFF OFF OFF HI
> 3.81V OFF OFF ON OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF HI
V+2R5D < 2.22V OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF OFF OFF Hi
> 2.81V OFF OFF OFF ON OFF ON ON OFF OFF OFF OFF OFF OFF OFF Hi
V+1R2D < 1.08V OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF < 1.08V
When an > 1.32V OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF > 1.32V
error is
generated V+15A < 13.38V OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON Low
> 16.74V OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF ON ON ON Low
V-15A < -18.57V OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON Low
> -11.83V OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF ON ON ON Low
C V+5A < 4.28V OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON ON ON Low
> 5.61V OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON Low
42 DJM-900NXS
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5.5 ABOUT THE PROTECTOR
This unit monitors the voltages of the main power-supply ICs, using the voltage-monitoring circuit. As the ICPs (IC protectors) A
are also used, some circuits cannot be monitored by the voltage-monitoring circuit when any wire for an ICP is broken.
(Circuits with thick frames in the figure below)
When any of the circuit blocks indicated in thick frames (located after the ICPs) in the figure below is in failure, also check for
a broken wire for the ICP.
Locations of the ICPs

MAIN ASSY
Voltage monitoring
V+12D OUTPUT RELAY

ICP INPUT RELAY SEND ASSY
non CIRCUIT
5V DC/DC converter B
P1204: DEK1103 3.3V DC/DC converter
1.2V DC/DC converter SEND CIRCUIT *5
34V DC/DC converter
POWER SUPPLY ASSY
V+15A
HP CIRCUIT *1
ICP OUTPUT CIRCUIT *3 INPUT ASSY

P1210: DEK1095
ICP
P1207: DEK1121
V-15A
HP CIRCUIT *2
C
INPUT CIRCUIT *6
ICP OUTPUT CIRCUIT *4

P1209: DEK1096
ICP
P1208: DEK1121
Names of the Power-Supply ICs

After the ICP (P1210) After the ICP (P1207)
V+15A Before the ICP *1
OUTPUT BLOCK *3&5 INPUT BLOCK *6
MAIN MAIN SEND MAIN INPUT
D
V+15A_1 V+15A_O V+15A_SE V+15A_IN V+15A_IN
V+15A_HP V+15A_SE
V+15A_HP_1 V+15A_SE_1
V+15A_BO
V+15A_M2
V+5A_REC
V+15A_M1
V+15A_M1_ICP
After the ICP (P1209) After the ICP (P1208)
V-15A Before the ICP *2
OUTPUT BLOCK *4&5 INPUT BLOCK *6
MAIN MAIN SEND MAIN INPUT
E
V-15A_1 V-15A_O V-15A_SE V-15A_IN V-15A_IN
V-15A_HP V-15A_SE
V-15A_HP_1 V-15A_SE_1
V-15A_BO
V-15A_M2
V-5A_REC
V-15A_M1
V-15A_M1_ICP
Diagnostic procedures when the wire for an ICP is broken

1. Unplug the AC power cord.
F
2. Check for any error, such as short-circuiting or defective parts, in the circuits subsequent to the ICP.
3. Repair the detective part.
4. Replace the ICP.
DJM-900NXS 43
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5.6 DIAGNOSIS OF V+34D
A
The driver power output for the FL (V+34D) is controlled with a transistor switch.
Diagnostic procedures when only V+34D is not output

1 Check V+34D_1 at the prior stage of the transistor (Q1409).
2 If no signal is detected at V+34D_1, the mounting status of the peripheral parts of the 34V DC/DC converter (IC1401)
may be improper or IC1401 itself may be defective.
3 If a signal is detected at V+34D_1, check the input signals to IC1403.
If PowerReset is L, check the connection up to SW power (DWR1492).
If FL_Vcont is L, the mounting status of the MAIN_CPU (IC2011) may be improper or IC2011 itself may be defective.
4 If both PowerReset and FL_Vcont are H:
If the output signal from IC1403 is L, the mounting status of IC1403 may be improper or IC1403 itself may be defective.
B 5 If the output signal from IC1403 is H, the mounting status of the peripheral parts of Q1408 or Q1409 may be improper or
Q1408/Q1409 may be defective.
2
5
G MAIN ASSY
1 4
44 DJM-900NXS
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5.7 ERROR INDICATIONS
A
Indications of Errors during Startup
If an error is detected during a boot sequence, it will be indicated by flashing of the LFO FORM (WAKE UP) LED.
Error (in the Detecting
order of detection) Microcomputer Indication Cause Diagnostic procedure
MAIN_CPU MAIN_CPU The unit will be forcefully started Error of the ROM inside the MAIN_ Troubleshooting: “LFO FORM (WAKE UP)
(IC2011) (IC2011) in Update mode. CPU (Depending on the degree of LED not flashing” in [1-1] No power,
LFO FORM (WAKE UP) LED: damage to the ROM, the unit may [1] Failure in Startup
Not flashing be in a state of power-off.)
DSP MAIN_CPU Repeated once flashing of the Error during the 1st command Troubleshooting: “LFO FORM (WAKE UP)
(IC701) (IC2011) LFO FORM (WAKE UP) LED communication between the MAIN LED flashing once” in [1-2] No power,
(lit and unlit for 250 ms each 1 _CPU and DSP (via FPGA) [1] Failure in Startup
time then unlit for 1 s)
B
ETHER UCOM MAIN_CPU Repeated 3-time flashing of the Error during the 1st command Troubleshooting: “LFO FORM (WAKE UP)
(IC501) (IC2011) LFO FORM (WAKE UP) LED communication between the MAIN LED flashing 3 times” in [1-3] No power,
(lit and unlit for 250 ms each 3 _CPU and ETHER UCOM [1] Failure in Startup
times then unlit for 1 s) (via FPGA)
SUB UCOM MAIN_CPU Repeated 5-time flashing of the Error during the 1st command Troubleshooting: “LFO FORM (WAKE UP)
(IC6601) (IC2011) LFO FORM (WAKE UP) LED communication between the MAIN LED flashing 5 times” in [1-4] No power,
(lit and unlit for 250 ms each 5 _CPU and SUB_UCOM (via FPGA) [1] Failure in Startup
times then unlit for 1 s)
USB UCOM MAIN_CPU Repeated 6-time flashing of the Serial communication error Troubleshooting: “LFO FORM (WAKE UP)
(IC1801) (IC2011) LFO FORM (WAKE UP) LED between the MAIN_CPU and LED flashing 6 times” in [1-5] No power,
(lit and unlit for 250 ms each 6 USB UCOM [1] Failure in Startup
DOUT DIT MAIN_CPU Repeated 7-time flashing of the Serial communication error Troubleshooting: “LFO FORM (WAKE UP)
(IC2405) (IC2011) LFO FORM (WAKE UP) LED between the MAIN_CPU and LED flashing 7 times” in [1-6] No power, C
(lit and unlit for 250 ms each 7 DOUT DIT [1] Failure in Startup
Indications of Errors during Power Failure

The LFO FORM LED infinite flashes (Intervals: 250 ms [Lit 125 ms/Unlit 125 ms]).
D
Indications of Errors during Updating
Effect Indication Parameter Indication Microcomputer in failure Correspondence
ERROR E001 MAIN CPU UPDATE error Please update it again.
ERROR E002 SUB UCOM UPDATE error Please update it again.
ERROR E003 DSP data UPDATE error Please update it again.
ERROR E004 DSP program UPDATE error Please update it again.
ERROR E005 USB UCOM UPDATE error Please update it again.
ERROR E006 ETHER UCOM UPDATE error Please update it again.
ERROR E007 FPGA UPDATE error Please update it again.
Download the update file again then
ERROR E008 Update file error
perform updating.
E
ERROR EE00 LINK cutting error Please update it again.
ERROR EEXX LINK error XX : Error generation task ID Please update it again.
DJM-900NXS 45
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5.8 CONNECTION CHECK WITH EACH INTERFACE
A
USB
[1. USB B connector]
Whether communication between the PC connected via the USB B connector and this unit is properly performed or not can
be confirmed on the PC.
Note: The driver software must be installed beforehand.
For checking, use the USB connection indicator of the unit.

Lit: The indicator lights when the driver is recognized after connection with the PC is established.
Flashing: If the driver cannot be recognized after PC connection, the LED flashes (Intervals: 500 ms [lit: 250 ms/unlit: 250 ms
Unlit: When communication between the PC and the unit is interrupted, the LED goes dark.
B Use Device Manager for checking.

If the PC and this unit are properly connected, the components of this unit are added in Device Manager (under Hardware)
as devices.
If all components are properly displayed, the PC and this unit are properly communicating via the USB connector.
In a case of Windows XP:

Start, Control Panel, System, Hardware, then Device Manager
Devices to be added:
• Universal Serial Bus controllers
USB Composite Device
• Under “Sound, video and game controllers”
PIONEER DJM-900nexus
C USB Audio Device
A communication check may be easily performed if connection

is made with Device Manager displayed on the PC screen.
LAN
[2. LINK]
You can check from this unit if the mixer can properly communicate via LAN.
*Use a Category 5 cable or a cable with higher specifications for connection.
Either a straight or cross LAN cable can be used when the unit is directly connected with the PC, but when the unit is
connected with the PC via a hub, be sure to use a straight cable.
Check the LAN conditions, using Test mode of this unit:

1 Start the unit in Test mode.
E 2 Open "DEVICE" in “MODE 12: DEVICE TEST.”
3 The IP Address and Subnet Mask are indicated.
4 Check if the LAN is properly connected.
When the LAN is properly connected:

IP Address: xxx . xxx . xxx . xxx
Subnet Mask: yyy . yyy . yyy . yyy
The above x’s and y’s mean any numeric digits 0–9.
Four blocks of numerical string delimited by dots
When the LAN is not properly connected:

IP Address: EE . EE . EE . EE
F Subnet Mask: EE . EE . EE . EE
All four blocks are filled with “EE.”
46 DJM-900NXS
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6. SERVICE MODE
6.1 TEST MODE
A
1. Description of Test Modes
The Following 12 test modes are provided for this unit:
1 Mode 1 : Confirmation of software version. "Version" 7 Mode 7 : Fader test. "FDRTEST"
2 Mode 2 : All LEDs & FL display "OFF" mode. "ALL CLR" 8 Mode 8 : Channel Level Indicator LED test. "LEDTEST"
3 Mode 3 : ALL LEDs & FL display "ON" mode. "ALL SET" 9 Mode 9 : X-PAD value test. "RBNTEST"
4 Mode 4 : KEY operating test. "KEY TEST" a Mode 10 : AD values of the rotary VRs test. "VOL AD"
5 Mode 5 : SELECT SW Operating test. "SW TEST" b Mode 11 : AD values of the fader test. "FDR AD"
6 Mode 6 : Rotary VRs value test. "VOLTEST" c Mode 12 : Device test. "DEVICE"
B
2. Test Mode
Test Mode : ON Cyclic operation
Mode 1 Mode 2 Mode 3

TAP
SOUND button Mode 12 Mode 4
(Rear panel)
COLOR
LINK CH-1 FX POWER ON Test Mode
TAP Mode 11 Mode 5
CUE CUE SPACE (Mode 1)
Mode 10 Mode 6
C
Mode 9 Mode 8 Mode 7
POWER SW
Test Mode : CANCEL
(Rear panel)
POWER OFF
DJM-900NXS 47
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1 2 3 4
A 3. Test mode Contents

1 Mode 1 : Confirmation of software version
• Mode for confirmation of the versions of the system, MAIN CPU, SUB UCOM, DSP (program), DSP (data),
ETHER UCOM, USB UCOM, FPGA and BOOT.
When this mode is entered, “Version” is displayed at the top of the FL display and the TAP key lights.
• Mode 1 consists of 9 pages for indicating the versions of the system, MAIN CPU, SUB UCOM, DSP (program), DSP (data),
ETHER UCOM, USB UCOM, FPGA and BOOT.
The pages can be changed by pressing the BEAT c, d button.
B When Mode 1 is entered, the System Version Display mode is automatically entered.
BEAT BEAT BEAT

d button d button d button
Software name
C BEAT BEAT BEAT

c button c button c button
version
BEAT BEAT
c button d button
BEAT BEAT BEAT

D d button d button d button
BEAT BEAT BEAT

BEAT BEAT
c button d button Software Name FL Display
E System SYS
MAIN CPU M
SUB UCOM SUB
DSP (program) D_P
DSP (data) D_D
ETHER UCOM ETH
USB UCOM USB
FPGA F
BOOT BT
48 DJM-900NXS
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A
2 Mode 2 : All LEDs & FL display “OFF” mode
• Mode for extinguishing all the LEDs and FL segments.
Only after this mode is entered, “ALL CLR” is displayed for 1 second at the top of the FL display.
Note: The seven CUE button LEDs light dimly.
3 Mode 3 : All LEDs & FL display “ON” mode

• Mode for lighting all the LEDs and FL segments.
Only after this mode is entered, “ALL SET” is displayed for 1 second at the top of the FL display.
B
4 Mode 4 : Key operating test
• Mode for indicating a pressed key with lighting of an LED and indication on the FL display.
When this mode is entered, “KEYTEST” is displayed at the top of the FL display and the TAP key lights.
• The name of a pressed key is indicated on the FL display.
Operating Keys Lighting LED FL Display Remark

FADER START 1 button FADER START 1 button LED FSCH1
C
CH1 CUE button CH1 CUE button LED CUE_1
LINK CUE button LINK CUE button LED CUE_L
MASTER CUE button MASTER CUE button LED CUE_M
EFFECT CUE button EFFECT CUE button LED CUE_E
D
SOUND COLOR FX SPACE button SOUND COLOR FX SPACE button LED CFX_1
SOUND COLOR FX DUB ECHO button SOUND COLOR FX DUB ECHO button LED CFX_2
SOUND COLOR FX GATE/COMP button SOUND COLOR FX GATE/COMP button LED CFX_3
SOUND COLOR FX NOISE button SOUND COLOR FX NOISE button LED CFX_4
SOUND COLOR FX CRUSH button SOUND COLOR FX CRUSH button LED CFX_5
SOUND COLOR FX FILTER button SOUND COLOR FX FILTER button LED CFX_6
LFO FORM (WAKE UP) button LFO FORM (WAKE UP) button LED LFO
ON/OFF (UTILITY) button ON/OFF (UTILITY) button LED MD_ON
START/STOP button None MD_ST E
BEAT c button None BEAT<

BEAT d button None BEAT>
AUTO/TAP button None AUTO
QUANTIZE button QUANTIZE button LED GRID
ON/OFF button ON/OFF button LED EFXon
DJM-900NXS 49
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A
5 Mode 5 : SELECT SW Operating test. "SW TEST"
• When this mode is entered, “SW TEST” is displayed at the top of the FL display and the TAP key lights.
Operating Switches Lighting LED Remark

: DIGITAL 4dB
DIGITAL, CD/ LINE, PHONO, LINE, : CD/LINE 7dB
USB 1/2 selector switch CH1 Channel Level Indicator LED
CH1 : PHONO 10dB
: USB 1/2 OVER
B : DIGITAL 4dB
CH2 : LINE 10dB
: USB 3/4 OVER
: DIGITAL 4dB
CH3 : LINE 10dB
: USB 5/6 OVER
: DIGITAL 4dB
C CH4 : PHONO 10dB
: USB 7/8 OVER
CROSS FADER ASSIGN : Assign A -24dB
(A, THRU, B) selector switch : THRU CH1 Channel Level Indicator LED -15dB
CH1 : Assign B -10dB
: Assign A -24dB
CROSS FADER ASSIGN
D
: OFF -1dB
OFF, ON, TALK OVER selector switch : ON CH1 Channel Level Indicator LED 0dB
: TALK OVER 1dB
MONO SPLIT, STEREO : MONO SPLIT -5dB
CH1 Channel Level Indicator LED
selector switch : STEREO -3dB
: MONO 0dB
MONO, STEREO selector switch CH2 Channel Level Indicator LED
: STEREO 1dB
E
EQ CURVE (ISOLATOR, EQ) : ISOLATOR -3dB
CH2 Channel Level Indicator LED
selector switch : EQ -2dB
: Left -1dB
CH FADER
: MID CH3 Channel Level Indicator LED 0dB
selector switch
: Right 1dB
: Left -1dB
CROSS FADER
: MID CH4 Channel Level Indicator LED 0dB
selector switch
: Right 1dB
50 DJM-900NXS
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Operating Switches Lighting LED Remark

:1 -24dB
:2 -15dB
:3 -10dB
1, 2, 3, 4, MIC, CF.A, CF.B, :4 Master Level Indicator LED -7dB
MASTER selector switch : MIC L CH -5dB
: CF.A -3dB
: CF.B -2dB
B
: MASTER -1dB
: DELAY -24dB
: ECHO -15dB
: SPIRAL -10dB
: REVERB -7dB
: TRANS -5dB
DELAY, ECHO, SPIRAL, REVERB,
TRANS, FILTER, FLANGER, : FILTER Master Level Indicator LED -3dB
PHASER, ROBOT, MELODIC, : FLANGER R CH -2dB
SLIP ROLL, ROLL, REV ROLL,
: PHASER -1dB
SND/RTN (MIDI LFO)
selector switch : ROBOT 0dB
: MELODIC 1dB C
: SLIP ROLL 2dB

: ROLL 4dB
: REV ROLL 7dB
: SND/RTN (MIDI LFO) 10dB
This mode is also used to check operation of the TIME control.

The value displayed on the FL display increases/decreases as you turn the TIME control:
Minimum value Initial value Maximum value D

Operation range
Initial value: 0
Maximum value: 100
Minimum value: -100
Turn Turn
counterclockwise. clockwise.
DJM-900NXS 51
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A
Correspondence diagram of Mode 5 : SELECT SW Operating test. "SW TEST"
POWER
MIC USB MASTER MIDI

START
ON/ OFF / STOP LFO FORM
MIC1 CD/ LINE PHONO CD/ LINE LINE CD/ LINE LINE CD/ LINE PHONO LEVEL
DIGITAL DIGITAL DIGITAL DIGITAL
B USB
1/ 2
USB
3/4
USB
5/ 6
USB
7/ 8
UTILITY WAKE UP
BEAT EFFECTS
0
TRIM TRIM TRIM TRIM
OVER OVER OVER OVER OVER CH SELECT
1 2 3 4
10 10 10 10 10
MIC 1 MIC A B MST
7 9 7 9 7 9 7 9 7 PARAMETER
0 LEVEL HI HI HI HI AUTO GRID

4 4 4 4 4
TAP BPM
2 2 2 2 2 %
MIC 2 ms
1
1 1 1 1 1
0
HI
0
-1
-26 /
MID
6
0
-1
-26 /
MID
36
0
-1
-26 /
MID
4
6
0
-1
-26 /
MID
6
0
-1
X- PAD
2
-2 -2 -2 -2 -2
12 12 EQ
C -3 EQ/ -3 EQ/ -3 EQ/ -3 EQ/ -3
ISO ISO ISO ISO
LOW -5 -5 -5 -5 -5
12 12 - 7 -26 / 6 - 7 -26 / 6 - 7 -26 / 6 - 7 -26 / 6 -7

TALK -10
LOW -10
LOW -10
LOW -10
LOW -10
OFF ON OVER
-15 -15 -15 -15 -15 BEAT
-24 -24 -24 -24 -24
dB dB dB dB L dB R AUTO QUAN-
-26 / 6 -26 / 6 -26 / 6 -26 / 6
/ TAP TAP TIZE
DUB GATE/ COLOR COLOR COLOR COLOR BALANCE

SPACE ECHO COMP
SOUND COLOR FX CUE
NOISE CRUSH FILTER LOW HI LOW HI LOW HI LOW HI L R
FLANGER PHASER
FILTER ROBOT
LINK CUE CUE CUE CUE CUE
D TRANS MELODIC
REVERB SLIP ROLL
CUE
SPIRAL ROLL
MONO STEREO ECHO REV ROLL
FADER START DELAY MIDI LFO
SND/ RTN
1
1 2 3 4 4 MIC
3 CF.A
10 10 10
2 CF.B
HEADPHONES 9 9 9 BOOTH MONITOR
1 MASTER
8 8 8
MONO SPLIT STEREO
7 7 7
6 6 6
5 5 5 TIME
4 4 4
MIXING 0
3 3 3
2 2 2
1 1 1
EQ CURVE
ISOLATOR EQ
0 0 0
E
CUE
LEVEL
MASTER
2 LEVEL / DEPTH
A THRU B A THRU B A THRU B A THRU B

CH FADER
0
3 MIN MAX
CROSS FADER ON / OFF

CROSS FADER ASSIGN
PHONES
4
A B
52 DJM-900NXS
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A
6 Mode 6 : Rotary VRs value test. "VOLTEST"
• Mode for confirmation of the AD conversion value for each rotary VR on the operation panel with lighting of a channel level
indicator LED or the segments on the FL display
When this mode is entered, “VOLTEST” is displayed at the top of the FL display and the TAP key lights.
• To indicate the AD conversion values for several rotary VRs with a single level meter, the rotary VRs are divided into 4
groups.
The group pages can be changed by pressing the BEAT c, d button.
Group 1 Group 2 Group 3 Group 4
B
BEAT BEAT BEAT
Group No. BEAT BEAT BEAT

[Use of this mode during repair]

• For failure judgment of the rotary VRs C
• For operation check of a rotary VR after replacement
• Group 1
Rotary VRs whose AD conversion values can be confirmed:
• CH1 TRIM control, CH2 TRIM control, CH3 TRIM control, CH4 TRIM control, EQ HI control,
EQ LOW control, CH1 COLOR control
VR to be tested Lit LED or FL Remarks
"-∞": Lights off
CH1 TRIM control CH1 Channel Level Indicator LED
"+9": Full Illuminate
D
"-∞": Lights off
"-∞": Lights off
"-∞": Lights off
"-12": Lights off
EQ HI control Master Level Indicator L LED
"-12": Lights off
EQ LOW control Master Level Indicator R LED
"LOW": Lights off E
CH1 COLOR control At the bottom of the FL display
"HIGH": Full Illuminate
DJM-900NXS 53
5 6 7 8
1 2 3 4
A
• Group 2
• CH1 EQ/ISO HI control, CH2 EQ/ISO HI control, CH3 EQ/ISO HI control, CH4 EQ/ISO HI control,
MIXING control, LEVEL control, CH2 COLOR control
"-∞/-26": Lights off
CH1 EQ/ISO HI control CH1 Channel Level Indicator LED
B "-∞/-26": Lights off
"CUE": Lights off
MIXING control Master Level Indicator L LED
"MASTER": Full Illuminate
"-∞": Lights off
LEVEL control Master Level Indicator R LED
"0": Full Illuminate
"LOW": Lights off
• Group 3
• CH1 EQ/ISO MID control, CH2 EQ/ISO MID control, CH3 EQ/ISO MID control, CH4 EQ/ISO MID control,
MASTER LEVEL control, BALANCE control, CH3 COLOR control
CH1 EQ/ISO MID control CH1 Channel Level Indicator LED
D
"-∞": Lights off
MASTER LEVEL control Master Level Indicator L LED
"L": Lights off
BALANCE control Master Level Indicator R LED
"R": Full Illuminate
"LOW": Lights off
E CH3 COLOR control At the bottom of the FL display
54 DJM-900NXS
1 2 3 4
5 6 7 8
A
• Group 4
• CH1 EQ/ISO LOW control, CH2 EQ/ISO LOW control, CH3 EQ/ISO LOW control, CH4 EQ/ISO LOW control,
BOOTH MONITOR control, LEVEL/DEPTH control, CH4 COLOR control
CH1 EQ/ISO LOW control CH1 Channel Level Indicator LED
"-∞/-26": Lights off B
"-∞": Lights off
BOOTH MONITOR control Master Levele Indicator L LED
"MIN": Lights off
LEVEL/DEPTH control Master Levele Indicator R LED
"MAX": Full Illuminate
"LOW": Lights off
POWER
MIC USB MASTER MIDI

: Group 1
START
ON/ OFF / STOP LFO FORM
MIC1 CD/ LINE PHONO CD/ LINE LINE CD/ LINE LINE CD/ LINE PHONO LEVEL
DIGITAL USB
1/ 2
DIGITAL USB
3/4
DIGITAL USB
5/ 6
DIGITAL USB
7/ 8
UTILITY WAKE UP
: Group 2
BEAT EFFECTS
TRIM TRIM TRIM TRIM

0
: Group 3
OVER OVER OVER OVER OVER CH SELECT
1 2 3 4
MIC 1
10
7 9
10
7 9
10
7 9
10
7 9
10
7
MIC A
PARAMETER
B MST : Group 4
0 LEVEL HI HI HI HI AUTO GRID
4 4 4 4 4
TAP BPM
2 2 2 2 2 %
MIC 2 ms
1 1 1 1 1
0
0
-26 / 6
0
-26 / 6
0
-26 / 6
0
-26 / 6
0
D
-1 -1 -1 -1 -1
HI MID MID MID MID
-2 -2 -2 -2 -2 X- PAD
12 12 EQ
-3 EQ/ -3 EQ/ -3 EQ/ -3 EQ/ -3
ISO ISO ISO ISO
LOW -5 -5 -5 -5 -5
12 12 - 7 -26 / 6 - 7 -26 / 6 - 7 -26 / 6 - 7 -26 / 6 -7

TALK -10
LOW -10
LOW -10
LOW -10
LOW -10
OFF ON OVER
-15 -15 -15 -15 -15 BEAT
-24 -24 -24 -24 -24
dB dB dB dB L dB R AUTO QUAN-
-26 / 6 -26 / 6 -26 / 6 -26 / 6
/ TAP TAP TIZE
DUB GATE/ COLOR COLOR COLOR COLOR BALANCE

SPACE ECHO COMP
SOUND COLOR FX CUE
NOISE CRUSH FILTER LOW HI LOW HI LOW HI LOW HI L R
FLANGER PHASER
FILTER ROBOT
LINK CUE CUE CUE CUE CUE TRANS MELODIC
REVERB SLIP ROLL
CUE
SPIRAL ROLL
MONO STEREO ECHO REV ROLL
FADER START DELAY MIDI LFO
SND/ RTN
1 2 3 4
3
4 MIC
CF.A E
10 10 10
2 CF.B
HEADPHONES 9 9 9 BOOTH MONITOR
1 MASTER
8 8 8
MONO SPLIT STEREO
7 7 7
6 6 6
5 5 5 TIME
4 4 4
MIXING 0
3 3 3
2 2 2
1 1 1
EQ CURVE
ISOLATOR EQ
0 0 0
CUE MASTER
LEVEL LEVEL / DEPTH
A THRU B A THRU B A THRU B A THRU B

CH FADER
0 MIN MAX
CROSS FADER ON / OFF

CROSS FADER ASSIGN
PHONES
A B
DJM-900NXS 55
5 6 7 8
1 2 3 4
7 Mode 7 : Fader test. "FDRTEST"

A
• Mode for confirmation of the values of CH1–4 Channel FADER and CROSS FADER with the channel level indicator LEDs.
When this mode is entered, “FDRTEST” is displayed at the top of the FL display and the TAP key lights.

• For failure judgment of the faders
• For operation check of a fader after replacement
Fader to be tested Lit LED Remarks

B "0": Lights off
CH1 Channel Fader CH1 Channel Level Indicator LED
"0": Lights off
"0": Lights off
"0": Lights off
"A": Full Illuminate
Cross Fader Master Level Indicator L LED
"B": Lights off
8 Mode 8 : Channel Level Indicator LED test. "LEDTEST"

• Mode for confirming lighting of the Channel Levele Indicator LEDs
When this mode is entered, “LEDTEST” is displayed at the top of the FL display and the TAP key lights.
The LEDs for CH1 CUE button, CH2 CUE button, CH3 CUE button, CH4 CUE button, MASTER CUE button,
and EFFECT CUE button light.
• Each time the CUE button is pressed, the channel level indicator LEDs for each channel light one by one from the bottom.
D
At first, all the LEDs are unlit.
If the CUE button is pressed after it was pressed 15 times (when the top LED is lit), all the LEDs become unlit again.
Button to be tested Lit Meter Remarks
CH1 CUE button CH1 Channel Level Indicator LED
E CH4 CUE button CH4 Channel Level Indicator LED
MASTER CUE button Master Level Indicator L LED
EFFECT CUE button Master Level Indicator R LED
56 DJM-900NXS
1 2 3 4
5 6 7 8
A
9 Mode 9 : X-PAD value test. "RBNTEST"
• Mode for confirmation of the X-PAD value with a channel level indicator LED and the FL display
When this mode is entered, “RBNTEST” is displayed at the top of the FL display.
• The data item for a touched position on the X-PAD is expressed with a figure in the range of 0 to 127 and displayed in the
middle of the FL display. The LEDs light according to the position touched on the X-PAD.
• The X-PAD consists of 8 sensors.

A touched sensor is indicated on the FL display so that you can judge if it is functioning properly.
The indication method is as shown below.
B
Touched
sensor
Touched position
C
Operating Section Lit LED or FL Remarks

Left: Lights off
X-PAD CH1 Channel Level Indicator LED
Right: Full Illuminate
Left: 0
X-PAD FL: BPM section on the FL display
Right: 127
CH section: Red frame around 1
X-PAD Sensor 1 CH and X-PAD sections on the FL display
X-PAD section: The 1st, 2nd, and 3rd segments light.
CH section: Red frame around 2 D
X-PAD section: The 5th, 6th, and 7th segments light.
CH section: Red frame around MIC
CH section: Red frame around A
CH section: Red frame around B
X-PAD section: The 25th, 26th, and 27th segments light. E
CH section: Red frame around MST
DJM-900NXS 57
5 6 7 8
1 2 3 4
a Mode 10 : AD values of the rotary VRs test. "VOL AD"

A
• Mode for displaying the AD values of rotary VRs on the FL display for confirmation.
When this mode is entered, “VOL AD” is displayed at the top of the FL display.
To indicate the AD values for several rotary VRs with a single level meter, the rotary VRs are divided into 4 groups.
The group pages can be changed by pressing the BEAT c, d button.
When the groups are switched, the name of the VR at the top of the group list is displayed at the bottom of the FL display.
The rotary VRs in a group can be changed by pressing the CH1–4 CUE button.
• The maximum amplitude value among AD conversion values for a rotary VR being tested can be confirmed on each page
of this mode.
The value is expressed with the number of segments lit at the bottom of the FL display. The measurement procedure is as
B indicated below.
Turn the rotary VR you wish to test to a desired position then press the EFFECT CUE key to start measurement. To reset,
press the EFFECT CUE key again. During measurement, the maximum amplitude value will be continuously displayed.
The EFFECT CUE key is lit during measurement and goes dark when reset.
Details on the amplitude value display are shown in the figures below.
An amplitude value in the range of ±1 to ±6 with regard to the VR value at the beginning of measurement is displayed.
For a value greater than +7 or less than -7, all the 7 segments are lit.

C
BEAT BEAT BEAT
AD value
(in hexadecimal d button d button d button
Name of the notation)
rotary VR
Amplitude
value
BEAT BEAT BEAT
CH1 CH2 CH3 CH4

CUE button CUE button CUE button CUE button
Note:
E If the CUE button is pressed while the last VR on each group list is displayed, the top VR on that group list will then be
displayed.
When the BEAT c, d button is pressed for a layer lower than the 2nd one, the top VR on the list of the next group
will be displayed.
58 DJM-900NXS
1 2 3 4
5 6 7 8
A
• For failure judgment of the rotary VRs
As a guide, amplitude values higher than +4 or lower than -4 may be judged as failure.
The VRs can be set to any position during measurement. Possible symptoms are shown below.
• The volume changes arbitrarily.
• Interrupted sound leakage occurs even if the volume is decreased to the minimum at the Master or ZONE.
• The MIDI signal is output even if the corresponding VR is not operated.
• For operation check of a rotary VR after replacement
• Group 1 B

• CH1 TRIM control, CH1 EQ/ISO HI control, CH1 EQ/ISO MID control, CH1 EQ/ISO LOW control,
CH1 COLOR control, EQ HI control, EQ LOW control
VR to be tested FL Display Name Remarks
"-∞": 000
CH1 TRIM control CH1_T
"+9": 3FE
"-∞/-26": 000
CH1 EQ/ISO HI control CH1_H
"+6": 3FE
"-∞/-26": 000
CH1 EQ/ISO MID control CH1_M
"+6": 3FE
C
"-∞/-26": 000
CH1 EQ/ISO LOW control CH1_L
"+6": 3FE
"LOW": 000
CH1 COLOR control CH1_C
"HIGH": 3FE
"-12": 000
EQ HI control MIC_H
"+12": 3FE
"-12": 000
EQ LOW control MIC_L
"+12": 3FE
*As an AD value that is displayed on the FL display is the one before a hysteresis removal process,
and as it has an amplitude, an error of about ±2 may be produced.
D
• Group 2
CH2 COLOR control, MIXING control, LEVEL control

"-∞": 000
"+9": 3FE
"-∞/-26": 000
"+6": 3FE E
"-∞/-26": 000
"+6": 3FE
"-∞/-26": 000
"+6": 3FE
"LOW": 000
"HIGH": 3FE
"CUE": 000
MIXING control HP_MX
"MASTER": 3FE
"-∞": 000
LEVEL control HP_LV
"0": 3FE
F
DJM-900NXS 59
5 6 7 8
1 2 3 4
A
• Group 3
CH3 COLOR control, MASTER LEVEL control, BALANCE control
"-∞": 000
"+9": 3FE
"-∞/-26": 000
"+6": 3FE
B "-∞/-26": 000
"+6": 3FE
"-∞/-26": 000
"+6": 3FE
"LOW": 000
"HIGH": 3FE
"-∞": 000
MASTER LEVEL control MSTLv
"0": 3FE
"L": 000
BALANCE control MST_B
"R": 3FE
C and as it has an amplitude, an error of about ±2 may be produced.
• Group 4
CH4 COLOR control, BOOTH MONITOR control, LEVEL/DEPTH control
"-∞": 000
"+9": 3FE
D "-∞/-26": 000
"+6": 3FE
"-∞/-26": 000
"+6": 3FE
"-∞/-26": 000
"+6": 3FE
"LOW": 000
"HIGH": 3FE
"-∞": 000
BOOTH MONITOR control BOOTH
"0": 3FE
"MIN": 000
LEVEL/DEPTH control LV/DP
E "MAX": 3FE
60 DJM-900NXS
1 2 3 4
5 6 7 8
b Mode 11 : AD values of the fader test. "FDR AD" A
• Mode for displaying the AD values of the faders on the FL display for confirmation
When this mode is entered, “FDR AD” is displayed at the top of the FL display and the TAP key lights.
• Mode 11 consists of 5 pages for indicating the values of 5 faders.

When the groups are switched, the name of the VR at the top of the group list is displayed at the bottom of the FL display
and its AD value is displayed in the middle.
• The maximum amplitude value among AD conversion values for a fader being tested can be confirmed on each page of
this mode. The value is expressed with the number of segments lit at the bottom of the FL display. The measurement
procedure is as indicated below. B
Set the fader you wish to test to a desired position then press the EFFECT CUE key to start measurement. To reset, press
the EFFECT CUE key again. During measurement, the maximum amplitude value will be continuously displayed.
The EFFECT CUE key is lit during measurement and goes dark when reset.
Details on the amplitude value display are shown in the figures below.
An amplitude value in the range of ±1 to ±7 with regard to the VR value at the beginning of measurement is displayed.
For a value greater than +7 or less than -7, all the 7 segments are lit.
BEAT BEAT
AD value d button d button
(in hexadecimal C
notation)
Fader name
BEAT BEAT
c button c button
Amplitude
value BEAT BEAT
c button d button
BEAT
c button
D
BEAT
d button

• For failure judgment of the faders
As a guide, amplitude values higher than +4 or lower than -4 may be judged as failure.
The VRs can be set to any position during measurement. Possible symptoms are shown below.
• The volume changes arbitrarily.
• Interrupted sound leakage occurs even if the volume is decreased to the minimum at the fader. E
• The MIDI signal is output even if the corresponding VR is not operated.
• For operation check of a fader after replacement
Faders that can be confirmed
Fader to be tested FL Display Name Remarks
"0": 000
CH1 Channel Fader CH1
"10": 3FE
"0": 000
CH2 Channel Fader CH2 "10": 3FE
"0": 000
"10": 3FE
"0": 000 F
"10": 3FE
"A": 000
Cross Fader CROSS "B": 3FE
DJM-900NXS 61
5 6 7 8
1 2 3 4
c Mode 12 : Device test. "DEVICE"

A
• Mode for displaying the device information for confirmation

When this mode is entered, “DEVICE” is displayed at the top of the FL display and the TAP button lights.
• Mode 12 consists of 4 pages for indicating the statuses of LAN, IP address, MAC address, and subnet mask.
• “OK” is displayed in the middle of the FL display when the device is operating properly, and “NG” is displayed when it is
not properly operating.
B BEAT BEAT BEAT

Check result
BEAT BEAT BEAT

Device name
C
• You can also check the address data for a device.
The address data that can be confirmed are MAC address, IP address, and IP address, and they are indicated by 3 digits
at a time in the middle of the FL display.
If an address cannot be obtained, “EE” is displayed.
The address data pages can be changed with the AUTO/TAP or QUANTIZE button.
On the address data page, the current page No. and the total number of pages are displayed with lit segments at the
bottom of the FL display.
Note: With the QUANTIZE button, the pages can be changed cyclically, but with the AUTO/TAP button, the pages change
only in one direction (the page will not change if you press the key on Page 1).
Example: When the IP address is “169.254.238.238”

D
QUAN- QUAN- QUAN-

TIZE TIZE TIZE
button button button
Address being
confirmed
Current page
AUTO AUTO AUTO
/TAP /TAP /TAP
button button button
E Total number of pages
Devices and addresses that can be confirmed

Device, Address FL Display Name Remarks
LAN LAN Properly operating: OK, Not properly operating: NG
LAN (MAC Address) MCAdd : Address value
LAN (IP Address) IPAd Properly operating: Address value, Not properly operating: EE *1
LAN (Subnet Mask) Subn Properly operating: Address value, Not properly operating: EE *2
*1 “EE” is also displayed while the IP address is being obtained. If “EE” is displayed for more than 15 seconds, something is wrong.
F
*2 “EE” is also displayed before the subnet mask data are obtained.
62 DJM-900NXS
1 2 3 4
5 6 7 8
4. Mode transition flowchart A
START
Mode 1:
Confirmation of software version. "Version"
BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT

System MAIN CPU SUB UCOM DSP(program) DSP(data) ETHER UCOM USB UCOM FPGA BOOT
Version display Version display Version display Version display Version display Version display Version display Version display Version display
TAP
Mode 2 :
All LEDs & FL display "OFF" mode. "ALL CLR"
TAP B
Mode 3 :
ALL LEDs & FL display "ON" mode. "ALL SET"
TAP
Mode 4 :
KEY operating test. "KEY TEST"
TAP
Mode 5 :
SELECT SW Operating test. "SW TEST"
TAP
Mode 6 :
Rotary VRs value test. "VOLTEST"
BEAT BEAT BEAT C

TAP
Mode 7 :
Fader test. "FDRTEST"
TAP
Mode 8 :
Channel Level Indicator LED test. "LEDTEST"
TAP
Mode 9 :
X-PAD value test. "RBNTEST"
TAP
D
Mode 10 :
AD values of the rotary VRs test. "VOL AD"
CH1 TRIM CH2 TRIM CH3 TRIM CH4 TRIM
CH1 CUE CH2 CUE CH3 CUE CH4 CUE
CH1 EQ/ISO HI CH2 EQ/ISO HI CH3 EQ/ISO HI CH4 EQ/ISO HI
CH1 EQ/ISO MID CH2 EQ/ISO MID CH3 EQ/ISO MID CH4 EQ/ISO MID
CH1 EQ/ISO LOW CH2 EQ/ISO LOW CH3 EQ/ISO LOW CH4 EQ/ISO LOW
BEAT BEAT BEAT
E
CH1 COLOR CH2 COLOR CH3 COLOR CH4 COLOR
EQ HI MIXING MASTER LEVEL BOOTH

MONITOR
EQ LOW LEVEL BALANCE LEVEL/

DEPTH
CH1 CUE CH2 CUE CH3 CUE
CH4 CUE
DJM-900NXS 63
5 6 7 8
1 2 3 4
A TAP
Mode 11 :
AD values of the fader test. "FDR AD"
BEAT BEAT BEAT BEAT

CH1 CH2 CH3 CH4
Channel Fader Channel Fader Channel Fader Cross Fader
Channel Fader
TAP
Mode 12 :
Device test. "DEVICE"
MAC address BEAT IP address BEAT Subnet mask

1st byte 1st byte 1st byte
B AUTO QUANTIZE AUTO QUANTIZE AUTO QUANTIZE

BEAT
2nd byte 2nd byte 2nd byte
LAN
AUTO QUANTIZE AUTO QUANTIZE AUTO QUANTIZE
6th byte 4th byte 4th byte
TAP
6.2 ABOUT THE DEVICE

Device Name Function Part No. Reference No. Assy
MAIN CPU Main control DYW1799 IC2011 MAIN Assy
FPGA For RAM, Digital input distinction, clock divider XC3S50A-4FTG256C IC2214 MAIN Assy
D
ETHER UCOM CONTROLLER for Ether net, R5S76700B200BG IC501 MAIN Assy
Main control support
FLASH (64M) Memory for Ether UCOM DYW1798 IC502 MAIN Assy
(Firmware in MAC Address)
SDRAM (128M) Memory for Ether UCOM (Work) MD56V72160B-6TAZ IC503 MAIN Assy
DSP Audio DSP D810K013BZKB400 IC701 MAIN Assy
FLASH (4M) Memory for DSP (Firmware) DYW1797 IC703 MAIN Assy
SDRAM (256M) Memory for DSP (Work) MD56V82160-6TAZ IC702 MAIN Assy
USB UCOM CONTROLLER for USB ADSP-BF524BBCZ-3A IC1801 MAIN Assy
E SDRAM (64M) Memory for USB UCOM (Work) IS42S16400F-6TL IC1802 MAIN Assy
ETHER PHY PHY for Ether net LINK RTL8201EL-VC-GR IC1603 MAIN Assy
SUB UCOM LED, FL, KEY, VR control DYW1800 IC6601 PNLA Assy
CDC SENSOR Contact position detection of a X-PAD AD7147ACPZ500RL7 IC3601 CDCB Assy
Two or more FLASH and SDRAM are mounted in this unit.

Please judge the device which you should diagnose in reference to this list.
64 DJM-900NXS
1 2 3 4
5 6 7 8
7. DISASSEMBLY
Note: Even if the unit shown in the photos and illustrations in this manual may differ from your product, the A
procedures described here are common.
Knobs and Volumes Location
F G
B
B
A
C H
D I
J C
K
E
E
L G
A Rotary SW Knob S (B) B Rotary SW Knob S (C) C Rotary SW Knob S (A) D Rotary SW Knob (HM) E Rotary Knob (BN)
(DAA1178) ×2 (DAA1204) ×4 (DAA1177) ×2 (DAA1256) ×4 (DAA1220) ×3
White
White White
White White
Gray Gray Black Silver Black
E
F FX Sel Knob G Rotary SW Knob (MA) H Rotary SW Knob (B) L Slider Knob 1 Slider Knob 2 Slider Knob Stopper
(DAA1213) ×5 (DAA1198) ×2 (DAA1176) ×12 (DAC2684) ×5 (DAC2685) ×5 (DNK5888) ×5
White White
White
Black Black Slider Knob 2
Black
White White
Slider Knob 1
I Rotary Knob Low (BN) J Select Knob K Rotary SW Knob (C)
(DAA1265) ×1 (DAA1205) ×1 (DAA1180) ×1
Black
White
White F
Black Black Slider Knob Stopper
Black Gray
Projection
DJM-900NXS 65
5 6 7 8
1 2 3 4
A Disassembly
[1] Exterior Section

[1-1] Exterior section
(1) Remove the three screws. (BCZ40P060FTB)
(2) Remove the two screws. (BSZ40P220FTB)
(3) Remove it to the front direction while lifting
front panel on the top.
B
2 ×2
3
1 ×3
Front panel
[1-2] Control panel section

D (1) Remove the two rotary SW knobs S (B). 1 ×2
(2) Remove the two washers. Rotary SW knob S (B) 3 ×4
(3) Remove the four rotary SW knob S (C). 6 ×2 Rotary SW knob S (C)
(4) Remove the two screws. (BBZ30P060FTB) 2 ×2
(5) Remove the two screws. (BBZ30P060FTC) Washer
(6) Remove the two screws. (BPZ30P120FTB) 4 ×2
(7) Remove the six screws. (CCZ30P080FTB)
Screw tightening order 7 ×3

7 ×3
5 ×2
66 DJM-900NXS
1 2 3 4
5 6 7 8
(8) Remove the control panel section.
Control panel section
D
[2] INPUT Assy
(1) Disconnect the four short pin plugs. 1 ×2 1 ×2 4
(2) Remove the three washers and three nuts. 5 5
(3) Remove the two screws. (PMH30P100FTB) 5 5
(4) Remove the one screw. (BBZ30P060FTB)
3 ×2
(5) Remove the four screws. (BPZ30P080FTB) 2 ×2 2
• Rear view
Nut tightening order
E
A B C
DJM-900NXS 67
5 6 7 8
1 2 3 4
(6) Remove the eight screws. (BBZ30P060FTC) TRIM Bracket
6
Screw tightening order 6
6
C 6
D
B
F 6 6
E
A B
6 6
G H
Center Stay
D
(7) Lift up the INPUT Assy to a front direction.
Control panel section
PNLA Assy
PNLB Assy INPUT Assy

Diagnosis
7
ACSW
Assy
FADC Assy
HPJK Assy
MAIN Assy
SEND Assy
POWER SUPPLY Assy
68 DJM-900NXS
1 2 3 4
5 6 7 8
A
Reference information
Screw tightening order (Rear panel) Nut tightening order (MAIN, SEND Assy)
A B
A B C D
C
E D
Rear panel
B
Screw tightening order (MAIN Assy)
Screw tightening order (Bracket PSW)
A B
B A
Bracket PSW
C
ACSW Assy
Screw tightening order (AC shield) Screw tightening order (MAIN, SEND Assy)
C
AC shield A MAIN Assy SEND Assy

A J
H I K
B
D
D
Nut tightening order (INPUT Assy) G
C
C D E F E F
A
B E
Screw tightening order (USB bracket)
C USB panel
TRIM bracket INPUT Assy
USB bracket
B
A
DJM-900NXS 69
5 6 7 8
1 2 3 4
A
[3] Panel Section
[3-1] Control panel and Fader panel
(1) Remove the all knobs. 1 ×31
(2) Remove the five silider knobs 2,
five slider knobs 1, five slider knob stoppers.
(See below.)
The reference of the direction
B
Side on which
the line reaches the bottom
Side on which
the line reaches
the bottom Stopper
(right direction)
2 ×5
• Disassembly of the slider knob

The new slider knob adopted by this product is designed so that it is not pulled out easily.
Therefore, the method for removing the slider knob is different from the conventional method; it can only be pulled out after
slider knob 2 is removed.
D
1 Find the side on which the line reaches 2 Insert a pair of tweezers etc. beneath 3 Remove the slider knob 2.
the bottom. the line then push the slider knob 2
upward. To protect the panel from being
scratched, use protective material.
Slider knob 2
Slider knob 2
E *: During reassembly, fully push

Tweezers Protective material down Slider knob 2 until it is
dented into Slider knob 1.
4 Remove the slider knob 1. 5 Remove the slider knob stopper.
Slider knob 1
Slider knob stopper
70 DJM-900NXS
1 2 3 4
5 6 7 8
(3) Remove the 6 screws. (CCZ30P080FTB)

(4) Remove the 5 screws. (CCZ30P080FTB) Control panel
4 ×5
(5) Remove the Control panel and Fader panel.
Note: 3 ×5
When you remove only Fader panel, it is a
process of step (2), (4). 3
Screw tightening order

(for MAIN unit)
H B D I B
Fader panel
G
A
J
C
N P
K
M
Q O
F E C L
[3-2] CDCB Assy

(1) Remove the CDCB Assy section. CDCB Assy section
(2) Disconnect the one flexible cable.
3
(CN5601)
(3) Remove the one screw. (BPZ26P080FTC)
(4) Remove the CDC holder. 1 CDC holder
(5) Disconnect the one flexible cable.
(CN3601) 4 E
(6) Remove the CDCB Assy. 2
CN5601
CDCB Assy 5
6 CN3601
CDC panel
F
• Bottom view
DJM-900NXS 71
5 6 7 8
1 2 3 4
A [3-3] Fader section

(1) Remove the two screws. (BBZ30P060FTC)
(2) Remove the FADC Assy. FAD1 Assy
(3) Disconnect the one connector. (CN7002)
(4) Remove the eight screws. (BSZ20P040FTB)
4 ×8 FAD2 Assy
(5) Remove the FAD1 to FAD4 Assemblies. FAD3 Assy
(6) Disconnect the four connectors. FAD4 Assy
(CN6609 to 6612)
(7) Release the jumper wire from clamper.
5
B
• Connectors color
Match the color of a connected connector.
6 ×4
CN6611
CN6609
CN7002 3
7
FAD1 W Y FAD4 1 ×2
(White) (Yellow)
FAD2 R B FAD3
(Red) (Blue)
2
CN6610
CN6612
C FADC Assy
FAD1 FAD2 FAD3 FAD4

FADC Assy Assy Assy Assy Assy
A D E H
D
B A
CRF stay
B C F G
B A
E FADC Assy
72 DJM-900NXS
1 2 3 4
5 6 7 8
• FAD1 to FAD4 Assemblies A

(1) Remove the four screws. (BPZ20P060FTC)
(2) Remove the FAD Assy with VR stay. 1 ×4
(3) Remove th two screws. (PMH20P040FTC)
(4) Remove the FAD Assy. 3 ×2
(5) Remove the two screws and remove the

guide shaft (S) and slider base section. FAD Assy
(CPZ26P080FTC)
(6) Remove the slider section from guide shaft (S). 4
(7) Remove the two screws and remove the 7 ×2
lever plate. (BPZ20P060FTC) VR stay Lever plate B

2
×2 5 7
FAD Assy
C D Guide shaft (S)
Slider base
6
VR stay
A B 5
C
VR stay Shaft holder
Note:
A B FAD Assy The grease application position when you assemble guide shaft(S)
refer to "9.4 CONTROL PANEL SECTION (1/2)."
D
[3-4] PNLA and PNLB Assy
(1) Remove the 30 flange nuts M9. 1 ×30
(2) Remove the one nut.
DJM-900NXS 73
5 6 7 8
1 2 3 4
(3) Remove the SW packing.

5
(4) Remove the one screw. (AMZ26P040FTC) 3 Lens (USB)
(5) Remove the lens (USB). SW packing 6 ×6
(6) Remove the six bushes. Bush
(7) Remove the five buttons (CUE).
(8) Remove the SW packing (EF). 4
(9) Remove the eight slide SW caps (W).
Button (CUE)
Slide SW Cap (W)
7 ×5
9 ×8 SW packing (EF)
8
(10) Reverse the control panel section.

(11) Disconnect the two flexible cables.
(12) Remove the 12 screws. (BBZ30P060FTC)
(13) Remove the barrier.
(14) Remove the 10 screws. (BBZ30P060FTC)
(15) Remove the PNLA and PNLB assemblies. 12 ×12
11
D 11
Barrier
13
PNLA Assy 14 ×10
2 PNLA Assy
1
E
6 PNLB Assy
7
15
5
3 9 8
4 15 18
19
14
20
16 17
21
13
11 10
F
12 22 • Bottom view
PNLB Assy
74 DJM-900NXS
1 2 3 4
5 6 7 8
8. EACH SETTING AND ADJUSTMENT

8.1 NECESSARY ITEMS TO BE NOTED
It is recommended that you take note of the setting data before starting repair. A
Use “8.5 Sheet for Confirmation of the User settings” for taking notes.
After repairing, be sure to check the version of the firmware (see “Mode 1: For confirmation of the version” in “TEST MODE” ),
and if it is not the latest one, update to the latest version.
Perform the each item when the following parts are replaced.
• MAIN Assy
(MAIN CPU: IC2011, FLASH MEMORY IC: IC703) • Confirmation of the version of the firmware
• PNLA Assy • Updating to the latest version of the firmware
(SUB UCOM: IC6601)
B
8.2 UPDATING OF THE FIRMWARE
[1] Downloading and Confirmation of the Updater Files
1. Download the zipped updater file for the latest firmware from Niis.
2. Unzip the downloaded file.
Unzipping the ZIP file generates the “DJM-900nexus_vxxx” folder.
Confirm that the following files are contained in the folder:
1 DJM-900nexus_vxxx.exe
2 DJM-900nexus_vxxx.upd
3 Update manual.pdf
• The above xxx denotes the version of new firmware.
C
• The extension (.exe or .upd) may not be displayed, depending on the setting of the computer.
[2] Preparation for Updating on the Main Unit
U PD ATE
Ver
X. XX
D
<STEP1>
Press [CUE (BEAT EFFECT)] and [ON/OFF (BEAT
EFFECT)] with power button.
Move to update mode.
<STEP2>
Check the current version of your firmware by "current
version" on VFD. (No need to update it if current version
shows as x.xx. It is the latest firmware.)
E
<STEP3>
Connect your computer with this unit by LAN cable.
Connect LAN cable to the LINK terminal on rear on this unit.

F
DJM-900NXS 75
5 6 7 8
1 2 3 4
A
[3] Network Setting on the PC
The network setting on the PC to be used for firmware updating must be set to DHCP or Auto IP.
For Microsoft Windows (Ex: Windows 7)

<STEP 1> <STEP 4>
Open "Control Panel" -> "Network and Internet" Open "Properties" of network device this unit connected.
-> Network Connections. (Right click on icon -> Property)
<STEP 5>
Select "Internet Protocol (TCP/IP) and click on "Properties."
(For Windows XP, check the checkbox “Notify me when this
<STEP 2> connection has limited or no connectivity.”)
C Open "Network and Sharing Center."
(For Windows XP, go to <STEP 4>.
<STEP 3>
Open "Change adapter setting".
<STEP 6>
Select "Obtain an IP address automatically","Obtain DNS
server address automatically".
E
76 DJM-900NXS
1 2 3 4
5 6 7 8
<STEP 7> A
Close “Network Connections” by clicking on "OK."
(For Windows XP, this completes the network setting.)
<STEP 8>
Right click on task bar -> Select "Properties".
<STEP 9>
Select "Notification area" then "Customize."
(For Windows Vista, check the “Network” checkbox.)
<STEP 10>
D
Select "Show icon and notifications" on network.
<STEP 11>
Close "Properties" by "OK".
For Mac OS X
Select “System Environment Settings,” “Network,”
“Ethernet,” then “Using DHCP”
DJM-900NXS 77
5 6 7 8
1 2 3 4
A
[4] Confirmation of Network Connection between the PC and this Unit
For Microsoft Windows
Check the connection status of the PC and this unit, with the icon on the task bar (on the right bottom of the PC screen).
Icon / Message
Status of connection
7 Vista XP
LAN cable is unconnected.
Check the cable is connected.
B
Checking the status of connection.
Wait a minute.
DJM-900NXS is connected.
Start update tool.
For Mac OS X
Check the connection status of the PC and this unit, by selecting “System Environment Settings,” “Network,” then “Ethernet.”
LAN cable is unconnected. Checking the status of connection. DJM-900NXS is connected.

Check the cable is connected. Wait a minute. Start update tool.
78 DJM-900NXS
1 2 3 4
5 6 7 8
A
[5] Executing Updating
* Close all of applications before updating.
* If you were setting firewall by security software, it would not be able to transfer the data to mixer.
Please read the operation manual of the security softwareor canncelt the firewall.
<STEP 1> <STEP 4>

Double click "DJM900nexus_vxxx.exe". Confirm the updating completed.
Start update tool. Updating completed when "SUCCESS" message shows.
<STEP 2>
Select language.
B
<STEP 5>
<STEP 3> Restart this unit.
Start updating by pressing "Start". * Please adjust network setting as original
* NEVER remove power/LAN cable on updating. if you adjusted it in 3-1.
* If the waiting picture remains more than 30 seconds, the C
network connection might not work. Press Cannel button
and update again after connecting it.
[6] Confirmation of the Firmware Version
U P D AT E
Ver
X.XX
E
<STEP1>
Press [CUE (BEAT EFFECT)] and [ON/OFF (BEAT
EFFECT)] with power button.
Move to update mode.
<STEP2>
Check it is the latest version.
Update was completed if it shows "x.xx".
DJM-900NXS 79
5 6 7 8
1 2 3 4
A
Error Message and Details (for Windows)
Title Message Detail
Cannot find the EXE file_I1 Cannot find the EXE file. Restart the application.
Cannot find the update file or update file is not correct.

Cannot find the UpdateFile_I4
Download the file and update again.
Cannot connect to the MIXER_I5 Failed connection with mixer.

Formatting Error Check the status of network and restart the application.
Cannot find the Network Interface_I6 Cannot find the network setting to connect with mixer.
Check the status of network and restart the application.
B Cannot find the Network Interface_I9 Cannot find network interface to connect with mixer.
Cannot connect the MIXER_C1 Could not connect with mixer.

Connection Error Cannot connect the MIXER_C2 Could not connect with mixer.
Cannot send the update data_C4 Failed data transfer to mixer.

Stand up mixer again by update mode and restart the application.
Cannot find the UpdateFile_S1 Cannot find the update file.

Data Transfer Error Cannot find the UpdateFile_S2 Failed data transfer to mixer. The file might have a problem.
C
Cannot find the UpdateFile_S3 Failed data transfer to mixer.

Error Message and Details (for Mac)

Title Message Detail
Cannot find the update file or update file is not correct.

Cannot find the UpdateFile_I4
D
Cannot get the host name.
Formatting Error Cannot get the Host name_I7
Cannot get IP address.

Cannot get the IP Address_I8
Check the status of network and restart application.
Cannot find network I/F to connect with mixer.

Cannot find the Network Interface_I9
Could not connect with mixer.

Cannot connect the MIXER_C1

E
Connection Error
Cannot send the update data_C4 Failed data transfer to mixer.

Cannot find the update file.

Cannot find the UpdateFile_S1
Failed data transfer to mixer. The file might have a problem.

Data Transfer Error Cannot find the UpdateFile_S2 Stand up mixer again by update mode and restart the application.
Failed data transfer to mixer.

Cannot find the UpdateFile_S3 Stand up mixer again by update mode and restart the application.
F
80 DJM-900NXS
1 2 3 4
5 6 7 8
8.3 HOW TO CONFIRM THE DVS
A
Necessary Items
• PC with the USB driver and TRAKTOR (demo version or TRAKTOR DDJ-T1 EDITION possible) installed
Can download the Traktor demo version from the following URL.
http://www.native-instruments.com/#/en/products/dj/traktor-pro-2/?page=1975
• Media (CD, etc.) for checking operations, CDJ player
Check Procedures
1. Connect this unit and a PC, using the USB cable.
2. Connect the audio output of CDJ Player to the CD/LINE of CH1 of this unit.
3. Set the DIGITAL, CD/LINE, PHONO, LINE, and USB */* selectors to USB1/2.
4. For details on settings to be made on the PC, see “Settings for the Driver” and “Settings on TRAKTOR” below.
B
5. Play back the CDJ Player, and check the following items:
• The level meters of Input Routing and Master Out on the TRAKTOR move in sync with audio output signals (see the
photos below).
• The USB audio input indicator of CH1 turn on.
• The Master Out is output normally.
*Repeat the above steps for channels 2 to 4, to check the DVS paths.
[TRAKTOR Input Routing level meter]
C
[USB audio input indicator]
[TRAKTOR Master Out level meter]
Note:
The Master Out signal will not be output if the MAIN volume control
(indicated with a red frame) is set to the minimum volume position.
If the MAIN volume indicators are not displayed on the screen, set the
D
TRAKTOR screen to Full screen.
[Connection Diagram (When the CDJ Player is Connected to CH1)]
DJM-900nexus DJM-900nexus
Computers
E
USB cable
Power amplifier
F
CDJ player
DJM-900NXS 81
5 6 7 8
1 2 3 4
A
Settings for the Driver
Start up the "DJM-900nexus Settings Utility".
(Reference)
For Windows
Click [Start] menu → [All Programs] → [Pioneer] → [DJM-900nexus] → [DJM-900nexus Settings Utility].
MIXER INPUT MIXER OUTPUT
When the DIGITAL, CD/LINE, PHONO, LINE, and Set the Timecode CD/LINE.
C USB */* selectors of the mixer are set to USB*/*, “USB” must
be displayed on the PC screen.
Settings on TRAKTOR
1 After starting TRAKTOR, select the deck layout, as shown below.
View > Layouts, or Layout selector
If a 4-deck screen option is not available, see Note 1.
D Master Out Layout Selector
82 DJM-900NXS
1 2 3 4
5 6 7 8
2 Click on the b symbol beneath A to D then select “Audio Through” from the pulldown menu.
3 Select Traktor then Preferences, or click on the Preferences button.

Preferences button
DJM-900NXS 83
5 6 7 8
1 2 3 4
A 4 In Audio Setup, select DJM-900nexus.

With the above settings, CH 1 of the mixer is assigned to
Deck A, CH 2 to Deck B, CH 3 to Deck C, and CH 4 to
Deck D.
7 Close the Preferences window, by clicking on the

Close (×) button.
Note 1:
How to add a 4-deck screen option
If a 4-deck screen option is not available on the Layouts
menu, proceed as follows:
Traktor > Preferences
5 In Output Routing, set Mixing Mode to External, and In Layout Manager, click on “Add” then select
Output Channel A-D, as shown in the figure below. “Tpro Ext.Mixer - 4Deck.”
6 In Input Routing, set Input Channel A–D, as shown in the After confirming that 4Deck is added to Layout, close the
figure below. Preferences window, by clicking on the Close (×) button.
84 DJM-900NXS
1 2 3 4
5 6 7 8
8.4 USER SETABLE ITEMS
A
FL Initial Value Part Content to be
Setting Item Display Setting Area Part No. Ref No. Assy Stored
(Factory settings) Name
Fader Start F.S. ON/OFF OFF
MIDI CH MIDI CH 1 to 16 1
USER MIDI Button Type MIDI BT Toggle/Trigger Toggle

SETUP
TALK OVER MODE TLK MOD ADVANCED / NORMAL ADVANCED
TALK OVER LEVEL TLK LVL -24dB/-18dB/-12dB/-6dB -18dB
Digital Master Out Level DOUT LV -19dB/-15dB/-10dB/-5dB -19dB

DYW1798 Flash IC502 MAIN UTILITY
Digital Out Sampling Rate DOUT FS 48kHz/96kHz 96kHz ROM setting
MASTER ATT. MST ATT -6dB/-3dB/0dB 0dB B
CLUB Auto Standby AUTOSTB ON/OFF ON

SETUP
Mic Output To Booth Monitor MIC BTH ON/OFF ON
PC Utility PC UTLY ON/OFF ON
Factory Reset INITIAL YES/NO NO
DJM-900NXS 85
5 6 7 8
1 2 3 4
8.5 SHEET FOR CONFIRMATION OF THE USER SETTING
A When you write down a setting item, please make use of this seat.
USER SETUP
Fader Start
OFF ON
MIDI CH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MIDI Button Type

TGL TRG
B
TALK OVER MODE

NOR ADV
TALK OVER LEVEL

-24dB -18dB -12dB -6dB
CLUB SETUP
Digital Master Out Level
C
-19dB -15dB -10dB -5dB
Digital Out Sampling Rate

48kHz 96kHz
MASTER ATT.
-6dB -3dB 0dB
Auto Standby
OFF ON
D
Mic Output To Booth Monitor
OFF ON
PC Utility
OFF ON
Factory Reset
NEVER perform FACTORY RESET before taking note of setting data.
86 DJM-900NXS
1 2 3 4
5 6 7 8
DJM-900NXS 87
5 6 7 8
1 2 3 4
9. EXPLODED VIEWS AND PARTS LIST

NOTES: - Parts marked by “NSP” are generally unavailable because they are not in our Master Spare Parts List.
A
- The > mark found on some component parts indicates the importance of the safety factor of the part.
- Screws adjacent to b mark on product are used for disassembly.
- For the applying amount of lubricants or glue, follow the instructions in this manual.
(In the case of no amount instructions, apply as you think it appropriate.)
9.1 PACKING SECTION
SYXJ8 only
C
KXJ5 only
or or or
or
88 DJM-900NXS
1 2 3 4
5 6 7 8
(1) PACKING SECTION PARTS LIST

Mark No. Description Part No.
> 1 Power Cord See Contrast table (2)
2 USB Cable DDE1128 A
3 CD-ROM DXX2619
4 Operating Instructions See Contrast table (2)

NSP 9 Warranty Card (WY) See Contrast table (2)
NSP 10 Flier See Contrast table (2)
B
NSP 11 Recycle Label (M) See Contrast table (2)
NSP 12 Polyethylene Bag AHG7117
13 Pad A DHA1854
14 Pad B DHA1855
15 Packing Case See Contrast table (2)
16 Packing Sheet RHC1023
(2) CONTRAST TABLE C

DJM-900NXS/SYXJ8, UXJCB, LXJ, KXJ5 and XJCN5 are constructed the same except for the following:
DJM-900NXS DJM-900NXS DJM-900NXS DJM-900NXS DJM-900NXS
Mark No. Symbol and Description
/SYXJ8 /UXJCB /LXJ /KXJ5 /XJCN5
> 1 Power Cord ADG7062 DDG1108 ADG7062 XDG3066 ADG7105
4 Operating Instructions DRB1533 Not used Not used Not used Not used
(En, Fr, De, It, Nl, Es, Ru)
5 Operating Instructions (En) Not used DRB1542 Not used Not used Not used
6 Operating Instructions (En, Es, Zhtw) Not used Not used DRB1543 Not used Not used
7 Operating Instructions (Ko) Not used Not used Not used DRB1545 Not used
8 Operating Instructions (En, Zhcn) Not used Not used Not used Not used DRB1544
D
NSP 9 Warranty Card (WY) ARY7107 Not used Not used Not used Not used
NSP 10 Flier DRH1108 DRH1109 DRH1109 DRH1107 DRH1107
NSP 11 Recycle Label (M) Not used Not used Not used DRW2307 Not used
15 Packing Case DHG2937 DHG2977 DHG2978 DHG2981 DHG2980
DJM-900NXS 89
5 6 7 8
1 2 3 4
9.2 EXTERIOR SECION
A Refer to
NON-CONTACT
CONTACT SIDE
"9.4 CONTROL PANEL SECTION (1/2)" .
SIDE
UXJCB
only
B
B
H
C
C
D
E
F
UXJCB
only
A
UXJCB, LXJ, KXJ5
only
D
B
I
UXJCB
only
F
UXJCB
only
Refer to
"9.3 BOTTOM SECTION" .
90 DJM-900NXS
1 2 3 4
5 6 7 8
(1) EXTERIOR SECTION PARTS LIST

1 INPUT Assy DWX3193 26 Rotary SW Knob S (B) DAA1178

2 MIC1 Assy DWX3207 27 Rotary SW Knob S (C) DAA1204 A
3 TRM1 Assy DWX3203 NSP 28 Caution Label See Contrast table (2)
4 TRM2 Assy DWX3204 NSP 29 Label See Contrast table (2)
5 TRM3 Assy DWX3205 NSP 30 Name Label See Contrast table (2)
6 TRM4 Assy DWX3206 31 • • • • •

7 USBI Assy DWX3192 32 • • • • •
8 HPJK Assy DWX3208 33 Flange Nut M9 DBN1008
9 Short Pin Plug AKM7008 34 Flange Nut M7 DBN1011
10 USB Cable (5P) DDA1041 35 Nut M12 DBN1018
36 Washer DEC2920 B
11 40P FFC DDD1550
12 Connector Assy PF04PP-S12 37 Nut NKX2FTC
13 Connector Assy PF11PP-D07 38 Washer WA62D095D025
14 HP Stay DNF1820 39 Terminal Screw AKE-031
15 TRIM Bracket DNF1864 40 Screw BBZ30P060FTB
16 USB Bracket DNF1868 41 Screw BBZ30P060FTC

17 Extension Shaft A DNK5365 42 Screw BCZ40P060FTB
18 Extension Shaft B DNK5366 43 Screw BPZ30P080FTB
19 Rivet (Plastic) AEC1877 44 Screw BPZ30P120FTB
20 Locking Mini Clamp DEC2439 45 Screw BSZ40P220FTB
C
21 Side Panel L DNK5363 46 Screw CCZ30P080FTB

22 Side Panel R DNK5364 47 Screw (M3x5) DBA1340
23 Front Panel DNK5845 48 Screw PMH30P100FTB
24 USB Panel DNK5847
25 USB Cover B DNK5868
(2) CONTRAST TABLE D

NSP 28 Caution Label Not used DRW2429 DRW2430 DRW2432 Not used
NSP 29 Label Not used DRW1975 Not used Not used Not used
NSP 30 Name Label DRW2463 DRW2472 DRW2473 DRW2476 DRW2475
DJM-900NXS 91
5 6 7 8
1 2 3 4
9.3 BOTTOM SECTION
PNLA
CN6602
HPJK G
CN9201
INPUT
USBI CN4002
CN3801 INPUT
CN4003
J
C
C D
C
D
UXJCB
only
E
A
T
B
F
*Note:
During MAIN Assy disassembly, if the silicone sheet is found to be
deformed, replace it with a new one.
92 DJM-900NXS
1 2 3 4
5 6 7 8
BOTTOM SECTION PARTS LIST

1 MAIN Assy DWX3190
2 SEND Assy DWX3195 A
3 ACSW Assy DWR1490
> 4 POWER SUPPLY Assy DWR1492
> 5 AC Inlet Assy See Contrast table (2)
6 Connector Assy DKP3901

7 Connector Assy PF06EP-S22
NSP 8 Chassis DNA1410
9 Rear Panel See Contrast table (2)
10 Bracket PSW DNF1759
B
11 Power Shield DNF1815
12 AC Shield DNF1816
13 Center Stay DNF1867
14 Foot (Rubber) REC-434
NSP 15 Spacer AEB7092
16 PCB Support AEC7513

NSP 17 Silicon Rubber D5 L DEB1456
18 Blind Label DEC2928
19 Tape DEC3053
20 Holder VEC1355 C
21 Power Knob DAC2306

22 Power Knob Guard DNK4534
23 Binder ZCA-SKB90BK
24 • • • • •
25 • • • • •
26 Washer DEC2920
27 Nut NKX2FTC
28 Screw BBZ30P060FTB
29 Screw BBZ30P060FTC D
30 Screw BPZ30P080FTB
31 Screw IBZ30P080FTB
32 Screw IMZ30P040FTC
33 Screw PPZ30P080FTB
34 Screw See Contrast table (2)
(2) CONTRAST TABLE

E
> 5 AC Inlet Assy (2P) DKP3762 Not used DKP3762 DKP3762 DKP3762
> 5 AC Inlet Assy (3P) Not used DKP3927 Not used Not used Not used
9 Rear Panel DNC2020 DNC2037 DNC2038 DNC2041 DNC2040
34 Screw Not used PMH40P080FTC Not used Not used Not used
DJM-900NXS 93
5 6 7 8
1 2 3 4
9.4 CONTROL PANEL SECTION (1/2)
C
or
M or O
or
N or P
D
W R
L
B Y
Top & Bottom Top & Bottom

Lubricating oil
(GYA1001)
Top & Bottom Top & Bottom
E Note:
Greasing must be performed at a total of 8 points, 2 points each for the
upper and bottom places of each shaft. (0.4 to 1 mg per point × 8 points)
After applying grease, move the slider base back and forth from one end
to the other for approximately 10 to 20 strokes, in order to fully spread
the grease.
W R
B Y
R
NON-CONTACT
CONTACT SIDE
F
SIDE
Refer to Nut:
"9.5 CONTROL PANEL SECTION (2/2)" . Attached part of
Rotary encoder (DSX1068)
94 DJM-900NXS
1 2 3 4
5 6 7 8
CONTROL PANEL SECTION (1/2) PARTS LIST

1 CDCB Assy DWX3191 46 Lens (CDC) DNK5871

2 FAD1 Assy DWX3198 47 Slider Knob Stopper DNK5888 A
3 FAD2 Assy DWX3199 48 • • • • •
4 FAD3 Assy DWX3200 49 • • • • •
5 FAD4 Assy DWX3201 50 Flange Nut M9 DBN1008
6 FADC Assy DWX3202 51 Screw AMZ26P040FTC

7 FFC DDD1582 52 Screw BBZ30P060FTC
8 Connector Assy PF03PP-B07 53 Screw BPZ20P060FTC
9 Connector Assy PF03PP-B12 54 Screw BPZ26P080FTC
10 Connector Assy PF03PP2B07 55 Screw BSZ20P040FTB
56 Screw CPZ26P080FTC B
11 Connector Assy PF03PP4B12
12 Connector Assy PF03PP6B07 57 Screw IMZ30P040FTC
13 CRF Stay DNF1870 58 Screw PMH20P040FTC
14 CDC Holder DNK5842 59 Screw CCZ30P080FTB
15 Bush DNK5974 60 Spacer TFTB DEC3300
16 SW Cushion HH48/2 DEC2538

17 Fader Packing DEC2903
18 SW Packing (EF) DEC2929
19 CDC Tape DEC3324
20 SW Packing DED1177 C
NSP 21 Guide Shaft (S) DLA1918

22 Lever Plate DNH2954
23 VR Stay DNH2955
24 Slider Base DNK5851
25 Shaft Holder DNK5852
26 Rotary SW Knob (B) DAA1176

27 Rotary SW Knob S (A) DAA1177
28 Rotary SW Knob (C) DAA1180
29 Rotary SW Knob (MA) DAA1198 D
30 Select Knob DAA1205
31 FX Sel Knob DAA1213

32 Rotary Knob (BN) DAA1220
33 Rotary SW Knob (HM) DAA1256
34 Rotary Knob Low (BN) DAA1265
35 Slide SW Cap (W) DAC2401
36 Button (CUE) DAC2503

37 Slider Knob 1 DAC2684
38 Slider Knob 2 DAC2685 E
39 FL Panel DAH2829
40 Fader Panel DAH2830
41 CDC Sheet DEC3325

42 Control Panel DNB1186
43 Lens DNK4532
44 CDC Panel DNK5846
45 Lens (USB) DNK5848
DJM-900NXS 95
5 6 7 8
1 2 3 4
9.5 CONTROL PANEL SECTION (2/2)
A • Bottom view
MAIN
CN1001
B
Q
A
E
NON-CONTACT
CONTACT SIDE
F
SIDE
96 DJM-900NXS
1 2 3 4
5 6 7 8
CONTROL PANEL SECTION (2/2) PARTS LIST

1 PNLA Assy DWX3196
2 PNLB Assy DWX3197 A
3 31P FFC DDD1551
4 31P FFC DDD1553
5 Panel Stay DND1265
6 Barrier FL DEC3351
7 Barrier DEC3382
8 Wire Saddle XEC3100
9 Effect Knob DAC2304
10 Slide SW Cap DAC2400
B
11 Button (TAP) DAC2653
12 Button (LINK) DAC2654
13 Button (MIDI) DAC2655
14 Button (CFX) DAC2656
15 Lens Holder DNK4533
16 Lens Holder (S) DNK5849

17 Lebel Meter Assy DXB1882
18 • • • • •
19 • • • • •
20 Screw BBZ30P060FTC C
DJM-900NXS 97
5 6 7 8
1 2 3 4
10. SCHEMATIC DIAGRAM

10.1 INPUT ASSY (1/11)
A
A 1/11 INPUT ASSY (DWX3193) IC4002 V+3R3D_IN
TC7SH08FUS1
C4002 2-1
5 0.1u/16
1
24M_CLK_SUB
MCLK INB
INA
4
V+3R3D_IN
2 IC4006
3 TC7SH08FUS1
OUTY
GNDD C4006 2-2

5 0.1u/16
1
BOARD IF
INB 4
INA
2 3
OUTY
V+3R3D_IN
IC4003 GNDD
TC7SH08FUS1
2-3
5 C4003
6M_CLK_SUB 1
0.1u/16
NOTES is STBY 4
NM
BCLK INB
INA
2 3
B RS1/10SR***J OUTY
IC4007 V+3R3D_IN
RS1/16SS***J
RS1/4SA***J TC7SH08FUS1
GNDD
C4007
2-4
D RS1/10SE****D 1 5 0.1u/16
INB 4
RN RN1/16SE****D
INA
2 3
CKSRYB OUTY
CKSSYB
CKSYB V+3R3D_IN
IC4004 GNDD
TC7SH08FUS1
HXS CFHXSQ
96K_CLK_SUB C4004
2-5
1 5
CH CCSRCH 4
0.1u/16
INB
CCSSCH LRCLK INA
2 3
LA CFTLA OUTY V+3R3D_IN
+ IC4008
JQ CEJQ TC7SH08FUS1
GNDD
C4008
2-6
NP CEANP 1 5 0.1u/16
INB 4
CEAT
INA
2 3
HAT CEHAT
OUTY
V+3R3D_IN
ZL CEHAZL
GNDD
C 2-7 IC4005
1 1CLR 14
VCC
: Voltage measuring point 2 1D
2CLR
13
3 1CK
12
: Waveform measuring point 2D

2-9
BCLK
4 1PR 11
2CK
5 1Q 10
2PR
6 9
1Q
2Q
7 GND 8
C4005
0.1u/16
2Q
TC74VHC74FK RESET CIRCUIT

for ADC
GNDD
RESET
ADAT_CH3_ANA
A 4/11 CH2_TRIM
7:12F
TC_SEL3
4:11C 7:2H
D From To CH2 INPUT Block LINE_SEL2
4:2H LINE_SEL3
6:2H
A 5/11 TC_SEL2
5:2H
ADAT_CH2_ANA
CH3_TRIM
6:11C
From To CH2 AD Block 5:12F
ADAT_CH4_ANA
A 2/11 CH1_TRIM
2-14 9:12F
TC_SEL4
9:2H
2:11C LINE_SEL4
From To CH1 INPUT Block LINE_SEL1 8:2H
2:2H 2-11 CH4_TRIM
A 3/11 TC_SEL1
3:2H 2-12
8:11C
From To CH1 AD Block ADAT_CH1_ANA

3:12F 2-13 ADAT_RETURN_AN
10:10E
A 11/11 ADAT_MIC_ANA
RETURN_IN
10:10E
From To MIC/MIDI Block 11:11E
MIDI_TXD
R4033
R4035
R4038
11:10F
0
2-15 V+3R3
AD/DA RESET
0
E CH1 & MIC side CH2 & CH3 center position R4052
KN4001 KN4002
VKN1811-A
CN4002
AKF7002-A AKF7002-A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
R4009 NM 1 R4005 NM 1
GNDD
MIDI TXD
MIC_DATA
CH1_DATA
GNDD
CH1_SEL(Time code)
CH1_SEL
CH1_TRIM
GNDD
CH2_DATA
GNDD
CH2_SEL(Time code)
CH2_SEL
CH2_TRIM
GNDD
MCLK
GNDD
BCLK
GNDD
LRCLK
GNDD
AD/DA_RESET
GNDD_REFA
GNDD_REFA
V+3R3DRERA
V+3R3DRERA
GNDD
CH3_DATA
GNDD
CH3_SEL(Time code)
CH3_SEL
CH3_TRIM
GNDD
CH4_DATA
GNDD
CH4_SEL(Time code)
CH4_SEL
CH4_TRIM
GNDD
RETURN_DATA
RETRUN_IN
R4010 NM R4006 NM GNDD_REFA
GNDD GNDD
R4011 NM R4007 NM
R4012 NM R4008 NM
GND_PO GND_PO
GNDA_1 GNDA_2
G 1/21 CN1002
GNDA_1T GNDA_2T
GNDA_3
F
GNDA_3T
A 1/11 GNDF
98 DJM-900NXS
1 2 3 4
5 6 7 8
To RETURN AD Block A 10/11

CH3 AD Block A 7/11
R4004 22
_IN
R4013 22
MCLK_IN_RE
10:10D CH4 AD Block A 9/11
MCLK_IN_CH3
R4014 22 7:2H
MCLK_IN_CH4
2-2 9:2H
6
R4015 22 MCLK_IN_CH1
3:2H
R4016 22
MCLK_IN_CH2
5:2H
R4017 22
MCLK_IN_MI
11:11E
R4018 22
BCLK_IN_RE
R4019 22 10:10D
BCLK_IN_CH3
D_IN R4020 22 7:2H B
BCLK_IN_CH4
2-4 9:2H
6 22
R4021
BCLK_IN_CH1
3:2H
R4022 22
BCLK_IN_CH2
R4023 22 5:2H
BCLK_IN_MI
11:11E
To MIC/MIDI A 11/11
R4024 22
LRCLK_IN_RE
CH1 AD Block A 3/11
10:10E
_IN
R4025
R4026
22
22
LRCLK_IN_CH3
7:2H
CH2 AD Block A 5/11
LRCLK_IN_CH4
8
2-6 9:2H
6
R4027 22
LRCLK_IN_CH1
R4028 22 3:2H
LRCLK_IN_CH2
V+3R3D_IN
IC4009 R4029 22 5:2H
TC7SH08FUS1 LRCLK_IN_MI
11:11E
1 5 R4054 2-8 C
INB 4 22 RESET_IN1
INA 7:2G;9:2H;10:10D
2 3
OUTY
V+3R3D_IN
IC4010
TC7SH08FUS1
GNDD
2-10 3:2G;5:2G;11:11D
5 C4010
1 R4056
0.1u/16 RESET_IN2
INB 4 22
INA
2 3
OUTY
GNDD
T
R4030
2.2k V+5D_IN V+12D_IN V+3R3D_IN V+5A_IN V+15A_IN

V-15A_IN
V+5D V+12D V+3R3D V+5A V-15A V+15A

ADAT_CH3_ANA V+5A_IN V+5A_IN
From To
7:12F
A 7/11
1000p/50
0.1u/16
23 19
1000p/50
1000p/50
1000p/50
CH3 AD Block
0.1u/16
22 24 21 20
0.1u/16
0.1u/16
TC_SEL3
NM
1000p/50
100u/25
1000p/50
R4034
NM
0.1u/25
0.1u/25
7:2H
NM
NM
13
From To D
100u/10
C4030
100u/10
C4022
LINE_SEL3
HAT
NM
100u/25
NM
NM
HAT
C4018
CH3 INPUT Block A 6/11 HAT
R4031
HAT
6:2H
390
R4036
C4023
C4024
CH3_TRIM
C4031
C4032
C4027
C4028
C4029
C4034
C4033
C4019
C4020
C4021
6:11C
C4015
C4016
C4017
C4011
C4012
C4013
C4014
C4025
13
From To
ADAT_CH4_ANA
9:12F
A 9/11
R4032
CH4 AD Block
R4037
390
TC_SEL4
13
9:2H
LINE_SEL4 From To GNDD
8:2H
CH4_TRIM
CH4 INPUT Block A 8/11 2 Q4002 GNDF
8:11C 3 GND_PO
LSC4081UB(QRS) (GNDA)
2 1
R4060
R4003
R4061
0 R4002
0 R4062
ADAT_RETURN_ANA 3
10:10E From To Q4001 1
R4001
RETURN_IN
RETURN Block LSC4081UB(QRS)
CH4 & RETURN side
0
0
0
10:10E
A 10/11 GNDD
KN4003
AKF7002-A
GNDF
2-15 V+3R3D_REFA R4063 NM

R4057
R4058
R4059
1
0
R4064 NM
KM200NA11L
0 To CH1 INPUT Block

CH2 INPUT Block GNDD E
CN4003
R4052
CH3 INPUT Block
VKN1811-A
CN4002
10
11
1
CH4 INPUT Block GNDD GNDF

(GNDA)
V+5D
GNDD
V+12D
GNDD
V+3R3D
GNDA_IN
V+5A
GNDA_IN
V-15A
GNDA_IN
V+15A
1
GNDA_4
RETRUN_IN
GNDD_REFA
GNDA_4T
G 2/21 CN1203
GNDF
A 1/11
DJM-900NXS 99
5 6 7 8
1 2 3 4

V+15A_IN
A C4225
R4235
R4238
0.1u/25
RN
RN
C4226
2k
2k
100u/25
CH1
CH
C4220 ZL
330p/50
GND_PO PHONO1_L
IC4201
R4229 47 6
8 C4230 (P1)
7 (1/2)
C4216
4 33u/16
0.022u/50 5 NP
NJM4580MD
R4243
100k
R4225
PHONO
2SK3320(BL)
1.2k V-15A_IN
3
Q4210
GNDF
RN
(P1) R4217
4
C4222
0.01u/16
C4218
470p/50
100
220p/50
330p/50
C4206
C4208
R4221
CH HXS
CH
RN
47k
R4231 R4241
D
75 7.5k
GNDP1 GNDP1GNDP1
470u/6.3
B
C4213
HAT
INPUT BUFFER
V+15A_IN
GNDP1
V+15A_IN
R4210 R4209
2.2k
HN1C01FU(YGR)
HN1C01FU(YGR)
R4234
R4237
R4203
Q 4 2 0 3 (1/2)
RN
RN
18k
2k
2k
Q 4 2 0 3 (2/2)
Q4202 2.2k
Q 4 2 0 2 (1/2)
6
2 CH
(2/2)
C4219
330p/50 IC4201 PHONO1_R
1 2 NJM4580MD
R4228 47 8 C4229
3 3 1 (2/2)
2 6 C4215
5 5
R L R L 4 1
4 0.022u/50 3
4
33u/16
NP
R4242
100k
C 4 2 2 8 ZL
R4211
R4215
R4219
(P1)
R4224
2SK3320(BL)
RN
RN
RN
470
470
470
100u/25
LINE 1.2k C4224
3
1
PHONO
Q4209
0.1u/25
V-15A_IN
C L L R4216
RN V-15A_IN GND_PO GNDF
4
C4221
C4217
470p/50
100 0.01u/16
GNDF
220p/50
330p/50
C4205
C4207
R4220
HXS
R R
CH
CH
RN
47k
R4230 R4240
D
75 7.5k
GNDP1 GNDP1GNDP1
470u/6.3
C4211
HAT
GNDP GNDF_1
(L1)
JA4201 1
GNDP1
2
LINE 3
4
V+15A_IN V+12D_IN
PHONO 5
6
R4205
C4223
NM
DKB1083-A
R4222
R4232
R4236
GND_PO 0.1u/25
1SS352 1SS352
RN
180k
RN
RY4201
D4203
GNDP1 GNDF
1k
1k
D
LINE1_L
R4226 180 6
GND_PO NP
8 C4231
D4204
7
D C4212
33u/16
4 IC4202
5
RN NJM4580MD
R4244
(L1) 4700p/50
100k
R4204 (1/2)
6 2
3 V-15A_IN
100 5 2 3
Q421
100p/50
100p/50
C4202
C4204
R4214
Q4205
Q 4 2 0 5(1/2)
CH
CH
RN
LTC1
47k
(2/2) 4 1 GNDF 1
HN1C01FU(YGR)
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
3
D4201
GNDD
C4209
Q4207
GNDF
5
V+15A_IN
INPUT BUFFER
R4207 R4206
V+15A_IN
4.7k
RN
HN1C01FU(YGR)
HN1C01FU(YGR)
R4201
18k
R4223
R4233
R4239
Q 4 2 0 4(2/2)
RN
RN
Q 4 2 0 4(1/2)
180k
Q4201 4.3k
RN
1k
1k
Q 4 2 0 1 (1/2)
6
E 2
IC4202
NJM4580MD LINE1_R
2-16
(2/2)
R4227 180 2 NP
1 8 (2/2) C4232
1
3 6 3 C4214
5 2 5 4 33u/16
3
R4245
4700p/50
100k
4 1 4
6
R4208
R4213
R4218
(1/2) 3
RN
RN
RN
2 5
470
470
470
Q4206
(2/2) C4227
HN1C01FU(YGR)
1 4 Q4206
0.1u/25
GNDF
V-15A_IN V-15A_IN GND_PO
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
1
C4210
D4202
Q4208
4
RN
R4202
100
100p/50
100p/50
C4201
C4203
R4212
CH
CH
RN
47k
F
LINE A 1/11
GNDF
From BOARD IF LINE_SEL1
A 2/11 1:2F
100 DJM-900NXS
1 2 3 4
5 6 7 8
A 2/11 INPUT ASSY (DWX3193) A
(P1)
C CN8201
V+3R3D_REFA
B
1 1 GNDD_REFA
1 0 VR-TRIM1
R_out1
L_out1
GNDA
GNDA
GNDA
GNDA
V+3R3D_REFA
R_in1
L_in1
CN4201
XKP3065-A 1
9
GNDF GNDD_REFA
C4233
0.1u/16
2-18 GNDD_REFA
A 1/11
1:2F
2-17 CH1_TRIM
To BOARD IF C
CH1_R_out 3:2E
CH1_R_out
(CH1 A) CH1_L_out 3:2B
Time code Trim pass Line

CH1_L_out
A 3/11
R4246 3:2G
(L1) 0
CH1_R_out_time
To CH1 AD Block
R4247 3:2F
CH1_L_out_time
0
(CH1 T)
L_audio line
V+12D_IN
10 10
6
9
7
9
VSR1008-A
1SS352 1SS352
RY4201
D4203
RELAY
D4204
D
5 5
1 1
2 2
3 3
4 4
2
R_audio line
3
Q4211
LTC124EUB
1
GNDD
: Waveform measuring point

NOTES NM is STBY
(P1)
RS1/10SR***J
RS1/16SS***J
: CH1 PHONO Signal (L CH)
(L1)
D RS1/10SE****D : CH1 LINE Signal (L CH)
RN RN1/16SE****D (CH1 A)
CKSRYB
: CH1 Audio Signal (L CH)
(CH1 T)
CKSSYB
: CH1 Timecode Signal (L CH) E
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
A 2/11
DJM-900NXS 101
5 6 7 8
1 2 3 4
Intermediate Buffer V+15A_IN

C4429
ZL
A 100u/25
V+15A_IN C4430 Balanced Direc

INPUT CH1 AD C4423
0.1u/25
C4424
0.1u/25
GND_PO
R4422
R4416
R4420
PHONO / CD
330k
RN
RN
2k
2k
D
6 8 0 RN
22u/50
1000p/50
ZL
C4434
R4448
C4459
NM
CH
IC4404
R4418 180 2 GND_PO (1/2)
CH1_L-
8 RN RN
R4424 6
8 R4439 R4460
C4418 7
1
(CH1 A) R4425 1.2k
4
R4452
3 IC4402 220 0
4700p/50 4
RN
330
NJM4580MD 1.2k 5
NJM4580MD RN 1SS3
(2/2) RN
R4440
3 3
6 V-15A_IN
Q4403 5 2
R4453
(2/2) Q 4 4 0 3(1/2) 430
RN
1k
4 1 HN1C01FU(YGR) C4439 D44
V-15A_IN
NM
HZU3R0(B1)
R4454
2SK3320(BL)
RN
1k
0.47u/6.3
V+15A_IN 1SS3
1
0 0
D4402
GNDF
C4416
Q4406
1000p/50
C4460
3
C4435
R4449
CH
RN
R4480 R4482
680
IC4404
R4455
NM
RN
330
(2/2)
R4426 RN D44
B RN 2
5
(CH1 A) LA LA LA 8 R4441 R4461
1
2:11D C4402 C4404 C4409 1.2k
CH1_L_out R4427
RN 1 . 2 k 4 220 0
C 4 4 1 4 CH
NM NM NM 3
NJM4580MD
R4405
100p/50 CH1_L+
NM
RN
R 4 4 4 2 RN
R4414
130k
RN
R4410
RN
20k
430
C4440
NM
GNDF C4431
GNDF
0.1u/25
V-15A_IN GND_PO
V+15A_IN
R4407 R4406
V+15A_IN
4.7k
RN
C4432
HN1C01FU(YGR)
HN1C01FU(YGR)
V+15A_IN
R4403
18k
0.1u/25
RN
Q 4 4 0 2 (1/2)
4.3k
Q 4 4 0 1 (1/2)
6 GND_PO
R4421
R4415
R4419
330k
2
2-19
RN
RN
Q4402
2k
RN
2k
D
NJM4580MD
Q4401
1000p/50
(2/2)
C4436
R4450
C4461
(2/2)
3 (1/2)
CH
680
3 IC4405 CH1
6 R4417 180 IC4402
NM
5 2 5 6
8 (1/2)
7 R4428 2 RN
RN 8 R4443 R4462
4 1 4 C4417 1
1.2k
4 R4429
R4456
5
R4408
R4411
R4413
4 220 0
RN
4700p/50
330
RN 1 . 2 k
RN
RN
RN
1SS3
470
470
470
3
C 4 4 2 5 ZL NJM4580MD
6 R4444
(1/2) 3 (2/2) 22u/50 3
Q4404 2 5 Q4404 C4422 RN
R4457
430
RN
1k
V-15A_IN 1 4 D44
V-15A_IN C4441
From CH1 INPUT
HN1C01FU(YGR) 0.1u/25
NM
HZU3R0(B1)
A 2/11
R4458
V-15A_IN GND_PO
RN
1k
V+15A_IN 1SS3
1
3
0.47u/6.3
D4401
GNDF
2SK3320(BL)
Q4405
C4415
1000p/50
C4462
3
C4437
R4451
0 0
CH
RN
680
R4459
IC4405
NM
RN
330
R4481 R4483 (2/2) D44
RN R 4 4 3 0 6 RN
5
LA LA LA 8 R4445 R4463
7
2:11D C4401 C4403 C4408 1.2k
CH1_R_out R4431
4 220 0
RN 5
NM NM NM 1.2k NJM4580MD
100p/50
R4404
R4412
C4411
CH1_
CH
130k
NM
RN
RN
R 4 4 4 6 RN
R4409
RN
20k
430
C4442
D GNDF GNDF ZL NM
C4426 C4433
100u/25 0.1u/25
2-22 CH1_
GND_PO GND_PO 0
V-15A_IN
V+15A_IN
R4464
C4405
NM
0.1u/25
Timecode Buffer 2-24
GNDD
GND_PO
CH1_TimeCode AD(TTL mode)
R446
6 RN CH1_TIME_L
8 R4401 C4412 (CH1 T)
(CH1 T) 7 V
2:11D V+5A_IN
CH1_TIME_R
R4402
CH1_L_out_time IC4401 12k 10u/50

4
5
2-2
2k
RN
RNB4580F HAT RAB4CQ103J

(1/2) R4432 V+5A_IN
IC4403 1 8 RB706F-40 RB706F-40
V+5A_IN 2-26 1 16 2 7
3
2
3
2
AINR CKS0 1 1
C4407 GNDF 2 15 3 6 D4403 D4404
AINL CKS2
E
0.1u/25 R4423 3
CKS1 DIF
14 4 5 2-28
10k 4 13 R4447
V-15A_IN GND_PO VCOM PDN
10k
0.1u/16
5 12 0 0
DCH1201-A
R4435
V+15A_IN AGND SCLK
C4419
C4420
10u/10
6 11 R4436 0
VA MCLK
2 RN 7 10 R4437 0
8 R4433 C4413
1 VD LRCK
2:11D 8 9 R4438 22
C4421
R4434
CH1_R_out_time
2.2u/10
IC4401 12k 10u/50 DGND SDTO

4
RN
3 RNB4580F HAT
2k
2-31
C4438
0.01u/25
V-15A_IN
(2/2)
AK5358AET 2-30
C4428
2-29
CCG1205-A
0.1u/16
GNDF
GNDA_1T GNDA_1T GNDD GNDA_1T GNDA_1T
A 1/11,5/11,11/11
RESET_IN2
1:11E;5:2G;11:11D
From BOARD IF
LRCLK_IN_CH1
1:11D
BCLK_IN_CH1
F
A 1/11 1:11C
MCLK_IN_CH1
1:11B
TC_SEL1
A 3/11 1:2F
102 DJM-900NXS
1 2 3 4
5 6 7 8

Balanced Direct ADC Driver
NM
CH1_L-
R4460
(CH1 A)
L-
R4452
0 V+5A_IN
RN
330
1SS302
2
3
1 NOTES NM is STBY
R4453
RN
1k
D4405 RS1/10SR***J
GNDA_1
RS1/16SS***J
R4454
V+5A_IN D RS1/10SE****D
RN
1k
1SS302
2 RN RN1/16SE****D
3
1 CKSRYB
R4455
NM
RN
330
D4406 CKSSYB
(CH1 A)
R4461 GNDA_1 L+
CKSYB
B
0 HXS CFHXSQ
CH1_L+
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
(CH1 A)
: CH1 Audio Signal (L CH) C
C4461
CH1_R- (CH1 T)
NM
R4462
2-20 R-
: CH1 Timecode Signal (L CH)
(CH1 D)
: CH1 DIGITAL Signal
R4456
0 V+5A_IN
RN
330
1SS302
2
3
1
R4457
RN
1k
D4407
GNDA_1
R4458
V+5A_IN
RN
1k
1SS302
2
3
1
R4459
NM
RN
330
D4408
R4463 GNDA_1 R+
CH1_R+
2-21
CH1_ADC(CMOS mode)
D
2-22
C4466 Buffer for ADC Driver
0.01u/16
330u/6.3
C4447
C4451
CH1_RESET 0.1u/16
ZL
C4445 5.1 V+15A_IN

0
0.1u/16 R4475 C4456
R4464 IC4406
Audio timecode select
C4443
GNDD 0.1u/25
NM
0.01u/16
100u/10
C4448
C4452
1 RST 24
ZL
FILT+
2-24 2-23
R4472 2 M/S
REFGND
23 GNDA_1 2
IC4407
8
1
GND
_PO
GNDD 0 10k 3 LRCK 22
V+3R3D_IN
VQ
0 4 (1/2)
R4471 4 SCLK 21 3
AINR+ RNB4580F
0.1u/16
R4465 0 R4467 5 MCLK 20 IC4408

C4458
C4449
AINR- 2200p/50 V-15A_IN
6 VD 19 1 8
CH
10u 10V
To BOARD IF
A VCC
C4444
C4446
V+3R3D_IN VA V+5A_IN V+15A_IN

0.1u/16
+5A_IN
GNDA_1
7 GND1
GND2
18
IC4407
2
B ST
7
GNDD A 1/11
2-25 8 VL
AINL-
17 6
8
7
3
Y SELECT
6
R4478
(CH1 D)
100u/10
0 4 5
C4453
C4454
0.1u/16
R4468 DCH1201-A 9 SDOUT 16 C4450

GND Y 1:2F
ZL
AINL+
NM
10k
2200p/50 CH 4 (2/2) 68
10 MDIV 15 5 ADAT_CH1_ANA
OVFL RNB4580F
R4473 11 HPF 14 R4477 0.1u/16 TC7WH157FK
M1 C4457
10k
R4469 12 I2S/LJ 13 10k C4455 GNDD select L Y=A
M0 V+3R3D_IN GNDD 0.1u/25 2-32 (AUDIO) E
10k GNDA_1 GNDD
R4470 R4476
CS5381-KZ select H Y=B
V-15A_IN GND_PO
CH1_ADAT
10k (TIMECODE)
GNDD 22 (CH1 D)
R4474 CH1_ADAT Time
(CH1 D)
2-27
GNDA_1T
A 3/11
DJM-900NXS 103
5 6 7 8
1 2 3 4

V+15A_IN
C4621
CH2
0.1u/25
A C4622
R4625
R4633
R4637
180k
RN
RN
1k
1k
D
100u/25
ZL
180 CD2_L
R4629 6 GND_PO
8
7 C4626 (C2)
C4616
CD
IC4601
R4641
4 33u/16
100k
5 (1/2) NP
4700p/50
NJM4580MD
3 6
5 2 V-15A_IN
(2/2)
Q4606 4 1 (1/2)
Q4606 GNDF
HN1C01FU(YGR)
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
3
D4604
Q4612
C4612
4
RN
(C2) R4612
100
100p/50
100p/50
C4603
C4607
R4620
CH
CH
RN
47k
B INPUT BUFFER
GNDF V+15A_IN
V+15A_IN
R4623
R4631
R4635
CD LINE
180k
RN
RN
1k
1k
D
R4607
4.7k
RN
R L R L IC4601
HN1C01FU(YGR)
R4627 180 NJM4580MD CD2_R

2
8
R4603
5pin 4pin 2pin 1pin 1 (2/2) C4627

18k
RN
R4608
Q 4 6 0 3 (1/2)
Q4601 4.3k
C4614
HN1C01FU(YGR)
4 33u/16
Q 4 6 0 1 (1/2)
3 ZL NP
R4638
6 4700p/50
100k
2 C4624
(2/2)
Q4603
(2/2)
1 (1/2) 6 100u/25
3 6 3 Q4607 2 5 3
(2/2) C4618
5 2 5 HN1C01FU(YGR)
1 4 Q4607
L L 4 1 4
0.1u/25
GNDF
R4609
R4615
R4617
HZU3R0(B1)
V-15A_IN GND_PO
2SK3320(BL)
RN
RN
RN
470
470
470
GNDF
0.47u/6.3
1
D4602
C4610
R R
Q4610
(C2)
V-15A_IN
C
4
GNDF_2 GNDF_2
RN
R4613
100p/50
100p/50
C4604
C4608
R4621
100
CH
CH
RN
47k
V+12D_IN
JA4601
1 GNDF
CD 2
1SS352 1SS352
D4605
3
4 V+15A_IN
LINE 5 R4602 C4619

6
D4606
NM 0.1u/25
DKB1083-A
R4624
R4632
R4636
180k
RN
RN
GND_PO
1k
1k
D
GNDF
LINE2_L 2
R4628 180 6 GND_PO
8 C4625 (L2) 3
7 Q4
C4615 LT
(1/2) 1
R4639
4 33u/16
100k
5 IC4602
4700p/50
D NJM4580MD
3 6
5 2 V-15A_IN
(2/2) 1 Q 4 6 0 8 (1/2) GNDD
Q4608 4 GNDF
HN1C01FU(YGR)
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
3
D4603
C4611
Q4611
5
RN
(L2) R4610
100
100p/50
100p/50
C4601
C4605
R4618
CH
CH
RN
47k
INPUT BUFFER
GNDF V+15A_IN
V+15A_IN
R4622
R4630
R4634
180k
RN
RN
1k
1k
D
R4604
E
4.7k
RN
IC4602
NJM4580MD LINE2_R
HN1C01FU(YGR)
R4626 180 2
HN1C01FU(YGR)
8
R4601
1 (2/2) C4628
18k
R4605
RN
Q 4 6 0 4 (1/2)
Q 4 6 0 4(2/2)
4.3k
C4613
(1/2)
4 33u/16
3 NP
6 4700p/50
100k
R4640
2
Q4602
Q4602
(2/2)
HN1C01FU(YGR)
1 (1/2) 6 3
Q4609
6 Q4609 2 5
3 C4617
5 2 5 3 HN1C01FU(YGR)
1 4
0.1u/25
4 1 4 GNDF
R4606
R4614
R4616
HZU3R0(B1)
V-15A_IN
2SK3320(BL)
RN
RN
RN
470
470
470
GND_PO
0.47u/6.3
1
D4601
C4609
Q4614
V-15A_IN
4
RN
R4611
100p/50
100p/50
C4602
C4606
R4619
100
CH
CH
RN
47k
F
LINE GNDF
A 1/11
A 4/11 From BOARD IF LINE_SEL2
1:2E
104 DJM-900NXS
1 2 3 4
5 6 7 8
D CN8401
V+3R3D_REFA
GNDD_REFA
VR-TRIM2
R_out2
L_out2
GNDA
GNDA
GNDA
GNDA
R_in2
L_in2
V+3R3D_REFA
CN4601 B
10
11
XKP3065-A
9
GNDF GNDD_REFA
C4629
0.1u/16
A 1/11
GNDD_REFA
1:2E
CH2_TRIM To BOARD IF
CH2_R_out
5:2E
CH2_R_out

CH2_L_out
Time code Trim pass Line To CH2 AD Block C
R4642 5:2G
0
R4643 5:2F
CH2_R_out_time
A 5/11
CH2_L_out_time
0
(CH2 T)
V+12D_IN
L_audio line
10 10
6
9
7
9
VSR1008-A
1SS352 1SS352
RY4601
D4605
RELAY
D4606
5 5
1 1
2 2
3 3
4 4
2
3 R_audio line
Q4613
LTC124EUB
1
D
GNDD
(C2)
: CH2 CD Signal (L CH)
(L2)
: CH2 LINE Signal (L CH)
(CH2 A)
NOTES NM is STBY
(CH2 T)
RS1/10SR***J
: CH2 Timecode Signal (L CH) RS1/16SS***J
D RS1/10SE****D
RN RN1/16SE****D
E
CKSRYB
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
A 4/11
DJM-900NXS 105
5 6 7 8
1 2 3 4

V+15A_IN
ZL
Intermediate Buffer C4829
Balanced Direct AD
A 100u/25
CH2 INPUT AD
CD / LINE
V+15A_IN
C4823
C4830
0.1u/25
0.1u/25
C4824 GND_PO
R4822
R4816
R4820
330k
RN
RN
2k
2k
D
6 8 0 RN
22u/50
C4834
CH
1000p/50
C4806
ZL
R4848
NM
R4818 180 2 GND_PO (CH2 A) IC4804
CH2_L-
8
RN R 4 8 2 4 6
8
RN
7 R4839 R4860
C4818 1
R4825 1.2k
4
R4852
3 IC4802 220 0
4700p/50 4 (1/2)
RN
330
NJM4580MD RN 1 . 2 k 5
NJM4580MD RN 1SS30
(2/2) R4840
6 3
3 5 2 V-15A_IN
R4853
(2/2) (1/2) 430
RN
1k
Q4803 4 1 Q4803 C4839 D4805
HN1C01FU(YGR) V-15A_IN
NM
HZU3R0(B1)
R4854
2SK3320(BL)
RN
1k
0.47u/6.3
V+15A_IN 1SS30
680
D4802
GNDF
C4816
Q4806
NM
1000p/50
3
C4835
R4849
C4810
0 0
RN
R4855
RN
330
CH
R4880 R4882 IC4804
R4826 RN D4806
RN 2
B
5
(CH2 A) LA LA LA 8 R4841 R4861
1
4:11D C4802 C4804 C4809 1.2k
CH2_L_out R4827
RN 1 . 2 k 4 (2/2) 220 0
NM NM NM 3
100p/50 NJM4580MD
R4805
C4814
CH2_L+
R4814
CH
R 4 8 4 2 RN
R4810
130k
RN
NM
RN
RN
20k
430
C4840
GNDF NM
GNDF C4831
0.1u/25
V-15A_IN GND_PO
V+15A_IN
R4807 R4806
V+15A_IN
4.7k
RN
C4832
HN1C01FU(YGR)
HN1C01FU(YGR)
V+15A_IN
R4803
18k
0.1u/25
RN
(1/2)
Q 4 8 0 2 (1/2)
Q4801 4.3k
GND_PO
R4821
R4815
R4819
6 2
330k
RN
RN
Q4802
2k
6 8 0 RN
2k
D
Q4801
(2/2)
IC4802
C
1000p/50
(2/2)
C4836
R4850
C4827
NJM4580MD
NM
CH
3 CH2_R-
5 3 R4817 180 (1/2)
2 6 5 6
8
IC4805
7 R4828 2 RN
RN 8 R4843 R4862
4 1 4 C4817 1
1.2k
4 R4829
R4856
5
4 (1/2)
R4808
R4811
R4813
220 0
RN
4700p/50
330
RN 1 . 2 k
RN
RN
RN
470
470
470
3 1SS30
C 4 8 2 5 ZL NJM4580MD
6 R4844
(1/2) 3 (2/2) 22u/50 3
Q4804 2 5 Q4804
C4822 RN
R4857
HN1C01FU(YGR) 430
RN
4
1k
V-15A_IN 1 D4807
0.1u/25 V-15A_IN C4841
From CH2 INPUT
NM
V-15A_IN GND_PO
HZU3R0(B1)
A 4/11
R4858
RN
1k
1SS30
2SK3320(BL)
0.47u/6.3
0 0 V+15A_IN
680
1
3
D4801
GNDF
C4815
1000p/50
C4859
3
Q4805
C4837
R4851
CH
RN
R4881 R4883
R4859
NM
RN
330
IC4805
D4808
RN R 4 8 3 0 6
8
RN
LA LA LA
5
7 R4845 R4863
4:11C C4801 C4803 C4808 1.2k
CH2_R_out R4831
RN 4 (2/2) 220 0
NM NM NM 1.2k 5
NJM4580MD
100p/50
R4804
R4812
C4811
CH2_R+
130k
NM
RN
RN
CH
R 4 8 4 6 RN
R4809
430
RN
20k
C4842
GNDF
D GNDF ZL NM
C4826 C4833
CH2_RE
100u/25 0.1u/25
0
GND_PO V-15A_IN GND_PO
R4864
V+15A_IN
C4843
NM
C4805
0.1u/25
Timecode Buffer GNDD
GND_PO CH2_TimeCode AD(TTL mode)

R4865
6 RN (CH2 T) CH2_TIME_L
8 R4832 C4812
(CH2 T) 7 V+3
4:11D V+5A_IN
CH2_L_out_time IC4801 12k 10u/50 CH2_TIME_R
4
R4833
5 HAT RAB4CQ103J V+5A_IN

RNB4580F
RN
2k
(1/2) R4801 RB706F-40 RB706F-40

IC4803 1 8 2 2
V+5A_IN 3 3
1 16 2 7 1 1
AINR CKS0
C4807 2 15 D4803 D4804
GNDF 3 6
AINL CKS2
0.1u/25 R4823 3 14 4 5
E 10k 4
CKS1 DIF
13 R4847
DCH1201-A
V-15A_IN GND_PO 10k

VCOM PDN
10u/10V
C4819
C4820
0.1u/16
5 12 R4835 0 0
V+15A_IN AGND SCLK
6 11 R4836 0
VA MCLK
2 RN 7 10 R4837 0
8 R4878 C4813
1 VD LRCK
CCG1205-A
4:11D 8 9 R4838 22
C4821
CH2_R_out_time IC4801 12k 10u/50 DGND SDTO

4
R4879
3 RNB4580F HAT
C4838
RN
0.01u/25
2k
(2/2)
V-15A_IN AK5358AET
C4828
0.1u/16
10V
2.2u
GNDF
A 1/11,3/11,11/11
RESET_IN2
1:11E;3:2G;11:11D
From BOARD IF
LRCLK_IN_CH2
1:11D
BCLK_IN_CH2
1:11C
F A 1/11 MCLK_IN_CH2
1:11B
TC_SEL2
A 5/11
1:2F
106 DJM-900NXS
1 2 3 4
5 6 7 8
Balanced Direct ADC Driver A 5/11 INPUT ASSY (DWX3193) A
CH2_L-
(CH2 A)
(CH2 A) L-
R4860
(CH2 T)
R4852
0 V+5A_IN
RN
330
1SS302
2
: CH2 Timecode Signal (L CH)
3 (CH2 D)
1
R4853
RN
1k
D4805
GNDA_2
R4854
V+5A_IN
RN
1k
1SS302 NOTES NM is STBY

2
3
1 RS1/10SR***J
R4855
RN
330
D4806 RS1/16SS***J
L+
R4861 GNDA_2 (CH2 A)
D RS1/10SE****D B
0 RN RN1/16SE****D
CH2_L+ CKSRYB
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
C
CH2_R-
R-
R4862
R4856
0 V+5A_IN
RN
330
1SS302
2
3
1
R4857
RN
1k
D4807
GNDA_2
R4858
V+5A_IN
RN
1k
1SS302
2
3
1
R4859
RN
330
D4808
R4863 GNDA_2 R+
CH2_R+
CH2_ADC(CMOS mode)
Buffer for ADC Driver D
C4866
CH2_RESET
0.01u/16
330u/6.3
C4847
C4851
0.1u/16
ZL
0 SR
C4845 5.1 V+15A_IN
R4864
0.1u/16 R4875 C4856
C4843
IC4806
NM
GNDD 0.1u/25
0.01u/16
100u/10
C4848
C4852
1 RST 24
Audio timecode select
ZL
FILT+
R4872 2 M/S 23 GNDA_2 2
IC4807 GND_PO
R4871 REFGND 8
GNDD 1
0 10k 3 LRCK 22
VQ V+3R3D_IN
0 4 (1/2)
4 SCLK 21 C4849 3
AINR+ RNB4580F
R4867 CH
0.1u/16
R4865 0 5 MCLK 20 IC4808

C4858
AINR-
2200p/50
V-15A_IN
6 VD 19 1 8
To BOARD IF
10u 10V
A VCC
C4844
C4846

A 1/11
0.1u/16
+5A_IN 7 GND1 18 2 7
GND2 B ST
GNDA_2 IC4807
3 6 GNDD
8 VL 17 C4850 6
8 Y SELECT
AINL- CH 7
R4884
(CH2 D) 1:2F
100u/10
4 5
C4853
C4854
0.1u/16
R4868 DCH1201-A 9 SDOUT 16

GND Y
ZL
AINL+
NM
10k 2200p/50 4 (2/2) 68
OVFL RNB4580F
R4873 11 HPF 14 R4877 0.1u/16 TC7WH157FK
M1 C4857
10k
12 I2S/LJ 13
GNDD
R4869 10k C4855
M0 V+3R3D_IN
GNDD 0.1u/25 select L Y=A E
10k
R4876 GNDA_2 GNDD (AUDIO)
R4870
CS5381-KZ select H Y=B
10k V-15A_IN GND_PO (TIMECODE)
CH2_ADAT
GNDD 22
R4874 CH2_ADAT Time (CH2 D)
(CH2 D)
NDA_2T
A 5/11
DJM-900NXS 107
5 6 7 8
1 2 3 4

V+15A_IN
C5021
CH3
0.1u/25
A C5022
R5025
R5033
R5037
180k
RN
RN
1k
1k
D
100u/25
ZL
R5029 180 GND_PO CD3_L
6 IC5001
8 C5026
7
C5016
(1/2)
R5041
4 33u/16 (C3)
100k
CD
5 NP
4700p/50 NJM4580MD
3
5 2 6 V-15A_IN
(2/2)
Q5005
4 1 (1/2)
Q5005 GNDF
HN1C01FU(YGR)
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
3
D5004
C5012
Q5012
5
4
RN
(C3) R5012
100 INPUT BUFFER

100p/50
100p/50
C5003
C5007
R5020
B
CH
CH
RN
47k
GNDF V+15A_IN
V+15A_IN
R5023
R5031
R5035
180k
RN
RN
1k
1k
D
R5008 R5007
HN1C01FU(YGR)
4.7k
RN
R5003
Q 5 0 0 2 (1/2)
IC5001 CD3_R
18k
R5027 180 NJM4580MD

CD LINE 2
8 C5027
1
RN
R L R L
Q5001 4.3k
HN1C01FU(YGR)
C5014 (2/2)
33u/16
Q 5 0 0 1 (1/2)
4 ZL
3 NP
6 4700p/50
100k
C5024
R5038
2
(2/2)
Q5002
(2/2)
1 6 3 100u/25
6 3 (1/2)
Q5006 2 5 (2/2)
3 Q5006 C5018
5 2 5 HN1C01FU(YGR)
1 4
0.1u/25
4 1 4 GNDF
L L
R5009
R5015
R5017
V-15A_IN GND_PO
HZU3R0(B1)
RN
RN
RN
470
470
470
0.47u/6.3
2SK3320(BL)
3
1
GNDF
C
C5010
D5002
Q5010
(C3)
R R V-15A_IN
4
GNDF_3 GNDF_3
RN
R5013
100p/50
100p/50
C5004
C5008
R5021
100
CH
CH
RN
47k
V+15A_IN V+12D_IN
C5019
10 10
JA5001
1 GNDF
0.1u/25
R5024
R5032
R5036
CD
180k
2
RN
RN
1SS352 1SS352
1k
1k
D
RY5001
D5005
3
4
LINE 5 R5002 R5028 180 6

IC5002 GND_PO LINE3_L
8 C5025
6 7
D5006
DKB1083-A NM C5015
1 1
4 (1/2)
R5039
33u/16 (L3)
100k
GND_PO 4700p/50
5
NJM4580MD NP
GNDF
3 6 2
5 2 V-15A_IN
D (2/2)
3
Q5013
Q5007 4 1 (1/2) LTC124
Q5007 GNDF 1
HN1C01FU(YGR)
HZU3R0(B1)
0.47u/6.3
3
2SK3320(BL)
D5003
C5011
Q5011
GNDD
5
RN
(L3) R5010
100
100p/50
100p/50
C5001
C5005
R5018
CH
CH
RN
47k
INPUT BUFFER
GNDF V+15A_IN
V+15A_IN
R5022
R5030
R5034
180k
RN
RN
1k
1k
D
R5005 R5004
4.7k
RN
LINE3_R
E
HN1C01FU(YGR)
R5026 180 IC5002

HN1C01FU(YGR)
2
8
R5001
1 C5028
18k
RN
Q 5 0 0 4 (1/2)
4.3k
C5013
Q 5 0 0 3 (1/2)
4 (2/2) 33u/16
3 NP
R5040
6 4700p/50 NJM4580MD
100k
2
(2/2)
Q5003
(2/2)
1 (1/2) 6 3
Q5004
6 3 Q5008 2 5
3 C5017
5 2 5 HN1C01FU(YGR)
1 4 (2/2)
Q5008 0.1u/25
4 1 4 GNDF
R5006
R5014
R5016
HZU3R0(B1)
V-15A_IN GND_PO
RN
RN
RN
470
470
470
2SK3320(BL)
0.47u/6.3
1
D5001
C5009
Q5009
V-15A_IN
4
RN
R5011
100p/50
100p/50
C5002
C5006
R5019
100
CH
CH
RN
47k
F
LINE GNDF
A 1/11
A 6/11 From BOARD IF LINE_SEL3
1:7E
108 DJM-900NXS
1 2 3 4
5 6 7 8
E CN8601
V+3R3D_REFA
GNDD_REFA
VR-TRIM3
R_out3
L_out3
GNDA
GNDA
GNDA
GNDA
R_in3
L_in3
V+3R3D_REFA
B
CN5001
10
11
1
9
XKP3065-A
GNDF GNDD_REFA
C5029
0.1u/16
GNDD_REFA
A 1/11
1:7F
CH3_TRIM
To BOARD IF
CH3_R_out
7:2E
CH3_R_out
C

CH3_L_out
A 7/11
7:2G
R5042
0
CH3_R_out_time To CH3 AD Block
R5043 7:2F
CH3_L_out_time
0 (CH3 T)
V+12D_IN L_audio line

10 10
6
9
7
9
VSR1008-A
1SS352 1SS352
RY5001
D5005
RELAY
D5006
5 5
1 1
2 2
3 3
4 4
2
R_audio line
3
Q5013 D
LTC124EUB
1
GNDD
(C3)
: CH3 CD Signal (L CH) NOTES NM is STBY
(L3)
: CH3 LINE Signal (L CH) RS1/10SR***J
(CH3 A)
: CH3 Audio Signal (L CH) RS1/16SS***J
(CH3 T) D RS1/10SE****D
E
: CH3 Timecode Signal (L CH) RN RN1/16SE****D
CKSRYB
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
A 6/11
DJM-900NXS 109
5 6 7 8
1 2 3 4

C5229
ZL
Balanced Direct ADC D
A
CH3 INPUT AD
CD / LINE
V+15A_IN
C5223
100u/25
C5230
0.1u/25
0.1u/25
C5224 GND_PO
R5222
R5216
R5220
330k
RN
RN
2k
2k
D
6 8 0 RN
22u/50
1000p/50
C5206
ZL
C5234
R5248
NM
CH
R5218 180 SIDE A 2 GND_PO IC5204 CH3_L-
8
1 RN R 5 2 2 4 6
8
RN
7 R5239 R5260
(CH3 A) R5225 1.2k
C5218 4
R5252
SIDE A 3
NJM4580MD 4 (1/2) 220 0
4700p/50
RN
330
RN 1 . 2 k 5
IC5202 NJM4580MD RN 1SS30
(2/2) R5240
3 6 3
5 2 V-15A_IN
R5253
(2/2) 430
RN
1k
Q5203 4 1 Q5203 D5205
V-15A_IN C5239
HN1C01FU(YGR)
(1/2) NM
HZU3R0(B1)
R5254
RN
1k
0.47u/6.3
V+15A_IN 1SS30
2SK3320(BL)
3
680
0 0
D5202
1000p/50
GNDF
C5216
Q5206
C5210
3
C5235
R5249
RN
R5280 R5292
NM
R5255
CH
RN
330
IC5204
R5226
2 RN D5206
RN
B
5
LA LA LA 8 R5241 R5261
(CH3 A) 1
6:11C C5202 C5204 C5209 1.2k
CH3_L_out R5227
RN 1 . 2 k 4 (2/2) 220 0
NM NM NM 3
NJM4580MD
R5205
100p/50
CH3_L+
C5214
NM
CH
RN
R 5 2 4 2 RN
R5214
130k
RN
R5210
RN
20k
430
C5240
NM
GNDF GNDF C5231
0.1u/25
V-15A_IN GND_PO
V+15A_IN
R5206
V+15A_IN
4.7k
RN
SR
C5232
HN1C01FU(YGR)
R5203
V+15A_IN
18k
0.1u/25
RN
R5207
Q 5 2 0 2 (1/2)
4.3k
GND_PO
HN1C01FU(YGR)
R5221
R5215
R5219
6
D SR
330k
2
RN
(1/2)
RN
Q5202
2k
6 8 0 RN
2k
(2/2)
Q5201
Q5201
NJM4580MD
1000p/50
C
(2/2)
C5236
R5250
C5259
IC5202
NM
CH
3 3
6 R5217 180 6 (1/2) IC5205 CH3_R-
5 2 5 8 R5228
7 2 RN
C5217 RN 8 R5243 R5262
4 1 4 1
1.2k
4 R5229
R5256
5
4 (1/2)
R5208
R5211
R5213
4700p/50 220 0
RN
330
ZL RN 1 . 2 k
RN
RN
RN
470
470
470
3
C5225 NJM4580MD 1SS30
6 R5244
(1/2) 3 22u/50 3
Q5204 2 5
RN
From CH3 INPUT
(2/2) C5222
R5257
HN1C01FU(YGR) 430
RN
1 4 Q5204
1k
V-15A_IN C5241 D5207
0.1u/25 V-15A_IN
NM
GND_PO
HZU3R0(B1)
A 6/11
V-15A_IN
R5258
RN
1
1k
0.47u/6.3
0 0 V+15A_IN 1SS30
Q5205
D5201
GNDF
2SK3320(BL)
C5215
1000p/50
C5227
3
C5237
R5251
NM
CH
RN
R5281 R5293
680
R5259
RN
330
IC5205
D5208
5
RN R 5 2 3 0 6
8
RN
LA LA LA 7 R5245 R5263
6:11C C5201 C5203 C5208 1.2k
CH3_R_out R5231
RN 4 (2/2) 220 0
NM NM NM 1.2k 5
100p/50
NJM4580MD CH3_R+
R5204
R5212
C5211
CH
130k
NM
RN
RN
R 5 2 4 6 RN
R5209
RN
20k
430
C5242 CH3_R
D GNDF GNDF ZL NM
C5226 C5233
0
100u/25 0.1u/25
R5264
GND_PO V-15A_IN GND_PO
C5243
NM
V+15A_IN
C5205
Timecode Buffer 0.1u/25
GNDD
GND_PO
IC5201
6 RN SIDE A R5265
8 R5232 C5212 (CH3 T) CH3_TIME_L
(CH3 T) 7 V+3
6:11D V+5A_IN
SIDE A
R5233
CH3_L_out_time 12k 10u/50

4 (1/2)
RN
5
2k
RNB4580F HAT CH3_TIME_R RAB4CQ103J

R5201 V+5A_IN
RB706F-40 RB706F-40
1 8 2 2
V+5A_IN 3 3
1 16 2 7 1 1
AINR CKS0
C5207 GNDF 2 15 D5203 D5204
3 6
AINL CKS2
0.1u/25 R5223 3 14 4 5
E 10k 4
CKS1 DIF
13 R5247
V-15A_IN GND_PO VCOM PDN
10k
5 12 R5235 0 0
V+15A_IN AGND SCLK
DCH1201-A
6 11 R5236 0
C5219
C5220
10u/10
VA MCLK
0.1u/16
2 IC5201 RN 7 10 0
8 R5237
1 R5278 C5213 VD LRCK
2.2u C C G 1 2 0 5 - A
6:11D 8 9 R5238 22
R5279
C5221
CH3_R_out_time DGND SDTO

4 (2/2) 12k 10u/50
3
RN
RNB4580F HAT
2k
0.01u/25
C5238
IC5203
V-15A_IN
AK5358AET C5228
10V
0.1u/16
GNDF
A 1/11,9/11,11/11
RESET_IN1
1:10D;9:2H;10:10D
From BOARD IF
LRCLK_IN_CH3
1:10D
BCLK_IN_CH3
1:10C
1:10B
TC_SEL3
A 7/11
1:7E
110 DJM-900NXS
1 2 3 4
5 6 7 8
lanced Direct ADC Driver A 7/11 INPUT ASSY (DWX3193) A

NM
CH3_L-
R5260 (CH3 A) L- (CH3 A)

R5252
0 V+5A_IN
RN
330
(CH3 T)
1SS302
3
2 : CH3 Timecode Signal (L CH)
1 (CH3 D)
R5253

RN
1k
D5205
GNDA_3
R5254
V+5A_IN NOTES NM is STBY

RN
1k
1SS302
2
3 RS1/10SR***J
1
R5255
RS1/16SS***J
RN
330
D5206 L+ D RS1/10SE****D
(CH3 A)
R5261 GNDA_3 B
RN RN1/16SE****D
0
CKSRYB
CH3_L+
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
C
CH3_R-
R-
R5262
R5256
0 V+5A_IN
RN
330
1SS302
2
3
1
R5257
RN
1k
D5207
GNDA_3
R5258
V+5A_IN
RN
1k
1SS302
2
3
1
R5259
RN
330
D5208
R5263 GNDA_3 R+
0
CH3_R+
CH3_ADC(CMOS mode)
CH3_RESET
Buffer for ADC Driver D
C5266
0
0.01u/16
330u/6.3
C5247
C5251
0.1u/16
ZL
R5264 R5275
C5245 5.1 V+15A_IN
C5243
C5256
NM
0.1u/16
IC5206
GNDD 0.1u/25 Audio timecode select
0.01u/16
100u/10
C5248
C5252
1 RST 24
ZL
FILT+
R5272 2 M/S 23 GNDA_3 2
IC5207 GND_PO
REFGND 8
1
GNDD 0 10k 3 LRCK 22
VQ V+3R3D_IN
0 4 (1/2)
R5271 4 SCLK 21 3
AINR+ RNB4580F
0.1u/16
0 R5267 5 MCLK 20 IC5208

C5258
C5249
AINR- 2200p/50 V-15A_IN
R5265 6 19 CH 1 8
VD
10u 10V
A VCC
To BOARD IF
C5244
C5246

A 1/11
0.1u/16
+5A_IN 7 18 2 7
GND1 B ST
GND2 IC5207 GNDD
GNDA_3 8 VL 17 6 3 6
8 Y SELECT (CH2 D) 1:7E
AINL- 7
DCH1201-A R5282
100u/10
4 5
C5253
C5254
0.1u/16
9 SDOUT 16 C5250 GND Y

N MR 5 2 6 8
ZL
AINL+
10k 2200p/50 4 (2/2) 68
OVFL CH RNB4580F
R5273 11 HPF 14 R5277 0.1u/16 TC7WH157FK
M1 C5257
10k
12 I2S/LJ 13
GNDD
R5269 10k C5255
M0 V+3R3D_IN
GNDD 0.1u/25
select L Y=A
E
10k GNDA_3 GNDD
R5276
R5270 (AUDIO)
CS5381-KZ
V-15A_IN GND_PO
10k select H Y=B
CH3_ADAT
GNDD 22 (TIMECODE)
(CH3 D)
NDA_3T
A 7/11
DJM-900NXS 111
5 6 7 8
1 2 3 4

V+15A_IN
A C5425
CH4
R5435
R5438
0.1u/25
RN
RN
C5426
2k
2k
CH 100u/25
C5420 ZL
330p/50 GND_PO PHONO4_L
R5429 IC5401
47 6 (P4)
8 C5430
7
PHONO
C5416
4 (1/2) 33u/16
0.022u/50 5 NP
R5443
NJM4580MD
100k
R5425
2SK3320(BL)
V-15A_IN
1.2k
Q5410
GNDF
RN
(P4) R5417
4
C5422
C5418
470p/50
100
220p/50
330p/50
C5406
C5408
R5421
HXS
CH
CH
RN
47k
0.01u/16
R5431 R5441
D
75 7.5k
GNDP4 GNDP4GNDP4
470u/6.3
B
C5413
HAT
INPUT BUFFER
V+15A_IN
GNDP4
V+15A_IN
R5410 R5409
HN1C01FU(YGR)
2.2k
R5403
18k
R5434
R5437
HN1C01FU(YGR)
Q 5 4 0 3 (1/2)
RN
RN 2 k
2k
Q5402 2.2k
Q 5 4 0 2 (1/2)
6 2 CH
(2/2)
Q5403
C5419 IC5401
330p/50
(2/2)
1 R5428 47
NJM4580MD PHONO4_R
6 3 2 C5429
8
3 1
5 2 5 C5415
(2/2)
PHONO LINE 4 1 4 0.022u/50 3
4 33u/16
NP
R5442
100k
R L R L C 5 4 2 8 ZL
R5411
R5415
R5419
R5424
(P4)
RN
RN
RN
470
470
470
2SK3320(BL)
100u/25
1.2k C5424
3
1
V-15A_IN Q5409 0.1u/25
GNDF
RN
C L L R5416
V-15A_IN GND_PO
4
C5421
C5417
470p/50
100
220p/50
330p/50
C5405
C5407
R5420
GNDF HXS
CH
CH
RN
47k
0.01u/16
R R R5430 R5440
D
75 7.5k
GNDP4 GNDP4GNDP4
470u/6.3
C5411
HAT
GNDP GNDF_4
JA5401
1 GNDP4
LINE 2 V+15A_IN
3
4 C5423 V+12D_IN
PHONO 5
R5422
R5432
R5436
R5405 0.1u/25
180k
6
RN
RN
1k
1k
D
DKB1083-A NM
1SS352 1SS352
LINE4_L
RY5401
D5403
GNDP4 GNDF GND_PO R5426 180 IC5402 GND_PO
6
8 C5431
7
C5412
4
(1/2) 33u/16 (L4)
D5404
5 NP
RN NJM4580MD
R5444
4700p/50
D (L4) (L4)
100k
R5404
3 6
5 V-15A_IN
100 (2/2) 2
100p/50
100p/50
C5402
C5404
R5414
Q5405 2
1 (1/2)
CH
CH
RN
47k
4 Q5405 GNDF
HN1C01FU(YGR) 3 Q5411
LTC124
1
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
3
D5401
C5409
Q5407
GNDF
GNDD
5
V+15A_IN INPUT BUFFER

R5407 R5406
V+15A_IN
4.7k
RN
R5401
HN1C01FU(YGR)
18k
HN1C01FU(YGR)
R5423
R5433
R5439
RN
Q 5 4 0 4 (1/2)
180k
4.3k
Q 5 4 0 4 (2/2)
RN
RN
1k
1k
D
Q 5 4 0 1 (1/2)
6
2 LINE4_R
IC5402
Q5401
R5427 180
(2/2)
2
8
E 1
6 3 1 C5432
3 C5414
5 2 5 4
(2/2) 33u/16
3 NP
NJM4580MD
R5445
4700p/50
100k
4 1 4
6
R5408
R5413
R5418
(1/2) 3
RN
RN
RN
2 5
470
470
470
Q5406 (2/2) C5427

HN1C01FU(YGR) Q5406
1 4
0.1u/25
GNDF
V-15A_IN V-15A_IN GND_PO
HZU3R0(B1)
2SK3320(BL)
0.47u/6.3
1
C5410
D5402
Q5408
4
RN
R5402
100
100p/50
100p/50
C5401
C5403
R5412
CH
CH
RN
47k
F
LINE GNDF
A 1/11
LINE_SEL4
A 8/11 From BOARD IF 1:7F
112 DJM-900NXS
1 2 3 4
5 6 7 8
F CN8801
V+3R3D_REFA
B
1 1 GNDD_REFA
1 0 VR-TRIM4
R_out4
L_out4
GNDA
GNDA
GNDA
GNDA
V+3R3D_REFA
R_in4
L_in4
CN5401
1
9
XKP3065-A
GNDF GNDD_REFA
C5433
0.1u/16
A 1/11
GNDD_REFA
1:7F
CH4_TRIM To BOARD IF C
CH4_R_out 9:2E
CH4_R_out

CH4_L_out A 9/11
R5446 9:2G
CH4_R_out_time
To CH4 AD Block
0
R5447 9:2F
CH4_L_out_time
0
(CH4 T)
V+12D_IN L_audio line

10 10
6
9
7
9
VSR1008-A
1SS352 1SS352
RY5401
D5403
RELAY
D5404
D
5 5
1 1
2 2
3 3
4 4
2
R_audio line
3 Q5411
LTC124EUB
1
GNDD
(P4)
: CH4 PHONO Signal (L CH) NOTES NM is STBY
(L4)
: CH4 LINE Signal (L CH) RS1/10SR***J
E
(CH4 A)
: CH4 Audio Signal (L CH) RS1/16SS***J
(CH4 T) D RS1/10SE****D
: CH4 Timecode Signal (L CH) RN RN1/16SE****D
CKSRYB
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL F
A 8/11
DJM-900NXS 113
5 6 7 8
1 2 3 4
A INPUT CH4 AD C5629

ZL
Balanced Direct ADC
100u/25
PHONO / CD C5630
V+15A_IN
C5623 0.1u/25
0.1u/25
C5624 GND_PO
R5622
R5616
R5620
330k
RN
RN
2k
2k
D
6 8 0 RN
22u/50
1000p/50
C5606
CH
ZL
C5634
R5648
GND_PO
NM
R5618 180 2 IC5604
8 NJM4580MD CH4_L-
RN R 5 6 2 4 6 8
RN
7 R5639 R5660
C5618 1
3 R5625 1.2k
4 (CH4 A) (1/2)
R5652
IC5602 4 220 0
4700p/50
RN
330
RN 1 . 2 k 5
(2/2) NJM4580MD RN 1SS3
R5640
3 6 3
5 2 V-15A_IN
R5653
(2/2) (1/2) 430
RN
1 Q5603
1k
Q5603 4 C5639 D560
HN1C01FU(YGR) V-15A_IN
NM
HZU3R0(B1)
R5654
RN
0 0
2SK3320(BL)
1k
0.47u/6.3
V+15A_IN 1SS3
680
D5602
1000p/50
GNDF
C5616
C5610
Q5606
C5635
R5680 R5682 3
R5649
RN
R5655
NM
B
CH
RN
330
IC5604
R5626 RN D560
RN 2
5
LA LA LA 8 R5641 R5661
(CH4 A) 1
8:11D C5602 C5604 C5609 1.2k
CH4_L_out R5627
3 4 (2/2) 220 0
C 5 6 1 4 CH
RN 1 . 2 k
NM NM NM NJM4580MD CH4_L+
R5605
100p/50
R 5 6 4 2 RN
R5614
130k
NM
RN
RN
R5610
RN
20k
430
STBY C5640
NM
GNDF GNDF C5631
0.1u/25
V-15A_IN GND_PO
V+15A_IN
R5607 R5606
V+15A_IN
4.7k
RN
R5603
18k
HN1C01FU(YGR)
C5632
V+15A_IN
HN1C01FU(YGR)
0.1u/25
RN
Q 5 6 0 2 (1/2)
Q5601 4.3k
Q 5 6 0 1 (1/2)
GND_PO
R5621
R5615
R5619
6
330k
C 2
RN
RN
(2/2)
2k
6 8 0 RN
2k
D
(1/2)
Q5602
1000p/50
C5627
1 IC5602
C5636
R5650
(2/2)
6 3
NM
CH
NJM4580MD
3 R5617 180 6 IC5605 CH4_R-
5 2 5 8 R5628
7 2 RN
RN 8 R5643 R5662
4 1 C5617 1
4 1.2k
4 R5629
R5656
5
4 (1/2)
R5608
R5611
R5613
220 0
RN
4700p/50
330
RN 1 . 2 k
RN
RN
RN
470
470
470
3
C 5 6 2 5 ZL NJM4580MD 1SS3
6 R5644
(1/2) 3 22u/50 3
Q5604 2 5
From CH4 INPUT
C5622 RN
R5657
HN1C01FU(YGR) 430
RN
1 4 (2/2)
1k
V-15A_IN C5641 D560
Q5604 0.1u/25 V-15A_IN
A 8/11
NM
V-15A_IN GND_PO
HZU3R0(B1)
R5658
RN
0.47u/6.3
1k
V+15A_IN 1SS3
2SK3320(BL)
680
1
3
C5615
D5601
0 0 GNDF
1000p/50
C5659
C5637
CH
3
Q5605
R5651
RN
NM
R5659
R5681 R5683
RN
330
IC5605
D560
LA LA LA RN R 5 6 3 0 6
8
RN
CH
7 R5645 R5663
8:11D C5601 C5603 C5608 1.2k
CH4_R_out R5631
RN 5 4 (2/2) 220 0
NM NM NM 1.2k NJM4580MD CH4_R+
100p/50
R5604
R5612
C5611
130k
NM
RN
RN
R 5 6 4 6 RN
R5609
RN
20k
430
D GNDF
C5642
CH4_
GNDF ZL NM
C5626 C5633
100u/25 0.1u/25 0
GND_PO V-15A_IN GND_PO R5664
C5643
V+15A_IN
NM
C5605
Timecode Buffer 0.1u/25
GNDD
GND_PO
IC5601
6 RN R5665
8 R5632 C5612 (CH4 T)
(CH4 T) 7 CH4_TIME_L V+
8:11D V+5A_IN
R5633
CH4_L_out_time CH4_TIME_R
4 (1/2) 12k 10u/50
RN
5
2k
RNB4580F HAT RAB4CQ103J

R 5 6 0 1 V+5A_IN RB706F-40 RB706F-40
IC5603 1 8 2 2
V+5A_IN 3 3
1 16 2 7 1 1
AINR CKS0
C5607 GNDF 2 15 D5603 D5604
3 6
AINL CKS2
E 0.1u/25 R5623 3 14 4 5
CKS1 DIF
10k 4 13 R5647
V-15A_IN GND_PO 10k
VCOM PDN
5 12 R5635 0 0
V+15A_IN AGND SCLK
6 11
DCH1201-A
R5636 0
VA MCLK
IC5601
C5619
C5620
RN
0.1u/16
2 7 10
10u/10
8 R5637 0
1 R5678 C5613 VD LRCK
2.2u C C G 1 2 0 5 - A
8:11D 8 9 R5638 22
R5679
C5621
CH4_R_out_time DGND SDTO

4 (2/2) 12k 10u/50
3
2k
RN
RNB4580F HAT
0.01u/25
C5638
V-15A_IN AK5358AET
C5628
0.1u/16
GNDF
10V

A 1/11,7/11,10/11
RESET_IN1
1:10D;7:2G;10:10D
From BOARD IF
LRCLK_IN_CH4
1:10D
BCLK_IN_CH4
1:10C
1:10B
TC_SEL4
A 9/11 1:7F
114 DJM-900NXS
1 2 3 4
5 6 7 8
alanced Direct ADC Driver A 9/11 INPUT ASSY (DWX3193) A

NM
CH4_L-
R5660 (CH4 A) L- (CH4 A)
R5652
0 V+5A_IN
(CH4 T)
RN
330
1SS302
3
2 : CH4 Timecode Signal (L CH)
1 (CH4 D)
R5653
RN
1k
D5605
GNDA_4
R5654
V+5A_IN
RN
NOTES NM is STBY
1k
1SS302
2
3
1 RS1/10SR***J
R5655
RS1/16SS***J
B
RN
330
D5606 L+
R5661 GNDA_4 (CH4 A) D RS1/10SE****D
RN RN1/16SE****D
0
CKSRYB
CH4_L+
CKSSYB
CKSYB
HXS CFHXSQ
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
C
NM
CH4_R-
R-
R5662
R5656
0 V+5A_IN
RN
330
1SS302
2
3
1
R5657
RN
1k
D5607
GNDA_4
R5658
V+5A_IN
RN
1k
1SS302
2
3
1
R5659
RN
330
D5608
R5663 GNDA_4 R+
0
CH4_R+
CH4_ADC(CMOS mode) D
CH4_RESET Buffer for ADC Driver
C5666
0.01u/16
330u/6.3
C5647
C5651
0
ZL
0.1u/16
C5645 5.1 V+15A_IN
R5664
C5656
C5643
0.1u/16 R5675
NM
IC5606
GNDD 0.1u/25 Audio timecode select
0.01u/16
100u/10
C5648
C5652
1 RST 24
ZL
FILT+
R5672 2 M/S 23 GNDA_4 2
IC5607 GND_PO
GNDD REFGND 8
1
0 10k 3 LRCK 22
VQ V+3R3D_IN
0 4 (1/2)
R5671 4 SCLK 21 3
AINR+ RNB4580F
0.1u/16
0 R5667 5 MCLK 20 C5649 IC5608

CH V-15A_IN
C5658
AINR-
R5665 6 VD 19
2200p/50 1 8
A 1/11
10u 10V
To BOARD IF
A VCC
C5644
C5646

0.1u/16
V+5A_IN 7 GND1 18 2 7
GND2 B ST
GNDA_4 8 VL 17 6
IC5607
3 6 GNDD
8 Y SELECT (CH4 D) 1:7F
0 AINL- 7
R5684
100u/10
4 5
C5653
C5654
0.1u/16
9 SDOUT 16 C 5 6 5 0 CH
R5668 DCH1201-A GND Y
ZL
AINL+
NM
10k 2200p/50 4 (2/2) 68
OVFL
RNB4580F
R5673 11 HPF 14 R5677 0.1u/16 TC7WH157FK
M1 C5657
10k
R5669 12 I2S/LJ 13 10k C5655
GNDD E
M0 V+3R3D_IN 0.1u/25
10k
GNDD select L Y=A
R5670 R5676 GNDA_4 GNDD
CS5381-KZ (AUDIO)
10k V-15A_IN GND_PO
select H Y=B
GNDD 22 CH4_ADAT
(TIMECODE)
(CH4 D)
GNDA_4T
A 9/11
DJM-900NXS 115
5 6 7 8
1 2 3 4
10.10 INPUT ASSY (10/11)
RETURN
INPUT Buffer
B V+15A_IN
C5807
47u/25
C5808
0.01u/25
GND_PO
IC5801
6 (RET A)
GNDF JA5801 5 (RET A) 8
7 C5811 V+5A_IN
R5802 R5804 R5806
4 V+3R3D_IN
4 (1/2) 10u/50
L 2
10V D C H 1 2 0 1 - A
5
100p/50
100 36k 0 HAT

C5801
3 RNB4580F
CH
RN
1000p/50
7
C5803
C5813
C5815
C5809
R5808
8
CH
15k
1 C5805
XKB3066-A 0.01u/25
GNDF NM
C5810
R5810
GNDF
NM
10u
0
RETURN
47u/25
R5812
V-15A_IN
GND_PO
DCH1201-A
GNDF
1000p/50
C
C5804
R5809
D5801
R5801
C5814
C5816
CH
V+15A_IN
NM
15k
NM
GNDF IC5801
2
GND_PO 8 C5812
JA5802 GNDF R5803 R5805 R5807
1
DKN1614-A 2 (2/2)
10V
10u/50
10u
R 3
1 100 36k 0 3
4
RNB4580F HAT
100p/50
RN
C5802
CH
V-15A_IN
C5806
GNDF
NM
GNDF
Pull up & ESD Main side
A 10/11
116 DJM-900NXS
1 2 3 4
5 6 7 8
RETURN_L
(RET A) 2-33
V+5A_IN
RETURN_R
RAB4CQ103J
R5820 RB706F-40 RB706F-40
V+5A_IN
2-34 IC5802 1 8 2 2
3 3
V+3R3D_IN 1 16 2 7 1 1
AINR CKS0
D5802 D5803
10V D C H 1 2 0 1 - A
2 15 3 6
R5811
AINL CKS2
A 1/11,7/11,9/11
C5813
C5815
0.1u/16
3 14 5
CKS1 DIF
4
2-35 R5819 RESET_IN1
10k 4 13 10k
VCOM PDN 1:10D;7:2G;9:2H
5 12 R5815 0 0
R5810
BCLK_IN_RE
AGND SCLK
NM
1:10C
From BOARD IF Block
10u
0
6 11 R5816 0 MCLK_IN_RE
VA MCLK 1:10B
R5812
7
VD LRCK
10 R5817 0 LRCLK_IN_RE
1:10C A 1/11
DCH1201-A
10V D C H 1 2 0 1 - A
8 9 R5818 22 C
D5801
0.1u/16
C5814
C5816
C5817
C5818
DGND SDTO
0.1u/16
NM
C5819
2-37
C5821
0.01u/16
NM
AK5358AET
2-36 2-38 C5820
10V
10u
10u
0.1u/16
GNDF GNDF GNDD GNDF GNDF
RETURN_ADC
1:7F
ADAT_RETURN_ANA To BOARD IF Block
(RET D)
1:7F
RETURN_IN
A 1/11
: Waveform measuring point NOTES NM is STBY
(RET A)
RS1/10SR***J
: RETURN Audio Signal (L CH) RS1/16SS***J
(RET D)
: RETURN DIGITAL Signal D RS1/10SE****D
RN RN1/16SE****D
CKSRYB
CKSSYB
CKSYB
HXS CFHXSQ E
CH CCSRCH
CCSSCH
LA CFTLA
+
JQ CEJQ
NP CEANP
CEAT
HAT CEHAT
ZL CEHAZL
A 10/11
DJM-900NXS 117
5 6 7 8
1 2 3 4
10.11 INPUT ASSY (11/11)
A
MIC/MIDI V+15A_IN
MIC1 AMP C
C
V+15A_IN
0.1
C6222
0.1u/25
2-40
0.01u/25
330p/50
R6220
R6222
RN 1 5 0
R6224
C6219
C6220
RN
RN
1.5k
1.5k
(2/2)
2-39 MIC1 LEVEL
IC6201 GNDF
6 JQ NP
8 C6224
7 6
8
NJM4580MD 1 0 u / 3 5 (MIC1 A)
4
5 4
C6223 5
(2/
R6231
RN
390
IC6
DCS1072-A
2
3
5
6
1 1 0.1u/25
B CKS3561-A MIC_COLD_1
VR6202
(MIC1 A) Q6202 Q6203 N
CN6201 R6209
2 3 2SK209(BL) 2SK209(BL) 3 2
V-15A_IN
0 GNDF
CN9001
CH
MIC1_COLD 6
4
C6216 CH
C6221 GNDF
D6208
C6205
C6209
R6214
C6203
MIC1_COLD 5 C
NM
NM
NM
NM
CH
CH
RN
10k
470p/50
GNDA 4 470p/50
0.1
RN RN RN GNDF
GNDA 3 R6218 R6221 R6227
MIC1_HOT 2 MIC1 TRIM C
4.7k 330 4.7k
B
MIC1_HOT 1 GNDF
470p/50
C6206
C6210
R6215
C6214
R6219
R6223
C6204
NM
NM
NM
CH
CH
RN
RN
RN
4.7k
4.7k
10k
D6212
NM
V-15A_IN
R6210
0
(MIC1 A)
MIC_HOT_1
V-15A_IN
MIC2 A
V+15A_IN
MIC2 AMP
C
R6250
R6252
V+15
RN
RN
V+15A_IN
1.5k
1.5k
CH
2-42 MIC2 LEVEL
330p 2
8
IC6201 JQ NP
C6218
2-43 (1
1
IC
C6241 2
8
4 (1/2) 10u/35 (MIC2 A)
Q6204 3
JA6201 NJM4580MD
R6225
LSC4081UB(QRS)
100k
VTF1093-A JQ 4
DKN1614-A (MIC2 A) 3
MIC2 2
L6201 C6207 R6204 (MIC2 A)
3
2 V-15A_IN N
RN
390
DCS1072-A
R6228
3
5
2
3
6
VR6201
10u/35 100 1
1 RN
2
GNDF
R6211
3 V-15A_IN
1000p/50
C6202
Q6205
D6213
GNDF
10k
C6201
RN
CH
NM
4
1000p
LSC4081UB(QRS)
CH
3.9k 1
R6213 R6216 GNDF
4.7k
RN
C6211 R6253 GNDF
C6213
100p 330 MIC2 TRIM
GNDA_MI CH RN 100p/50
R6249
R6251
CH
4.7k
4.7k
RN
RN
R6254
C6215
R6212
D
CH
10k
1000p
NM R6201
NM
GNDF GNDF
GND_PO JQ
GNDF C6212 R6207
R6255
V-15A_IN
10u/35 100
0 RN
GNDF GNDF
MIDI OUT JA6202 V+5D_IN

DKN1188-A
7 6
GNDD GNDD V+3R3D_IN
R6208
3 1
0
R6202 R6205 C6208

5 4
0 220 0.01u
2
GNDD IC6202
R6226
C6217
10k
MIDI_TxD
0.1u/16
5 1
VCC NC
GNDD 2
INA
E MIDI_OUT
R6203 R6206
4
OUTY GND
3
0 220 2 GNDD
TC7S04FU
V+5D_IN V+5D_IN Q6201 3
LTC124EUB GNDD
2 2 1
3 3
1 1 GNDD
1SS302 1SS302
D6201 D6202
GNDD GNDD
DNH2736-A / SHIELD CASE(MIDI)
F
GNDD GNDD
A 11/11
118 DJM-900NXS
1 2 3 4
5 6 7 8

V+15A_IN
MIC1 ADC Driver

C6244
NM
GND_PO
NOTES is STBY
C6240 : Waveform measuring point NM
0.1u/25 (MIC1 A) RS1/10SR***J

: MIC1 Audio Signal RS1/16SS***J
GNDF (MIC2 A) D RS1/10SE****D
2-40 RN : MIC2 Audio Signal RN RN1/16SE****D
R6232
(MIC D)
LEVEL
390 MIC1 ADC IN : MIC DIGITAL Signal CKSRYB
6
8
RN
R6233
JQ
C6226
2-41 CKSSYB
7
CKSYB
4 220 10u/35 (MIC1 A)
5 HXS CFHXSQ
(2/2)
R6231
RN
390
IC6203 CH CCSRCH
2
3
5
6
NJM4580MD
CCSSCH B
LA CFTLA
+
1
JQ CEJQ
GNDF C 6 2 3 8 GNDF
NP CEANP
0.1u/25
GNDF CEAT
GNDF CEHAT
1 TRIM C6245 HAT
NM ZL CEHAZL
GND_PO
V-15A_IN
RAB4CQ103J
MIC2 ADC Driver R6217
1 8
MIC_ADC 2
3
7
6
C6242
C
V+15A_IN 4 5
RN
R6229 0.1u/25
10k
2-43 MIC2 ADC IN GNDD GNDF
2
(1/2) 390
I C 6 2 0 3 RN JQ 2-44
IC6204
2-45 A 1/11,3/11,5/11
8 R6230 C6225 (MIC2 A) R6248 0
1 1 16 RESET_IN2
AINR CKS0
1:11E;3:2G;5:2G
C6233
220 10u/35 (MIC1 A) 2 15
0.01u/25
3
4 (MIC2 A) AINL CKS2
NJM4580MD V+3R3D_IN V+5A_IN R6239 3 14
RN
390
R6228
V+5A_IN V+5A_IN CKS1 DIF

5
2
3
From To BOARD IF Block

10k 4 13
GNDD
RB706F-40
RB706F-40
VCOM PDN
3
3
D6209
D6210
R6237
R6236
5 12 R6243 BCLK_IN_MI
NM
V-15A_IN AGND SCLK 1:11C

0
6 11 0
1
1
2
R6244
1
VA MCLK MCLK_IN_MI
GNDF 0 1:11B
7 10 R6245
VD LRCK LRCLK_IN_MI
8 9 0 1:11D
R6246
100u/10
ADAT_MIC_ANA
C6243
D6211
C6227
C6228
C6229
C6230
C6231
C6232
DGND SDTO
0.1u/16
0.1u/16
0.1u/16
HAT
GNDF
NM
GNDF GNDF 22 1:2F

(MIC D)
C2 TRIM AK5358AET 2-47
2-48 ADAT_MIC_ANA
2-46 A 1/11
10u 10V
10u 10V
DCH1201-A
DCH1201-A
DCH1201-A
1 0 u 1 0V
GNDF D
A 1/11
MIDI_TXD
1:2F E
A 11/11
DJM-900NXS 119
5 6 7 8
1 2 3 4
10.12 MIC1 and TRM1 to TRM4 ASSYS
A
MIC MIC SHIELD:DNF1849 B MIC1 ASSY (DWX3207) NOTE
JA9001 C
CKS3533-A LA
1 CN9001
RN RN
CN6201
2 R9001 R9003 R
1 MIC1_HOT
3 100 100
2 MIC1_HOT
4
3 GNDA
5
A 11/11
RN RN 4 GNDA
6 R9002 R9004
5 MIC1_COLD
D9002 D9001
7 D9004 D9003 100 100

6 MIC1_COLD
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
0.01u/50
0.01u/50
C9007
LA C 9 0 0 1
LA C 9 0 0 2
CH C 9 0 0 3
CH C 9 0 0 4
C9005
CH C 9 0 0 6
CH C 9 0 0 8
1000p/50
B
CH
CH
DKB1108-A
UDZS15(B)
UDZS15(B)
GNDA UDZS15(B)
UDZS15(B)
NOT
C
C TRM1 ASSY (DWX3203) D TRM2 ASSY (DWX3204)
TRIM VR TRIM VR
VR8201 VR8401
DCS1119-A DCS1119-A
3 3
2 2
6 6
5 5
9 9
8 8
D
147 147
C8201 C8401
0.1u 0.1u
Rch
Rch
Lch
Lch
E
XKP3076-A
XKP3076-A
CN8201
CN8401
10
GNDREF 1 1
10
GNDREF 1 1
1
GNDA 2
GNDA 4
GNDA 6
GNDA 8
1
GNDA 2
GNDA 4
GNDA 6
GNDA 8
9
V+3R3REF
V+3R3REF
VR_TRIM3
VR_TRIM3
L_out
L_out
R_out
R_out
R_in
R_in
L_in
L_in
A 2/11 CN4201 A 4/11 CN4601

F
B C D
120 DJM-900NXS
1 2 3 4
5 6 7 8
NOTES NM is STBY A
CH CCSRCH
LA CFTLA
RN RN1/16SE****D
NOTES
CKSRYB
E TRM3 ASSY (DWX3205) F TRM4 ASSY (DWX3206) C
TRIM VR TRIM VR
VR8601 VR8801
DCS1119-A DCS1119-A
3 3
2
2
6 6
5
5
9 9
8
8
D
147 147
C8601 C8801
0.1u 0.1u
Rch
Rch
Lch
Lch
E
XKP3076-A
XKP3076-A
CN8601
CN8801
10
GNDREF 1 1
8
9
10
GNDREF 1 1
1
GNDA 2
GNDA 4
GNDA 6
GNDA 8
1
GNDA 2
GNDA 4
GNDA 6
V+3R3REF
VR_TRIM3
GNDA
V+3R3REF
VR_TRIM3
L_out
L_out
R_out
R_out
R_in
R_in
L_in
L_in
A 6/11 CN5001 A 8/11 CN5401

F
E F
DJM-900NXS 121
5 6 7 8
1 2 3 4
10.13 MAIN ASSY (1/21)
(CH1 D)
A DIP nonZIF 1.25mm pitch

V+5D V+12E V + 3 R 3 D V + 3 4 D V + 3 R 3 D _ R E F A (CH2 D)
CN1001
C1001
9604S-31C 0.1u/10 (CH3 D)
V+5D_LED 1 (CH4 D)
GNDD_LED 2
(MI D)
V+5D_LED 3
GNDD_LED 4 GNDD_LED (RET D)

V+12STB 5
R1006 0 (SEND D)
12:14D
STANDBY_LED
STBY_KEY
6
7
R1007 0
STBY_LED
12:12A From/To Main CPU G 12/21
STBY_KEY
R1014 0 17:2G
MVR_MUTE 8
R1012 0
MVR_MUTE
12:14B
To OUTPUT IF Block G 17/21
CROSSS_FADER 9 100k R1005 VR_FADER_CRS
EFX_ON/OFF 10
R1013 0 12:2C
BF_SW
To Main Ucom G 12/21
GNDD 11
CN6602
V+3R3D 12
GNDD 13
B
V+34D 14
GNDD 15
SUB_CPU_RESET 16
R1016 0 9:2H;10:2C;12:14I
SUB_SH_RESET
G 9/21,10/21,12/21
K 1/2
R1017 0
12:14G
SUB_CTRL 17
SUB_INT 18
R1015 0
SUB_CTRL
12:14A From/To Main CPU
SUB_INT
GNDD 19
R1020 0 FPGA_CLK
G 12/21
FPGA_CLK 20
(FFC : DDD1551-)
GNDD 21
FPGA_TXD_DAT
FPGA_TX_DAT 22
R1019 22 FPGA_RXD_DAT
FPGA_RX_DAT
FPGA_SIGNAL
23
24
R1018 0 FPGA_SIGNAL G 13/21
13:4B
GNDD 25
GNDD SUB_UCOM To FPGA
V+3R3D_REFA 26
R1008 0 12:14C
VR_FADER1 27 100k R1001 VR_FADER1
GND_REFA 28
VR_FADER2 29 100k R1002

R1009 0 12:14C
VR_FADER2
To Main Ucom
0
C VR_FADER3 30
R1010 12:14C
VR_FADER4 31
100k
100k
R1003
R1004
R1011 0
VR_FADER3
12:14B
VR_FADER4
G 12/21
GNDREF_A
A 1/1
2 9 CH3_SEL(Time code)
39 RETURN_DATA
2 5 V+3R3DRERA
2 4 V+3R3DRERA
2 3 GNDD_REFA
GNDD REFA
40 RETRUN_IN
2 7 CH3_DATA
3 3 CH4_DATA
37 CH4_TRIM
3 1 CH3_TRIM
36 CH4_SEL
3 0 CH3_SEL
38 GNDD
3 2 GNDD
2 8 GNDD
2 6 GNDD
3 4 GNDD
D
0
0
0
0
R1021
V+3R3D_REFA
R1035
R1023
R1024
R1022
From MAIN CPU Block
NOTES
SEL_4
SEL_3
is STBY
VR_4
VR_3
TC_4
TC_3
NM
RS1/16S****J GNDD GNDREF
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J From LAN UCOM_2 Block DIR_ADC_DAC_RESET
1/4W RS1/4S****J 10:15H;17:2F;21:2E
E 2W RS2****J G 10/21,17/21,21/21
VR_2
VR_1
VR_4
VR_3
TC_2
TC_1
TC_4
8 SEL_1
7 SEL_2
6 SEL_3
5 SEL_4
RAB4CQ****J
8
6
5
7
6
R1038
R1037
R1036
10
0
CKSRYB****
2
3
4
2
3
2
3
1
CKSSYB****
LINE_SEL1
LINE_SEL2
LINE_SEL3
LINE_SEL4
CH CCSRCH****
TC_SEL2
TC_SEL1
TC_SEL4
CCSSCH****
CCSQCH****
12:2G
+
+
CEVW*** G 12/21 RETURN_IN
HA CEHVAW**
From/To MAIN Ucom Block 12:14I
NP CEVWNP*** CH_TC_SELCT
13:3I
96K_CLK_AIN
F G 13/21 13:3J
6M_CLK_AIN
From FPGA Block
13:3J
G 1/21
24M_CLK_AIN
122 DJM-900NXS
1 2 3 4
5 6 7 8
(CH1 D)
(CH2 D)
: CH1 DIGITAL Signal (from INPUT Assy) G 1/21 MAIN ASSY (DWX3190) A
: CH2 DIGITAL Signal (from INPUT Assy)
(CH3 D)
(CH4 D)
(MI D)
V+5A_O V+5A_SE
: MI DIGITAL Signal (from INPUT Assy)
V+15A_SE
V-15A_SE
(RET D)
V+5A_SE
: RET DIGITAL Signal (from INPUT Assy)
(SEND D) V+15A_SE
V+15A_O DIP 1.25mm pitch Bridge
: SEND OUT DIGITAL Signal
CN1003
AKM7077-A
R1046 1 GND_PO
0
V-15A_O V-15A_SE
2 V+15A_SE
R1047 0
3 V-15A_SE
4 GND_PO
GNDA_O GNDA_SE
GND_PO 5 GNDA_SE
B
CN6401
R1048 0
(SEND D) 6 V+5A_SE
MUTE_OUT
G 17/21,19/21,20/21 17:9B;19:2D;19:2H;20:2H
R1044
0
7
8
MUTE_OUT
GNDA_SE
9 GNDA_SE
R1040
MCLK_OUT_SE 10 MCLK_SE
17:9E 0
J
11 GNDD_O
R1041
BCLK_OUT_SE 12 BCK_SE
17:9E 0
13 GNDD_O
R1042
From OUTPUT IF Block ADAT_SEND_OUT 14 ADAT_SEND_OUT
17:9G 0
G 17/21 LRCLK_OUT_SE
R1043
15
16
GNDD_O
LRCK_OUT
17:9F 0
17 GNDD_O
R1045
RESET_OUT 18 RESET_OUT
17:9F;18:2C;19:2E;20:2C 0
19 GNDD_O
G 17/21-20/21 TP B side C
GNDA_SE GNDD
A 1/11 CN4002 (FFC : DDD1550-)

CH1_SEL(Time code)
2 1 AD/DA_RESET
2 5 V+3R3DRERA
2 4 V+3R3DRERA
2 3 GNDD_REFA
2 2 GNDD_REFA
2 7 CH3_DATA
CH2_DATA
CH1_DATA
MIC_DATA
1 3 CH2_TRIM
CH1_TRIM
MIDI TXD
3 0 CH3_SEL
1 2 CH2_SEL
CH1_SEL
1 9 LRCLK
2 8 GNDD
2 6 GNDD
2 0 GNDD
1 8 GNDD
1 6 GNDD
1 4 GNDD
1 0 GNDD
GNDD
GNDD
1 5 MCLK
1 7 BCLK
CN1002
VKN2050-A
9
SMT nonZIF 0.5mm pitch

TP B side
D
Analog Block
0
0
0
R1021
R1028
R1025
R1026
R1027
R1039
R1022
0
1
R1032
8 (CH2 D) 15:13G
Digital Block
ADAT_CH2_ANA
SEL_3
To DSP_2 Block
TC_3
2 7 15:13G
(CH1 D)
SEL_2
SEL_1
GNDREF_A ADAT_CH1_ANA
VR_2
VR_1
TC_2
TC_1
3 6
(MI D) 15:13G
4 5 ADAT_MIC_ANA
1 8 (RET D) 15:13G
G 15/21
ADAT_RETURN_ANA
2 7
(CH4 D) 15:13G
3 6 ADAT_CH4_ANA
(CH3 D) 15:13G
4 5 ADAT_CH3_ANA
0 R1029
E
VR_2
VR_1
VR_4
VR_3
TC_2
TC_1
TC_4
TC_3
From/To MAIN Ucom Block

8
7
6
5
8
7
5
R1038
12:14D
10
10
MIDI_TXD
2
3
3
4
1
12:14C
VR_TRIM3
BOARD IF
TC_SEL2
TC_SEL1
TC_SEL4
TC_SEL3
12:14C
VR_TRIM4 G 12/21
12:14C
VR_TRIM1
12:14C
VR_TRIM2
G 1/21
DJM-900NXS 123
5 6 7 8
1 2 3 4
10.14 MAIN ASSY (2/21)

STBY
V+15A_1 V+5A V+9HP V+5A
STBY
STBY
R1220
HN1A01FU(YGR)
R1217
A
R1214
R1210
R1207
R1202
NM
Q1203
(D)
10k
NM
(F)
(F)
11k
(1/2)
(F)
HN1A01FU(YGR) NM
NM
Q 1 2 0 1 (1/2) NM
A side
Analog voltage abnormality A side 1 6 R1209 4
1 6 A side R1219 4
Q120
detect circuit
Q1201
R1215
5
R1203
5 V+5A 2 NM (2/2)
(F)
NM
V+5A 2 A side 3
(2/2)
1k
20k
R1218
3
(F)
NM
R1208
NM
(D)
22k
(F)
R1216
R1204
NM
10k
V-15A_1 V-9HP V-9HP
V-15A_1
D1201 D1204
1SS301 NM
Analog Block
A side V+15A_1
V+15A
B 3
1000p/50
C1210
100u/25
C1202
C1207
0.1u/50
CH
A side
V-15A
CN1201 4
AKM1277-A
CH
KN1203
CKF1089-A
1000p/50
C1211
100u/25
P1201
C1203
1 C1208
0.1u/50
VMUTE V-15A_1
NM A side
1
P2
+15VA 2
2 1 V+5A
Analog GND basis
+5VA 3
2
P1202
1 5
GNDA 4 NM
S
GNDA 5
GNDA
-15VA 6
CH
2 NM 1 A side
GND_PO GNDA_HP
1000p/50
P1203 GND
100u/25
0.1u/10
R1231
R1230
C1204
C1209
TP B side
C1212
STBY
0
STBY
D1205 V+9HP
HP Block NM
V+15A_HP V+9HP
Drop Resister V+9HP_UNREG IC1201 A side
STBY STBY
P1211 R1206
C1216
0.33u/50
KIA7809API C1218
0.1u/16
D1203
RB501V-40 9
GNDA_HP_RTN_1
IN OUT
1 2 1 GND 3
NM
1000p/50
NM
C1206
C1270
100u/25
C1221
R1227
2W
47u/16
2 B side
NM
CH
R1228
JP1206
DDC1022-A
0
R1232
NM
STBY
D GNDA_HP_1
1 GNDA_HP
STBY
D1206
KN1202 NM
CKF1089-A V-9HP_UNREG
V-9HP
Drop Resister IC1202
STBY STBY KIA7909PI A Side
P1212 R1205 OUT
D1202
RB501V-40 10
IN
1 2 2 GND 3
C1220
NM
CCG1254
NM
47u/16
1000p/50
C1217
C1219
2W 1
C1271
100u/25
B Side
C1213
C1269
1u/16
!
22u/16
CH
R1229
NM
V-15A_HP JP1205
DDC1022-A
0
STBY
GNDA_HP GNDA_HP V-9HP
R1201
VMUTE 0 VMUTE
1 A side P1205 2
1 2
NM
E STBY
V+12D
Digital Block V+12D

A side
7 CN1204
1 V+12D
NM
V+12V STBY 2 GNDD

470u/16
C1201
C1205
0.1u/16
CN1202 1-1 A side V+12STBY V+12E

AKM1278-A V+12STBY V+12E STBY
6 8 P1206 SPECIAL MODEL LED
1 POWER SUPPLY STB
+12V STBY P1204 2 1
+12V Switched 2 NM !
P3
C1214
C1215
2 1
0.1u/16
47u/16
466.250
+12V Switched 3 DEK1103-A
466003. ! STBY
GNDD 4
S
GNDD 5
STBY Control 6
RESET 7
1000p/50
C1272
CH
Digital block disposition

F KN1207 KN1204 KN1201
CKF1089-A CKF1089-A CKF1089-A
KN1208 KN1205 KN1206
CKF1089-A 1 CKF1089-A 1 CKF1089-A 1 GNDD
G 2/21 1 1 1
124 DJM-900NXS
1 2 3 4
5 6 7 8
V+5A V+12D
LTA124EUB
STBY
R1220 G 2/21 MAIN ASSY (DWX3190)
Q1206
A
NM
NM
4
VADET G 3/21
R1219
LTC124EUB
5
Q1203
R1222 3:2C
VADET
To Power Block Low value Hi value
NM (2/2)
Q1205
3 0
R1221
NM
10k
V+5A 4.28V 5.61V
NM
V+9HP 8.23V 9.94V
V-9HP -5.96V -11.82V

P
GNDD GNDD V+15A 13.38V 16.74V
D1204
NM -18.57V
V-15A -11.83V
15W cut ICP V+5A

P1207
DEK1121-A
CN1203 CAUTION
1 2
AKM1282-A FOR CONTINUED PROTECTION
! 0437.750
AGAINST RISK OF FIRE.
REPLACE ONLY SAME TYPE NO,
A 1/11 CN4003
11 V+15A
B
P1208 10 GNDA_IN
1 2
9 V-15A 466.250 (DEK1093-A-T 250mA)
! DEK1121-A
0437.750
8 GNDA_IN MFD. BY LITTELFUSE INC . FOR P1206
7 V+5A
15W cut ICP V+3R3D 6 GNDA_IN 0437.750 (DEK1121-A-T 750mA)
GNDA_IN
5 V+3R3D MFD. BY LITTELFUSE INC . FOR P1207,P1208
V+12D 4 GNDD
3 V+12D 466.750 (DEK1096-A-T 750mA)
V+5D
2 GNDD MFD. BY LITTELFUSE INC . FOR P1209
1 V+5D
466.500 (DEK1095-A-T 500mA)

GNDD
MFD. BY LITTELFUSE INC . FOR P1210
V+5A
466003. (DEK1103-A-T 3A)
MFD. BY LITTELFUSE INC . FOR P1204
V+15A
15W cut ICP
C
1 2
P1210
! DEK1095-A
466.500
To OUTPUT IF Block
GNDA_O
The > mark found on some component parts

V+9HP GNDA_M1
P1209 indicates the importance of the safety factor of the part.
!
V+9HP 1 2
Therefore, when replacing, be sure to use parts
A side DEK1096-A of identical designation.
9 466.750
V-15A
15W cut ICP
47u/16
B side
D
To HP AMP Block : Voltage measuring point
V-9HP
A Side
B Side
NOTES
is STBY
NM
V-9HP
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
V+18VMUTE RN1/10S****J
To OUTPUT IF Block (D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J E
2W RS2****J
CN1204
1 V+12D RAB4CQ****J
NM
2 GNDD
CKSRYB****
STBY CKSSYB****
ECIAL MODEL LED CH CCSRCH****

WER SUPPLY STB CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
G 12/21 NP CEVWNP***
12:2E
P-CON
3:2F;12:2H From To Main Ucom
PowerReset
G 3/21,12/21 F
G 2/21
DJM-900NXS 125
5 6 7 8
1 2 3 4
10.15 MAIN ASSY (3/21)
A
Digital voltage abnormality detect circuit
V+12D V+1R
LSA1576UB(QRS)
V+2R5D V+12D
V+5D V+3R3D V+2R5D
V+2R
V+34D
HN1A01FU(YGR)
HN1A01FU(YGR)
HN1A01FU(YGR)
V+3R
HN1A01FU(YGR)
V+12D V+5D V+3R3D
0.1u/10
C1411
R1421
STBY STBY STBY
6.2k
STBY
(F)
V+5
Q 1 4 0 2 (1/2)
NM
Q1404
Q 1 4 1 0 (1/2)
Q 1 4 0 2 (2/2)
NM NM NM R1417
1000p/50
Q 1 4 1 0 (2/2)
V+1
0.1u/16
R1453 R1404 R1409
C1471
R1455
C1401
R1401
C1404
R1406
C1407
R1410
0.1u/10
0.1u/10
9.1k
30k
15k
15k
R1422
GNDD V+3
1.8k
4 R1420
(F)
R1454 1 R1403 4 R1408 1 R1414
V+12D
2 6 5 3 2 5 10k
R1456
R1402
R1407
R1411
1k 1k 1k 6 1k 3
GNDD GNDD GNDD GNDD
12k
12k
56k
22k
1SS352
V+1R2D
D1415
1SS352
D1401
GNDD
LTA124EUB
Q1406
GNDD GNDD GNDD GNDD
C1413
0.1u/10
R1423
R1424
470
1.5k
D1414
D1402 Q1405
1SS301 LTC124EUB
1SS301 GNDD
B GNDD
RKZ3.3KG(B2)
D1406
R1425
NM
STBY
G 2/21 2:8A
VADET
Q1407
LTC124EUB
From POWER_IF Block
(Analogl voltage abnormality detect)
GNDD GNDD GNDD
NOTES
is STBY
NM
RS1/16S****J
RN
RS1/10S****J
RN1/16S****J
3.3V 2.5V 12V 3.3V
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D V+3R3D
STBY
V+2R5D STBY (Only
(F) RS1/16S****F V+12E
RS1/10S****F 3.3V REGULATOR
D1403
C 1/8W RS1/8S****J D140
NM
1/4W RS1/4S****J
NM
2W RS2****J 15 IC1404
2.5V REGULATOR
! A side ! 1
CONTROL VIN
5
RAB4CQ****J IC1402
2
S-1170B25UC-OTK R1416 GND
VIN NC 3 4
4 3 V+2R5D
NC VOUT
0
DCH1201-A
VSS
DCH1201-A
CKSRYB**** 2
1 0 u 10V
1 0 u 10V
1/8W
C1410
C1402
C1417
C1419
47u/16
0.1u/16
NM
C1405
C1408
C1409
VOUT
47u/16
CKSSYB**** ON/OFF NJM2831F33
1u
5 1
CH CCSRCH****
CCSSCH****
CCSQCH**** STBY
+
CEVW*** GNDD
+ GNDD
HA CEHVAW**
NP CEVWNP***
GNDD
1-4 V+34D Block
V+12D
12V 34V (To FL)
V+34D_1
16
D1405
1/8W A side
R1405
RB160L-40 LSA157
R1503
Q140
0
R1428
V+3R3E
C 1 4 7 0 10u 16V
DTL1123-A
100k
DC/DC converter
470uH
C1414
L1401
CCG1182-A
IC1403
R1413
R1415
1/8W
1/8W
IC1401 0.1u/10
1.5
1.5
TC7SH08FUS1
100u/16
C1403
! 1 8 1.2k
R1429
CS CD
18k
(F)
1 VCC 5
2 7
R1418
R1412 GNDD
C1415
CH 4 7 p / 5 0
ES SI
2
3 6
47k
CT V+
100u/50
R1426
1000p/50
C1412
3 4
C1490
4 5 GND Q140
CH
GND IN- 22k LSC4

C1416
C1418
R1427
C1406
NM
NM
22k
47p/50
R1419
NJM2392M GNDD
1 . 8 k (F)
CH
STBY
E GNDD
G 2/21,12/21 GNDD
GNDD
GNDD
IC1403
From POWER IF 2:8H;12:2H
PowerReset PowerReset FL_Vcont OUTPUT V+34D
High High High
From MAIN_CPU 12:14J
FL_Vcont Low High Low
G 12/21 High Low Low
Low Low Low
The > mark found on some component parts

F indicates the importance of the safety factor of the part. :
Therefore, when replacing, be sure to use parts :
of identical designation.
G 3/21
126 DJM-900NXS
1 2 3 4
D
3
2
1
1.5k
ow
ow
ow
DD
igh
C1416 D1406
403
2V
Q1406
TPUT
NM
NC
RKZ3.3KG(B2)
D GNDD
GND
C1418
16
CONTROL
STBY
IC1404
NM
LTA124EUB
A side
V REGULATOR
C1413
VIN
VOUT
NJM2831F33
R1427 0.1u/10
STBY
4
5
V+34D
22k C1417 R1425
GNDD
R1429 R1428 R1424
0.1u/16 NM
GNDD
GNDD
C1419 470
18k
V+1R2D
100k
GNDD
1u
NM
V+5D
Q1409
D1407
C1479
Q1408
V+2R5
V+34D
V+12D
V+3R3D
V+1R2D
1000p/50
CH
1.08V
LSA1576UB(QRS)
>1.32V
<1.08V
3.3V(EuP)
NORMAL
5
5
LSC4081UB(QRS)
10.4V
4.33V
2.85V
2.22V
1.08V
25.58V
ABNORMAL
Low value
STBY (Only debugger line)
V+34D
17
V+3R3E
1.32V
A side
A side
VDET
V+3R3E
V+34D
12:14C
3.81V
5.82V
2.81V
1.32V
13.24V
Hi value
1-3
11
V+3R3E
Block
: Voltage measuring point

G 12/21
To MAIN_CPU
1-5
C1421
0.1u/16 R1430 0 C1422
V+12D
1/4W
1 0 u 16V C1423 0.1u/16 R1431 0
V+12D
1/4W
V+5D Block
CCG1182-A 1 0 u 16V C1424
C1426 C1425 R1432

CCG1182-A
NM 0.1u/16
6
C1427
6
0
V+12D
1 0 u 16V C 1 4 2 8
1-2
1/4W
NM
STBY
C1429 R1433 D1408
CCG1182-A
STBY
C1430 R1434 D1409
NM NM NM C1431
D1410 NM NM NM
NM
D1411
CMS03 C1432 R1435 D1412
STBY
C1433
0.1u/16 CMS03
NM NM NM
C1434
!
D1413
4
3
2
1
V+3R3D Block
!
0.1u/16
4
3
2
1
CMS03 C1435
SW
VIN
BST
GND
0.1u/16
SW
VIN
BST
GND
2A parts
IC1405
!
(D)
GNDD
4
3
2
1
BD9325FJ
3A parts
R1437
IC1406
FB
GNDD
SS
EN
COMP
DC/DC converter
5
6
7
8
5.1k
SW
BD9326EFJ
VIN
FB
SS
EN
BST
GND
DJM-900NXS
COMP
C1436
5
6
7
8
(D)
DC/DC converter
15u
R1438 C1438 2200p/50 CH
15u
L1402
5u
L1403
IC1407
C1472
GNDD
R1436
L1404
22k 2200p/50 CH
100k
BD9326EFJ
FB
SS
EN
2200p/50
CTH1253-A-TLB
CH
COMP
CH
0.1u/16
CTH1253-A-TLB
(F)
DC/DC converter
BTH1110-A-T
C1441
C1437
5
6
7
8
12V
C 1 4 7 6 CH R1440 C1442
1000p/50 15k 1000p/50
NM
12V
STBY C1440
12V
C1439
7
7
R1439
NM R1442 100k
STBY
CH 2 2 0 0 p / 5 0
C1445 C1444 C1443
0.1u/16 100k
V+3R3D
0.1u/16
NM
G 3/21
(D) (D) C1446 0.1u/16

STBY
R1446 R1445 R1444 C1447 0.1u/16

(D) (D) (D)
R1449 R1448 R1447
5V
4.7k 22k 0
C1448
10k 2.2k 1.2k
C1449
C1450 0.1u/16
10u 10V (D) (D) (D)
1.2V
DCH1201-A R1452 R1451 R1450

3.3V
C1451 1 0 u 10V
DCH1201-A 10k 22k 4.7k
C1452
10u 10V
DCH1201-A C1453
1 0 u 10V
C1454 DCH1201-A
1 0 u 10V
C1455 DCH1201-A
0.1u/10
C1456
C1492 0.1u/10
1 0 u 10V
1000p/50 C1493 DCH1201-A
CH C1459
1000p/50
1/4W
R1498
12 CH 0.1u/10
C1458
1/4W C1494
14
C1457 R1499
NM 0 1000p/50
V+5D
A side
CH
13
STBY NM 0 1/4W
8
8
V+1R2D
STBY R1500
A side
C1460
V+5D
NM
GNDD_LED
0
A side
V+3R3D
STBY
V+1R2D
DIGITAL POWER SUPLLY CIRCUIT
MAIN ASSY (DWX3190)
V+3R3D
127
G 3/21
F
E
B
A
D
C
1 2 3 4
10.16 MAIN ASSY (4/21)

From LAN_Ucom CH1SRC_RESET
10:15H
A G 10/21
USB1/DIGITAL1 IN
CH1 DIR
DIGITAL IN R137
DIR1_SCLK
22
V+3R3D IC110 V+3R3D
1pin 1 28
5pin
4ch
4pin
2ch 1ch
2pin
3ch
1-7 2
AUDIO CKSEL
27 DIR1_ERROR
FSOUT0 ERROR
3 26
DCH1201-A
TP B side V+3R3D FSOUT1 FMT1 C119
10u/10
10u/10
0.1u/10
4 25
C117
C113
(CH1 Di IN) SCKO FMT0
Ni plate
C103 R104 R113 C107 5
VDD VCC
24 DCH1201-A
1-12 1-1
DKB1110-A 6 23 C120 (D)
0.01u/50 10 47k 0.1u/10 0.1u/10
DGND AGND R141
2ch 1ch 6 7 22 GNDD 680
5 XTO FILT
R145
0.068u/16
100k
IC101 8 21
STBY
STBY
CH 2 2 0 p / 5 0
C123
C101
C102
R101
R102
R103
4 XTI RST C122
NM
NM
470
GNDA_F
(D)
75
3 1 VCC 8 9 20 4700p/50
2.2k
4ch 3ch 2 R116 CLKST RXIN
JA101 1
GNDD 5025size
2
3
7
6
CH
C108
1-8 10
11
LRCKO RSV
19
18 1-11
GNDD
47p/50 GNDD
BCKO BFRAME
22p/50
C104
4 5
GNDA_F GNDA_F 12 17
CH
GND R115 GNDD CH1_SPDIF R 1 1 9 DOUT EMPH
0.01u/16
R 1 2 4 (D) 1 0 k 13 16
C121
REAR view TC7WU04FU 22 0 PSCK0 UOUT
R 1 2 5 (D) 1 0 k 14 15
R118
PSCK1 COUT
0
B GNDD GNDD GNDD GNDD 1-6 GNDD GNDD
1-9 DIR9001PW GNDD
R133 22 R142 0
R134 22 R143 0
1-10 R135 22 R144 0
0
(CH1 Di IN)
R138
R139
R140
G 5/21-7/21,10/21
From LAN_Ucom 5:3E;6:3E;7:3E;10:15F
DIR_RESET
G 12/21 From Main_Ucom 15I;5:3E;6:3E;7:3E

12:14B
DIG_SEL1
R105
6M_CLK_USBIN
From OWN (MASTER SRC) 15K;5:3E;6:3E;7:3E
0
R106
G 5/21-7/21 From USB Input 96K_CLK_USBIN
ADAT_USBIN1
11:2H
0
STBY
V+3R3D (CH1 U IN)
C G 11/21 C116
1 NM
VCC 5
R109 2
13:4E;16:3B
24M_CLK_SRC NM 3 4 G N D DR 1 2 9
GND
NM
IC108
GNDD NM
V+3R3D
C114
From FPGA R110

1
2
VCC 5
0.1u/10
13:4D;16:2F R127
G 13/21,16/21 6M_CLK_SRC 0 3
GND
4 GNDD 22
IC106 V+3R3D
G N D D TC7SH08FUS1
C115
1 0.1u/10
VCC 5
R111 2
13:4C;16:2F R128
96K_CLK_SRC 0 3 4 GNDD 22
GND
V+3R3D
STBY
IC107
G N D D TC7SH08FUS1 R126
C110
1 0.1u/10 NM
VCC 5
R107 2
R122
0 3 4 GNDD 22
D GND
R136
IC103 V+3R3D
0
G N D D TC7SH08FUS1
C111
1 0.1u/10
VCC 5
R108 2
R123
0 3 4 GNDD 22
GND CH
STBY
R132
G 12/21 IC104
0
G N D D TC7SH08FUS1 R120
NM
12:14B
From Main Ucom TC_OUT_SEL1
2
G 12/21 R149
100
4
5
12:14K
From MAIN_CPU 24M_CLK_USB
R150 7
R148
100k 100
G 15/21 GNDD T
From DSP 15:3H
ADAT_USB1
(CH1 U OUT)
(CH1 Digi T)
E G 10/21 USBOUT_SRC_MS_SEL
10:15I
10:15F
From LAN_Ucom USBOUT1_SRC_RESET
10:15I
USBOUT_CK_SW
Oscillator
V+3R3D
R112
NOTES
0
NM is STBY
24M/22MHz CLK SW
0.1u/10
C112
0.1u/10
RS1/16S****J
C105
IC102 IC105
RS1/10S****J Vcc
N C1 5 1 VCC 5 IC109 V+3R3D
RN RN1/16S****J
RN1/10S****J C118
I N A2 2
GNDD
1
VCC
8
(D) RS1/16S****D A
RS1/10S****D 3 4 3 4 R121 2 7 0.1u/10
GND B ST
(F) GND0 OUTY
RS1/16S****F 22 3 6 R130
RS1/10S****F Y SELECT
TC7SHU04FUS1 TC7SH08FUS1 4 5
1/8W RS1/8S****J GNDD R114 GNDD GND Y 100k
Silk print A side
1/4W RS1/4S****J 1MEG [MCLK_USB]
R117
1.5k
2W RS2****J TC7WH157FK
X101 GNDD R131 GNDD
4 3
GND2 X2 22
RAB4CQ****J
1
GND1
2 select 6pin 6pin
X1
OUTPUT Low High
12p/50
12p/50
C106
C109
CH
CH
DSS1202-A
CKSRYB****
F CKSSYB****
22.5792MHz
5pin Y
A B
24.576MHz 22.5792MHz
CH CCSRCH****
CCSSCH**** GNDD GNDD
CCSQCH****
+
CEVW*** fs=96kHz 256fs
+
22.5792MHz 24.576M fs=48kHz 512fs
G 4/21
HA CEHVAW**
NP CEVWNP***
22.5792M fs=44.1kHz 512fs
128 DJM-900NXS
1 2 3 4
5 6 7 8
G 13/21
13:2J
CH1_SPDIF
5:15B;6:15B;7:15B;13:4L
To FPGA A
DIF_config
V+2R5D V+2R5D_INSRC
G 5/21-7/21,13/21
DIR1_SCLK 1-13 STBY
R153
CH1 SRC
DCH1201-A
0
IC113 V+3R3D_INSRC V+3R3D
10u/10
0.1u/10
C125
C128
C129
NM
1 20 R157 R167
1-14 XTO SRC_UNLOCK
G 4/21
47k
STBY
DCH1201-A
2 19 0
MAIN ASSY (DWX3190)

R158
DIR1_ERROR XTI SAIF 2k
(D)
10u/10
0.1u/10
3 18
C132
C134
C136
R159
NM
R156
VD SAOF 62k
4 17 (D)
GNDD
0
GND1 VL
5 16
1-12 1-15 6
RST GND2
15 R160
CH1 DIGI/USB SW C127 BYPASS MS_SEL 1k
GNDD
1 0.01u/16 7 14
ILRCK OLRCK
8 13
R145
0.068u/16
100k
ISCLK OSCLK
C123
/50
IC111 V+3R3D 9
SDIN SDOUT
12 R162
47k
1 16 10 11
SEL VCC V+3R3D MCLK_OUT TDM_IN
GNDD
2 15
1A ST R154 Silk print A side
0.1u/10
C124
GNDD 3
1B 4A
14
47k CS8421-CZ GNDD [UDIN1]
1-17 (CH1 U/D IN)
R146
68
4
5
1Y 4B
13
12
GNDD
R161
220
15:15H
ADAT_UDIN1
To DSP
2A 4Y
R147
6
7
2B
2Y
3A
3B
11
10
GNDD
G 15/21 B
68 8 9 R151
GND 3Y
100
0 TC74LCX157FK
2
3 0
GNDD
1-16
4 0
G 5/21
5:2C
CH2_DIGI To DIGITAL_IN2
6:2C
CH3_DIGI
7:2C
To DIGITAL_IN3 G 6/21
CH4_DIGI
To DIGITAL_IN4
G 7/21
C
STBY
R155
NM
R164
R166
5:3F;6:3F;7:3F
24M_CLK_INSRC
5:3F;6:3F;7:3F
6M_CLK_INSRC
5:3F;6:3F;7:3F
G 5/21-7/21
96K_CLK_INSRC
To DIGITAL_IN2
DIGITAL_IN3
DIGITAL_IN4
5:3G;6:3G;7:3G
6M_CLK_OUTSRC
5:3G;6:3G;7:3G
96K_CLK_OUTSRC
(CH1 Di IN)
USB OUT1 : CH1 DIGITAL Input Signal

(CH1 U IN)
: CH1 USB Input Signal D
(CH1 U/D IN)
V+2R5D
R163
V+2R5D_OUTSRC
: CH1 USB/DIGITAL Input Signal
(CH1 Digi T)
DCH1201-A
STBY 0
: CH1 Digital Timecode out Signal
10u/10
0.1u/10
C130
C133
C135
NM
CH1 DIGI/USB SW USBOUT SRC V+3R3D_OUTSRC V+3R3D (CH1 U/D OUT)

IC114 R180
: CH1 USB/DIGITAL Output Signal
IC112
DCH1201-A
V+3R3D 1 20 R169
0 STBY (CH1 U OUT)
GNDD
XTO SRC_UNLOCK 47k
: CH1 USB Output Signal
10u/10
0.1u/10
D
C137
C138
C139
1 16 2 19
NM
R170
SEL VCC XTI SAIF 2k
2 15 3 18 (D) R171
1A ST VD SAOF
0.1u/10
BCLK
62k
C126
3 14 4 17 (D)
1B 4A GND1 VL
R149 4 13 5 16
100 5
1Y 4B
12 0.01u/16 6
RST GND2
15
GNDD
Silk print A side
[UDOUT1] G 5/21-7/21
LRCLK
C131
2A 4Y
GNDD
BYPASS MS_SEL
6 11 7 14 R177 22 5:3J;6:3J;7:3J
2B 3A ILRCK OLRCK 96K_CLK_USBOUT
To USB INPUT Block
DATA
R150 7 10 8 13 R178 22 5:3J;6:3J;7:3J

R148 2Y 3B ISCLK OSCLK 6M_CLK_USBOUT
100k 100 8 9 R152 9 12 R179 22 11:2G
GND 3Y SDIN SDOUT ADAT_UDOUT1
G 11/21
100 10 11 V+3R3D
V+3R3D MCLK_OUT TDM_IN (CH1 U/D OUT)
R176
47k
GNDD TC74LCX157FK R165

C140
47k CS8421-CZ GNDD
1 VCC 5
0.1u/10
Silk print A side
GNDD R181 [BCLK_USBI N]
2
GNDD R185
GNDD 22
To OWN
) 0 3 4 3E;5:3E;6:3E;7:3E DIGITAL_IN2
GND 6M_CLK_USBIN
DIGITAL_IN3 E
IC115
G N D D TC7SH08FUS1
V+3R3D
G 5/21-7/21 DIGITAL_IN4
R172
R174
3.9k
16k
(D)
(D)
C141
1 0.1u/10
V+3R3D VCC 5 Silk print A side
R168
R173
R175
R182 [BCLK_USB]
10k
2
(D)
R186
Q103 0 3 4 GNDD 22
11:2H
LTC124EUB GND 6M_CLK_USB To USB Block
Q102
LTC124EUB
IC116
G N D D TC7SH08FUS1
V+3R3D
C142
G 11/21
1 0.1u/10
VCC 5 Silk print A side
Q101
R183 [LRCK_USBIN]
LTC124EUB 2
R187 To OWN
0 GNDD 22
GNDD 3
GND
4 3E;5:3E;6:3E;7:3E
96K_CLK_USBIN
DIGITAL_IN2
DIGITAL_IN3
Low
3.9k
Hi
16k
IC117
G N D D TC7SH08FUS1
V+3R3D
C143
G 5/21-7/21 DIGITAL_IN4
0.1u/10
XTI = 24.576MHz 1 VCC 5 Silk print A side
USBOUT_SRC_MS_SEL 96KHz 48KHz R184 2
[LRCK_USB]
R188
XTI = 22.5792MHz 0 3 4 GNDD 22
11:2H To USB Block
GND
USBOUT_SRC_MS_SEL 44.1KHz 96K_CLK_USB
IC118
G N D D TC7SH08FUS1
G 11/21
F
DIGITAL IN_1
G 4/21
DJM-900NXS 129
5 6 7 8
1 2 3 4
10.17 MAIN ASSY (5/21)
A
G 10/21
USB2/DIGITA
10:15H
CH2 DIR R224

DIR2_SCLK
22
V+3R3D IC202 V+3R3D
1 28
AUDIO CKSEL
2 27 DIR2_ERROR
FSOUT0 ERROR
3 26
DCH1201-A
FSOUT1 FMT1 C209
From DIGITAL_IN1 V+3R3D 10u/10
10u/10
0.1u/10
4 25
C207
C208
5 24 DCH1201-A
C203 R204 R214 C205
4:15E VDD VCC
CH2_DIGI
0.01u/50 10 47k 0.1u/10
6 23 C210 (D) CH2
DGND AGND 0.1u/10 R228
7 22 G N D D6 8 0
G 4/21 XTO FILT
R232
0.068u/16
100k
IC201 8 21
STBY
STBY
CH 2 2 0 p / 5 0
C213
B
C201
C202
R201
R202
R203
XTI RST C212

NM
NM
470
(D)
75
1 VCC 8 9 20 4700p/50
2.2k
R216 CLKST RXIN
2 7 10 19
CH GNDD
C206 LRCKO RSV
3 6 CH2_SPDIF 11 18
5025size
0.01u/16
47p/50 GNDD
BCKO BFRAME
C211
22p/50
C204
4 5 12 17
CH
GND GNDD DOUT EMPH R234

R215 R218
R 2 1 9 (D) 1 0 k 13 16
TC7WU04FU 22 0 PSCK0 UOUT 68
R 2 2 0 (D) 1 0 k 14 15
R217
PSCK1 COUT
0
GNDD
R235
GNDD GNDD
GNDD GNDD GNDD GNDD
DIR9001PW 68
R221 22 R229 0 GNDD T

R222 22 R230 0
R223 22 R231 0
0
(CH2 Di IN)
R225
R226
R227
G 4/21,6/21,7/21,10/21
4:3E;6:3E;7:3E;10:15F
From LAN_Ucom DIR_RESET
C G 12/21
From Main_Ucom 12:14B
DIG_SEL2
G 4/21,6/21,7/21 4:15I;4:3E;6:3E;7:3E
6M_CLK_USBIN
R205
From MASTER SRC 4:15K;4:3E;6:3E;7:3E

96K_CLK_USBIN
R206
0
(CH2 U IN)
From USB Input ADAT_USBIN2
11:2H
G 11/21
4:15F;6:3F;7:3F R207
6M_CLK_INSRC
0
4:15F;6:3F;7:3F R208
96K_CLK_INSRC
0
4:15F;6:3F;7:3F R209
G 4/21,6/21,7/21 24M_CLK_INSRC
NM
STBY
D From FPGA
4:15G;6:3G;7:3G R210
96K_CLK_OUTSRC 0
4:15G;6:3G;7:3G R211
6M_CLK_OUTSRC 0
G 12/21 12:14B
TC_OUT_SEL2
From Main Ucom R233
100k
E GNDD
R236
100
R237
100
G 15/21 (CH2 U OUT)

From DSP ADAT_USB2
15:3H
(CH2 Digi T)
G 10/21
10:15G
F G 4/21,6/21,7/21 4:15I;6:3J;7:3J
6M_CLK_USBOUT
R212
From DIGITAL_IN1 4:15I;6:3J;7:3J

96K_CLK_USBOUT
R213
G 5/21
130 DJM-900NXS
1 2 3 4
5 6 7 8
/DIGITAL2 IN G 5/21 MAIN ASSY (DWX3190) A
G 13/21
13:2K
CH2_SPDIF
4:15B;6:15B;7:15B;13:4L
DIF_config
To FPGA
V+2R5D_INSRC G 4/21,6/21,7/21,13/21
K CH2 SRC
DCH1201-A
IC205 V+3R3D_INSRC
10u/10
0.1u/10
C217
C218
1 20 R242
XTO SRC_UNLOCK 47k
DCH1201-A
2 19 R243
OR XTI SAIF 2k
(D)
10u/10
0.1u/10
3 18
C220
C222
R244
R241
VD SAOF 62k
4 17 (D)
GNDD
0
GND1 VL
5 16
RST GND2
6 15 R245
CH2 DIGI/USB SW C216 0.01u/16
BYPASS MS_SEL 1k
GNDD
7 14
ILRCK OLRCK
8 13
R232
100k
ISCLK OSCLK
IC203 V+3R3D 9
SDIN SDOUT
12 R247
47k
B
1 16 10 11
SEL VCC V+3R3D MCLK_OUT TDM_IN
GNDD
2
1A ST
15
R240
Silk print A side
[UDIN2] G 15/21
0.1u/10
C214
3 14
R234
1B 4A 47k CS8421-CZ R246
GNDD
15:15H
4 13
68 5
1Y 4B
12
GNDD
220
ADAT_UDIN2 To DSP
2A 4Y (CH2 U/D IN)
6 11
2B 3A GNDD
R235 7 10
2Y 3B
68 8 9 R238
GND 3Y
100
GNDD TC74LCX157FK
(CH2 Di IN)
: CH2 DIGITAL Input Signal
(CH2 U IN)
: CH2 USB Input Signal
(CH2 U/D IN)
(CH2 Digi T)
(CH2 U/D OUT) C
(CH2 U OUT)
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W
1/4W
RS1/8S****J
RS1/4S****J
D
2W RS2****J
RAB4CQ****J
USB OUT2 CH
CKSRYB****
CKSSYB****
CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
V+2R5D_OUTSRC
DCH1201-A
10u/10
0.1u/10
C221
C223
CH2 DIGI/USB SW USBOUT SRC

R233
100k
IC206 V+3R3D_OUTSRC
IC204 V+3R3D 1
XTO SRC_UNLOCK
20 R250
47k
GNDD
DCH1201-A
1 16 2 19
GNDD
SEL VCC XTI SAIF
(D)
R251
2k E
10u/10
0.1u/10
2 15 3 18
C224
C225
R252
1A ST VD SAOF
0.1u/10
BCLK
62k
C215
3 14 R249 4 17 (D)
R236
1B 4A
0
GND1 VL
4 13 5 16
1Y 4B RST GND2
100 5 12 6 15 R253
0.01u/16
LRCLK
C219
2A 4Y
GNDD
BYPASS MS_SEL 1k
GNDD Silk print A side
6 11 7 14
2B 3A ILRCK OLRCK [UDOUT2]
G 11/21
DATA
R237 7 10 8 13
2Y 3B
R239
ISCLK OSCLK
100 8 9 9 12 R255 22 11:2H
GND 3Y
100
V+3R3D
10
SDIN SDOUT
MCLK_OUT TDM_IN
11
(CH2 U/D OUT)
ADAT_UDOUT2
To USB INPUT
R254
47k
47k CS8421-CZ GNDD
GNDD
GNDD
G 5/21
DJM-900NXS 131
5 6 7 8
1 2 3 4
10.18 MAIN ASSY (6/21)
A
G 10/21
USB3/DIGITAL3
10:15H
CH3 DIR R324

DIR3_SCLK
22
V+3R3D IC302
V+3R3D
1 28
AUDIO CKSEL
2 27 DIR3_ERROR
FSOUT0 ERROR
3 26
DCH1201-A
FSOUT1 FMT1 C309
10u/10
0.1u/10
4 25
C307
C308
5 24 DCH1201-A
C303 R304 R314 C305
4:15E VDD VCC
CH3_DIGI
0.01u/50 10 47k 0.1u/10
6 23 C310 (D) CH3 DIGI/USB SW
CH
7 22 GNDD 680
G 4/21 XTO FILT
R332
0.068u/16
100k
IC301 8 21
STBY
STBY
220p/50
C313
IC303
C301
C302
R301
R302
R303
XTI RST C312

NM
NM
470
(D)
75
1 VCC 8 9 20 4700p/50
B 2 7
2.2k
R316
10
CLKST RXIN
19 GNDD
1
SEL VCC
16
C306 LRCKO RSV 2 15

3 6
4 7 p / 5 0 CH3_SPDIF 11 18 1A ST
5025size
0.01u/16
GNDD
BCKO BFRAME 3 14
C311
CH
22p/50
C304
4 5 12 17 1B 4A
CH
GND GNDD DOUT EMPH R334 4 13

R315 R318
R 3 1 9 (D) 1 0 k 13 16 1Y 4B
TC7WU04FU 22 0 PSCK0 UOUT 68 5 12
R 3 2 0 (D) 1 0 k 14 15 2A 4Y
R317
PSCK1 COUT 6 11
0
GNDD 2B 3A
R335 7 10
GNDD GNDD
GNDD GNDD GNDD GNDD 2Y 3B
DIR9001PW 68 8
GND 3Y
9
R321 22 R329 0 GNDD TC74LCX157FK

R322 22 R330 0
R323 22 R331 0
0
(CH3 Di IN)
R325
R326
R327
G 4/21,5/21,7/21,10/21 4:3E;5:3E;7:3E;10:15F
C G 12/21
12:14B
From Main_Ucom DIG_SEL3
G 4/21,5/21,7/21 4:15I;4:3E;5:3E;7:3E R305

6M_CLK_USBIN
0

96K_CLK_USBIN
R306
11:2H
(CH3 U IN)
G 11/21
4:15F;5:3F;7:3F R307
6M_CLK_INSRC
0
4:15F;5:3F;7:3F R308
96K_CLK_INSRC
0
4:15F;5:3F;7:3F R309
G 4/21,5/21,7/21 24M_CLK_INSRC
NM
STBY
From FPGA
D
4:15G;5:3G;7:3G R310
96K_CLK_OUTSRC 0
4:15G;5:3G;7:3G R311
6M_CLK_OUTSRC 0
G 12/21
12:14B CH3 DIGI/USB
R333
100k
IC304
GNDD 1
SEL VC
E 2
1A S
BCLK
3
1B 4A
R336 4
1Y 4B
100 5
LRCLK
2A 4Y
6
2B 3A
DATA
R337 7
2Y 3B
100 8
GND 3Y
G 15/21 (CH3 U OUT)

GNDD TC74LCX15
15:3H
From DSP ADAT_USB3
(CH3 Digi T)
G 10/21
10:15G
F G 4/21,5/21,7/21 4:15I;5:3J;7:3J
6M_CLK_USBOUT
R312
0
R313
96K_CLK_USBOUT 0
G 6/21
132 DJM-900NXS
1 2 3 4
5 6 7 8
GITAL3 IN G 6/21 MAIN ASSY (DWX3190) A
G 13/21
13:2K
CH3_SPDIF
4:15B;5:15B;7:15B;13:4L
DIF_config
To FPGA
V+2R5D_INSRC
G 4/21,5/21,7/21,13/21
DCH1201-A
CH3 SRC
10u/10
0.1u/10
C316
C318
IC305 V+3R3D_INSRC
1 20 R342
XTO SRC_UNLOCK 47k
DCH1201-A
2 19 R343
GNDD XTI SAIF 2k
(D)
10u/10
0.1u/10
3 18
C320
C322
R344
R341
VD SAOF 62k
4 17 (D)
GND1 VL
0 5 16
RST GND2
6 15 R345
BYPASS MS_SEL 1k
GNDD
7 14
ILRCK OLRCK
8 13
ISCLK OSCLK
IC303 V+3R3D 9
SDIN SDOUT
12 R347
47k
1
SEL VCC
16
V+3R3D
10
MCLK_OUT TDM_IN
11 B
2 15 Silk Print A side
1A ST R340 [UDIN3]
G 15/21
0.1u/10
C314
3 14
R334
1B 4A 47k CS8421-CZ R346
GNDD
4 13 15:15H
1Y 4B GNDD
68 5
2A 4Y
12 220
(CH3 U/D IN)
ADAT_UDIN3
To DSP
6 11
2B 3A GNDD
R335 7 10
2Y 3B
68 8 9 R338
GND 3Y
100
GNDD TC74LCX157FK
(CH3 Di IN)
(CH3 U IN)
(CH3 U/D IN)
(CH3 Digi T)
(CH3 U/D OUT)
: CH3 USB/DIGITAL Output Signal C
(CH3 U OUT)
NOTES
NM is STBY
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
D
RAB4CQ****J
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
USB OUT3 V+2R5D_OUTSRC

DCH1201-A
10u/10
0.1u/10
C321
C323

33
0k
IC306 V+3R3D_OUTSRC
IC304 V+3R3D 1
XTO SRC_UNLOCK
20 R350
47k
1 16 GNDD 2 19 R351
DCH1201-A
SEL VCC XTI SAIF 2k

(D)
E
10u/10
0.1u/10
2 15 3 18
C324
C325
R352
1A ST VD SAOF
0.1u/10
BCLK
62k
C315
3 14 R349 4 17 (D)
R336
1B 4A
0
GND1 VL
4 13 5 16
1Y 4B RST GND2
100 5 12 6 15 R353
0.01u/16
LRCLK
C319
2A 4Y
GNDD
BYPASS MS_SEL 1k
GNDD Silk print Aside
6 11 7 14
2B 3A ILRCK OLRCK [UDOUT3]
G 11/21
DATA
R337 7 10 8 13
2Y 3B
R339
ISCLK OSCLK
100 8 9 9 12 R355 22 11:2H
GND 3Y
100
V+3R3D
10
SDIN SDOUT
MCLK_OUT TDM_IN
11
ADAT_UDOUT3
To USB INPUT
R354
(CH3 U/D OUT)

47k
47k CS8421-CZ GNDD
GNDD
GNDD
G 6/21
DJM-900NXS 133
5 6 7 8
1 2 3 4
10.19 MAIN ASSY (7/21)
A
G 10/21 USB4/DIGITA
10:15H
CH4 DIR R424

DIR4_SCLK
22
V+3R3D IC402
V+3R3D
1 28
AUDIO CKSEL
2 27 DIR4_ERROR
FSOUT0 ERROR
3 26
DCH1201-A
FSOUT1 FMT1 C409
10u/10
0.1u/10
4 25
C407
C408
DCH1201-A
C403 R404 R414 C405 5 24
4:15E VDD VCC
CH4_DIGI
0.01u/50 10 47k 0.1u/10
6 23 C410 (D) CH4 DIG
7 22 GNDD 680
G 4/21 XTO FILT
R432
0.068u/16
100k
IC401
8 21
STBY
STBY
CH 2 2 0 p / 5 0
C413
C401
C402
R401
R402
R403
XTI RST C412

NM
NM
470
(D)
75
1 VCC 8 9 20 4700p/50
B 2 7
2.2k
R416
10
CLKST RXIN
19 GNDD
1
SE
CH
3 6 C406 LRCKO RSV 2
CH4_SPDIF 11 18 1A
5025size
0.01u/16
47p/50 GNDD
BCKO BFRAME 3
C411
22p/50
C404
4 5 12 17 1B
CH
GND GNDD DOUT EMPH R434 4

R415 R418
R 4 1 9 (D) 1 0 k 13 16 1Y
TC7WU04FU 22 0 PSCK0 UOUT 68 5
R 4 2 0 (D) 1 0 k 14 15 2A
R417
PSCK1 COUT 6
0
GNDD 2B
R435 7
GNDD GNDD
GNDD GNDD GNDD GNDD 2Y
DIR9001PW 68 8
G
R421 22 R429 0 GNDD TC7

R422 22 R430 0
R423 22 R431 0
0
(CH4 Di IN)
R425
R426
R427
G 4/21-6/21,10/21 4:3E;5:3E;6:3E;10:15F
C G 12/21
12:14B
From Main_Ucom DIG_SEL4
G 4/21-6/21 4:15I;4:3E;5:3E;6:3E R405

6M_CLK_USBIN
0

96K_CLK_USBIN
R406
0
(CH4 U IN)
11:2H
G 11/21
4:15F;5:3F;6:3F R407
6M_CLK_INSRC
0
4:15F;5:3F;6:3F R408
96K_CLK_INSRC
0
4:15F;5:3F;6:3F R409
G 4/21-6/21 24M_CLK_INSRC
NM
STBY
From FPGA
D
R410
4:15G;5:3G;6:3G
96K_CLK_OUTSRC 0
R411
4:15G;5:3G;6:3G
6M_CLK_OUTSRC 0
G 12/21
12:14B C
R433
100k
GNDD
E
R436
100
R437
100
G 15/21 (CH4 U OUT)

GND
From DSP ADAT_USB4

15:3H
(CH4 Digi T)
G 10/21
10:15G
F G 4/21-6/21 4:15I;5:3J;6:3J
6M_CLK_USBOUT
R412
0
R413
96K_CLK_USBOUT 0
G 7/21
134 DJM-900NXS
1 2 3 4
5 6 7 8
DIGITAL4 IN G 7/21 MAIN ASSY (DWX3190) A
G 13/21
13:2L
CH4_SPDIF
4:15B;5:15B;6:15B;13:4L
DIF_config
To FPGA
V+2R5D_INSRC G 4/21-6/21,13/21
CH4 SRC
DCH1201-A
IC405 V+3R3D_INSRC
10u/10
0.1u/10
C417
C418
1 20 R442
XTO SRC_UNLOCK 47k
DCH1201-A
2 19 R443
XTI SAIF 2k
(D)
10u/10
0.1u/10
3 18
C420
C422
R444
R441
VD SAOF 62k
4 17 (D)
GNDD
0
GND1 VL
5 16
RST GND2
6 15 R445
BYPASS MS_SEL 1k
GNDD
7 14
ILRCK OLRCK
8 13
R432
100k
ISCLK OSCLK
IC403 V+3R3D 9
SDIN SDOUT
12 R447
47k
GNDD
1
SEL VCC
16
V+3R3D
10
MCLK_OUTTDM_IN
11 B
2 15 Silk print A side
[UDIN4]
G 15/21
1A ST R440
0.1u/10
C414
R434
3
1B 4A
14
47k CS8421-CZ GNDD
4 13 R446
GNDD 15:15H
1Y 4B
68 5
2A 4Y
12 220
(CH4 U/D IN)
ADAT_UDIN4
To DSP
6 11
2B 3A GNDD
R435 7 10
2Y 3B
68 8 9 R438
GND 3Y
100
GNDD TC74LCX157FK
(CH4 Di IN)
(CH4 U IN)
(CH4 U/D IN)
(CH4 Digi T)
(CH4 U/D OUT)
: CH4 USB/DIGITAL Output Signal C
(CH4 U OUT)
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
RAB4CQ****J
D
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
USB OUT4 V+2R5D_OUTSRC

DCH1201-A
10u/10
0.1u/10
C421
C423

R433
100k
IC406 V+3R3D_OUTSRC
IC404 V+3R3D 1
XTO SRC_UNLOCK
20 R450
47k
GNDD
DCH1201-A
GNDD 1 16 2 19 R451
SEL VCC XTI SAIF 2k
(D)
E
10u/10
0.1u/10
2 15 3 18
C424
C425
R452
1A ST VD SAOF
0.1u/10
BCLK
62k
C415
3 14 R449 4 17 (D)
R436
1B 4A
0
GND1 VL
4 13 5 16
1Y 4B RST GND2
100 5 12 6 15 R453
0.01u/16
LRCLK
C419
2A 4Y BYPASS MS_SEL 1k
6
2B 3A
11 GNDD 7
ILRCK OLRCK
14 GNDD Silk print Aside
[UDOUT4] G 11/21
DATA
R437 7 10 8 13
2Y 3B ISCLK OSCLK
100 8
GND 3Y
9 R439
100
9
10
SDIN SDOUT
12
11
R455 22 11:2H
ADAT_UDOUT4
To USB INPUT
V+3R3D MCLK_OUT TDM_IN
R454
(CH4 U/D OUT)

47k
47k CS8421-CZ GNDD
GNDD
GNDD
G 7/21
DJM-900NXS 135
5 6 7 8
1 2 3 4
10.20 MAIN ASSY (8/21)
STBY
S1
G1
D2
LAN_RXER
ETHER-PHY
1-18 T1601, F1601, F1602 Block IC1603
RTL8201EL-VC-GR
(F)
B STBY near 48pin
R1618
2.49k
R1614 NM +1.2V_Analog
VTH1056-A
DCH1201-A
3 2
0.1u/10
R1615
10u 10V
C1606
NM
C1608
4 1
TRANS
F1601
T1601
48
47
46
45
(LINK IN)
PWOUT12A
GND_47
RSET
TD+IN 1 16 TD+OUT MDI-0_TX 1
JA1601 VTH1056-A TCTIN 2 15 TCTOUT

(LINK IN)
2
3 2 TD-IN 3 14 TD-OUT MDI+0_TX 3

TD+ 1
NC14 13 NC4 4
TD- 2 4 1 MDI+[1]
F1602
NC25 12 NC3 5
Ether connector
VKN2023-A
RD+ 3 (LINK IN) MDI-[1]

R1605 0 R D + O U T6 11 RD+IN 6
MDI-1_RX
TCT1 4 AVDD33_6
STBY
R C T O U T7 10 RCTIN 7
TCT2 5
4
F1603
1
(LINK IN) GND_7
DVDD33 15
R D - O U T8 9 RD-IN MDI+1_RX 8
RD- 6 NC_8
3 2 9
7 NC_9
RXDV
RCT1
RXD0
NM 10
RCT2 8 R1606 0 BTX1044-A NC_10
C1602
C1603
0.1u/10
0.1u/10
R1607 0 11
NC_11
TP Bside STBY 12
F1604 NC_12
4 1
13
14
15
16
3 2
NM GNDD
C R1608 0
R1610
R1612
75
75
R1619 22
R1620 22
R1621 22
R1609
R1611
75
75
ACG1127-A
1000p/2kV
C1601
LAN_RXD[0]
LAN RXD[1]
LAN_RXDV
C1622
0.1u/10
C1623
0.01u/16
Oscillator
ACG1127-A
C1625
1000p/2kV V+3R3D
R1613
GNDD_F GNDD
0
C1604
0.1u/10
IC1601 IC1602
N C1 5 1 VCC
Vcc
INA 2 2
3 4 OUTY 3
GND
D GND0
TC7SHU04FUS1 TC7SH08FUS1
GNDD R1616 GNDD
R1617
1MEG
1k
X1601
4 X2 3
GND2
1 2
X1 GND1
C1605
C1607
12p/50
12p/50
CH
DSS1205-A
CH
25MHz
25M
GNDD GNDD
From LAN UCOM 9:15G

RESET_PHY
G 9/21
G 8/21
136 DJM-900NXS
1 2 3 4
5 6 7 8
G 8/21 MAIN ASSY (DWX3190) A
STBY
LAN INPUT
R1636
Q1601
0
NM
S1 1 6 D1
G12 5 G2
STBY
V+3R3D
C1610
R1635
D2 3 4 S2
NM
NM
R1622
1-20 V+3R3D
L1601
0
QTL1013-A
R1625
DCH1201-A
C1619
C1613
C1615
NM R1630
R1638
10u 10V
LAN_RXER
0.1u/10
0.1u/10
STBY
22
GNDD
LAN_CRS
33
THER-PHY
GNDD
C1603
TL8201EL-VC-GR
DCH1201-A
C1614
C1616
C1617
10u 10V
C1620
0.1u/10
0.1u/10
0.1u/10
R1634 0 LAN_COL
(F)
near 48pin
R1618
B
R1628
R1637
10k
10k
2.49k
2V_Analog
PHYAD=01(1) GNDD
DCH1201-A
0.1u/10
10u 10V
C1606
C1608
48
47
46
45
44
43
42
41
40
39
38
37
GNDD
R1639
R1640
R1641
PWOUT12D
PWOUT12A
RXER/FXEN
GND_47
RSET
CKXTAL2
CKXTAL1
DVDD33_37
AVDD33_41
4.7k
4.7k
4.7k
NC_45
NC_44
COL/SNI
1 36
2 35
3 34 R1647
MDI+[0]
4 33 22
MDI-[0]
MDI+[1]
NC_3
5 CRS/RPTR/CRS_DV 32
MDI-[1] INTB
LED1/PHYAD1 R1642 22 LAN_MDIO
6 LED0/PHYAD0 31
AVDD33_6 MDIO
GND_33 R1643 33
7 30 LAN_MDC
GND_7 MDC
DVDD33_15
8 29
NC_8 PHYRSTB
9 28
NC_9 DVDD12
RXDV
RXD0
DVDD33_21
10 27 R1644 0 LAN_TXEN
NC_10 TXEN
TXD0
TXD1
GND_20
11 26 R1645 33 LAN_TXD[3]
TXC
NC_11 TXD3
RXD1
RXD2
RXD3
12 25 R1646 33
RXC
LAN_TXD[2]
NC_12 TXD2
DCH1201-A
10V
C1611
C1612
0.1u/10
near 28pin
13
14
15
16
17
18
19
20
21
22
23
24
10u
1-19 C
C1621
33
33
R1619 22
R1620 22
R1621 22
R1623 22
R1624 22
R1627 22
R1631 22
0.01u/16
R1632
R1633
GNDD
1-19
LAN_RX_CLK
LAN_TX_CLK
LAN_RXD[0]
LAN_RXD[1]
LAN_RXD[2]
LAN_RXD[3]
LAN_TXD[0]
LAN_TXD[1]
LAN_RXDV
C1609
0.1u/10
1 IC1602
Silk print Aside
5
Vcc
1 VCC 5 [25M_CLK_PHY] 1-21
2
GNDD
4 OUTY 3 4 R1629
GND
22
D
4FUS1 TC7SH08FUS1 LNKSTA
6 GNDD
Silk print Aside
[LNKSTA]
R1617
G
1k
1
10:15D
X2 3 LNKSTA
2
G 10/21
GND1
(LINK IN) From To LAN_Ucom
C1607
12p/50
5-A
CH
Hz
25MHz 10:15D
MII_BUS
GNDD
STBY
R1626
NM
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
(LINK IN) RN RN1/16S****J
: LINK AUDIO INPUT RN1/10S****J
(D) RS1/16S****D
RS1/10S****D E
(F) RS1/16S****F
RS1/10S****F
: Waveform measuring point 1/8W

1/4W
RS1/8S****J
RS1/4S****J
2W RS2****J
RAB4CQ****J
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
G 8/21
DJM-900NXS 137
5 6 7 8
1 2 3 4
10.21 MAIN ASSY (9/21)
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
GNDD
A
SH_ADRS[22] R 5 1 7
SH_ADRS[21] R 5 1 8
SH_ADRS[20] R 5 1 9
SH_ADRS[19] R 5 2 0
SH_ADRS[18] R 5 2 1
SH_ADRS[17] R 5 2 2
1-22 V+3R3D_L
[countermeasure] Simulation V+3R3D_LAN V+3R3D_LAN _ME
R613
DCH1201-A
0
10u 10V
STBY
C543
C544
NM
R501
SH_DATA[0] B12 A2 C545
D00 A00 R505 R614 0.01u/16
4 5 C12 A17 1
SH_DATA[1] 8 SH_ADRS[1] SH_DATA[0] 1 8
SH_DATA[2]
3
2
6
7
A11
D01
D02
Ether UCOM A01
A02
B17 2 7 SH_ADRS[2] SH_DATA[1] 2 7 C546
0.01u/16
SH_DATA[3] B11 C17 3 6 SH_ADRS[3] SH_DATA[2] 3 6
D03 A03
SH_DATA[4]
4
R502
5
1
22
8 C11
A10
D04 IC501 A04
A16
B16
4 5
R506
SH_ADRS[4] SH_DATA[3] 4 5
SH_DATA[5] 1 8 SH_ADRS[5]
SH_DATA[6]
3 6 B10
D05
D06
R5S76700B200BG A05
A06
C16
22
2 7 SH_ADRS[6]
47
R615
2 7 C10 A15
SH_DATA[7] 3 6 SH_ADRS[7] SH_DATA[4] 1 8
D07 A07
1 8 R503 B7 B15
B SH_DATA[8]
SH_DATA[9]
22
4 5 A7
D08 A08
C15 1
R507
8
4
22
5 SH_ADRS[8]
SH_ADRS[9]
SH_DATA[5]
SH_DATA[6]
2
3
7
6
C547
0.01u/16
D09 A09
3 6 B8 A14
SH_DATA[10] 2 7 SH_ADRS[10] SH_DATA[7] 4 5
D10 A10
2 7 C8 B14
SH_DATA[11] 3 6 SH_ADRS[11] 47
D11 A11
R504 1 8
SH_DATA[12] 22 A8 C14 4 5 SH_ADRS[12]
D12 A12 R508
4 5 C9 A13
SH_DATA[13] 22 1 8 SH_ADRS[13] C548
D13 A13 0.01u/16
3 6 B9 B13 22
SH_DATA[14] 2 7 SH_ADRS[14] SH_WE0/DQMLL R622
D14 A14
2 7 A9 C13 22
SH_DATA[15] 3 6 SH_ADRS[15] SH_RDWR R623
D15 A15
1 8 R512 K20 A12 47
22 1 8 4 5 SH_ADRS[16] SH_CAS R624
D16 A16 R509
Bus State Controller
2 7 K19 A1 1 8 22 SH_ADRS[17] SH_RAS R625 47

D17 PA17/A17
3 6 J20 B2 2 7 SH_ADRS[18] SH_SDRAM_CS R626 22
D18 PA18/A18 R616
4 5 J19 B1 3 6 SH_ADRS[19] SH_ADRS[13] 1 8
R513 D19 PA19/A19
1 8 10k H20 C3 4 5 SH_ADRS[20] SH_ADRS[14] 2 7
D20 PA20/A20 R510
2 7 H19 C2 22 1 8 SH_ADRS[21] SH_ADRS[11] 3 6
D21 PA21/A21
3 6 G20 C1 2 7 SH_ADRS[22] SH_ADRS[1] 4 5
D22 PA22/A22 R617
4 5 G19 D3 3 6 SH_ADRS[2] 1 8 33
R514 D23 PA23/A23
10k 1 8 E18 D2 4 5 SH_ADRS[3] 2 7
D24 PA24/A24
2 7 D20 D1 22 SH_ADRS[4] 3 6
D25 HIFMD/PA25/A25
E19 R546 10k
3 6 4 5
D26
4 5 F18 C20 R547 47 G N D D SH_CLKOUT C549
33
D27 CKIO 0.01u/16
R515
10k E20
D28 V+3R3D_LAN
4 5 F19 C6
SH_FLASH_CS
R548 22
D29 CS0 R561 4.7k
3 6 F20 B18 47 SH_SDRAM_CS
R549 4.7k
D30 CS3 R562
2 7 G18 A5 22 SH_FPGA_CS
C 1
10k
8
D31 PB06/CS4
B3
R550
R563 4.7k
PB05/CS5/CE1A/IRQ3/TEND1
B6
GNDD PB07/BS
B5 R551 22 SH_RD
RD R564 4.7k
C7 R552 10 SH_WE0/DQMLL
WE0/DQMLL R565 4.7k
A6 R553 100 SH_WE1/DQMLU
WE1/DQMLU/WE
D18 R554 22 SH_WE3/DOMUU R566 NM SH_DATA[0] R516 220 SH_DATA2[0
WE3/DQMUU/ICIOWR
D19 R555 22 SH_WE2/DQMUL R567 NM SH_DATA[1] R523 220 SH_DATA2[1
WE2/DQMUL/ICIORD
C19 R556 22 SH_RDWR R568 NM SH_DATA[2] R526 220 SH_DATA2[2
RDWR
R569 NM SH_DATA[3] R527 220 SH_DATA2[3
B20 R557 47 SH_CKE SH_DATA[4] R528 220 SH_DATA2[4
CKE
A18 R558 47 SH_RAS SH_DATA[5] R529 220 SH_DATA2[5
RAS
A19 R559 47 SH_CAS R570 NM SH_DATA[6] R530 220 SH_DATA2[6
CAS
R571 NM SH_DATA[7] R531 220 SH_DATA2[7
STBY
R560
R524
NM
SH_DATA[8] 1 8 SH_DATA2[8
SH_DATA[9] 2 7 SH_DATA2[9
STBY
SH_DATA[10] 3 6 SH_DATA2[10]
GNDD
220
R525
D SH_DATA[15] 4 5 SH_DATA2[15]
220
G 1/21,10/21,12/21 [countermeasure] Simulation
1:4B;10:2C;12:14I
From Main CPU SUB_SH_RESET
V+1R2D V+1R2D_LAN
V+1R2D_LAN Silk print Aside
[V+1R2D_LAN]
L502
QTL1013-A
1-23 H4 G4
Vcc_00 Vss_00
1608size P4 T4
Vcc_01 Vss_01
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
470p/50
0.1u/10
10u 10V
R4 U4
Vcc_02 Vss_02
Ether UCOM
DCH1201-A
U12 U13
Vcc_03 Vss_03
0.1u/10
C504
C509
NM
R17 T17
Vcc_04 Vss_04
IC501
C511
C515
C517
C525
C528
C530
C533
C535
C538
K17 L17
Vcc_05 Vss_05
STBY D13 D14
D7
Vcc_06 R5S76700B200BG Vss_06
D5
V+3R3D V+3R3D_LAN Vcc_07 Vss_07
GNDD
QTL1013-A
L501 F4 E4
VccQ_00 VssQ_00
1608size K4 J4
VccQ_01 VssQ_01
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
470p/50
10u 10V
0.1u/10
L4 N4
VccQ_02 VssQ_02
DCH1201-A
U6 U5
VccQ_03 VssQ_03
0.1u/10
C501
C502
E
NM
U14 U16
VccQ_04 VssQ_04
C503
C505
C506
C516
C518
C519
C521
C524
C526
C529
C531
C534
C536
C539
U15 U17
VccQ_05 VssQ_05
STBY N17 P17
VccQ_06 VssQ_06
Power Suply
H18 J18
VccQ_07 VssQ_07
H17 J17
VccQ_08 VssQ_08
GNDD G17 E17
VccQ_09 VssQ_09
F17 D17
VccQ_10 VssQ_10
D15 D16
VccQ_11 VssQ_11
Silk print Aside D10 D12
VccQ_12 VssQ_12
[V+3R3D_LAN]
D9 D8
1-24 D6
VccQ_13
VccQ_14
VssQ_13
VssQ_14
D4
V+3R3D_LAN A20
VssQ1
B19
[countermeasure] DEMITAS_NX VssQ2
C18
VssQ3
V+3R3D_LAN Silk print Aside
[V+1R2D_LPLL]
V+1R2D_LPLL VssQ4
D11
K18
V+1R2D V+1R2D_LAN_PLL
1-25 VssQ5
M4
0.01u/16
VssQ6
QTL1013-A
M17
L503 VssQ7
T18
1608size VssQ8
U3
C508
VssQ9
U7
DCH1201-A
VssQ10
1000p/50
10u 10V
0.01u/16
100p/50
0.1u/10
V2
C514
C522
C527
C532
C537
0.1u/10
C507
VssQ11
F GNDD
U20
PLLVcc VssQ12
V7
V8
VssQ13
Y20 V9
PLLVss VssQ14
W1
VssQ15
GNDD
G 9/21
W11
VssQ16
GNDD
138 DJM-900NXS
1 2 3 4
5 6 7 8
LAN UCOM1
1-22 V+3R3D_LAN_MEM
13:16H
SH_BUS
+3R3D_LAN V+3R3D_LAN _MEM SDRAM 128M

R613 FLASH 64M
IC503
DCH1201-A
0
MD56V72160B-6TAZ IC502
10u 10V
G 13/21 To FPGA
C543
C544
V+3R3D_LAN_MEM V+3R3D_LAN_MEM
NM
DYW1798- /J C542
DCH1201-A
R572
1 54 SH_ADRS[16] 1 8 1 48 1 0 u 1 0V R593 0 SH_ADRS[17]
C545
R614 0.01u/16 R634 A15 A16
VCC1 VSS3 53
0] 1 8 2 1 8 SH_DATA[15] SH_ADRS[15] 2 7 2 47
DQ1 DQ16 A14 BYTE#
1] 2 7 C546 3 52 2 7 SH_DATA[14] SH_ADRS[14] 3 6 3 46
0.01u/16 V C C Q 1 VSSQ4 A13 VSS2 R594
2] 3 6 4 51 3 6 SH_DATA[13] SH_ADRS[13] 4 5 4 45 1 8 SH_DATA2[15] 13:16G
DQ2 DQ15 R573 A12 DQ15/A-1 SH_DATA
3] 4 5 5 50 4 5 SH_DATA[12] SH_ADRS[12] 1 8 22 5 44 2 7 SH_DATA2[7]
DQ3 DQ14 A11 DQ7
47 6 49 C550 47 SH_ADRS[11] 2 7 6 43 3 6 SH_DATA2[14]
V S S Q 1 VCCQ4 0.01u/16 A10 DQ14
7 48 SH_ADRS[10] 3 6 7 42 4 5 SH_DATA2[6]
R615 DQ4 DQ13 R635 A9 DQ6 R595
4] 1 8 8 47 1 8 SH_DATA[11] SH_ADRS[9] 4 5 8 41 22 1 8 SH_DATA2[13]
DQ5 DQ12 R574 A8 DQ13
5] 9 46 SH_DATA[10] SH_ADRS[20] 9 40 SH_DATA2[5]
6]
2
3
7
6
C547
0.01u/16
10
VCCQ2 VSSQ3
45
2
3
7
6 SH_DATA[9] SH_ADRS[21]
22 1
2
8
7 10
A19 DQ5
39
2
3
7
6 SH_DATA2[12]
B
DQ6 DQ11 A20 DQ12
7] 4 5 11 44 4 5 SH_DATA[8] SH_ADRS[22] 3 6 11 38 4 5 SH_DATA2[4]
DQ7 DQ10 WE# DQ4
12 43 SH_ADRS[19] 4 5 12 37 C541
47 C551 47 22
VSSQ2 VCCQ3 R E S E T #V C C R596
13 42 0.01u/16 13 36 0.1u/10
22 1 8 SH_DATA2[11]
DQ8 DQ9 A21 DQ11
C548 14 41 SH_WE0/DQMLL R582 22 14 35 2 7 SH_DATA2[3]
0.01u/16 VCC2 VSS2 WP#/ACC DQ3
DQMLL R622 22 15 40 15 34 3 6 SH_DATA2[10]
LDQM NC2 RY/BY# DQ10
R623 22 16 39 R642 47 SH_WE1/DQMLU 16 33 4 5 SH_DATA2[2]
WE UDQM R575 A18 DQ2 R597
R624 47 17 38 R643 22 SH_CLKOUT SH_ADRS[18] 1 8 17 32 22 1 8 SH_DATA2[9]
CAS CLK A17 DQ9
R625 47 18 37 R644 47 SH_CKE SH_ADRS[8] 2 7 18 31 2 7 SH_DATA2[1]
RAS CKE A7 DQ1
M_CS R626 22 19 36 SH_ADRS[7] 3 6 19 30 3 6 SH_DATA2[8]
R616 CS NC1 R636 A6 DQ8
13] 1 8 20 35 1 8 SH_ADRS[12] SH_ADRS[6] 4 5 20 29 4 5 SH_DATA2[0]
BA0 A11 R576 A5 DQ0
14] 2 7 21 34 2 7 SH_ADRS[10] SH_ADRS[5] 22 1 8 21 28 R610 0 22 SH_RD
BA1 A9 A4 OE#
11] 3 6 22 33 3 6 SH_ADRS[9] SH_ADRS[4] 2 7 22 27
A10 A8 A3 VSS1
1] 4 5 23 32 4 5 SH_ADRS[8] SH_ADRS[3] 3 6 23 26 R611 22 SH_FLASH_CS
R617 A0 A7 R637 A2 CE#
2] 1 8 33 24 31 33 1 8 SH_ADRS[7] SH_ADRS[2] 4 5 24 25 R612 22 SH_ADRS[1]
A1 A6 A1 A0
3] 2 7 25 30 2 7 SH_ADRS[6] 22
A2 A5
4] 3 6 26 29 3 6 SH_ADRS[5]
A3 A4
4 5 27 28 4 5
VCC3 VSS1 GNDD
0.01u/16
C549
C540
33 33
0.01u/16
S29GL064N90TFI030-K (SPANSION)
GNDD
label : VRW1773-
GNDD
AXW7015- -J C
MAC Label
ZDX-DURA.DLH-60
R516 220 SH_DATA2[0]
R523 220 SH_DATA2[1]
R526 220 SH_DATA2[2]
R527 220 SH_DATA2[3]
R528 220 SH_DATA2[4]
R529 220 SH_DATA2[5]
R530 220 SH_DATA2[6]
R531 220 SH_DATA2[7]
R524
1 8 SH_DATA2[8]
2 7 SH_DATA2[9]
3 6 SH_DATA2[10]
4 5 SH_DATA2[11]
220
R525
1 8 SH_DATA2[12]
2 7 SH_DATA2[13]
3 6 SH_DATA2[14]
4 5 SH_DATA2[15] D
220
ountermeasure] Simulation
G 8/21
RESET_PHY
8:3I
To LAN INPUT
E
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
: Waveform measuring point 1/8W

1/4W
RS1/8S****J
RS1/4S****J
2W RS2****J
RAB4CQ****J
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
G 9/21
DJM-900NXS 139
5 6 7 8
1 2 3 4
10.22 MAIN ASSY (10/21)
Ether UCOM
IC501
G 12/21 R5S76700B200BG
12:14K V20
EXTAL
20M_CLK_SH
W20
XTAL
From Main CPU R532
SUB_SH_RESET W18
1:4B;9:2H;12:14I RES
0
0.01u/16
G 1/21,9/21,12/21
T20
C552
V+3R3D_LAN
ASEBRK/ASEBRKAK
V17
STBY TCK
R659
R660
R661
JTAG
Y19
V+3R3D_LAN TMS
Y18
NM TRST
GNDD CN501 V18
TDI
W19
V+3R3D 1 TDO
4.7k
4.7k
4.7k
B V+3R3D 2
M2
ASEMD
V+3R3D_LAN
SH_ASEMD 3
SH_TCK 4
W12
SH_TRST 5 USB_X1
R680
JTAG SH_TDO 6
R656
10k
Y12
USB_X2 P
SH_ASEBRK 7 PC0
NM Y8
SH_TMS 8 DM PC0
Y9
SH_TDI 9 DP PC0
SH_RESET 1 0 PC0
W9
GNDD 1 1 VBUS
R662
1k
GNDD 1 2 GNDD
GNDD GNDD
Y7
DV33 P
USB2.0
EtherC
Emulator not use then V+3R3D_LAN U9
Y10
DV12 PC0
AV33 PC0
TCK,ASEMD pull up V+1R2D_LAN U11
470p/50
0.1u/10 AV12
0.1u/10
PC0
C553
C554
C555
U10
TRST pull down UV12 PC0
470p/50
0.1u/10
0.1u/10
0.1u/10
C556
C557
C558
C559
TMS,TDI,TDO open(TMS,TDI internal pull up) W8
U8
DG33
GNDD DG12
W10
AG33 P
V11
GNDD AG12 P
C V10
UG12
GNDD
Y11
REFRIN
V+3R3D_LAN
R667 10k A4
PB00/WAIT/SDA P
Silk print Aside R668 10k C5
[USB_RST] B4
PB01/IOIS16/SCL
Ether UCOM PF01/S
G 11/21 11:9I
USB_CTS_SPI
C4
A3
PB02/CE2B/IRQ0
PB03/CS6/CE1B/IRQ1/DREQ1
IC501
PF02/S
PF03/S
From To USB R673 10k PB04/CE2A/IRQ2/DACK1 PF04/S
11:2K
USB_RESET
R669 10k
R3
PD00/IRQ0/SDDAT0
R5S76700B200BG PF05/S
PF06/ST0_D
From To DSP Silk print Aside

[DSP_RST]
Silk print Aside
[DFLASH_RST]
R671
R674
22
22
P1
P2
PD01/IRQ1/SDDAT1 PF07/ST0
G 15/21 1-26 1-27 R672 22 P3

PD02/IRQ2/SDDAT2
PD03/IRQ3/SDDAT3
PF
PF09/ST0
15:3C N1
DSP_RESET PD04/IRQ4/SDWP PF10/ST0
N2
G 14/21 14:15H
FLASH_DSP_RESET
15:15B
R670 10k
N3
PD05/IRQ5/SDCD PF11/ST0
SPI/UART change
DSP_CTL R677 PD06/IRQ6/SDCMD

10k
M3
STBY PD07/IRQ7/SDCLK P
11:2J R657 NM R675 10k
USB_UART0_RX
11:2J R652 NM P
R676 10k Y15
D USB_UART0_TX
R658
0 22 V14
PE00/ST1_D0/RxD2 P
G 11/21 11:2I R678

USB_MOSI PE01/ST1_D1/TxD1 P
11:2I R653 0 W14
USB_MISO PE02/ST1_D2/RxD1 P
R679 22 V15
From To USB Ucom V+3R3D_LAN

IC505
V+3R3D_LAN
Y13
PE03/ST1_D3/SCK1
PE04/ST1_D4/CTS1
P
P
GNDD W13
5 1
VCC NC NM R654 PE05/ST1_D5/RTS1 P
V13
2
INA NM R655 PE06/ST1_D6/SSIDATA1 P
V12
11:2I 4 3 PE07/ST1_D7/SSIWS1 P
USB_SCK OUTY GND STBY R663 68 Y16
PE08/ST1_REQ/TxD2 P
C510
68 Y14
0.1u/10
TC7SH04FUS1 R664
PE09/ST1_VLD/SCK2 P
W15
PE10/ST1_SYC/CTS2 P
W16
GNDD PE11/ST1_PWM/RTS2 P
P
R665 0 R19
ST0_CLKIN/SSISCK0 P
R666 R20
ST0_VCO_CLKIN P
G 13/21 13:13K
SH_FPGA_TXD2
13:13K
GNDD
R511
10k
0
W17
V16
ST1_CLKIN/SSISCK1
ST1_VCO_CLKIN/AUDIO_CLK
P
PG
To FPGA SH_FPGA_SCK2
Y17
P
ST_CLKOUT
13:4F
6M_CLK_LAN
G 13/21 13:4F
E From FPGA 24M_CLK_LAN
13:4E
96K_CLK_LAN
G 10/21
140 DJM-900NXS
1 2 3 4
5 6 7 8

STB
V+3R3D_LAN
LAN UCOM2
R701
R724
R728
NM
NM
NM
M
R702
R725
R729
0
0
GNDD
BG
T19
MD_BW
V19
MD_CK0
U18
MD_CK1
V+3R3D_LAN
U19 R693
NMI
10k
M1 R694
TESTMD
R18 10k
WDTOVF
8:15H
MII_BUS G 8/21
J2 From LAN INPUT B
LAN_COL
PC14/COL
J3 LAN_CRS 8:15H
PC15/CRS LNKSTA
F1 LAN_TX_CLK
PC13/TX_CLK
H1 R695 33 LAN_TXD[0]
PC04/MII_TXD0
H2 R696 33 LAN_TXD[1]
PC05/MII_TXD1
H3 R697 33 LAN_TXD[2]
PC06/MII_TXD2
G1 R698 33 LAN_TXD[3]
PC07/MII_TXD3
G2
PC11/TX_ER
G3 R699 22 LAN_TXEN
PC12/TX_EN
J1 LAN_RX_CLK
PC10/RX_CLK
L1 LAN_RXD[0]
PC00/MII_RXD0
L2 LAN_RXD[1]
PC01/MII_RXD1
L3 LAN_RXD[2]
PC02/MII_RXD2
K1 LAN_RXD[3]
PC03/MII_RXD3
K3 LAN_RXER
PC09/RX_ER
K2 LAN_RXDV
PC08/RX_DV
Silk print Aside[UOUT1_RST]

Silk print Aside[DIR_RST]
E1
PC18/LNKSTA
E2
PC19/EXOUT
PC20/WOL
E3
C
V+3R3D
F2 R700 22 LAN_MDIO
PC16/MDIO
F3 LAN_MDC C560
PC17/MDC 1 0.1u/10
VCC 5
V+3R3D_LAN 2 To DIGITAL_IN_1
G 4/21-7/21
R730
3 4 GNDD 22
4:3E;5:3E;6:3E;7:3E DIGITAL_IN_2
GND DIR_RESET
DIGITAL_IN_3
R726
DIGITAL_IN_4
R727
4.7k
4.7k
GNDD IC504
G 4/21
N20
PF00/ST0_D0 TC7SH08FUS1
N18 Silk print Aside
PF01/ST0_D1/TxD0 4:3J
M18
RS232C_TxD USBOUT1_SRC_RESET To DIGITAL_IN_1
PF02/ST0_D2/RxD0
PF03/ST0_D3/SCK0
M19
M20
Silk print Aside
RS232C_RxD
5:3J
USBOUT2_SRC_RESET
6:3J
USBOUT3_SRC_RESET
To DIGITAL_IN_2
To DIGITAL_IN_3
G 5/21
PF04/ST0_D4/CTS0 7:3J
G PF05/ST0_D5/RTS0
PF06/ST0_D6/SSIDATA0
L18
L19 R703 68
Silk print Aside[LA NIN]
(LINK IN)
USBOUT4_SRC_RESET
15:15H
ADAT_LANIN
To DIGITAL_IN_4
To DSP_2
G 6/21
G 7/21
L20 R704 0
G 15/21
PF07/ST0_D7/SSIWS0
P19 R714 22 12:14B
PF08/ST0_REQ CK_MODE
P20 R715 22 12:14J
PF09/ST0_VLD/DREQ0 SH_CTRL
To Main Ucom
G 12/21
N19
PF10/ST0_SYC/DACK0
P18
PF11/ST0_PWM/TEND0
1-28
G 13/21
W4 R716 22
PG00/HIFD00
PG01/HIFD01
R681
V4
R682
10k
10k
R705 22
13:13K
SH_FPGA_RST_X To FPGA
Y3
PG02/HIFD02 R683 10k
R717 22 4:3B
CH1SRC_RESET D
PG03/HIFD03
W3
R684
V3
10k
R718
R706
22
22
5:3B
CH2SRC_RESET
6:3B
To DIGITAL IN
PG04/HIFD04 R685 10k CH3SRC_RESET
PG05/HIFD05
PG06/HIFD06
Y2
W2
R686 10k
R707 22
7:3B
CH4SRC_RESET G 4/21-7/21
V1 R708 22
PG07/HIFD07
PG08/HIFD08
R687
Y1
R688
U1
10k
10k
R709
R710
22
22
1:5G;17:2F;21:2E
DIR_ADC_DAC_RESET
16:3C
G 1/21,17/21,21/21
PG09/HIFD09 R689 DIT_RESET
10k
To DOUT G 16/21
U2 R711 22 16:3E
PG10/HIFD10 DOUT_MS_SEL
T1 16:3D
PG11/HIFD11 DOUT_SRC_RESET
T2
PG12/HIFD12
T3 11:9H
PG13/HIFD13
PG14/HIFD14
R1
USB_ERR_SH
11:2I
From To USB Ucom
HWAIT
PG15/HIFD15
PG16/HIFEBL
R2
W7
R719
R720
22
22
11:9I
USB_RTS_SPI G 11/21
V6 R712 22 4:3J
PG17/HIFRDY USBOUT_CK_SW
G 4/21
R690 10k
PG18/HIFDREQ
W6
Y6
R721 22 4:3J
USBOUT_SRC_MS_SEL To DSP
PG19/HIFINT
Y5 R722 22
PG20/HIFRD
W5 R723 22 13:13K
PG21/HIFWR R691 SH_FPGA_DONE
10k
PG22/HIFRS
PG23/HIFCS
V5
R692
Y4
10k
R713 22 13:4C
SH_FPGA_XPGM
13:13K
SH_FPGA_XINIT
To FPGA G 13/21
GNDD E
1-29 1-30
Silk print Aside[DSRC_RST]
Silk print Aside[DIT_RST]
Silk print Aside[AD/DA_RST]
Silk print Aside[UI N4_RST]
Silk print Aside[FPGA_RST]
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
RAB4CQ****J
CKSRYB****
CKSSYB**** (LINK IN)
CH CCSRCH****
CCSSCH****
: LINK AUDIO INPUT
CCSQCH****
+
CEVW*** F
+
HA CEHVAW**
NP CEVWNP*** : Waveform measuring point
G 10/21
DJM-900NXS 141
5 6 7 8
1 2 3 4
10.23 MAIN ASSY (11/21)
USB UCOM
A Silk print Aside
[V+1R2D_USB] IC1801
V+1R2D V+1R2D_USB
L1802
V+1R2D_USB 1-31 ADSP-BF524BBCZ-3A
QTL1013-A
G12 A1
VDDINT1 VSS1
DCH1201-A
1608size G13 A17

10u 10V
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
VDDINT2 VSS2
470p/50
0.1u/10
G14 A20
STBY VDDINT3 VSS3
H14 B20
C1802
VDDINT4 VSS4
0.1u/10
C1804
NM
J14 H9
VDDINT5 VSS5
C1805
C1807
C1809
C1824
C1826
C1830
C1834
C1837
C1840
C1843
C1847
K14 H10
VDDINT6 VSS6
L14 H11
VDDINT7 VSS7
M14 H12
GNDD
Silk print Aside VDDINT8 VSS8
[V+3R3D_USB] N14 H13
V+3R3D V+3R3D_USB VDDINT9 VSS9
L1801
QTL1013-A R1804
1-32 V+3R3D_USB
P12
VSS10
J9
J10
VDDINT10 VSS11
1608size 0 P13 J11
10u 10V
VDDINT11 VSS12
470p/50
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
P14 J12
DCH1201-A
VDDINT12 VSS13 R1835

STBY USB_ADRS[1] W20
F19 J13 ADDR1
C1801
VDDEXT1 VSS14 4 5
0.1u/10
C1803
USB_ADRS[2] W19
NM
G7 K9 ADDR2
VDDEXT2 VSS15 3 6 Y19
C1806
C1808
C1810
C1825
C1828
C1832
C1835
C1838
C1841
C1845
C1849
C1851
C1855
C1858
K10
USB_ADRS[3]
G8 ADDR3
VDDEXT3 VSS16 2 7 W18
K11
USB_ADRS[4]
G9 ADDR4
VDDEXT4 VSS17 R1836 1 8
USB_ADRS[5] 120 Y18
G10 K12 ADDR5
VDDEXT5 VSS18 4 5
Power Suply
USB_ADRS[6] W17
G11 K13 ADDR6
VDDEXT6 VSS19 3 6
B GNDD V+3R3D_USB_MEM H7
VDDEXT7 VSS20
L9
USB_ADRS[7]
USB_ADRS[8]
2 7
Y17
W16
ADDR7
H8 L10 ADDR8
R1806 VDDEXT8 VSS21 1 8 R1837 Y16
120
J7 L11 ADDR9
0 VDDEXT9 VSS22 4 5 W15
L12
USB_ADRS[9]
J8
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
ADDR10
USB_ADRS[10]
DCH1201-A
K7 L13 ADDR11
VDDEXT11 VSS24 2 7
10V
1-33 K8 M9
USB_ADRS[12] W14
C1822
ADDR12
120
L7 M10 ADDR13
C1846
C1850
C1852
C1856
C1859
V+3R3D_
10u
VDDEXT13 VSS26 W13

M11 ADDR14
VSS27
USB_MEM L8
VDDMEM1 VSS28
M12
Y13
ADDR15
W12
M7 M13 ADDR16
VDDMEM2 VSS29 Y12
V+3R3D_USB_IF GNDD M8 N9 ADDR17
VDDMEM3 VSS30 W11
USB_ADRS[18] R1846 47
N7 N10 ADDR18
R1807 VDDMEM4 VSS31
USB_ADRS[19] R1847 47 Y11
N8 N11
CH
ADDR19
CH
CH
0 VDDMEM5 VSS32 K20

USB_S_CLK R1848 47
P7 N12 CLKOUT
VDDMEM6 VSS33
C1813 1000p/50
100p/50
100p/50
USB_S_CKE R1849 56 P20

P8 N13 SCKE
VDDMEM7 VSS34 R19
USB_S_MS R1850 56
P9 Y1 SMS
VDDMEM8 VSS35 T19
USB_S_RAS R1851 56
P10 Y20 SRAS
VDDMEM9 VSS36
C1853
C1857
USB_S_CAS R1852 56 U20

P11 SCAS
0.1u/10
VDDMEM10 T20
USB_S_WE R1853 56
SWE
GNDD USB_S_ABE[0] R1854 56 V19
D19 ABE0/SDQM0
VDDUSB1 V20
USB_S_ABE[1] R1855 56
G20 ABE1/SDQM1
C1844
GNDD VDDUSB2
USB_S_SA10 R1856 120 U19
SA10
A16
V+2R5D V+2R5D_USB_PLL VDDRTC
C
R1817 R20
STBY VDDOTP
DCH1201-A
0 L19
C1814
C1848
C1854
VPPOTP
0.1u/10
0.1u/10
C1827
NM
10V
10u
Silk print Aside

1-34 V+2R5D_UPLL
[V+2R5D_UPLL]
GNDD
Oscillator
24MHz
STBY Silk print Aside
R1808
[24M_CLK_USB] USB UCOM
NM
1-35
R1818
1k
X1801
4 3
X2
GND2
22
D IC1801
G 4/21-7/21
1 2
GND1
X1
ADSP-BF524BBCZ-3A
R1820
C1811
C1820
12p/50
10p/50
DSS1203-A
(CH1 U/D OUT) 24MHz
CH
CH
4:15I A11
From DIGITAL IN_1
RTC
Clock
ADAT_UDOUT1 CLKIN
5:15I
(CH2 U/D OUT) A10 A14 R1822
From DIGITAL IN_2 ADAT_UDOUT2
(CH3 U/D OUT)
XTAL RTXI
10k
6:15I GNDD C19 A15
(CH4 U/D OUT) F1
CLKBUF RTXO
A7
GNDD
7:15I PF0/PPI_D0/DR0PRI_/ND_D0A PH0/ND_D0/HOST_D0
4:15K E1 B7
96K_CLK_USB PF1/PPI_D1/RFS0/ND_D1A PH1/ND_D1/HOST_D1 12:14F
E2 A8 R1823 22 USB_ERR_
From DIGITAL IN_1 6M_CLK_USB
4:15J PF2/PPI_D2/RSCLK0/ND_D2A PH2/ND_D2/HOST_D2
4:3E (CH1 U IN) R1809 22 D1 B8 R1824 22
ADAT_USBIN1 PF3/PPI_D3/DT0PRI/ND_D3A PH3/ND_D3/HOST_D3
5:3F (CH2 U IN) R1810 22 D2 A9 10:15I
From DIGITAL IN_2 ADAT_USBIN2
(CH3 U IN) R1811 22 C1
PF4/PPI_D4/TFS0/ND_D4A/TACLK0 PH4/ND_D4/HOST_D4
B9
USB_ERR_
6:3F
(CH4 U IN) R1812 22 C2
PF5/PPI_D5/TSCLK0/ND_D5A/TACLK1 PH5/ND_D5/HOST_D5
B10
Port H
7:3F
Port F
PF6/PPI_D6/DT0SEC/ND_D6A/TACI0 PH6/ND_D6/HOST_D6
B1 B11
PF7/PPI_D7/DR0SEC/ND_D7A/TACI1 PH7/ND_D7/HOST_D7
B2 A12 TEST
V+3R3D_USB PF8/PPI_D8/DR1PRI PH8/xSPISEL4/HOST_D8/TACLK2
A2 B12
PF9/PPI_D9/RSCLK1/xSPISEL6 PH9/xSPISEL5/HOST_D9/TACLK3
R1801
STBY
B3 A13
NM
PF10/PPI_D10/RFS1/xSPISEL7 PH10/xND_CE/HOST_D10
A3 B13
PF11/PPI_D11/TFS1/CZM PH11/xND_WE/HOST_D11
V+3R3D_USB B5 B14
R1802
PF12/PPI_D12/DT1PRI/xSPISEL2/CDG PH12/xND_RE/HOST_D12
10k
A5 B15
PF13/PPI_D13/TSCLK1/xSPISEL3/CUD PH13/xND_BUSY/HOST_D13
R1805
B6 B16 10
R1803
STBY
10k
PF14/PPI_D14/DT1SEC/UART1TX PH14/ND_CLE/HOST_D14 U
NM
R1830 22
SPI Master=SH2A,Slave=BF GNDD A6 B17 10
PF15/PPI_D15/DR1SEC/UART1RX/TACI3 PH15/ND_ALE/HOST_D15
U
R1825
R1826
R1829
10:15I R1813 47 R2 F2
10k
10k
10k
HWAIT PG0/HWAIT PPI_FS1/TMR0 V+3R3D_USB

Port J
P1 G2
E 10:2H P2
PG1/xSPISS/xSPISEL1 PPI_CLK/TMRCLK
A4
PG2/SCK SCL
R1827
R1831
R1832
R1833
STBY
USB_SCK
G 10/21
NM
NM
NM
NM
10:2H R1814 22 N1 B4
USB_MISO PG3/MISO/DR0SECA SDA
10:2H N2 V2
USB_MOSI PG4/MOSI/DT0SECA TCK
From LAN_Ucom M1
PG5/TMR1/PPI_FS2 TDO
T1
JTAG
M2 R1
PG6/DT0PRIA/TMR2/PPI_FS3 TDI
Port G
10:2H R1815 22 L1 U2
PG7/TMR3/DR0PRIA/UART0TX TMS
USB_UART0_TX U1
10:2G L2
PG8/TMR4/RFS0A/UART0RX/TACI4 TRST
USB_UART0_RX K1 T2
From Main_Ucom R1838

K2
PG9/TMR5/RSCLK0A/TACI5
PG10/TMR6/TSCLK0A/TACI6 EXT_WAKE0
EMU
J20
Regulation
MIDI_TXD_USB J1
R1834
PG11/TMR7/xHOST_WR
4.7k
0
Voltage
12:14F
V+3R3D_USB R1816 33 J2 H20
PG12/DMAR1/UART1TXA/HOST_ACK EXT_WAKE1
G 12/21
I/F
H1
PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2
IC1803 R1828 22 H2 G19 R1879 GNDD
1 C1812 PG14/TSCLK0A1/xHOST_RD PG
VCC 5 G1 10k
2 PG15/TFS0A/HOST_CE
NM GNDD
V+3R3D_USB Y10
GNDD
R1839 BMODE0
3 4
GND R1819 B19 W10
USB_RESET NMI BMODE1
NM 10k B18 Y9
GNDD NM RESET Mode Control BMODE2
W9
BMODE3
STBY
0.01u/16
C1831
12:14F
G 12/21 USB_UART1_TXA V+3R3D_USB

8
12:14F
R1821
USB_UART1_RXA
10k
12:14F
F From Main_Ucom USB_REQ GNDD

2
4
1
12:14F
USB_RCV
10:2G
1-36
From LAN_Ucom USB_RESET
G 10/21 GNDD
G 11/21
142 DJM-900NXS
1 2 3 4
5 6 7 8
USB
USB UCOM
IC1801 SDRAM 64M

ADSP-BF524BBCZ-3A V+3R3D_USB_MEM
IC1802
DATA0
Y8 1
R1861
8 USB_DATA[0] IS42S16400F-6TL
W8 2 7 USB_DATA[1]
DATA1
Y7 3 6 USB_DATA[2] C1862 1 54
DATA2 R1882 0.01u/16 R1902
VDD1 VSS3 53
W7 4 5 USB_DATA[3] USB_DATA[0] 1 8 2 1 8 USB_DATA[15]
DATA3 R1862 DQ0 DQ15
Y6 47 1 8 USB_DATA[4] USB_DATA[1] 2 7 C1863 3 52 2 7 USB_DATA[14]
DATA4 0.01u/16 V D D Q 1 VSSQ4
W6 2 7 USB_DATA[5] USB_DATA[2] 3 6 4 51 3 6 USB_DATA[13]
Data Bus
DATA5 DQ1 DQ14

Y5 5 50
B
Address Bus
3 6 USB_DATA[6] USB_DATA[3] 4 5 4 5 USB_DATA[12]

DATA6 DQ2 DQ13
W5 4 5 USB_DATA[7] 47 6 49 C1867 47
DATA7 R1863 VSSQ1 VDDQ4 0.01u/16
Y4 1 8 47 USB_DATA[8] 7 48
DATA8 R1883 DQ3 DQ12 R1903
0 DATA9 DQ4 DQ11
Y3 3 6 USB_DATA[10] USB_DATA[5] 2 7 C1864 9 46 2 7 USB_DATA[10]
1 DATA10 0.01u/16 VDDQ2 VSSQ3
2 DATA11 R1864 DQ5 DQ10
Y2 47 1 8 USB_DATA[12] USB_DATA[7] 4 5 11 44 4 5 USB_DATA[8]
3 DATA12 DQ6 DQ9
W2 2 7 USB_DATA[13] 47 12 43 C1868 47
4 DATA13 VSSQ2 VDDQ3 0.01u/16
W1 3 6 USB_DATA[14] 13 42
5 DATA14 DQ7 DQ8
V1 4 5 USB_DATA[15] C1865 14 41
6 DATA15 0.01u/16 VDD2 VSS2
47 USB_S_ABE[0] R1890 47 15 40
7 LDQM NC2
USB_S_WE R1891 47 16 39 R1910 47 USB_S_ABE[1]
8 /WE UDQM
USB_S_CAS R1892 47 17 38 R1911 47 USB_S_CLK
9 /CAS CLK
J19 USB_S_RAS R1893 47 18 37 R1912 47 USB_S_CKE
UT AMS0 /RAS CKE
K19 19 36
SDRAM Controller
USB_S_MS R1894 47
AMS1 R1884 /CS NC1 R1904
M19 USB_ADRS[18] 1 8 20 35 1 8 USB_ADRS[12]
AMS2 BA0 A11
AMC
L20 USB_ADRS[19] 2 7 21 34 2 7 USB_ADRS[10]

AMS3 BA1 A9
N19 USB_S_SA10 3 6 22 33 3 6 USB_ADRS[9]
AWE A10/AP A8
M20 USB_ADRS[1] 4 5 23 32 4 5 USB_ADRS[8]
ARE R1885 A0 A7 R1905
N20 USB_ADRS[2] 1 8 120 24 31 120 1 8 USB_ADRS[7]
SDQM0 AOE A1 A6
P19 USB_ADRS[3] 2 7 25 30 2 7 USB_ADRS[6]
SDQM1 ARDY A2 A5
USB_ADRS[4] 3 6 26 29 3 6 USB_ADRS[5]
A3 A4
4 5 C1866 27 28 4 5
0.01u/16 VDD3 VSS1
120 120
C
GNDD
NOTES
(CH1 U IN)
is STBY
: CH1 USB Input Signal NM
RS1/16S****J
(CH2 U IN) RS1/10S****J
: CH2 USB Input Signal RN RN1/16S****J

RN1/10S****J
(CH3 U IN) (D) RS1/16S****D
RS1/10S****D
STBY (TEST LED) : CH3 USB Input Signal (F) RS1/16S****F

RS1/10S****F
(CH4 U IN)
1/8W RS1/8S****J
: CH4 USB Input Signal 1/4W RS1/4S****J
ERR WD (CH1 U/D OUT) 2W RS2****J
V+3R3D_USB
(CH2 U/D OUT) RAB4CQ****J
R1857 R1859
: CH2 USB/DIGITAL Output Signal D
NM NM (CH3 U/D OUT) CKSRYB****
Silk print Aside Silk print Aside

: CH3 USB/DIGITAL Output Signal CH
CKSSYB****
CCSRCH****
[ERR] [WD] CCSSCH****
D1801 D1802 (CH4 U/D OUT) CCSQCH****
NM NM
: CH4 USB/DIGITAL Output Signal +
CEVW***
(USB IN/OUT) +
Q1801 Q1802 HA CEHVAW**
NM NM
: USB IN/OUT
2
2
12:14F
USB_ERR_MAIN To MainUCOM G 12/21 NP CEVWNP***
GNDD
10:15I
USB_ERR_SH To LAN_Ucom G 10/21
USB UCOM V+5VBUS
IC1801
CN3801
R1830 22
10:2G
USB_CTS_SPI
G 10/21 ADSP-BF524BBCZ-3A
AKM1276-A
CN1802
(USB IN/OUT)
10:15I
USB_RTS_SPI From LAN_Ucom A19
USB_XI USB_VBUS
E19 R1877
STBY
1 GNDD
10k
V+3R3D_USB 2 GNDD
A18 0 L1803
USB_XO
E20
USB_D+ R1880 NM
1 2
3 D-USB E
USB_DP
D+USB
R1831
R1832
R1833
USB_D- NM 4
STBY D20 F20 R1881
NM
NM
NM
NM
USB_RSET UDB2.0 HS OTG USB_DM 4 3 5 V+5VBUS

H
NM
CH N M
C1815
C1816
C1869
2p/50
2p/50
V+3R3D_USB H19 C20

NM STBY USB_VREF USB_ID STBY
CN1801 (USB IN/OUT)
R1878
NM
R1858
C1861
0.1u/10
STBY
NM
1 V+3R3D V+3R3D_USB GNDD GNDD

2 V+3R3D
3 BF_EMU
USB_ID use OTG
4 BF_TMS not use then opne 1-37 V+5VBUS
JTAG
R1834
5 BF_TCK GNDD
4.7k
6 BF_TRST USB_RSET,USB_VREF use test mode 18

7 BF_TDI not use then
GNDD
BF_TDO
USB_RSET opne
8
USB_VREF 0.1uF(GND)
9 GNDD
10 GNDD
GNDD
USB
: Voltage measuring point
: Waveform measuring point F
G 11/21
DJM-900NXS 143
5 6 7 8
1 2 3 4
10.24 MAIN ASSY (12/21)

NOTES
A G 12/21 MAIN ASSY (DWX3190) RN

NM
is STBY
RS1/16S****J
RS1/10S****J
RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
MAIN CPU (F)
1/8W
RS1/16S****F
RS1/10S****F
RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
RAB4CQ****J
: Waveform measuring point CKSRYB****

CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
G 1/21 NP CEVWNP***
From BOARD IF 1:4B

BF_SW
DITD_CS
16:3B
DIT_TXD
B From To DIGITAL OUT 16:3B

DIT_RXD
16:3B
G 16/21
DIT_SCK
16:3B
CBC_INT
CDC c
G 2/21
From POWER IF P-CON
2:8H
STBY(TEST LED)
V+3R3D V+3R3D
R2022
NM
22k
V+3R3E
C D2004
NM
R2028
G 17/21,21/21 Low MUTE Silk print Aside
NM
Q2002
High MUTE release [CPU_MUTE] LTA124EUB DBG_PORT1
To OUTPUT IF Block CPU_MUTE
17:2C;21:2G
R2014 Q2001
1-38 DBG_PORT0
22
HP AMP Block V+3R3E
C2007
GNDD
CN2001 Low MUTE release
NM D2001 D2002 D2003 NM
High MUTE
GNDD
V+3R3D 1 R2026 10k
NM NM NM
debugger
RESET_OUT 2
RESET_IN 3
R2027 10k
RxD 4
R
FLMDO 5
C2017 R
CLK_IN 6 0.01u/16 GNDD
GNDD 7
R
GNDD Silk print Aside[V+3R3D_M]
C2022
STBY V+3R3D
1u/10
V+3R3E V+3R3E_M
G 1/21
R2015
C2023
100k
0.1u/10
R2024 R2025 C2024
1:5G
From BOARD IF Block RETURN_IN
V+3R3E
0 0 0.1u/10
DCH1201-A
Silk print Aside
D C2018
1 0 u 10V
C2021
[CPU_RST] 0.01u/16 GNDD
C2019
C2020
NM
NM
R2021
1-39 STBY
47k
R2023
From POWER _IF 2:8H;3:2F
PowerReset
R2061 470k
POWER NM
RESET IC STBY
0.01u/16
C2036
IC2010
G 2/21,3/21 V+3R3E 1
OUT CD
5
V+3R
R2043
2
1500p/50
C2016
VDD
C2015
3 4
1u/10
VSS NC
Oscillator
V+3R3D
S-80927CNMC-G8X
R2063
R2001
GNDD GNDD
0
0 V
C2008
0.1u/10
V+3R3D
IC2003
C2001
IC2001
0.1u/10
1-40
1 NC 5 1 VCC 5
Vcc Silk print Aside C2010
pull up
2 INA 2
[20M_CLK] 1 0.1u/10
GNDD VCC 5
R2007 R2009
3 4 3 4 2
GND R2019
GND0 OUTY 22 3 4 GNDD 22
0
Digi Tr drive
GND
TC7SHU04FUS1 TC7SH08FUS1
GNDD R2003 GNDD
GNDD IC2005
R2005
1M TC7SH08FUS1
STBY
1.5k
X2001
4 3 V+3R3D
GND2 X2
R2059
1-41
0
C2011
1 2
E X1 GND1 1 VCC 5
NM
C2003
C2005
12p/50
12p/50
R2010
CH
CH
CSS1795-A 2
20MHz R2020
3 4 GNDD 22
NM
GND
GNDD GNDD
IC2006
GNDD NM
20MHz(MAIN/SH) STBY then , SH CLK supply off

V+3R3D
Oscillator Silk print Aside

[24.576M_CLK]
V+3R3D 1-42 1 VCC 5

C2012
0.1u/10
R2011 2
R2016
R2002
0 3 4 GNDD 0
0
GND
IC2007
C2009
0.1u/10
GNDD
IC2002
C2002
IC2004
0.1u/10
TC7SH08FUS1
1 5 1 VCC 5
NC Vcc V+3R3D
2 2
GNDD
INA R2008
3 4 3 4
GND C2013
GND0 OUTY 0.1u/10
22 1 VCC 5
TC7SHU04FUS1 TC7SH08FUS1 R2012 2
GNDD R2004 GNDD R2017
0 3 4 GNDD 22
R2006
1M GND
1k
X2002
4 3 IC2008
GND2 X2 GNDD
TC7SH08FUS1
V+3R3D
F 1
X1 GND1
2
C2004
C2006
12p/50
12p/50
C2014
CH
CH
DSS1204-A
24.576MHz 1 0.1u/10
VCC 5
R2013 2
R2018
GNDD GNDD 0 3 4 GNDD 22
G 12/21
GND
24.576MHz(DSP/FPGA) GNDD IC2009

TC7SH08FUS1
144 DJM-900NXS
1 2 3 4
5 6 7 8
1:4B
STBY_KEY
From BOARD IF Block
G 1/21 G 1/21 A
1:4C
SUB_INT
From BOARD IF (Sub CPU)
10:15G
CK_MODE
4:3H
To LAN Ucom G 10/21
TC_OUT_SEL1
5:3H
To DIGITAL_IN1
TC_OUT_SEL2 To DIGITAL_IN2
6:3H
TC_OUT_SEL3 To DIGITAL_IN3
7:3H
To DIGITAL_IN4
TC_OUT_SEL4
4:3E
DIG_SEL1 From DIGITAL_IN1
G 4/21-7/21
5:3E
DIG_SEL2
From DIGITAL_IN2
6:3E
DIG_SEL3
From DIGITAL_IN3
7:3E
DIG_SEL4
From DIGITAL_IN4
1:4B
VR_FADER_CRS
1:4D
G 1/21
VR_FADER4
1:4D
VR_FADER3 From BOARD IF
1:4C
VR_FADER2
1:4C
VR_FADER1
G 3/21
3:7B
VDET From POWER
1:10G
VR_TRIM4
1:10G
VR_TRIM3
1:10H
VR_TRIM2
1:10G
VR_TRIM1
V+3R3D_REFA
IC2012
TC74HC4052AFT
B
C2035
0.1u/10
VR_TRIM1 1 16
0Y VCC
VR_TRIM2 2 15
2Y 2X
3
Y_COM 1X
14
From BOARD IF Block
DBG_PORT2
4 13 R2090
CBC_SCK
3Y X_COM
CBC_INT
G 1/21
CBC_SO
CBC_CS
VR_TRIM3 5 12
CBC_SI
1Y 0X 100k
VR_TRIM4 6 11
INH 3X
CDC control STB 7 10
VEE A
R2082 8 9
VR_TRIM
GND B
100k
1:10G
GNDREF_A GNDREF_A MIDI_TXD
560
100 R2062 1:4B

330 R2064
330 R2066
330 R2068
330 R2070
R2058
V+3R3E STBY_LED
Silk print Aside

[V+3R3D_REFA]
R2031
R2056
C2025 470p/50
10k
100
V+3R3D_REFA V+3R3D
C2026 470p/50
470p/50 L2001
C2027
22
22
22
22
LCTAW330J2520
0
C2028 470p/50
33u
R2040
R2042
R2069
470p/50
10k
C2029
R2074
C2033
C2034
0.1u/10
10k
NM
R2033
R2034
R2035
R2036
R2046
R2048
R2050
R2053
0
470p/50 Q2003
V+3R3D STBY C2030
22
22
22
22
LTC124EUB
R2038
C2040 C2031 470p/50

10k
R2045
R2047
R2049
R2052
STBY
10k R2060
NM
22
22
22
22
R2089
0
22k
R2029 10k
GNDREF_A
C
R2028
Silk print Aside

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
R2030 10k [GNDREF_A]

AVSS
R2080
P130
P01/TO00
81 50
P04/xSCK10/SCL1
P02/SO10/TxD1
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P157/ANI15
DBG_PORT1 P120/INTP0/EXLVI GNDD

P131/TI06/TO06
P03/SI10/RxD1/SDA1
49 10k R2079 100

82
DBG_PORT0 P47/INTP2
83 48 R2081 100
P46/INTP1/TI05/TO05
84 47 R2073
P45/SO01
AVREF0 46 0
85
P44/SI01 P111/ANO1 P10/EX24/xSCK00
P110/ANO0 45 11:9H
86
AVREF1
G 11/21
P43/xSCK01 P11/EX25/Si00/RxD0 USB_ERR_MAIN
R2077
P142/xSCK20/SCL2
P144/SO20/TxD2
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
44
P00/TI00
R2026 87 R2085 22 11:2J

P145/TI07/TO07
10k
P143/SI20/RxD2/SDA2
P42/TI04/TO04 P12/EX26/SO00/TxD0 MIDI_TXD_USB

43
88
89
P41/TOOL1
IC2011 P13/EX27/TxD3
42
R2086 22 0 11:2K
USB_UART1_RXA
11:2K
From To USB UCOM
P122/X2/EXCLK
R2027 10k
90
P40/TOOL0
xRESET
DYW1799- /J P15/EX29/RTCDIV/RTCCL
P14/EX28/RxD3
41 R2087 22
USB_UART1_TXA
11:2K
USB_RCV
R2110 10k 91 40
11:2K
P124/XT2 UCOM UPD78F1166AGF-GAS-K P16/EX30/TI01/TO01/INTP5
USB_REQ
R2111 10k 92 39 22
R2088
P123/XT1 Label VRW1773- P17/EX31/TI02/TO02
38
93
FLMD0 P57/EX15
94
MAIN_CPU P56/EX14
37
P30/INTP3/RTC1HZ
P77/EX23/KR7/INTP11
P76/EX22/KR6/INTP10
P31/TI03/TO03/INTP4
R2112 10k 95
P75/EX21/KR5/INTP9
P74/EX20/KR4/INTP8
Silk print Aside[V+3R3D_M] 36

P86/EX6
P87/EX7
P121/X1 P55/EX13
1:4C
To BOARD IF(SUB CPU)
EVDD1
C2022 96 VSS 35
SUB_CTRL
REGC EVSS0 P54/EX12
34
P73/EX19/KR3
P72/EX18/KR2
P71/EX17/KR1
P70/EX16/KR0
1u/10 97 VDD
P05/CLKOUT
G 1/21
EVDD0 P53/EX11
33
P06/xWAIT
98 P52/EX10
P65/xWR0
P66/xWR1
P61/SDA0
P67/ASTB
P60/SCL0
V+3R3E V+3R3E_M P51/EX9

P64/xRD
P80/EX0
P81/EX1
P82/EX2
P83/EX3
P84/EX4
P85/EX5
C2023 99 32
P50/EX8
EVSS1
0.1u/10 100 31
P62
P63
R2025 C2024
0 0.1u/10
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DCH1201-A
1 0 u 10V
D
C2021
C2019
C2020
NM
NM
8
7
6
5
R2075
8
6
5
BY
22
22
22
C2032
0.1u/10
22
R2054
22
0.01u/16
C2039
V+3R3E_M
2
3
4
1
GNDD
8
7
6
5
2
3
4
1
R2076
8
7
6
5
R2037
R2039
R2041
R2043
22
R2072
R2057
10k
10k
22
3
4
1
R2078
MCPU_DATA[5] 2
MCPU_DATA[6] 3
MCPU_DATA[7] 4
MCPU_DATA[4] 1
MCPU_DATA[10]
MCPU_DATA[11]
MCPU_DATA[12]
MCPU_DATA[13]
MCPU_DATA[14]
MCPU_DATA[15]
MCPU_DATA[0]
MCPU_DATA[1]
MCPU_DATA[2]
MCPU_DATA[3]
MCPU_DATA[8]
MCPU_DATA[9]
470k
MCPU_ASTB
MCPU_WR0
MCPU_RD
V+3R3D
2.2k
5 4
MCPU_BUS
13:4B To FPGA G 13/21
R2071
V+3R3D
22
6 3
Digi Tr drive , pull up
R2055
7 2 8 1 STBY
8 1 7 2
G 1/21
C2037
CH_TC_SELCT
To BOARD IF
NM
R2032
LINE_SEL1
LINE_SEL2
LINE_SEL3
LINE_SEL4
6 3 1:5G
R2067 0
TC_SEL4
TC_SEL3
TC_SEL2
TC_SEL1
5 4
10k GNDD V+3R3D
IC2013
G 1/21,9/21,10/21
Silk print Aside
C2038 [SUB_SH_RST]
1 VCC 5
2 NM 1-43
R2065
GNDD
To BOARD IF(SUB CPU) E
R2051
3 4 SUB_SH_RESET
10k
GND
NM
1:4B;9:2H;10:2C LAN_UCOM1
8
7
6
5
LAN_UCOM2
R2044
GNDD NM
10k
STBY
GNDD
From LAN_UCOM2 G 10/21
2
3
4
1
SH_CTRL
10:15G
FL_Vcont
To POWER
GNDD 3:2G
G 3/21
DSP_LINT
15:3B
DSP_MINT
15:3B
DSP_HINT
15:3B
From DSP G 15/21
10:2C
20M_CLK_SH
To LAN_UCOM2 G 10/21
15:3E
24M_CLK_DSP To DSP_2 G 15/21
13:15B
24M_CLK_FPGA To FPGA G 13/21
4:3I
24M_CLK_USB To DIGITAL_IN1 G 4/21
F
G 12/21
DJM-900NXS 145
5 6 7 8
1 2 3 4
10.25 MAIN ASSY (13/21)

V+3R3D_FPGA Silk print Aside
[V+3R3D_FPGA]
Silk pr
V+3R3D V+3R3D_FPGA V+1R2D V+1R2D_FPGA [V+1
R2239
1-50 R2268
A 0 0
C2214
C2215
C2216
C2218
C2220
C2222
C2224
C2226
C2228
C2229
C2230
C2231
C2235
C2237
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
47u/16
47u/16
V+3R3D_FPGA_A
GNDD GNDD R2280
C2217
C2219
C2221
C2223
C2225
C2227
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0.1u/10
0
C2234
C2236
0.1u/10
0.1u/10
STBY
R2276 R2281
GNDD
NM 10k
GNDD
From To BOARD IF(SUB_CPU) SUB_UCOM

1:4C
FPGA RXD DAT

G 1/21
From To MAIN_CPU MCPU_BUS
G 14/21 12:14I
From To DSP_1
G 12/21
DSP_BUS
14:15C R2311
DSP_DATA[3] FDSP_DATA[3]
FDSP_ADRS[3]
FDSP_ADRS[4]
FDSP_ADRS[5]
FDSP_ADRS[6]
FDSP_ADRS[8]
FDSP_ADRS[9]
8
FDSP_ADRS[13]
FDSP_ADRS[15]
FDSP_ADRS[14]
1
2 7
From LAN_UCOM_1 SH_FPGA_XPGM
10:15I
DSP_DATA[1] 3 6 FDSP_DATA[1] V+3R3D
DSP_DATA[0] 4 5 FDSP_DATA[0]
G 10/21 STBY
22
0
22 C2211
NM 5 VCC 1
R2321
R2267
B DSP_DATA[11]
DSP_DATA[10]
1
2
8
7
FDSP_DATA[11]
FDSP_DATA[10]
R2221
2 R2233 FPGA
GNDD NM 4 3 47
96K_CLK_SRC
DSP_DATA[9]
DSP_DATA[8]
3
4
6
5
FDSP_DATA[9]
FDSP_DATA[8]
4:3G;16:2F GND
IC2214
NM I C 2 2 1 1
GNDD
22
R2330 R2225 0
V+3R3D
XC3S50A-4FTG256C
STBY
C2212
DSP_DATA[5] 3 6 FDSP_DATA[5] NM 5 VCC 1
DSP_DATA[4] 4 5 FDSP_DATA[4] R2234
2
R2222
33 To DIGITAL_IN_1
IO_L19P_0
IO_L18P_0
VCCO_0_1 IO_L17P_0
IO_L15P_0
PROG_B
NM 47
Silk print Aside[24M_CLK_SRC]

GNDD 4 3
Silk print Aside[96k_CLK_SRC]

R2340 6M_CLK_SRC
Silk print Aside[6M_CLK_SRC]
GND1
DSP_DATA[15] 1 8 FDSP_DATA[15] DIGITAL_OUT 4:3G;16:2F GND
A1
A2
A3
A4
A5
A6
DSP_DATA[14] 2 7 FDSP_DATA[14] NM I C 2 2 1 2
GNDD
G 4/21,16/21
3 6 R2223 0 TMS
DSP_DATA[12] FDSP_DATA[12] V+3R3D
IO_L19N_0
IO_L18N_0
IO_L15N_0
4 5
STBY TDI
TMS
22
TDI
B1
B2
B3
B4
B5
B6
C2213
R2250
DSP_BA[1] FDSP_BA[1] NM 5 VCC 1
FDSP_ADRS[2]
IO_L20P_0/V REF_0
22 R2235
2
R2224 FDSP_ADRS[1]
IO_L17N_0
IO_L01N_3
IO_L16N_0
VCCO_3_1 IO_L01P_3
R2252 GNDD NM 4 3 47
DSP_ADRS[3] 1 8 FDSP_ADRS[3] 24M_CLK_SRC
GND5
GND
4:3F;16:3B
C1
C2
C3
C4
C5
C6
DSP_ADRS[2] 2 7 FDSP_ADRS[2]
NM I C 2 2 1 3 FDSP_BA[1]
DSP_ADRS[1] 6 FDSP_ADRS[1] GNDD
GND7IO_L20N_0/PUDC_B
3
FDSP_ADRS[0]
DSP_ADRS[0] 4 5 FDSP_ADRS[0] R2226 0 FDSP_ADRS[16]
IO_L02N_3
IO_L03P_3
IO_L02P_3
33
IP_0_2
D1
D2
D3
D4
D5
D6
R2271
G 10/21 FDSP_ADRS[10]
IO_L03N_3
IP_L04P_3
C DSP_ADRS[14] 4 5 FDSP_ADRS[14]
96K_CLK_LAN R2236 47 R2241 0
IP_0_4
10:2J
N.C.5
N.C.6
E1
E2
E3
E4
E5
E6
6M_CLK_LAN R2237 47
DSP_ADRS[7]
33
R2278
FDSP_ADRS[7]
To LAN_UCOM_2 10:2I
47
DIR1_ERROR
N.C.16IP_L04N_3/VREF_3
1 8 24M_CLK_LAN R2238
10:2I DIR4_ERROR
VCCAUX2
IO_L08P_3
GND10
IO_L11P_3/LHCLK0 GND9
N.C.10
F1
F2
F3
F4
F5
F6
96K_CLK_DSP R2242
To DSP_2 15:3F
22
IO_L08N_3/VREF_3
22 6M_CLK_DSP
R2287 15:3F
G 15/21 1-49
IO_L12P_3/LHCLK2N.C.15
N.C.17
N.C.18
G1
G2
G3
G4
G5
G6
R2240 22
V+3R3D
1-48
IO_L11N_3/LHCLK1
DSP_ADRS[8] 4 5 FDSP_ADRS[8] 0
R2244
C2205
VCCO_3_2
22 0.1u/10 5 VCC 1 R2243 22
R2299
N.C.22
N.C.24
N.C.23
DSP_ADRS[10] FDSP_ADRS[10] R2227
H1
H2
H3
H4
H5
H6
2
22 R2209
IO_L12N_3/IRDY2/LHCLK3
STBY GNDD 22
4 3 0
R2307 R 2 3 0 1 FDSP_BUS_CLK 96K_CLK_AOUT R2245
DSP_BUS_CLK GND 22
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
17:2F;21:2D
NM R2246 22
NM
NM
VCCO_3_3
IC2205 GNDD
DSP_CS_FPGA R 2 3 2 3 0 FDSP_CS_FPGA R2217 R2247 0
TC7SH08FUS1
N.C.26
N.C.27
DSP_CS_FLASHR 2 3 0 9 100 FDSP_CS_FLASH STBY
J1
J2
J3
J4
J5
J6
IO_L15P_3/TRDY2/LHCLK6
DSP_WE R2303 33 FDSP_WE
V+3R3D
1-47 FSH_WE0/DQMLL
N.C.32IO_L15N_3/LHCLK7
DSP_OE R2345 22 FDSP_OE C2207
FSH_DATA[15]
IP_L21N_3
0.1u/10
IP_L21P_3
Silk print Aside[24M_CLK_AD/DA]
Silk print Aside[96k_CLK_AD/DA]
5 VCC 1
Silk print Aside[6M_CLK_AD/DA]
GND16
N.C.30
R2228 DIR3_ERROR
K1
K2
K3
K4
K5
K6
2
R2211
GNDD 22 0
6M_CLK_AOUT 4 3
DIR2_ERROR
To OUTPUT IF GND
IP_L25N_3/VREF_3
17:2E;21:2C
HP AMP NM IC2207
IP_L25P_3
R2212 GNDD
TC7SH08FUS1
N.C.33
N.C.34
N.C.35
STBY
L1
L2
L3
L4
L5
L6
D G 17/21,21/21 V+3R3D
C2208
MCPU_DATA[15]
R2256
22
VCCO_3_4
FSH_DATA[7]
IO_L03N_2/VS1 VCCAUX4
IO_L01P_2/M1 IO_L24N_3
IO_L20P_3
0.1u/10 5 VCC 1
GND21
N.C.39
M1
M2
M3
M4
M5
M6
2 R2229 R2258 0
R2213
GNDD 22 0
24M_CLK_AOUT 4 3 FSH_DATA[13]
GND
17:2D;21:2B FSH_DATA[6]
IP_2/VREF_2_6
FSH_DATA[14]
IO_L20N_3
IO_L22P_3
IO_L24P_3
NM IC2208
R2218 GNDD
TC7SH08FUS1
N1
N2
N3
N4
N5
N6
STBY
FSH_DATA[12]
0
VCCO_2_2IO_L01N_2/M0
IO_L05N_2/D7 IO_L06P_2IO_L04N_2/VS
FSH_DATA[5]
IO_L22N_3
IO_L02P_2/M2 IO_L23N_3
V+3R3D
IO_L03P_2/RDWR_BGND23
N.C.48
P1
P2
P3
P4
P5
P6
C2206 R2264 0
0.1u/10 5 VCC 1
2 R2230
FSH_DATA[11]
IO_L23P_3
R2210
GND25
GNDD 22 4 3 0
96K_CLK_AIN
R2
R3
R4
R5
R6
R1
GND
1:5H
NM IC2206
IO_L02N_2/CSO_B
R2219 TC7SH08FUS1 G N D D
IO_L04P_2/VS2
IO_L06N_2/D6
STBY
1-44
IO_L05P_2
V+3R3D
GND27
G 1/21
T1
T2
T3
T4
T5
T6
C2209
0.1u/10 5 VCC 1
To BOARD_IF R2214
2 R2231
GNDD 22 4 3 0
6M_CLK_AIN
GND
1:5H
NM IC2209
R2215
TC7SH08FUS1G N D D
R2274
E V+3R3D
STBY
G 4/21
0
STBY
1-45 V+3R3D
C2204
IC2204
NM
1 5 C2210
From INB VCC 0.1u/10 5 VCC 1
2
R2288
CH1_SPDIF
DIGITAL_IN1 INA R2232
MCPU_DATA[14] 2 2
4:15B 3 4 R2206 2
R2216
GND OUTY GNDD 22 0
24M_CLK_AIN 4 3
NM GND
NM 1:5H
GNDD R2207
NM IC2210
V+3R3D 0 R2220 TC7SH08FUS1G N D D
G 5/21 STBY
1-46 STBY
C2202
IC2202
NM
From 1
INB VCC
5
DIGITAL_IN2 CH2_SPDIF 2
INA
5:15B R2204
3 4
GND OUTY
NM
NM
GNDD R2201
0
V+3R3D
STBY
G 6/21
FSH_ADRS[18]
FSH_DATA[10]
C2203
IC2203
FSH_DATA[3]
FSH_DATA[4]
FSH_DATA[2]
FSH_DATA[0]
FSH_DATA[1]
FSH_DATA[8]
FSH_DATA[9]
NM
1 5
From 2
INB VCC
CH3_SPDIF
DIGITAL_IN3 6:15B
3
INA
4 R2205
GND OUTY
NM NM
GNDD R2208
From
V+3R3D
STBY
0
DIGITAL_IN1
DIGITAL_IN2
F G 7/21 DIF_CONFIG
C2201
IC2201
DIGITAL_IN3
NM
4:15B;5:15B;6:15B;7:15B
1 5
From 2
INB VCC DIGITAL_IN4
CH4_SPDIF
INA
DIGITAL_IN4 7:15B
3 4
R2203
GND OUTY
NM
G 4/21-7/21
G 13/21
NM
GNDD R2202
146 DJM-900NXS
1 2 3 4
[ ]
47u/16
R2274
0 T3 R3 P3 N3 M3 L3 K3 J3 H3 G3 F3 E3 D3 C3 B3 A3 FDSP_ADRS[3]
C2230
FSH_DATA[2] FDSP_ADRS[4]
R2D_FPGA
0.1u/10
IO_L05P_2 VCCO_2_2IO_L01N_2/M0
IO_L01P_2/M1 IO_L24N_3 N.C.35 N.C.30 N.C.26 N.C.22 IP_L04P_3
N.C.16IP_L04N_3/VREF_3 IO_L20P_0/V REF_0
IO_L02P_3 IO_L18N_0 IO_L18P_0
NM
FDSP_ADRS[5]
R2276
STBY
C2231
FSH_ADRS[18] T4 R4 P4 N4 M4 L4 K4 J4 H4 G4 F4 E4 D4 C4 B4 A4 0.1u/10
FSH_DATA[0]
FSH_DATA[1] FDSP_ADRS[14]
0
FSH_DATA[8]
10k
IP_2/VREF_2_6
IO_L05N_2/D7 IO_L06P_2IO_L04N_2/VS 0 GND21 IP_L25P_3 IP_L21P_3 VCCO_3_3 N.C.23 N.C.17 VCCAUX2 IO_L17N_0
GND7IO_L20N_0/PUDC_B VCCO_0_1 IO_L17P_0
R2281
R2280
FDSP_ADRS[6]
C2234
R2288
MCPU_DATA[14] 2 2 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 0.1u/10
FSH_DATA[9] C2235
FDSP_ADRS[8] C2236
0.1u/10
IO_L06N_2/D6 GND25 N.C.48 IP_L25N_3/VREF_3
IO_L03N_2/VS1 VCCAUX4 IP_L21N_3 N.C.27 N.C.24 N.C.18 GND10 IP_0_4 IP_0_2 IO_L16N_0 IO_L15N_0 IO_L15P_0 0.1u/10
FDSP_ADRS[9]
GNDD
C2237
T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 R2292 22 FPGA_RXD_DAT 0.1u/10

FSH_ADRS[1]
V+3R3D_FPGA_AUX
FSH_ADRS[17]
FDSP_ADRS[7]
N.C.51 N.C.50 IO_L08P_2/D5 N.C.45 IP_2/VREF_2_3 IP_2_1 GND17 IP_L13N_3 IP_L13P_3 VCCINT1 IP_0_5 N.C.7 IO_L16P_0 N.C.3 GND3 N.C.1
Silk print Aside
FSH_ADRS[10]
[V+1R2D_FPGA]
R2296 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 C7 B7 A7 FDSP_WE
MCPU_DATA[13] 2 2
FSH_ADRS[11] FDSP_ADRS[11]
5
5
FDSP_ADRS[12]
FSH_ADRS[9] IO_L10N_2/GCLK15 IO_L08N_2/D4
IO_L10P_2/GCLK14
VCCO_2_3 IP_2/VREF_2_4 IP_2_2 VCCINT5 GND15 VCCINT3 GND11 N.C.11 VCCO_0_4 IO_L11P_0/GCLK8
IO_L11N_0/GCLK9 IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
FDSP_BUS_CLK
1-52
1-51
T8 R8 P8 N8 M8 L8 K8 J8 H8 G8 F8 E8 D8 C8 B8 A8 R2302 0 FPGA_SIGNAL
DIR4_SCLK
R2304 0 FPGA_CLK
DIR2_SCLK
0 FDSP_OE
DIR1_SCLK R2306
IO_L12P_2/GCLK2
IO_L12N_2/GCLK3 IO_L11P_2/GCLK0
IO_L11N_2/GCLK1 VCCO_2_1IP_2/VREF_2_1 GND18 VCCINT4 GND14 VCCINT2 IP_0_6 IP_0/VREF_0
IO_L09N_0/GCLK5 IO_L10N_0/GCLK7
VCCO_0_2
IO_L10P_0/GCLK6
R2305 0
DIR3_SCLK T9 R9 P9 N9 M9 L9 K9 J9 H9 G9 F9 E9 D9 C9 B9 A9
FSH_ADRS[13]
FSH_ADRS[12]
FSH_ADRS[15] FDSP_CS_FLASH
N.C.40
FDSP_DATA[9]
IO_L14N_2 GND26 N.C.46
IO_L14P_2/MOSI/CSI_B IP_2/VREF_2_2 VCCINT6 N.C.28 IP_L13P_1 GND12 IP_0_7 N.C.8 IO_L08P_0
N.C.4 IO_L09P_0/GCLK4 IO_L08N_0
FDSP_DATA[0]
T10 R10 P10 N10 M10 L10 K10 J10 H10 G10 F10 E10 D10 C10 B10 A10 R2313 47 MCPU_DATA[2]
V+1R2D_FPGA
FSH_ADRS[3]
1-53
FSH_ADRS[14]
FDSP_DATA[11]
IO_L15N_2/DOUT
IO_L15P_2/AWAKE IO_L16P_2 IO_L16N_2IP_2/VREF_2_5 GND19 IP_L04P_1 N.C.29 IP_L13N_1 IP_L21N_1 IP_L25N_1 VCCAUX1 IO_L03N_0 IO_L07P_0 GND4 IO_L07N_0
FDSP_DATA[10]
V+3R3D_FPGA_AUX
FSH_ADRS[16] T11 R11 P11 N11 M11 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11 R2319 0 FPGA_TXD_DAT
FSH_ADRS[2]
FDSP_DATA[12]
R2322 10k
FDSP_CS_FPGA
IO_L17P_2/INIT_BVCCO_2_4IO_L17N_2/D3 N.C.47 GND22 IO_L10P_1
IP_L04N_1/VREF_1
VCCAUX3 VCCO_1_2
IP_L21P_1/V REF_1
IP_L25P_1/VREF_1 G N D 8 IP_0_3 IO_L03P_0 IP_0_1 N.C.2
R2324
0
T12 R12 P12 N12 M12 L12 K12 J12 H12 G12 F12 E12 D12 C12 B12 A12
MCPU_RD
R2325 47 MCPU_DATA[3]
FSH_ADRS[4]
C2238 IO_L18P_2/D2
IO_L20P_2/D1 N.C.49 IO_L01P_1/HDC N.C.41 N.C.36 N.C.31 IO_L10N_1 N.C.25 N.C.19 IO_L20N_1 IO_L23P_1 IO_L01P_0 IO_L01N_0 VCCO_0_3 IO_L04N_0
FDSP_DATA[14]
0.01u/16
GNDD
T13 R13 P13 N13 M13 L13 K13 J13 H13 G13 F13 E13 D13 C13 B13 A13 FDSP_DATA[13]
FDSP_DATA[8]
IO_L18N_2/D0/DIN/MISO
IO_L20N_2/CCLK GND24 IO_L01N_1/LDC2 N.C.42 N.C.37IO_L11N_1/RHCLK1 IO_L14N_1/RHCLK5N.C.20
IO_L14P_1/RHCLK4 N.C.12 IO_L20P_1 IO_L23N_1 GND6 IO_L02N_0 IO_L04P_0
FDSP_DATA[15]
6
6
FSH_ADRS[5] T14 R14 P14 N14 M14 L14 K14 J14 H14 G14 F14 E14 D14 C14 B14 A14 FDSP_DATA[1]
IO_L02N_1/LDC0VCCO_1_4
DONE IO_L02P_1/LDC1 N.C.43 GND20 IO_L15P_1/IRDY1/RHCLK6
VCCO_1_3
IO_L11P_1/RHCLK0 GND13 N.C.13 VCCO_1_1 IO_L22N_1 IO_L02P_0/VREF_0
IO_L24N_1 TCK
R2334
R2333
TCK
R2335
33
33
22 TDO
R2336
10k GND28 SUSPEND IO_L03P_1 IO_L03N_1 N.C.44 IO_L12N_1/TRDY1/RHCLK3
N.C.38IO_L12P_1/RHCLK2 IO_L15N_1/RHCLK7N.C.21 N.C.14 N.C.9 IO_L22P_1 IO_L24P_1 TDO GND2
1-54
10:2I
10:2I
10:15I
10:15I
10:15G
SH_FPGA_TXD2
SH_FPGA_SCK2
SH_FPGA_XINIT
SH_FPGA_DONE
SH_FPGA_RST_X
R2337
10k
GNDD
From To LAN_UCOM_2
R2356
R2355
R2352
R2351
R2348
R2362
R2361
R2347
R2360
R2346
R2295
R2294
R2343
DJM-900NXS
0
0
47
47
47
47
47
47
47
47
47
47
47
G 10/21
FSH_RDWR
FDSP_DATA[7]
FDSP_DATA[6]
FDSP_DATA[5]
FDSP_DATA[4]
FDSP_DATA[3]
FDSP_DATA[2]
FSH_ADRS[7]
FSH_ADRS[6]
FSH_ADRS[8]
FSH_RD
FSH_FPGA_CS
7
7
MCPU_WR0
MCPU_ASTB
MCPU_DATA[11]
MCPU_DATA[12]
MCPU_DATA[10]
MCPU_DATA[9]
MCPU_DATA[8]
MCPU_DATA[7]
MCPU_DATA[6]
MCPU_DATA[1]
MCPU_DATA[0]
MCPU_DATA[5]
MCPU_DATA[4]
G 13/21
FPGA
FSH_RD
FSH_RDWR
FSH_DATA[7]
FSH_DATA[6]
FSH_DATA[3]
FSH_DATA[2]
FSH_DATA[5]
FSH_DATA[4]
FSH_DATA[0]
FSH_DATA[8]
FSH_DATA[1]
FSH_DATA[9]
FSH_ADRS[1]
FSH_ADRS[9]
FSH_ADRS[2]
FSH_ADRS[3]
FSH_ADRS[4]
FSH_ADRS[5]
FSH_ADRS[6]
FSH_ADRS[7]
FSH_ADRS[8]
FSH_DATA[15]
FSH_DATA[14]
FSH_DATA[11]
FSH_DATA[10]
FSH_DATA[13]
FSH_DATA[12]
FSH_ADRS[17]
FSH_ADRS[13]
FSH_ADRS[14]
FSH_ADRS[15]
FSH_ADRS[16]
FSH_ADRS[10]
FSH_ADRS[11]
FSH_ADRS[12]
FSH_ADRS[18]
FSH_WE0/DQMLL
1
1
1
1
1
1
1
1
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
R2350
R2349
R2254
FSH_FPGA_CS R 2 3 5 3
22
22
22
22
22
22
22
22
22
22
R2310
R2320
R2359
R2354
R2260
R2265
R2277
R2289
R2298
R2293

0
82
82
22
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
12:14K
24M_CLK_FPGA
(F)
(D)
1/4W
1/8W
2W
RN
SH_DATA2[15]
SH_DATA2[14]
SH_DATA2[11]
SH_DATA2[10]
SH_DATA2[13]
SH_DATA2[12]
SH_DATA2[7]
SH_DATA2[6]
SH_DATA2[3]
SH_DATA2[2]
SH_DATA2[5]
SH_DATA2[4]
SH_DATA2[0]
SH_DATA2[8]
SH_DATA2[1]
SH_DATA2[9]
SH_RD
SH_ADRS[17]
SH_ADRS[13]
SH_ADRS[14]
SH_ADRS[15]
SH_ADRS[16]
SH_ADRS[10]
SH_ADRS[11]
SH_ADRS[12]
SH_ADRS[18]
SH_ADRS[1]
SH_ADRS[9]
SH_ADRS[2]
SH_ADRS[3]
SH_ADRS[4]
SH_ADRS[5]
SH_ADRS[6]
SH_ADRS[7]
SH_ADRS[8]
SH_FPGA_CS
NP
HA
SH_RDWR
CH
SH_WE0/DQMLL
NOTES
NM
+
+
8
8
is STBY
RS2****J
CEVW***
RS1/4S****J
RS1/8S****J
CEHVAW**
CEVWNP***
RS1/10S****J
RS1/16S****J
CKSSYB****
RN1/10S****J
RN1/16S****J
CKSRYB****
RS1/10S****F
RS1/16S****F
9:16C
CCSSCH****
RS1/10S****D
RS1/16S****D
RAB4CQ****J
CCSRCH****
G 12/21
CCSQCH****
9:16B
SH_BUS
SH_DATA
From MAIN_CPU
G 9/21
From To LAN_UCOM1
MAIN ASSY (DWX3190)
147
G 13/21
F
E
B
A
D
C
1 2 3 4
10.26 MAIN ASSY (14/21)
R731
DSP_DATA[0] 1 8 T13 R8 R752 100 DSP_BA[0]
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] EMA_BA[0]/GP1[14]
DSP_DATA[2] 2 7 R15 P8 R753 4.7 DSP_BA[1]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] EMA_BA[1]/UHPI_HHWIL/GP1[13]
DSP_DATA[9] 3 6 R13
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
DSP_DATA[10] 4 5 P15 T9 R754 10 DSP_ADRS[0]
R732 EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] EMA_A[0]/GP1[0] R755 DSP
DSP_DATA[4] 1 8 10 P13 R9 1 8 DSP_ADRS[12]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] DSP
DSP_DATA[5] 2 7 N15 P9 2 7 DSP_ADRS[8]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] DSP
DSP_DATA[14] 3 6 N13 N9 3 6 DSP_ADRS[11]
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] EMA_A[3]/GP1[3] DSP
DSP_DATA[13] 4 5 M15 T10 4 5 DSP_ADRS[9]
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] EMA_A[4]/GP1[4] R756
10 R10 1 8 10 DSP_ADRS[6]
R733 EMA_A[5]/GP1[5]
EMA_D[8]/UHPI_HD[8]/GP0[8] EMA_A[6]/GP1[6] DSP
DSP_DATA[3] 2 7 T14 N10 3 6 DSP_ADRS[7]
EMA_D[9]/UHPI_HD[9]/GP0[9] EMA_A[7]/GP1[7] DSP
DSP_DATA[11] 3 6 R14 T11 4 5 DSP_ADRS[5]
EMA_D[10]/UHPI_HD[10]/GP0[10] EMA_A[8]/GP1[8] R757 DSP
DSP_DATA[12] 4 5 P16 R11 10 1 8 DSP_ADRS[1]
R734 EMA_D[11]/UHPI_HD[11]/GP0[11] EMA_A[9]/GP1[9] DSP
EMIFA
DSP_DATA[6] 1 8 10 P14 N8 2 7 DSP_ADRS[2]
EMA_D[12]/UHPI_HD[12]/GP0[12] EMA_A[10]/GP1[10]
EMA_D[13]/UHPI_HD[13]/GP0[13] EMA_A[11]/GP1[11]
DSP_DATA[8] 3 6 N14 N11 4 5 DSP_ADRS[10]
EMA_D[14]/UHPI_HD[14]/GP0[14] V+3R3D_DSP
EMA_A[12]/GP1[12]
DSP_DATA[15] 4 5 M16 10
EMA_D[15]/UHPI_HD[15]/GP0[15] DSP
10 V+3R3D_DSP R12 R767 33 DSP_BUS_CLK STBY STBY
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] DSP
B
R779
R780
R781
R747 10k N6 T12
NM
NM
DSP R768 27 DSP_BUS_CKE
10k
EMA_WAIT[0]/UHPI_HRDY/GP2[10] EMA_SDCKE/GP2[0] DSP
T8 R769 33 DSP_CS_SDRAM
EMA_CS[0]/UHPI_HAS/GP2[4] DSP
P7 R770 0 DSP_CS_FLASH
IC701 EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
EMA_CS[3]/AMUTE2/GP2[6]
T7 R771 22 DSP_CS_FPGA
DSP
D810K013BZKB400 EMA_RAS/EMA_CS[5]/GP2[2]
N7
L16
R772
R773
100
100
DSP_RAS
DSP_CAS
DSP
DSP
EMA_CAS/EMA_CS[4]/GP2[1] DSP
M13 R774 4.7 DSP_WE
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] DSP
M14 R775 100 DSP_LDQM_SDRAM
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] DSP
P12 R776 100 DSP_UDQM_SDRAM
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] DSP
R7 R777 22 DSP_OE
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] DSP
R735
DSP_ADRS[13] 1 8 F16 C9
EMB_D[0]/GP6[0] EMB_BA[0]/GP7[1]
DSP_ADRS[14] 2 7 G13 B9
EMB_D[1]/GP6[1] EMB_BA[1]/GP7[0]
DSP_ADRS[15] 3 6 G16
DSP_ADRS[16] 4 5 H13
EMB_D[2]/GP6[2]
EMB_D[3]/GP6[3]
DSP EMB_A[0]/GP7[2]
D10
10 H16 C10
J13
EMB_D[4]/GP6[4]
EMB_D[5]/GP6[5]
IC701 EMB_A[1]/GP7[3]
EMB_A[2]/GP7[4]
B10
STBY (TEST LED)
J15
J16
EMB_D[6]/GP6[6] D810K013BZKB400 EMB_A[3]/GP7[5]
A10
D11
DSP
DSP
EMB_D[7]/GP6[7] EMB_A[4]/GP7[6] V+3R3D_DSP
C16 C11 DSP
EMB_D[8]/GP6[8] EMB_A[5]/GP7[7]
C D13
EMB_D[9]/GP6[9] EMB_A[6]/GP7[8]
B11
R778
DSP
D14 A11 NM DSP
EMB_D[10]/GP6[10] EMB_A[7]/GP7[9]
D15 D12 DSP
EMB_D[11]/GP6[11] EMB_A[8]/GP7[10]
D16 C12 DSP
EMB_D[12]/GP6[12] EMB_A[9]/GP7[11] D701
E13 A9 NM DSP
EMB_D[13]/GP6[13] EMB_A[10]/GP7[12]
E16 B12
EMIFB
EMB_D[14]/GP6[14] EMB_A[11]/GP7[13]
F13 B15
EMB_D[15]/GP6[15] Q701
EMB_A[12]/GP3[13]
NM
G15 DSP
EMB_D[16]
H14 C14
EMB_D[17] EMB_CLK
H15 C13
EMB_D[18] EMB_SDCKE GNDD
J14 D9
EMB_D[19] EMB_CS[0]
K13 A8
EMB_D[20] EMB_RAS
K16 L13
EMB_D[21] EMB_CAS
L14 K15 DSP
EMB_D[22] EMB_WE
L15 K14 DSP
EMB_D[23] EMB_WE_DQM[0]/GP5[15]
A13 C15 DSP
EMB_D[24] EMB_WE_DQM[1]/GP5[14]
B14 B13 DSP
EMB_D[25] EMB_WE_DQM[2]
A14 A12 DSP
EMB_D[26] EMB_WE_DQM[3]
E14 DSP
EMB_D[27]
E15 DSP
EMB_D[28]
F14 DSP
EMB_D[29]
F15
EMB_D[30]
G14
EMB_D[31]
D
Silk print Aside
[V+3R3D_DSP]
1-55 V+3R3D_DSP
V+3R3D V+3R3D_DSP
L702
QTL1013-A
B16 A1
DVDD1 Vss1
E5 A2
DVDD2 Vss2
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
0.01u/16
470p/50
0.1u/10
E8 A3
DVDD3 Vss3
E9
DVDD4
DSP A15
0.1u/10
Vss4
STBY
C702
C703
NM
E12 A16
DVDD5 Vss5
C705
C707
C719
C721
C723
C725
C727
C729
C731
C733
C735
C737
C739
C741
C743
C745
C747
C749
F5 B2
F11
DVDD6
DVDD7
IC701 Vss6
Vss7
B3
F12
G5
DVDD8 D810K013BZKB400 Vss8
E6
E7
DVDD9 Vss9
GNDD G12 E10
DVDD10 Vss10
K5 E11
DVDD11 Vss11
K12 F8
DVDD12 Vss12
L5 F9
DVDD13 Vss13
L11 F10
DVDD14 Vss14
L12 G8
DVDD15 Vss15
M5 G9
DVDD16 Vss16
M8 H8
E M9
DVDD17 Vss17
H9
DVDD18 Vss18
M12 J8
DVDD19 Vss19
Silk print Aside
R1 J9
Power Supply
[V+1R2D_DSP] DVDD20 Vss20
V+1R2D
L701
V+1R2D_DSP 1-56 V+1R2D_DSP R16
DVDD21 Vss21
K8
K9
QTL1013-A Vss22
F6 L7
CVDD1 Vss23
G6 L8
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
1000p/50
CVDD2 Vss24
470p/50
0.1u/10
G7 L9
CVDD3 Vss25
G10 L10
CVDD4
0.1u/10
Vss26
C701
47u/16
C704
G11 M6
CVDD5 Vss27
C706
C708
C724
C726
C728
C730
C732
C734
C736
C738
C740
C742
C744
C746
C748
H6 M7
CVDD6 Vss28
H7 M10
CVDD7 Vss29
H10 M11
CVDD8 Vss30
H11 T1
CVDD9 Vss31
GNDD H12 T2
CVDD10 Vss32
J6 T15
[countermeasure] DEMITAS_NX CVDD11 Vss33
J7 T16
CVDD12 Vss34
GNDD
V+3R3D_DSP J10
CVDD13 Silk print Aside V+1R2D_DPLL
J11 [V+1R2D_DPLL]
CVDD14
J12 1-57 V+1R2D_DSP
0.01u/16
0.01u/16
0.01u/16
CVDD15
K6
CVDD16 3216size
K7 D1 L703
CVDD17 PLL0_VDDA
K10 E1 CTF1579-A
F CVDD18 PLL0_VSSA
C709
C711
C713
BLM31PG601SN1
0.01u/16
100p/50
0.1u/10
K11
C751
C752
C750
CH
CVDD19
L6
CVDD20
3216size
L704
GNDD
F7
G 14/21
RSV1 CTF1579-A
B1 BLM31PG601SN1
RSV2
GNDD
148 DJM-900NXS
1 2 3 4
5 6 7 8
SDRAM 256M
A
V+3R3D_DSP_MEM IC702
V+3R3D_DSP V+3R3D_DSP_MEM
MD56V82160-6TAZ
DCH1201-A
R782
10u 10V
0
STBY
C755
C753
NM
1-58
C756 1 54
R783 0.01u/16 VCC1 VSS3 53 R825
DSP_DATA[0] 1 8 2 1 8 DSP_DATA[15]
DQ1 DQ16
DSP_DATA[1] 2 7 C757 3 52 2 7 DSP_DATA[14]
0.01u/16 V C C Q 1 VSSQ4
DSP_DATA[2] 3 6 4 51 3 6 DSP_DATA[13]
DQ2 DQ15
DSP_DATA[3] 4 5 5 50 4 5 DSP_DATA[12]
DQ3 DQ14
33 6 49 C761 33
V S S Q 1 VCCQ4 0.01u/16
7 48
R784 DQ4 DQ13 R826
DSP_DATA[4] 1 8 8 47 1 8 DSP_DATA[11]
DQ5 DQ12
DSP_DATA[5] 2 7 C758 9 46 2 7 DSP_DATA[10]
VSSQ3
G 13/21
0.01u/16 VCCQ2
DSP_DATA[6] 3 6 10 45 3 6 DSP_DATA[9]
DQ6 DQ11
DSP_DATA[7] 4 5 11 44 4 5 DSP_DATA[8]
DQ7 DQ10
12 43 DSP_BUS
33
13
VSSQ2 VCCQ3
42
C762
0.01u/16
33
13:1C
From To FPGA
DQ8 DQ9
V+3R3D_DSP
C759 14 41
0.01u/16 VCC2 VSS2
DSP_LDQM_SDRAM R791 47 15 40
STBY STBY LDQM NC
DSP_WE R792 100 16 39 R833 47 DSP_UDQM_SDRAM
B
R779
R780
R781
WE UDQM
NM
NM
10k
DSP_CAS R793 47 17 38 R834 33 DSP_BUS_CLK

CAS CLK
DSP_RAS R794 47 18 37 R835 27 DSP_BUS_CKE
RAS CKE R836
19 36
G 14/21
DSP_CS_SDRAM R795 33 1 8 DSP_ADRS[12]
CS A12
DSP_BA[0]
DSP_BA[1]
DSP_ADRS[10]
R796
R797
R798
47
100
22
20
21
22
BA0
BA1
A11
A9
35
34
33
2
3
4
7
6
5
DSP_ADRS[11]
DSP_ADRS[9]
DSP_ADRS[8]
MAIN ASSY (DWX3190)
R799 A10 A8 R837
DSP_ADRS[0] 1 8 23 32 22 1 8 DSP_ADRS[7]
A0 A7
24 31
DSP_1
DSP_ADRS[1] 2 7 2 7 DSP_ADRS[6]
A1 A6
DSP_ADRS[2] 3 6 25 30 3 6 DSP_ADRS[5]
A2 A5
DSP_ADRS[3] 4 5 26 29 4 5 DSP_ADRS[4]
A3 A4
22 C760 27 28 22
0.01u/16 VCC3 VSS1
V+3R3D_DSP_MEM
GNDD
FLASH 4M
DCH1201-A
IC703
10u 10V
C764
DYW1797- /J
R803
DSP_ADRS[14] 1 8 1 48 R844 22 DSP_ADRS[15]
A15 A16
DSP_ADRS[13] 2 7 2 47
A14 BYTE#
DSP_ADRS[12] 3 6 3 46
A13 GND2 R845
DSP_ADRS[11]
R804
4 5 4
A12 Q15/A-1
45 1 8 DSP_DATA[15] C
DSP_ADRS[10] 1 8 22 5 44 2 7 DSP_DATA[7]
A11 Q7
DSP_ADRS[9] 2 7 6 43 3 6 DSP_DATA[14]
A10 Q14
DSP_ADRS[8] 3 6 7 42 4 5 DSP_DATA[6]
A9 Q6 R846
DSP_ADRS[7] 4 5 8 41 22 1 8 DSP_DATA[13]
A8 Q13
22 STBY R 8 1 1 NM 9 40 2 7 DSP_DATA[5]
NC1 Q5
R812 NM 10 39 3 6 DSP_DATA[12]
NC2 Q12
DSP_WE R813 100 11 38 4 5 DSP_DATA[4]
WE# Q4
12 37 22
C763
R E S E T #V C C 0.1u/10 R853
R814 NM 13 36 1 8 DSP_DATA[11]
C754 NC3 Q11
0.01u/16 R815 NM 14 35 2 7 DSP_DATA[3]
NC4 Q3
15 34 3 6 DSP_DATA[10]
RY/BY# Q10
R816 NM 16 33 4 5 DSP_DATA[2]
GNDD R817 NC5 Q2 R854
DSP_ADRS[16] 1 8 STBY 17 32 22 1 8 DSP_DATA[9]
A17 Q9
DSP_ADRS[6] 2 7 18 31 2 7 DSP_DATA[1]
A7 Q1
DSP_ADRS[5] 3 6 19 30 3 6 DSP_DATA[8]
A6 Q8
DSP_ADRS[4] 4 5 20 29 4 5 DSP_DATA[0]
R818 A5 Q0
DSP_ADRS[3] 22 1 8 21 28 R861 22 22 DSP_OE
A4 OE#
DSP_ADRS[2] 2 7 22 27
A3 GND1
DSP_ADRS[1] 3 6 23 26 R862 100 DSP_CS_FLASH
A2 CE#
DSP_ADRS[0] 4 5 24 25 R863 100 DSP_BA[1]
A1 A0
22
GNDD
D
MX29LV400CTTI-70G (MACRONIX)
Label : VRW1773-
G 10/21
FLASH_DSP_RESET
10:2G
From LAN_UCOM_2
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
RAB4CQ****J
CKSRYB****
CKSSYB****
_DSP
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
HA
+
CEHVAW** F
: Waveform measuring point NP CEVWNP***
G 14/21
DJM-900NXS 149
5 6 7 8
1 2 3 4
10.27 MAIN ASSY (15/21)
A
D
V+3R3D_DSP
IC
D810K01
R870
10k
R889
10k T5
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
G 12/21 12:14J
DSP_LINT
R864 22 R5
R6
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
12:14J R865 22
To MAIN Ucom DSP_MINT
R890
10k
P6
N4
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
12:14J R866 22
DSP_HINT SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
R891
10k T6
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
R4
SPI1_ENA/UART2_RXD/GP5[12]
P5
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
G 10/21 GNDD
N5
P4
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
10:2G SPI1_SCS[0]/UART2_TXD/GP5[13]
From LAN_UCOM_2 DSP_RESET
C1
NC1
B
JTAG
0.1u/10
C2
C765
STBY NC2
F3
NC3
V+3R3D_DSP H4
NC4
GNDD G3
NM
NM
NM
NM
NM
RESET
CN701
K1
V+3R3D 1 GP7[14]
R867
R868
R869
R871
R888
V+3R3D 2
J1
DSP_TMS 3 TMS
J2
DSP_TDI 4 TDI
J3
JTAG
DSP_TDO 5 TDO
J4
DSP_TCK 6 TRST
H3
DSP_EMU 7 TCK
J5
DSP_TRST 8 EMU[0]/GP7[15]
GNDD 9
R892
GNDD 1 0
10k
NM
C
GNDD
R893
0
G 12/21
From MAIN_CPU 12:14K
24M_CLK_DSP
13:4F
6M_CLK_DSP
From FPGA 13:4F
G 13/21 96K_CLK_DSP
IC
DSP
D810K01
R872 0 B5
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
R873 0 C5
ACLKX0/ECAP0/APWM0/GP2[12]
R874 0 D5
AFSX0/GP2[13]/BOOT[10]
D
R875 0 A4
AHCLKR0/GP2[14]/BOOT[11]
G 21/21 21:2E ADAT_HP (HP D)

R876
R877
0
0
B4
C4
ACLKR0/ECAP1/APWM1/GP2[15]
ADAT_HP AFSR0/GP3[12]
To HP AMP Block
17:2G ADAT_MASTER (MA D) R878 22 B8
ADAT_MASTER AXR0[0]/AFSR2/GP3[0]
G 17/21 17:2G
ADAT_BOOTH
ADAT_BOOTH (BO D) R879
R880
22
22
C8
D8
AXR0[1]/ACLKX2/GP3[1]
McASP0
AXR0[2]/AXR2[3]/GP3[2]
To OUTPUT IF Block 17:2G
ADAT_SEND
ADAT_SEND (SEND D) R881 22 A7
AXR0[3]/AXR2[2]/GP3[3]
17:2G ADAT_REC (REC D) R882 22 B7
ADAT_REC AXR0[4]/AXR2[1]/GP3[4]
G 16/21 16:3D ADAT_DOUT

(DIG OUT) R883
R884
68
22
C7
D7
AXR0[5]/AFSX2/GP3[5]
AXR0[6]/ACLKR2/GP3[6]
ADAT_DOUT
To DIGITAL OUT R885 22 A6
AXR0[7]/GP3[7]
R886 22 B6
AXR0[8]/GP3[8]
R887 22 C6
UART1_RXD/AXR0[9]/GP3[9]
4:3I ADAT_USB1 (CH1 U OUT) D6
To DIGITAL_IN_1 ADAT_USB1 UART1_TXD/AXR0[10]/GP3[10]
5:3I ADAT_USB2 (CH2 U OUT) A5
To DIGITAL_IN_2 ADAT_USB2 AXR0[11]/AXR2[0]/GP3[11]
6:3I ADAT_USB3 (CH3 U OUT)
To DIGITAL_IN_3 ADAT_USB3
(CH4 U OUT) L4
7:3I ADAT_USB4
To DIGITAL_IN_4 ADAT_USB4 AMUTE0/RESETOUT
E
G 4/21-7/21
(HP D)
: HP OUT Digital Signal
(MA D)
: MASTER OUT Digital Signal
(BO D)
: BOOTH OUT Digital Signal D
(SEND D)
: SEND OUT Digital Signal IC
(REC D)
: REC OUT Digital Signal D810K01
(DIG OUT)
: DIGITAL OUT Signal
(CH1 U OUT)
: CH1 USB Output Signal H5
USB0_VDDA33
(CH2 U OUT)
E3
: CH2 USB Output Signal C3
USB0_VDDA18
US
(CH3 U OUT) STBY USB0_VDDA12

C766
F
NM
(CH4 U OUT)
: CH4 USB Output Signal GNDD
G 15/21
150 DJM-900NXS
1 2 3 4
5 6 7 8

DSP
IC701
DSP_2
D810K013BZKB400
P3
T[2] UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
A/GP5[3]/BOOT[3] UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
R3 R901 22 10:2G
DSP_CTL
To LAN_UCOM_2
R899
BOOT[0]
10k
/BOOT[1] G 10/21
P0B/GP5[4]/BOOT[4]
GNDD (CH1 D)
OT[7] : CH1 Digital Signal (from INPUT ASSY)
2] (CH2 D)
5]/BOOT[5]
: CH2 Digital Signal (from INPUT ASSY)
(CH3 D)
6]/BOOT[6]
[13]
: CH3 Digital Signal (from INPUT ASSY)
(CH4 D)
V+1R2D_DSP : CH4 Digital Signal (from INPUT ASSY)
(MI D)
: MIC Digital Signal (from INPUT ASSY) B
G1
0.1u/10
(RET D)
C768
R910
RTC_CVDD
10k
: RETURN Digital Signal (from INPUT ASSY)
H1 (LINK IN)
RTC_XI
RTC_XO
H2 : LINK AUDIO INPUT
(CH1 U/D IN)
G2
RTC_VSS (CH2 U/D IN)
GNDD (CH3 U/D IN)
JTAG
R900
(CH4 U/D IN)
0
OSCIN
F2
F1
OSCOUT
E2
OSCVSS
NOTES
GNDD
is STBY
V+1R2D NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
IC704
C767
(D) RS1/16S****D
RS1/10S****D
C
1 0.1u/10 Silk print Aside
VCC 5 (F) RS1/16S****F
[24M_CLK_DSP] RS1/10S****F
2
3 4
R896
0 GNDD 1-59 1/8W RS1/8S****J
GND 1/4W RS1/4S****J
R893
2W RS2****J
0
GNDD TC7SG08FU
RAB4CQ****J
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
DSP IC701 HA
+
CEHVAW**
D810K013BZKB400 NP CEVWNP***
K2 R904 0
CLKIN/GP2[11] AHCLKX1/EPWM0B/GP3[14]
K3 R905 0
2] ACLKX1/EPWM0A/GP3[15]
K4 R906 0
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
D
L1 R907 0
AHCLKR1/GP4[11]
L2 R908 0
5] ACLKR1/ECAP2/APWM2/GP4[12]
L3 R909 0
AFSR1/GP4[13]
T3 (CH1 D) 22 R911 1:10F

ADAT_CH1_ANA
AXR1[0]/GP4[0]
AXR1[1]/GP4[1]
R2 (CH2 D) 22 R912 1:10F
ADAT_CH2_ANA G 1/21
McASP1
P2 (CH3 D) 1 8 1:10G
McASP0
ADAT_CH3_ANA
AXR1[2]/GP4[2]
AXR1[3]/EQEP1A/GP4[3]
P1 (CH4 D) 2 7 1:10G
ADAT_CH4_ANA
From BOARD IF Block
N2 (MI D) 3 6 1:10F
AXR1[4]/EQEP1B/GP4[4] ADAT_MIC_ANA
N1 (RET D) 4 5 1:10F
AXR1[5]/EPWM2B/GP4[5] ADAT_RETURN_ANA
M4 22 R913
AXR1[6]/EPWM2A/GP4[6]
M3 (CH1 U/D IN)
AXR1[7]/EPWM1B/GP4[7]
M2 (CH2 U/D IN)
AXR1[8]/EPWM1A/GP4[8]
M1 (CH3 U/D IN)
AXR1[9]/GP4[9]
AXR1[10]/GP5[10]
AXR1[11]/GP5[11]
N3
T4
(CH4 U/D IN)
(LINK IN)
G 10/21
10:15G
D4
ADAT_LANIN
From LAN_UCOM_2
AMUTE1/EPWMTZ/GP4[14]
E
4:15C
ADAT_UDIN1 From DIGITAL_IN_1
5:15C
6:15C
7:15C
G 4/21-7/21
DSP
IC701
D810K013BZKB400
D3
USB0_VBUS
E4
USB0_DRVVBUS/GP4[15]
F4
USB0_DP
USB2.0 G4
USB0_DM
D2
F
USB0_ID
G 15/21
DJM-900NXS 151
5 6 7 8
1 2 3 4
10.28 MAIN ASSY (16/21)
1-65 1-66
G 12/21 DIT_RXD
12:2C
DIT_TXD
12:2C
From To Main_Ucom DIT_SCK

12:2C
DITD_CS
12:2C
V+3R3D 1-67
C2404
G 4/21,13/21 1 VCC 5
0.1u/10
R2403
B From FPGA 4:3F;13:4E 2
R2407
24M_CLK_SRC 0 22 GNDD
3 4
GND
IC2403
G N D D TC7SH08FUS1 1-68
R2409
0
1-69
10:15H
DIT_RESET
0.01u/16
R2408
C2411
0.01u
0
GNDD
G 10/21
From LAN_UCOM_2 C2406
V+2R5D
DOUT SRC V+3R3D
DCH1201-A IC2404
C 1 0 u 10V 1 20 R2413 47k
XTO SRC_UNLOCK
C2403 2 1 9 (D) R 2 4 1 4 2 k
0.1u
XTI SAIF
DCH1201-A
GNDD 3 1 8 (D) R 2 4 1 5 6 2 k
1-63
1 0 u 10V
C2407
C2408
VD SAOF
0.1u
C2405 4 17
36
35
34
33
0.01u/16
GND1 VL
10:15H 5 16
DOUT_SRC_RESET RST GND2 INT1
OCKS0/CSN/CAD0
6 15
OCLS1/CCLK/SCL
INT0
BYPASS MS_SEL 37
AVDD
7 14 R2419
1-60 ILRCK OLRCK
22
C2410 0.1u 38
G 15/21 (DIG OUT)
8
ISCLK OSCLK
13 R2420
R2421
22
R2422 (D) 18k 39
R
VCOM
15:3G 9 12
From DSP_2 ADAT_DOUT V+3R3D SDIN SDOUT
22
C2409 0.47u 40
R2418
10 11 AVSS
(DIG OUT)
47k
R2404 MCLK_OUT TDM_IN 41
RX0
47k 1-70 1-72
42
NC_AVSS3
CS8421-CZ
NC_AVSS1
43
IPS0/RX4
RX1
GNDD
1-64 GNDD
R2411
R2416
44
3.9k
16k
TEST1
(D)
1-71
Silk print Aside[LRCK_DOUT]
Silk print Aside[BCLK_DOUT]

(D)
45
RX2
V+3R3D 46
R2410
R2412
R2417
NC_AVSS4
10k
47
0
D
G 10/21 48
RX3
4
1
Q2403
From LAN_UCOM_2 10:15H
DOUT_MS_SEL
Q2402
LTC124EUB
LTC124EUB
V+3R3D
C2401 Q2401
0.1u/10 LTC124EUB
1 VCC 5
R2401 2
4:3G;13:4C R2405 GNDD
96K_CLK_SRC 22 GNDD
0 3 4
GND
G 4/21,13/21
IC2401
G N D D TC7SH08FUS1 Low Hi
1-61 3.9k 16k
From FPGA V+3R3D
DOUT_MS_SEL 96KHz 48KHz
C2402
1 0.1u/10
VCC 5
R2402 2
4:3G;13:4D R2406
E 6M_CLK_SRC 0 3
GND
4 22 GNDD
IC2402
G N D D TC7SH08FUS1
1-62
G 16/21
152 DJM-900NXS
1 2 3 4
5 6 7 8
DIGITAL OUT
1-69
0.01u/16
C2411
0.01u
V+3R3D_DIT
22
GNDD
1-73 V+3R3D_DIT
R2433
V+3R3D
R2425
C
0
DCH1201-A
1 0 u 10V
C2413
36
35
34
33
32
31
30
29
28
27
26
25
MCKO2
DAUX
SDTO
CM0/CDTO/CAD1
PDN
XTO
BICK
CM1/CDTI/SDA
XTI
INT1
OCKS0/CSN/CAD0
OCLS1/CCLK/SCL
INT0
37 24
AVDD
10 38 LRCK 23 V+5D
0.1u
R MCKO1
22 (D) 18k 39 DVSS 22 C2414
100u/16
C2415
C2416
VCOM DVDD
0.1u
0.01u/50
09 0.47u 40 21
AVSS DOUT DIT VOUT
R2427
41 20
1-74
1.8k
RX0 UOUT
42
NC_AVSS3
IC2405 COUT
19
GNDD
NC_AVSS1
43
AK4114VQ 18
IPS0/RX4
DIF0/RX5
RX1 BOUT (DIG OUT)

Q2404
STBY
44 17 R2434 R2426
2SC2412K(RS)
TEST1 NC_DVSS1 TX1
45 TVDD 16 22
NC_AVSS2
2.7k
RX2 TX0 1
DIF1/RX6
DIF2/RX7
R2430 R2432 L2401

IPS1/IIC
46 15
Digital OUT
TEST2
NC_AVSS4
C2417 NM 2
68 0
XTL0
XTL1
P/SN
47 14 C2412
0.1u/25
VIN
RX3 JA2401
D
R2428
R2429
R2431
48 13 0.1u DKB1089-A
100k
220
3.9k
9
2
8
1
10
11
12
10k
R2424
R2423
10k
GNDD
XTAL:24.576MHz GNDD
NOTES
(DIG OUT) NM is STBY

: DIGITAL OUT Signal RS1/16S****J
RS1/10S****J
RN RN1/16S****J
: Waveform measuring point RN1/10S****J
E
(D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J
2W RS2****J
RAB4CQ****J
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH****
+
CEVW***
+
HA CEHVAW**
NP CEVWNP***
F
G 16/21
DJM-900NXS 153
5 6 7 8
1 2 3 4
10.29 MAIN ASSY (17/21)
A
V+15A
R2605 0 1/4W
V-15A
V+5A
From POWER IF Block GNDA_O
GNDA_M1
V+18VMUTE
R2607 0
B
Digital Analog
CPV_MUTE_O
G 12/21,21/21 R2608 0
CPU_MUTE
From MAIN CPU Block 12:2F;21:2G
Low MUTE
High MUTE release
NOTES
is STBY
NM
RS1/16S****J
RS1/10S****J
RN RN1/16S****J
RN1/10S****J
C (D) RS1/16S****D
RS1/10S****D
(F) RS1/16S****F
RS1/10S****F
1/8W RS1/8S****J
1/4W RS1/4S****J V+12D R2609 0 1/4W
2W RS2****J
V+3R3D 0
R2610 1/4W
RAB4CQ****J V+5D 0
R2611 1/4W
CKSRYB****
CKSSYB****
CH CCSRCH****
CCSSCH****
CCSQCH**** GNDD
+
CEVW***
+
HA CEHVAW** 13:3H;21:2B
24M_CLK_AOUT
CEVWNP*** R2614
NP
0
D
1-75
From FPGA Block 13:3G;21:2C

6M_CLK_AOUT
R2615
G 13/21,21/21 0
1-76
13:3G;21:2D
96K_CLK_AOUT
R2616
E 1-77
G 1/21,10/21,21/21 1-78
R2601 0
From LAN UCOM_2 Block DIR_ADC_DAC_RESET
1:5G;10:15H;21:2E
(SEND D) R2617 0
ADAT_SEND
G 15/21 15:3G
ADAT_BOOTH
(BO D)
(REC D)
R2618 0
15:3G R2619 0
From DSP_2 Block ADAT_REC
(MA D)
15:3G R2620 0
ADAT_MASTER
15:3G
G 1/21 MVR_MUTE
R2621 0
1:4B
From BOARD IF Block
F (PANL A )
G 17/21
154 DJM-900NXS
1 2 3 4
5 6 7 8
V+15A_O
OUTPUT IF
V-15A_O GNDA_M2 GNDA_REC GNDA_BO
V+5A_O

STBY
R2624 NM (SEND D)
R2625 NM
STBY
(BO D)
C2606 NM
GNDA_SE
1
C2607 NM (REC D)
: BOOTH OUT Digital Signal
KN2601
CKF1089-A
(MA D)
: REC OUT Digital Signal
R2633 0
GNDA_M1
GNDA_F GNDD
V+18VMUTE_O
VMUTE_O B
R2629
R2635
51k
22k
LSA1576UB(QRS)
Q2603
nalog
R2637 R2636
MUTE_O
1-83 G 1/21,19/21,20/21
11k
R2630
51k
LSC4081UB(QRS)
CH 1 0 0 0 p / 5 0
C2608
MUTE_OUT
11k
1:11C;19:2D;19:2H;20:2H To MASTER1 Block
C2602
R2638
100p/50
Q2601
MASTER2/REC Block
CH
51k
Low MUTE release
Q2602
R2639
High MUTE BOOTH Block
LTC124EUB 51k
GNDA_BO
BOARD IF(SEND) Block
GNDA_O GNDA_OV-15A_O
GNDA_O
CPU_MUTE_OUT
18:2K
To MASTER1 Block
V+12D_O V+3R3D_O V+5D_O
STBY
Low MUTE G 18/21
High MUTE release
DCH1201-A
NM
C2612 1000p/50
C
10u 10V
CH
C2613
C2614
GNDD
IC2602 V+3R3D_O
TC7SH08FUS1 GNDD
C2603 1-79
0.1u/10
1 5
R2602 24M G 20/21
INB 4 1 8 20:2B
To BOOTH Block
2
INA
3 2 7 19:2E
MCLK_OUT_BO
To MASTER2/REC Block
G 19/21
OUTY 1:11C
MCLK_OUT_RE
D
3
4
6
5 18:2D
MCLK_OUT_SE To BOARD IF(SEND) Block G 1/21
GNDD To MASTER1 Block
V+3R3D_O
22
MCLK_OUT_M1
G 18/21
IC2603
TC7SH08FUS1 1-80
1 5
C2604
0.1u/10 R2603
6M G 20/21
INB 4 1 8 20:2B
To BOOTH Block
2
INA
3 2 7 19:2E
BCLK_OUT_BO
To MASTER2/REC Block
G 19/21
OUTY BCLK_OUT_RE
3
4
6
5
1:11C
18:2D
BCLK_OUT_SE To BOARD IF(SEND) Block G 1/21
GNDD To MASTER1 Block
V+3R3D_O
22
BCLK_OUT_M1
G 18/21
IC2604
TC7SH08FUS1 1-81
1 5
C2605
0.1u/10
R2622 96k G 19/21
INB 4 1 8 19:2E
To BOOTH Block
2
INA
3 2 7 20:2B
LRCLK_OUT_RE
LRCLK_OUT_BO To MASTER2/REC Block

G 20/21
OUTY
GNDD
3
4
6
5
1:11D
18:2D
LRCLK_OUT_SE To BOARD IF(SEND) Block G 1/21 E
LRCLK_OUT_M1 To MASTER1 Block
22 G 18/21
V+3R3D_O V+3R3D_O
IC2601
TC7SH08FUS1 1-82
R2634
10k
C2601
1 5 0.1u/10 RESET To BOARD_IF(SEND) Block
INB
INA
4 R2623
22
RESET_OUT
MASTER1 Block
MASTER2/REC Block
G 1/21,18/21-20/21
2 3 1:11D;18:2C;19:2E;20:2C
OUTY BOOTH Block
BOARD IF Block
GNDD ADAT_SEND_OUT
1:11C
20:2B
To BOARD IF Block G 1/21
To BOOTH Block
ADAT_BOOTH_OUT
19:2E
ADAT_REC_OUT To MASTER2/REC Block G 20/21
18:2D
ADAT_MASTER_OUT
G 19/21
18:2D
To MASTER1 Block
MVR_MUTE_OUT
G 18/21 F
G 17/21
DJM-900NXS 155
5 6 7 8
1 2 3 4
10.30 MAIN ASSY (18/21)
A 32BIT DAC Shaping Noise Filter V+15A_M1

C2854
0.1u/50
STBY
1 point contact V+15A_M1
C2855
R2885
V+15A_M1_ICP 220u/35
HA
R2869
R2877
R2882
NM
330k
2.2k
2.2k
RN
RN
GND_PO
(D)
V+5A_O V+5A_M1 (1/2) C2863
C2848 IC2803
4700p/50 NJM4580MD
220u/35
0.047u/50
C2810
6
HA
ZZ2801 8 C2864
7
R2873 180
V+15A_O V+15A_M1 470u/16
4 HA
5
HN1C01FU(YGR)

DJM 900 Nexus

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ORDER NO.

THIS MANUAL IS APPLICABLE TO THE FOLLOWING MODEL(S) AND TYPE(S).

DJM-900NXS SYXJ8 AC 220 V to 240 V

DJM-900NXS UXJCB AC 120 V

DJM-900NXS KXJ5 AC 220 V

DJM-900NXS XJCN5 AC 220 V to 240 V

For details, refer to "Important Check Points for good servicing".

PIONEER CORPORATION 1-1, Shin-ogura, Saiwai-ku, Kawasaki-shi, Kanagawa 212-0031, Japan

(FOR USA MODEL ONLY)

1 Use specified parts for repair.

Use genuine parts. Be sure to use important parts for safety.

2 Do not perform modifications without proper instructions.

3 Make sure the soldering of repaired locations is properly performed.

4 Make sure the screws are tightly fastened.

5 Make sure each connectors are correctly inserted.

9 There should be no spark traces or similar marks on the power plug.

a Safe environment should be secured during servicing.

3. Lubricants, Glues, and Replacement parts E

5. Shipping mode and Shipping screws

10.21 MAIN ASSY (9/21).................................................................................................................................................. 138

Do NOT use a soldering iron whose tip temperature cannot be controlled.

The following lead-free solders are available as service parts:

1.2 NOTES ON REPLACING

1.3 SERVICE NOTICE

FLASH ROM ON THE MAIN Assy

1.4 ON MODIFICATION OF THE VOLTAGE-MONITORING CIRCUITS

STBY D1205 V+9HP

STBY C1216 KIA7809API C1218 D1203

GNDA_HP GNDA_HP V-9HP

Timing of the production:

numbers beginning with KC or KD

2 Soldering of a lead wire or a piece of wire to R1205

2. Securing the lead wires (pieces of wire) to

2 Mounting pieces of wire [DDC1022] instead of the resistors [R1205, R1206].

2.2 PANEL FACILITIES

3. BASIC ITEMS FOR SERVICE

9 USB B The device must be properly recognized by the PC.

3.2 JIGS LIST

Lubricants and Glues List

Name Part No. Remarks

3.3 PCB LOCATIONS

FAD2 ASSY N O FAD3 ASSY

> 1..POWER SUPPLY ASSY DWR1492

of the safety factor of the part. L

K K 1/2, K 2/2 MIC1 ASSY

L= 125mm L= 75mm L= 75mm L= 125mm

WHITE RED BLUE YELLOW

36 CH1 SEL(Time code)

FAD1 ASSY FAD2 ASSY FAD3 ASSY FAD4 ASSY CN6602

(DWX3198) (DWX3199) (DWX3200) (DWX3201) 31 V+5D_LED

5 CH1 SEL(Time code)

31P FFC 14 14 KEY_MTX_SEL5 3 VR_FADER2

PF03PP-B07 PHONES CN9201

20 GNDD 21 GNDD 7 R_out

40P FFC L=90mm P=0.5mm

29 29 CH3_SEL(Time code) 12 12 CH3_SEL(Time code)

MAIN ASSY (DWX3190)

33 33 CH4_DATA 8 CH4_DATA XKP3065-A XKP3076-A

Digital power supply