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    EE230Project Muhammad&Chad

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    This document describes a 1.9 GHz CP PLL design using a 45nm CMOS technology. It includes Matlab and VerilogA simulations of the PLL components including a PFD, charge pump, loop filter, LC VCO, current starved ring VCO and divider. System simulations show the PLL locks with less than 2.1us using either VCO, but the LC VCO achieves lower RMS jitter of 1.54ps versus 18.96ps for the ring VCO. Corner simulations demonstrate the output frequency ranges from 1.916 to 1.946 GHz and feedback frequency ranges from 30.015 to 30.077 MHz after locking.

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    EE230Project Muhammad&Chad

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    10 views56 pages
    This document describes a 1.9 GHz CP PLL design using a 45nm CMOS technology. It includes Matlab and VerilogA simulations of the PLL components including a PFD, charge pump, loop filter, LC VCO, current starved ring VCO and divider. System simulations show the PLL locks with less than 2.1us using either VCO, but the LC VCO achieves lower RMS jitter of 1.54ps versus 18.96ps for the ring VCO. Corner simulations demonstrate the output frequency ranges from 1.916 to 1.946 GHz and feedback frequency ranges from 30.015 to 30.077 MHz after locking.

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    EE230Project_Muhammad&Chad

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    This document describes a 1.9 GHz CP PLL design using a 45nm CMOS technology. It includes Matlab and VerilogA simulations of the PLL components including a PFD, charge pump, loop filter, LC VCO, current starved ring VCO and divider. System simulations show the PLL locks with less than 2.1us using either VCO, but the LC VCO achieves lower RMS jitter of 1.54ps versus 18.96ps for the ring VCO. Corner simulations demonstrate the output frequency ranges from 1.916 to 1.946 GHz and feedback frequency ranges from 30.015 to 30.077 MHz after locking.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    10 views56 pages

    EE230Project Muhammad&Chad

    Uploaded by

    Trần Tấn Đại
    This document describes a 1.9 GHz CP PLL design using a 45nm CMOS technology. It includes Matlab and VerilogA simulations of the PLL components including a PFD, charge pump, loop filter, LC VCO, current starved ring VCO and divider. System simulations show the PLL locks with less than 2.1us using either VCO, but the LC VCO achieves lower RMS jitter of 1.54ps versus 18.96ps for the ring VCO. Corner simulations demonstrate the output frequency ranges from 1.916 to 1.946 GHz and feedback frequency ranges from 30.015 to 30.077 MHz after locking.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 56

    EE230 – Final Project

    1.9 GHz CP PLL Design


    (using 45nm CMOS Technology)

    Muhammad Aldacher
    Chad Santos
    Overview
    1) Project Target
    2) Matlab Simulations
    3) VerilogA Simulations
    4) PLL Circuits
    a. PFD
    b. Charge Pump
    c. Loop Filter
    d. VCO
    i. LC tank
    ii. Current-Starved Ring
    e. Divider
    5) System Simulations
    6) Corner Simulations
    7) Summary
    (1)
    Project Target
    Target

    𝑃𝑜𝑤𝑒𝑟
    𝐹𝑂𝑀 = 10 log 𝐽𝑖𝑡𝑡𝑒𝑟 2 . < −220 𝑑𝐵
    1 𝑚𝑊
    PLL Block Diagram
    (2)
    Matlab Simulations
    System Parameters
    Parameter Value
    FREF 30 MHz
    FOUT 1.9 GHz
    MDivider 64
    ICP 100 uA
    KVCO 600 MHz/V
    RP 6.5 KΩ
    CP 100 pF
    C2 10 pF
    Open-Loop Bode Plots
    Closed-Loop Bode Plots
    Bode Plot Parameters

    Parameter Value

    Zero fz 0.245 MHz

    Unity-Gain BW fugb 0.871 MHz

    Pole fp3 2.693 MHz

    Max Phase Margin PMMax 56.44°


    Phase Margin PM 56.38°
    Closed-Loop BW BW 1.41 MHz
    (3)
    VerilogA Simulations
    Test Bench
    Waveforms
    Ref

    Fb

    Freq_Fb

    Up

    Dn

    Vcontrol

    VCO_out

    Freq_out
    (4)
    PLL Circuits
    1- PFD
    2- Charge Pump
    2- Charge Pump

    OpAmp
    3- Loop Filter
    PFD/CP
    Vcontrol

    Dn

    Up_Bar

    Ref

    Feedback

    Reference lagging by 1ns


    PFD/CP
    Vcontrol

    Dn

    Up_Bar

    Ref

    Feedback

    Reference leading by 1ns


    4- VCO
    a) LC VCO
    LC Oscillator

    VCO_Out

    VCO_Freq
    LC Oscillator

    VCO_Freq
    sweep

    Vcontrol Tuning Range


    LC Oscillator

    Phase
    Noise

    Phase Noise at 1MHz Offset


    4- VCO
    b) Current Starved Ring VCO

    Inverter stages
    Current Starved Ring Oscillator

    VCO_Out

    VCO_Freq
    Current Starved Ring Oscillator

    VCO_Freq
    sweep

    Vcontrol Tuning Range


    Current Starved Ring Oscillator

    Phase
    Noise

    Phase Noise at 1MHz Offset


    5- Divider
    ➢Divide-by-64
    (6 Divide-by-2 blocks)

    CMOS TSPC
    5- Divider
    a) TSPC Flipflop
    5- Divider
    b) CMOS Flipflop
    (5)
    PLL System Simulations
    Test Bench
    A. Using LC VCO
    Waveforms
    Ref

    Fb

    Freq_Fb

    Up

    Dn

    Vcontrol

    VCO_out

    Freq_out
    RMS Jitter
    RMS Jitter

    RMS Jitter = 1.5431 ps


    (integrated from 1KHz to 1GHz)
    Pk-Pk Jitter
    PkPk Jitter
    @diff. BERs
    (integ. From
    1K to 1G)
    Eye Diagram Jitter
    Eye Diagram Jitter
    B. Using Current-Starved Ring
    VCO
    Waveforms
    Ref

    Fb

    Freq_Fb

    Up

    Dn

    Vcontrol

    VCO_out

    Freq_out
    RMS Jitter
    RMS Jitter

    RMS Jitter = 18.9632 ps


    (integrated from 1KHz to 1GHz)
    Pk-Pk Jitter
    PkPk Jitter
    @diff. BERs
    (integ. From
    1K to 1G)
    Comparison
    PLL with LC VCO PLL with Ring VCO

    Tuning Range 1.68 GHz – 2.02 GHz 0.5 GHz – 3 GHz

    Locking Time < 2.1 us < 1.5 us

    P dissipation 1.26175 mW 1.21701 mW

    RMS Jitter 1.5421 ps 18.9632 ps

    FOM -235.23 dB -213.59 dB


    (6)
    Corner Simulations
    All Corners

    Freq_out

    Freq_Fb
    Nominal
    TT, 27°, 1 VDD

    Freq_out

    Freq_Fb
    FF, 125°, 0.9 VDD

    Freq_out

    Freq_Fb
    FF, 125°, 1.1 VDD

    Freq_out

    Freq_Fb
    FF, -40°, 0.9 VDD

    Freq_out

    Freq_Fb
    FF, -40°, 1.1 VDD

    Freq_out

    Freq_Fb
    SS, 125°, 0.9 VDD

    Freq_out

    Freq_Fb
    SS, 125°, 1.1 VDD

    Freq_out

    Freq_Fb
    SS, -40°, 0.9 VDD

    Freq_out

    Freq_Fb
    SS, -40°, 1.1 VDD

    Freq_out

    Freq_Fb
    (7) Summary
    • Our work shows a comparison between a CP-PLL using
    a Ring VCO & another using an LC VCO:
    – The Ring VCO gives a higher KVCO, which affects the PLL’s
    stability & gives a higher jitter than that in the LC VCO.
    – Using the LC VCO, we were able to achieve a low RMS jitter
    with a reasonable power dissipation, achieving the
    required FOM.

    • In our corners’ analysis:


    – The range of the output frequency after the PLL locks is
    between 1.916 GHz & 1.946 GHz.
    – The range of the feedback frequency after the PLL locks is
    between 30.015 MHz & 30.077 MHz.

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