1948 JOURNAL OF MODERN POWER SYSTEMS AND CLEAN ENERGY, VOL. 11, NO.

6, November 2023

Fault Detection for Microgrid Feeders

Using Features Based on Superimposed
Positive-sequence Power
Salauddin Ansari, Om Hari Gupta, Senior Member, IEEE, and Om P. Malik, Life Fellow, IEEE

Abstract—
—With the integration of distributed generation (DG) may fail to detect the faults correctly. Moreover, there is a
into a microgrid, fault detection has become a major task to ac‐ lot of discussion in the literature on the difficulties and chal‐
complish. A scheme for microgrid feeder protection based on a
newly proposed feature, DRP, defined as the ratio of the sum of
lenges that the microgrid faces in terms of protection. It is
positive-sequence real power (PSRP) at the two ends of the feed‐ recommended in [4] that primary and backup protection
er to the larger of the PSRPs among the two ends, is proposed. should be provided by measuring the change in fault current
If DRP is larger than a threshold, an internal fault is detected; in a steady state. However, in the event of high-resistance
otherwise, the fault is external or there is no fault. The pro‐ faults, this scheme may not provide satisfactory results. In
posed scheme is tested in various scenarios, including fault
type, fault resistance, fault location, fault inception angle, vary‐ [5], the impact of DG penetration on relay coordination is
ing DG penetration levels, and simultaneous, evolving, and com‐ analyzed and an adaptive protection scheme is proposed. But
posite faults. In addition to this, the proposed scheme offers a this scheme only works well for low penetration of the DGs.
robust performance when subjected to noise, synchronization er‐ Furthermore, a neural network-based fault detection is pre‐
ror, changes in sampling frequency, and changes in the topology sented in [6], necessitating a significant amount of data stor‐
of a microgrid. The dominancy of the proposed scheme is prov‐
en by a comprehensive comparative study with various avail‐ age. In [7], a differential phase jump pilot protection scheme
able recent schemes. Test results on the IEEE 13-bus network to determine faulty branches in a distribution system is sug‐
indicate the viability of the proposed protection scheme for a gested which may fail if there is a high resistance fault.
microgrid. Finally, the proposed scheme has been validated on Next, a positive-sequence current based scheme for a mi‐
a real-time simulator.
crogrid, presented in [8], can only be applied when there is
Index Terms— —Fault detection, distributed generation, mi‐ a low-resistance fault. Another adaptive scheme that uses a
crogrid, protection, superim, posed power. cycle-to-cycle comparison and current signal is proposed in
[9]. However, the upgradation of the relay setting is required
for any network changes. In [10], a differential technique for
I. INTRODUCTION
calculating the differential spectral energy content at the pro‐

A S conventional fossil-fuel energy sources cause environ‐

mental pollution, the incorporation of clean energy
sources such as solar, wind, and fuel cells, in the form of
tected feeder ends using Hilbert-Huang and S-transforms is
proposed. The scheme may fail due to unbalanced loads and
DG transients. Further, a traveling wave based algorithm,
distributed generators (DGs) in a microgrid, is rising rapidly. proposed in [11], requires high sampling rate. In [12], a pro‐
The presence of DGs significantly affects the operation of tection scheme based on wavelet transform and fuzzy logic
the network and traditional protection schemes may become is developed for fault identification in the microgrid. Howev‐
ineffective [1]. The conventional fault detection schemes are er, the primary challenge in using this scheme is the com‐
based on overcurrent [2] and distance-based relaying [3], plexity of finding proper membership functions and fuzzy
and most of these schemes operate mainly with radial net‐ rules. Next, in empirical mode [13], the current signal is de‐
works. Nonetheless, because of the bidirectional power flow composed to find out the differential energy for fault detec‐
in a microgrid, a conventional overcurrent protection scheme tion. The only thing in this scheme is that the effect of high
fault resistance and noise in the measurement is not consid‐
Manuscript received: August 8, 2022; revised: December 1, 2022; accepted: ered. In another scheme proposed in [14], a change in the
January 20, 2023. Date of CrossCheck: January 20, 2023. Date of online publi‐ current frequency component is calculated from both ends of
cation: February 22, 2023.
This article is distributed under the terms of the Creative Commons Attribu‐ the protected feeder for fault detection in the microgrid.
tion 4.0 International License (http://creativecommons.org/licenses/by/4.0/). Since in this scheme, a frequency is injected through the DG
S. Ansari (corresponding author) and O. H. Gupta are with the Department of
Electrical Engineering, National Institute of Technology, Jamshedpur 831014, In‐
interface whenever there is a fault, it continuously degrades
dia (e-mail: [email protected]; [email protected]). the power quality. Next, a time-frequency transform-based
O. P. Malik is with the Department of Electrical and Software Engineering, scheme, introduced in [15], uses differential current as a
University of Calgary, 2500 University Drive NW, Calgary Alberta T2N 1N4,
Canada (e-mail: [email protected]). fault detection index. This scheme finds limitation since it is
DOI: 10.35833/MPCE.2022.000499 sensitive to noise and has slow speed. The next scheme, pre‐
ANSARI et al.: FAULT DETECTION FOR MICROGRID FEEDERS USING FEATURES BASED ON SUPERIMPOSED POSITIVE-SEQUENCE POWER 1949

sented in [16], contains protection scheme for microgrids by II. PROPOSED FAULT DETECTION SCHEME
applying a short-time correlation transform of superimposed In the proposed scheme, the feature DRP derived below is
voltage and current signal. This technique does not include utilized for the identification of an internal fault.
the high-resistance faults in the study. Further, a current sig‐
nal is used to identify faults in microgrids using the transient A. Relaying Feature
energy function approach in [17]. As a result, this scheme is Consider a typical two-terminal feeder as presented in
sensitive to measurement noise and large load connections, Fig. 1. The feeder to be protected, with positive-sequence im‐
and may not provide accurate results. Next, a current-based pedance Z, is joined between the ends m and n. Em, En and
fault current approach for microgrid protection has been pro‐ Zm, Zn are the Thevenin’s equivalent voltages and impedanc‐
posed in [18], in which the difference between positive se‐ es at the ends m and n, respectively; and Vm, Vn and Im, In
quence current fault component and pre-fault bus voltage is are the positive-sequence voltages and currents at the ends m
utilized to detect the fault in the feeder. However, this and n, respectively.
scheme is not verified for high-impedance fault, noise in the
End m Protected feeder End n
measuring device, and some of the critical non-fault events
Im In
like load and capacitor switching. In [19], the detection of Zm Z Zn
single line-to-ground faults with and without line breaks has
Em Vm Vn En
been proposed using phase difference voltages between
faulty phases and non-faulty phases at the load end. This
Fig. 1. Equivalent diagram of a two-terminal feeder.
scheme uses a phasor measurement unit to calculate phase
differences which requires a high sampling rate and is also
costly. Apart from that, this scheme is also not tested for On the occurrence of a fault at any point in the microgrid,
noise in the measuring device, load, and capacitor switching. variables such as voltage and current experience consider‐
Overall, the above-mentioned schemes (e. g., current-based, able changes with respect to their respective pre-fault values.
differential-based, feature extraction-based) have their own Therefore, every electrical variable under fault consists of
limitations in accurately detecting the fault events with high two components: the pre-fault component and the superim‐
resistance, measurement noise, and some of the critical non- posed component [20]. The change in variable, i.e., the incre‐
fault events like load switching and capacitor switching. mental or superimposed component, is denoted by the prefix
Therefore, to address the abovementioned shortcomings, a “ Δ”. Hence, every arbitrary variable ψ(t) under a fault can
protection scheme based on a newly proposed feature, DRP, be represented by:
is introduced. DRP is defined as the ratio of the sum of posi‐ ψ f (t) = ψ pf (t) + Dψ(t) (1)
tive-sequence real power (PSRP) at the two ends of the feed‐ where ψ f (t), ψ pf (t), and Dψ(t) are the fault, pre-fault, and su‐
er to the maximum of the PSRPs among the two ends. The perimposed components, respectively. Thus, using (1), the su‐
key contributions of the DRP-based scheme are described as perimposed component can be represented as:
follows.
Dψ(t) = ψ f (t) - ψ pf (t) (2)
1) Symmetrical and unsymmetrical faults with up to 500 Ω
fault resistance can be detected. It is to be noted that the superimposed component is ab‐
2) It is unaffected by the changes in the location of the sent during normal/pre-fault conditions but will be induced
fault, the amount of DG penetration, and the angle of incep‐ by the fault within the microgrid. The superimposed compo‐
tion of the fault. nent can be obtained in the discrete form [21] by subtracting
3) It is unaffected by the change in a network configura‐ the current sample of a variable from its corresponding sam‐
tion as there will not be any change in the threshold settings. ple to the cycle before this one and mathematically ex‐
4) It works successfully for evolving, simultaneous, and pressed as:
composite faults. Dψ x (k) = ψ x (k) - ψ x (k - N) (3)
5) It is robust against measurement noise, changes in sam‐ where ψ = V or I, denoting the power system voltage or cur‐
pling frequency, changes in the topology of the microgrid,
rent signals, respectively; k is the sampling step; N is the
capacitor switching, load switching, and induction motor
number of samples in one cycle which is taken as 50; and x
starting, etc.
defines the relaying end, i.e., x = m or n for the end m or end
6) It is unaffected by wide-range synchronization errors.
n, respectively. The proposed relaying feature, i. e., DRP, is
7) Since it is based on a sample-based windowing ap‐
defined as:
proach, the proposed scheme is easy to implement. Com‐
DP m + DP n
pared with a few recent schemes, the performance of the pro‐ DRP = (4)
posed scheme is found to be better. DP α
Subsequent sections are laid out as follows. The proposed where DP n = Re(DSˉn ); DP m = Re(DSˉm ); and the value DP α de‐
fault detection scheme is illustrated in Section II, and de‐ pends upon the conditions that are given in (5).
tailed simulation results are described in Section III. The ad‐ DSˉn = DVˉn DIˉn*, DSˉm = DVˉm DIˉm*, and DP m, DP n, DSˉm, DSˉn, DVˉm,
ditional studies are presented in Section IV. Real-time valida‐ DVˉn, DIˉm, DIˉn are the superimposed positive-sequence (SPS)
tion results, obtained to validate the proposed scheme, are real power, apparent power, voltages, and currents at the
given in Section V. Conclusion is given in Section VI. ends m and n, respectively.
1950 JOURNAL OF MODERN POWER SYSTEMS AND CLEAN ENERGY, VOL. 11, NO. 6, November 2023

ì DP m
ï | DP m | > | DP n | End m Protected feeder End n
ï ΔIm ΔIn
| DP n | > | DP m |
Zm Z Zn
DP α = í DP n (5)
ï +
ïî DP m or DP n | DP m | = | DP n | F2 
vf ΔVm ΔVn

The outcome of DRP depends on the fault conditions and (a)

will be different under different fault conditions, as shown End m Protected feeder End n
below. Zm ΔIm Z ΔIn Zn

B. Internal Fault ΔVm ΔVn

+
vf

Consider an SPS two-bus network for an internal fault as F3

displayed in Fig. 2. The fault, at a distance ρ (per unit) less (b)

than 1 from the end m, is within the protected feeder. And vf Fig. 3. Equivalent SPS two-bus network for an external fault. (a) At end
is the fault point voltage. m. (b) At end n.

End m End n
Protected feeder 1) Case 1
In this case, | DP m | > | DP n |, i. e., DP α = DP m. Consider an
Zm ΔIm ρZ (1ρ)Z ΔIn Zn

ΔVm
+
vf ΔVn equivalent SPS two-bus network for an external fault at the
F1  end m, as displayed in Fig. 3(a). In this case, DP m = (R +
R n ) | DIˉm | and DP n = -R n| DIˉn | , where R is the line resis‐
2 2
Fig. 2. Equivalent SPS two-bus network for an internal fault.
tance. Now, DRP can be written as:
(R + R n ) | DIˉm | - R n| DIˉn | R n| DIˉn |
2 2 2
Using Fig. 2, DP m and DP n can be derived as DP m =
DRP = =1- (9)
-R m| DIˉm | and DP n = -R n| DIˉn | [22] and will be the same for (R + R n ) | DIˉm | (R + R n ) | DIˉm |
2 2 2 2

different cases of internal faults. Here, R n = Re(Zˉn ) and R m =

2) Case 2
Re(Zˉm ). However, the value of DP α will be different for dif‐
In this case, | DP n | > | DP m |, i. e., DP α = DP n. Consider an
ferent cases/locations of internal faults. The three different
equivalent SPS two-bus network for an external fault at end
cases can be below.
n, as displayed in Fig. 3(b). In this case, DP m = -R m| DIˉm |
2
1) Case 1
In this case, | DP m | > | DP n |, i. e., DP α = DP m. DRP, as de‐ and DP n = (R + R m ) | DIˉn | . Now, DRP can be written as:
2

(R + R m ) | DIˉn | - R m| DIˉm | R m| DIˉm |

fined in (4), can be written as: 2 2 2

-R m| DIˉm | - R n| DIˉn | R n| DIˉn | DRP = =1-

2 2 2

(R + R m ) | DIˉn | (R + R m ) | DIˉn |
2 2
DRP = =1+ (6)
-R m| DIˉm | R m| DIˉm |
2 2
(10)
2) Case 2 It can be observed from (9) and (10) that DRP will be al‐
In this case, | DP n | > | DP m |, i. e., DP α = DP n. DRP can be ways less than 1 for an external fault in each case.
written as: D. Relaying Scheme
-R m| DIˉm | - R n| DIˉn | R m| DIˉm |
2 2 2
As per (6)-(10), the value of DRP will be high for the in‐
DRP = =1+ (7)
-R n| DIˉn | R n| DIˉn |
2 2 ternal fault while low for the external fault. For the imple‐
mentation of a relaying scheme, the threshold selection plays
3) Case 3 a crucial role and the same is discussed next.
In this case, DP m = DP n, i.e., DP α = DP n = DP m. DRP can be 1) Threshold Selection
written as: In a practical system, when an internal fault is incepted
close to the end m, | DI m | will be far more than | DI n | and
-R m| DIˉm | - R m| DIˉm |
2 2

DRP = =1+1=2 (8) Thevenin’s equivalent resistance at the end m and end n
-R m| DIˉm |
2
will be comparable. Therefore, for such internal faults, the
second term in (6) can be very small compared with 1 and
It can be observed from (6)-(8) that in each of the cases,
DRP will be more than 1 but by a very small margin (say
DRP will be always more than 1 for an internal fault.
1.05). Similarly, the second term in (7) can be also very
C. External Fault small compared with 1 and DRP can again be just above 1
Assuming that the charging current in a distribution net‐ (in magnitude). Also, it is clear from (8) that the maximum
work is zero, the formulas of SPS real power, i.e., DP m and value of DRP is 2. For the external fault, DRP will be very
DP n, can be obtained using Fig. 3 [22]. Again, DP α will be small and close to zero. The reason for this is that the sec‐
different in different cases, which are described in the fol‐ ond term in (9) and (10) will be close to 1 because | DI m |
lowing text. and | DI n | will be approximately equal. R n and R + R n will al‐
ANSARI et al.: FAULT DETECTION FOR MICROGRID FEEDERS USING FEATURES BASED ON SUPERIMPOSED POSITIVE-SEQUENCE POWER 1951

so be nearly the same due to the negligible value of feeder powered DGs are incorporated into the conventional IEEE
resistance R. Overall, the value of DRP, for the internal 13-bus network at buses 634, 671, 675, and 680. At the two
fault, will vary between 1 to 2 while for external fault it will ends of the protected line, two measurement devices (Mm
be close to zero. The same is depicted in Fig. 4. Based on and Mn) are installed to calculate the voltages and currents.
rigorous study, the minimum value of DRP for internal faults The results obtained are discussed next.
is found to be 1.056 and the maximum value of DRP for ex‐ 650 Protected zone
ternal faults is found to be 0.042. With a sufficient safety
646 645 633 T 634
margin and for accurate detection of internal fault, the thresh‐ 632
Mm Mn DG1
old value Ka is selected to be 0.5.
F2 F1 F3
DG2 Relay CB
0 1 2
External fault; Internal fault 671
DG3
Fig. 4. Variation of ΔRP under internal and external faults. 684
611 692 675
680 2-phase feeder
652
DG4 1-phase feeder
2) Implementation of Proposed Scheme
Whenever DRP exceeds Ka, an internal fault is detected; Fig. 6. Modified IEEE 13-bus network.
otherwise, it is the case of external disturbance, external
fault, or healthy condition. A flow chart of the proposed TABLE I
scheme is shown in Fig. 5. At the beginning, 3-phase voltag‐ PARAMETERS OF INTEGRATED SOLAR-BASED DGS
es and currents are measured at both ends of the protected
feeder, and the phasors of the voltage and current signals are Parameter Symbol Value
calculated using discrete Fourier transform (DFT) [23]. The maximum power point (MPP) power Pmpp 100 kW
Next, DRP is computed using (4). If the value of DRP is Number of strings in parallel Nsp 66
more than the threshold, i.e., Ka, an internal fault is detected Number of series modules for each string Nsmes 5
and a trip signal is produced; otherwise, it is a case of the Number of cells for each module Ncem 96
external fault. Then, the scheme goes to the return block. Voltage under open-circuit condition Vocc 64.2 V
Current under short-circuit condition Iscc 5.96 A
Start
MPP voltage Vmpp 54.7 V
Measure 3-phase voltages and currents at MPP current Impp 5.58 A
both the ends of the protected feeder

Obtain phasor with the help of DFT TABLE II

PARAMETERS OF TRANSFORMER
Compute ΔRP using (4)
Parameter Value
N Rated power 500 kVA
ΔRP > Ka?
Rated primary voltage 480 V
Y
Rated secondary voltage 4.16 kV
Internal fault External fault
detected detected Configuration of winding Yg
Inductance of winding 0.02 p.u.
Trip Return Resistance of winding 0.011 p.u.
Frequency 60 Hz
End
Fig. 5. Flow chart of proposed scheme.
A. Effects of Fault Type, Fault Location, and Fault Resis‐
tance R f
III. SIMULATION RESULTS The current I, DRP, and FDSs for an a-g internal fault in
The scheme has been tested for changes in Rf, fault loca‐ the middle of the protected feeder with R f = 20 Ω at 0.1 s, as
tion, fault inception angle, and DG penetration (DGP) level. one illustrative example, are shown in Fig. 7.
It has also been tested for simultaneous faults and evolving It is noticed that DRP exceeds the threshold Ka and, as a
faults. The index DRP has been used to generate a fault de‐ result, an FDS signal is generated at 0.10733 s. The results
tection signal (FDS). Whenever there is an internal fault, for different fault types, fault locations, and fault resistance
FDS should be 1; otherwise, it should be zero. A modified are given in Table III. All examined events of fault are iden‐
IEEE 13-bus network [24], as shown in Fig. 6, is applied to tified correctly within the average detection time Td of 7.422
assess the functioning of the suggested technique – the cir‐ ms. For internal fault events, DRP is more than Ka (FDS
cuit breaker (CB) is in an open condition normally. The pa‐ turns 1), and for external fault events, DRP is less than Ka
rameters of the incorporated solar-based DGs and transform‐ (FDS turns 0). It is concluded from the obtained results that
er are presented in Tables I and II, respectively. Four solar- the proposed technique effectively detects internal faults.
1952 JOURNAL OF MODERN POWER SYSTEMS AND CLEAN ENERGY, VOL. 11, NO. 6, November 2023

400 Phase a; Phase b; Phase c TABLE IV

200 RESULTS FOR HIGH-RESISTANCE FAULTS
I (A)
0
-200
-400 Fault Fault Internal/
ΔRP=1.414 Rf (Ω) ΔRP Td (ms) FDS
1.5 Threshold ΔRP type location (m) external
ΔRP

1.0 is crossed Ka
0.5 c-g 30.48 100 Internal 1.1170 18.00 1
0 b-g 45.72 300 Internal 1.1930 25.00 1
1 a-g 76.20 500 Internal 1.1536 14.67 1
FDS

Fault is incepted (0.10733 s,1.00000)

abc-g 91.44 500 Internal 1.1540 10.00 1
0
0.08 0.09 0.10 0.11 0.12 0.13 0.14
Time (s)
1.5 ΔRP ΔRP=1.1536
Fig. 7. Results for an a-g internal fault in middle of protected feeder with Threshold
1.0 Ka is crossed

ΔRP
R f = 20 Ω. 0.5
0
-0.5
TABLE III 1

FDS
RESULTS FOR DIFFERENT FAULT TYPES, LOCATIONS, AND RESISTANCES Fault is incepted (0.11467 s,1.00000)
0
Fault Fault Internal/ 0.08 0.09 0.10 0.11 0.12 0.13 0.14
Rf (Ω) ΔRP Td (ms) FDS Time (s)
type location (m) external
a-g 0.3048 0.1 Internal 1.326 1.00 1 Fig. 8. Results for an a-g internal fault in middle of protected feeder with
R f = 500 Ω.
a-g 76.2000 20.0 Internal 1.414 7.33 1
ab 3.0480 5.0 Internal 1.170 1.00 1
1.0 ΔRP
ab-g 76.2000 10.0 Internal 1.278 2.00 1
Ka
abc-g 21.3360 1.0 Internal 1.246 1.00 1 ΔRP 0.5
b-g 30.4800 70.0 Internal 1.190 11.00 1 0
bc 45.7200 20.0 Internal 1.490 4.67 1 1
FDS

bc-g 60.9600 30.0 Internal 1.517 5.00 1 Fault is incepted

abc-g 76.2000 100.0 Internal 1.446 9.00 1 0
0.08 0.09 0.10 0.11 0.12 0.13 0.14
c-g 91.4400 0.1 Internal 1.121 1.00 1 Time (s)
ac 106.6800 80.0 Internal 1.234 12.00 1 Fig. 9. Results for an abc-g bolted external fault at F2.
a-g 121.9200 50.0 Internal 1.312 12.00 1
ac-g 137.1600 125.0 Internal 1.233 12.00 1
It is observed from the results that DRP has not crossed
abc-g 144.7800 200.0 Internal 1.238 12.00 1
the threshold Ka. Therefore, FDS is 0, indicating that there is
b-g 149.3520 150.0 Internal 1.159 20.33 1
an external fault or external disturbance. Based on the re‐
abc-g 0.3048 1.0 External 0.015 NA 0 sults, it can be concluded that the proposed scheme is capa‐
abc-g 153.0100 0.1 External 0.042 NA 0 ble of effectively distinguishing between external and inter‐
nal faults.
B. High-resistance Faults D. Effect of Fault Inception Angle
Since the fault current remains low and may not cross the To study the effect of change in the fault inception angle,
threshold value, most conventional schemes fail to detect various bc-g faults in the middle of the protected feeder with
high-resistance faults [25]. The results obtained for an a-g in‐ varying fault inception angles have been created. The obtained
ternal fault in the middle of the protected feeder with R f = results for varying fault inception angles are represented in Ta‐
500 Ω are shown in Fig. 8. It can be seen that DRP exceeds ble V. It can be noticed from Table V that all faults are accu‐
K a; therefore, FDS becomes 1 indicating an internal fault rately identified within an average fault detection time Td of
with a detection time of 14.67 ms. The proposed scheme has 5.48 ms.
been examined for high-resistance faults at various fault loca‐
TABLE V
tions and it can be perceived from the results shown in Ta‐ RESULTS OBTAINED FOR DIFFERENT FAULT INCEPTION ANGLES
ble IV that all faults have been identified correctly with an
average fault detection time Td of 16.91 ms. It shows the ef‐ Inception angle (°) Internal/external ΔRP Td (ms) FDS
fectiveness of the proposed scheme for high-resistance faults. 45 Internal 1.438 7.25 1
90 Internal 1.332 6.16 1
C. External Faults
135 Internal 1.242 4.42 1
The protection scheme must respond to internal faults and
180 Internal 1.110 5.34 1
be resistant to external faults. External faults are incepted at
225 Internal 1.301 6.25 1
locations F2 (bus 632 side) and F3 (bus 633 side). For a bolt‐
ed abc-g fault at F2, incepted at 0.1 s, the obtained DRP and 270 Internal 1.389 5.17 1
FDS are shown in Fig. 9. 315 Internal 1.245 3.75 1
ANSARI et al.: FAULT DETECTION FOR MICROGRID FEEDERS USING FEATURES BASED ON SUPERIMPOSED POSITIVE-SEQUENCE POWER 1953

E. Simultaneous and Evolving Faults 1.5 ΔRP ΔRP=1.2206

1.0 Ka

ΔRP
The simultaneous fault occurs when two faults are incept‐ 0.5
0 Threshold is crossed
ed in a network at the same time but at different locations of -0.5
the network. To assess the effectiveness of the proposed 1 a-g (Rf =200 Ω)
scheme under that condition, an external fault with R f = 0.1

FDS
fault is incepted (0.10833 s, 1.00000)
Ω and an internal ab-g fault with R f = 150 Ω have been creat‐ 0
0.08 0.09 0.10 0.11 0.12 0.13 0.14
ed at 0.1 s simultaneously. It can be observed from Fig. 10 Time (s)
that ΔRP is more than Ka which results in FDS becoming 1
Fig. 12. Results for an a-g internal fault in middle of protected feeder
at 0.101 s, indicating an internal fault. Therefore, it can be with R f = 200 Ω and 40% DGP level.
concluded that the proposed scheme can detect internal
faults even during simultaneous faults.
TABLE VI
2.0 RESULTS FOR DIFFERENT DGP LEVELS
1.5 ΔRP=1.7898 ΔRP
ΔRP

1.0 Threshold crossed Ka

0.5 Fault Internal/
DGP level (%) Rf (Ω) ΔRP Td (ms) FDS
0 type external
1 10 abc-g 100 Internal 1.0560 18.00 1
(0.101 s, 1.000)
FDS

20 ac-g 200 Internal 1.1100 25.00 1

0
0.08 0.09 0.10 0.11 0.12 0.13 0.14 30 bc 50 Internal 1.1320 14.67 1
Time (s) 40 a-g 200 Internal 1.2206 8.33 1
Fig. 10. Results for a simultaneous fault. 50 c-g 400 Internal 1.3300 12.67 1

In an evolving fault, two faults are incepted at two differ‐

To recreate this event, an a-g fault with R f = 120 Ω is in‐
ent times at the same fault location of the network. First, an
cepted in the middle of the protected feeder at 0.1 s, and at
a-g fault with R f = 10 Ω and then a bc-g fault with R f = 10 Ω
the same time, DG2 is disconnected. The results of the simu‐
are created in the middle of the protected feeder at 0.1 s and
lated event are presented in Fig. 13. As seen from Fig. 13,
0.11 s, respectively. The obtained results are shown in Fig.
the suggested scheme detects the composite fault event in
11. It is found that ΔRP crosses the threshold Ka so that
less than 5 ms. Based on these results, one may conclude
FDS goes to 1, indicating an internal fault. The proposed
that the proposed scheme correctly detects the fault in the
scheme is proven to be accurate for evolving faults.
event of composite faults.
1.5 ΔRP=1.3039 ΔRP ΔRP
1.0 1.0
ΔRP

Threshold is crossed Ka Ka
0.5 0.5
ΔRP

0 0 Threshold is crossed
0.10567 s,1.00000) -0.5
1 a-g (Rf =10 Ω) 1
BCG (Rf =10 Ω) Composite fault
FDS

FDS

fault is incepted fault is incepted is incepted

0 0
0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.08 0.09 0.10 0.11 0.12 0.13 0.14
Time (s) Time (s)
Fig. 11. Results for an evolving fault. Fig. 13. Results for a composite fault.

F. Effect of Different DGP Levels

H. Effect of Noise in Measurement
Results for an a-g internal fault, incepted in the middle of
the protected feeder with R f = 200 Ω and 40% DGP level, It is difficult to avoid the effect of noise in the measure‐
presented in Fig. 12, show that ΔRP crosses Ka. So, accord‐ ments and it may have an impact on the performance while
ing to the relaying criterion, FDS becomes 1 declaring an in‐ practically implemented. So it should be taken into consider‐
ternal fault. The scheme is evaluated for various DGP levels. ation during the assessment. It is done by injecting Gaussian
The results obtained for the same are reported in Table VI noise with different signal-to-noise ratios (SNRs) into the
for various fault types. It is noticed that the proposed measured voltage and current signals [26]. A 50 dB noise is
scheme can identify faults accurately for a wide variation of added to the measured voltage and current signals and an a-
DGP levels. g internal fault with R f = 20 Ω is incepted in the middle of
the protected feeder at 0.1 s, as displayed in Fig. 14. It is ob‐
G. Effect of Composite Faults served that the proposed scheme preserves its high perfor‐
When an internal fault in the microgrid and a non-fault mance even under such a condition.
event like a DG outage occur simultaneously, this situation The proposed scheme has been tested under different
is referred to as a composite fault. Such an event must be de‐ noise levels and the acquired results are shown in Table VII.
tected by the relay so that the other components of the mi‐ All internal faults are identified which confirm the accuracy
crogrid are not damaged. of the proposed scheme in noisy environments.
1954 JOURNAL OF MODERN POWER SYSTEMS AND CLEAN ENERGY, VOL. 11, NO. 6, November 2023

1.5 ΔRP proposed scheme is tested for several typical sampling fre‐
1.0 Ka
quencies, i.e., 1.5, 3, 6, and 12 kHz, and the obtained results
ΔRP
0.5
0 Threshold is crossed are summarized in Table VIII. It is noticed from this table
-0.5 that, the suggested technique successfully identifies the inter‐
1 a-g (Rf =20 Ω) nal faults for different sampling frequencies, and it is also
FDS

with 50 dB noise (0.10733 s, 1.00000)

0 observed that as the sampling frequency increases, fault de‐
0.08 0.09 0.10 0.11 0.12 0.13 0.14 tection time decreases slightly. One case of 6 kHz sampling
Time (s) frequency with a-g internal fault in the middle of the protect‐
Fig. 14. Results for an a-g internal fault in middle of protected feeder ed feeder with R f = 200 Ω is shown in Fig. 16. It is observed
with R f = 20 Ω and 50 dB noise. that DRP crosses Ka and FDS becomes 1 at 0.10683 s, declar‐
ing an internal fault. Thus, an internal fault is identified within
TABLE VII 7 ms of fault inception with a 6 kHz sampling frequency.
RESULTS OBTAINED FOR DIFFERENT NOISE LEVELS
TABLE VIII
SNR Fault Fault Internal/ Td RESULTS OBTAINED FOR DIFFERENT SAMPLING FREQUENCIES
Rf (Ω) ΔRP FDS
(dB) type location (m) external (ms)
30 a-g 20 76.2 Internal 1.316 7.46 1 Sampling fre‐ Fault Fault loca‐ Internal/
R (Ω) ΔRP Td (ms) FDS
quency (kHz) type f tion (m) external
40 a-g 20 76.2 Internal 1.360 7.82 1
1.5 a-g 200 76.2 Internal 1.293 7.85 1
50 a-g 20 76.2 Internal 1.426 7.33 1
3.0 a-g 200 76.2 Internal 1.345 7.12 1
60 a-g 20 76.2 Internal 1.342 7.21 1
6.0 a-g 200 76.2 Internal 1.238 6.83 1
12.0 a-g 200 76.2 Internal 1.266 5.96 1
I. Effect of No-fault Events
False operation of the protective relay under crucial no- 1.5 ΔRP
1.0 Ka
fault events is one of the major concerns that must be ad‐
ΔRP
0.5
dressed. In such situations, sometimes, the voltage, current, 0 Threshold is crossed
-0.5
and frequency all deviate from their rated values by a signifi‐
1 a-g (R =200 Ω) at 6 kHz
cant amount for a short period. However, the protection re‐
FDS

f (0.10683 s, 1.00000)
sampling frequency
lay should be stable. The proposed scheme has been tested 0
for severe non-fault cases such as capacitor switching, DG 0.08 0.09 0.10 0.11 0.12 0.13 0.14
Time (s)
outage, and load switching. The capacitor switching, load
switching, and DG outage are simulated by connecting 100 Fig. 16. Results for an a-g internal fault in middle of protected feeder
kvar, 200 kW, and disconnection of DG1 very close to the with R f = 200 Ω at 6 kHz sampling frequency.
protected feeder, i.e., at the bus 632 (Fig. 6). All severe non-
fault events are incepted at 0.1 s, as indicated in Fig. 15. It K. Effect of Topology Changes
can be concluded that the proposed scheme is not sensitive The changes in microgrid topology from radial to mesh
to severe no-fault situations. and vice versa may affect the amount and direction of the
0.6 current. As a consequence, the protection schemes may be
0.5
impacted because of the varying fault current levels and be‐
Capacitor switching havior. The topology of the simulated microgrid was
0.4 Load switching changed from radial to mesh by connecting buses 634 and
0.3
DG1 outage 675 with the help of CB, as shown in Fig. 6. The perfor‐
ΔRP

Ka
mance of the proposed scheme for an a-g internal fault in
0.2
the middle of the protected feeder with R f = 100 Ω and mesh
0.1 type topology at 0.1 s is displayed in Fig. 17. As observed
0 from this figure, the proposed scheme detects faults in less
than 8 ms. Moreover, various other cases are simulated and
-0.1
0.08 0.09 0.10 0.11 0.12 0.13 the results are summarized in Table IX. This table leads to
Time (s) the conclusion that the proposed scheme correctly detects
Fig. 15. ΔRP in non-fault cases at bus 632. the fault in different topologies of the microgrid. One impor‐
tant feature of the proposed scheme is that its settings need
not be changed for different topologies of the microgrid.
J. Effect of Change in Sampling Frequency
The performance of the proposed scheme can be impacted L. Comparison with Incremental Reactive Power Coefficient
by the change in the sampling frequency of the measuring (IRPC) and Differential Current Based Schemes
device. As measuring devices have sampling rate restric‐ A protection scheme based on IRPC is proposed in [22].
tions, the selected sampling rate should be within the range Whenever IRPC is less than the threshold of -0.5, it is de‐
of these devices to assist the application of a protective clared as an internal fault; otherwise, it is declared as an ex‐
scheme. To assess the impact of the sampling frequency, the ternal fault or external disturbance.
ANSARI et al.: FAULT DETECTION FOR MICROGRID FEEDERS USING FEATURES BASED ON SUPERIMPOSED POSITIVE-SEQUENCE POWER 1955

1.5 ΔRP fault in the middle of the protected feeder with R f = 150 Ω at
1.0 Ka
Threshold is crossed 0.1 s. The threshold of the dI-based scheme is set at 10% of
ΔRP
0.5
0 the rated current [28]. Therefore, when the differential cur‐
-0.5
rent magnitude crosses 10 A, the relay will trip. It is ob‐
1 a-g fault (Rf =100 Ω)
(0.108 s, 1.000) served from Fig. 19(a) that the differential current obtained
FDS

with mesh topology

0 for the fault does not cross the threshold (TH d = 10 A) where‐
0.08 0.09 0.10 0.11 0.12 0.13 0.14 as the proposed scheme crosses the threshold (K a = 0.5), as
Time (s)
shown in Fig. 19(b). Therefore, from the result, it is noticed
Fig. 17. Results for an a-g internal fault in middle of protected feeder that the dI-based scheme fails to identify high-resistance
with Rf=100 Ω and mesh type topology.
fault (a-g fault with R f = 150 Ω) whereas the proposed
scheme detects the high-resistance fault within 20 ms of
The IRPC for 100 kVA capacitor bank switching at bus fault inception. In addition, a comprehensive comparison
632 at 0.1 s is obtained. As shown in Fig. 18(a), the IRPC- study is also made between other recently available schemes
based scheme detects this capacitor switching as an internal and the proposed scheme. The obtained results of the study
fault since IRPC is less than -0.5, whereas, as observed in are summarized in Table X.
Fig. 18(b), since ΔRP is less than threshold Ka, the proposed
a-g fault
scheme does detect this as an external disturbance and not 15
(Rf =150 Ω) is incepted
as an internal fault. Therefore, an IRPC-based scheme finds

dI (A)
10
limitations whereas the proposed scheme accurately differen‐ 5 dI
THd
tiates the external disturbance. 0
1.5 ΔRP=1.2006 ΔRP
TABLE IX 1.0 Ka

ΔRP
RESULTS OBTAINED FOR CHANGE IN TOPOLOGY (MESH TOPOLOGY) 0.5
0 Threshold is crossed
-0.5
Fault Fault Internal/ 0.08 0.09 0.10 0.11 0.12 0.13 0.14
Rf (Ω) ΔRP Td (ms) FDS
type location (m) external Time (s)
a-g 76.2000 100.0 Internal 1.460 8.00 1
Fig. 19. Differential current and proposed schemes for a-g internal fault in
a-g 0.3048 0.1 Internal 1.312 1.40 1 middle of protected feeder with R f = 150 Ω (a) dI. (b) ΔRP.
a-g 76.2000 20.0 Internal 1.421 7.41 1
ab 3.0480 7.0 Internal 1.190 1.20 1 The schemes are compared in Table X based on twelve
ab-g 76.2000 10.0 Internal 1.292 2.31 1 different criteria, including the DG penetration, high-resis‐
abc-g 21.3360 1.0 Internal 1.251 1.10 1 tance fault, fault location variation, different fault inception
b-g 30.4800 50.0 Internal 1.230 10.20 1 angles, sampling frequency, noise immunity, threshold modi‐
bc 45.7200 20.0 Internal 1.510 4.89 1 fication needed, non-fault event discrimination, simultaneous
bc-g 60.9600 35.0 Internal 1.470 6.00 1 faults, evolving faults, composite fault, and real-time valida‐
abc-g 76.2000 100.0 Internal 1.430 8.22 1 tion. The performance of the proposed scheme has been test‐
c-g 91.4400 0.1 Internal 1.132 1.00 1 ed for 50% DGP level, and it is found that it effectively de‐
ac 106.6800 80.0 Internal 1.244 13.10 1 tects the fault events. However, scheme H has only been test‐
ag 121.9200 50.0 Internal 1.292 12.71 1 ed for 40% DGP, and the rest of the schemes have not con‐
ac-g 137.1600 125.0 Internal 1.291 12.00 1
sidered the DGP. The proposed scheme has considered the
fault resistance up to 500 Ω whereas schemes B, E, H, J,
abc-g 144.7800 200.0 Internal 1.249 12.42 1
and K have considered 25 Ω, 250 Ω, 100 Ω, 100 Ω, and 50
bg 149.3500 150.0 Internal 1.152 21.33 1
Ω, respectively. The rest of the schemes have not even men‐
1.0 IRPC
tioned (NM) the fault resistance up to which it can efficient‐
0.5 Threshold ly detect the faults. The sampling frequency required by the
IRPC

0 proposed scheme is 3 kHz, which is a sufficiently low value

-0.5
-1.0 100 kVA capacitor Threshold is crossed
for the microgrid protection relaying. Schemes B and C,
switching
-1.5 however, require a sampling frequency of 50 kHz or higher
0.8 to perform effectively. The performance of the proposed
0.6
scheme will not be affected by the presence of noise. Con‐
ΔRP

0.4 ΔRP
0.2 Ka versely, schemes A, C, F-I are not reliable in noisy condi‐
0 tions. Another advantage of the proposed scheme is that
-0.2
0.08 0.09 0.10 0.11 0.12 0.13 0.14 there is no need to modify the threshold value. The ability to
Time (s) distinguish non-fault events makes the proposed scheme su‐
Fig. 18. IRPC-based and proposed schemes for 100 kVA capacitor bank perior to the other studied schemes. Another feature of the
switching at bus 632. proposed scheme is that it can efficiently detect some of the
critical fault events such as simultaneous faults, evolving
The proposed scheme is also compared with the differen‐ faults, and composite faults, for which most of the schemes
tial current based (dI-based) scheme [27] for an a-g internal have not even been tested.
1956 JOURNAL OF MODERN POWER SYSTEMS AND CLEAN ENERGY, VOL. 11, NO. 6, November 2023

TABLE X
COMPREHENSIVE COMPARISON STUDY WITH PROPOSED SCHEME

Protection scheme
Criteria
A [17] B [29] C [30] D [31] E [32] F [3] G [33] H [28] I [24] J [34] K [35] L [36] Proposed
DGP considered NM NM NM NM NM NM NM 40% NM NM NM NM 50%
The maximum value of Rf con‐
NM 25 Ω NM NM 250 Ω NM NM 100 Ω 1000 Ω 100 Ω 50 Ω 1000 Ω 500 Ω
sidered
Tested for fault location variation Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes
Tested for different fault incep‐
No No No No Yes No No No No Yes No No Yes
tion angle
Required sampling frequency 5 kHz 70 kHz 50 kHz 10 kHz 7.6 kHz NM NM 1.44 kHz 3 kHz NM NM 2 kHz 3 kHz
Noise immunity considered No Yes No Yes Yes No No No No Yes Yes Yes Yes
Threshold modification needed No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes No
Non-fault events discrimination
No Yes Yes No Yes No No Yes Yes Yes Yes Yes Yes
tested
Simultaneous fault considered No No No No Yes No No No No No No No Yes
Evolving fault considered No No No No No No No No No No No No Yes
Composite fault considered No No No No Yes No No No No No No No Yes
Real-time validation No No Yes No Yes No No Yes Yes Yes Yes No Yes

M. Effect of Induction Motor Starting and 5 (i. e., 36° ), respectively, and the corresponding ΔRP
Mal-operation of the protective relay during the starting of for an a-g internal fault in the middle of the protected feeder
the induction motor is a major concern that must be ad‐ with R f = 80 Ω at 0.1 s is depicted in Fig. 21. It is observed
dressed. In such cases, current during starting increases sig‐ from Fig. 21 that the proposed scheme detects a-g internal
nificantly; however, the protective relay must be robust faults accurately within fault detection time of 7 ms because
against such events. To test the performance of the proposed ΔRP crosses the threshold Ka even with very high SE of 36°
scheme during an induction motor starting, a 5 high-pressure (i. e., 1636 times more than that of specified in [38]). The
(HP) induction motor located very close to the protected proposed scheme is thus found to be unaffected by sample
feeder, i.e., bus 632 (Fig. 6), is connected at 0.1 s. The ob‐ SEs, which shows its accuracy.
tained ΔRP and FDS are obtained for such case and shown 1.5
in Fig. 20. It is observed from Fig. 20 that after induction mo‐
1.0
tor starting, DRP increases slightly; however, it does not cross
ΔRP

the threshold Ka, and consequently, FDS remains 0, indicating 0.5

a non-faulty case. Therefore, it is concluded that the proposed 0
scheme remains robust during induction motor starting.
-0.5
ΔRP 0.08 0.09 0.10 0.11 0.12 0.13
1.0 Ka Time (s)
0.5
ΔRP

Without SE; 36° SE; 28.9° SE; 14.4° SE; Ka

0
-0.5 Fig. 21. Results for an a-g internal fault in middle of protected feeder
1 with R f = 80 Ω and different SEs, i.e., 14.4°, 28.9°, and 36°.
5 HP induction
FDS

motor starting
0 IV. ADDITIONAL STUDIES
0.08 0.09 0.10 0.11 0.12 0.13 0.14
Time (s) The proposed scheme has also been applied to detect
Fig. 20. Results for a 5 HP induction motor starting at bus 632. faults in a medium transmission line. Although detailed stud‐
ies are not included here, the results of studies show that it
N. Effect of Synchronization Error (SE) can also be applied in detecting faults in medium transmis‐
sion lines.
For satisfactory working of a relaying scheme [37] as per
All the results, plotted and included in this paper are tak‐
IEEE Standard C37.118.1a-2014 [38], the sample data of all
en under unbalanced conditions, as shown in Fig. 6. From
the measurements must be synchronized to the coordinated
the results, it is clear that the unbalanced conditions do not
universal time with a maximum SE of 0.022° for a 60 Hz
affect the performance of the proposed scheme.
system. To check the performance and accuracy of the
scheme, the proposed scheme has been tested for a variety
of SEs, i. e., 14.4° , 28.9° , and 36° , respectively. It is pre‐ V. REAL-TIME VALIDATION
sumed that the voltage and current samples that are ob‐ Operational validation of the proposed scheme is conduct‐
tained from the end n are not synchronized correctly, re‐ ed at the laboratory level utilizing the OPAL-RT real-time
sulting in a sample delay of 2 (i.e., 14.4°), 4 (i.e., 28.9°), simulator, as illustrated in Fig. 22.
ANSARI et al.: FAULT DETECTION FOR MICROGRID FEEDERS USING FEATURES BASED ON SUPERIMPOSED POSITIVE-SEQUENCE POWER 1957

Control of the It is observed that ΔRP is more than Ka, and as a result,
model using Host PC
FDS becomes 1, indicating an internal fault. Therefore, an in‐
RT-LAB software
ternal AG fault with R f = 500 Ω is detected within 20 ms of
OP4510 (front view) fault inception and ΔRP value goes to 1.24, as clearly shown
OP5330 DAC Capturing real-time result in Fig. 23.
Module using DSO (MDO3014)
OP4510 (back view)
VI. CONCLUSION
A novel fault detection scheme for microgrid feeders is
Ethernet cable proposed based on ΔRP, which is a newly introduced feature
Fig. 22. Setup for real-time validation of proposed scheme using OP4510
that uses the calculated positive sequence superimposed pow‐
simulator. ers. The performance of the proposed scheme has been test‐
ed thoroughly using simulations for different conditions in‐
Several components have been used in the prototype in‐ cluding internal and external fault events. Additionally, tests
cluding an OPAL-RT (simulator is OP4510, operating sys‐ have been conducted for various fault locations, fault types,
tem is Redhat v2.6.29.6-opalrt-6.3.0, total core is 4 and fault resistances, fault inception angles, DGP levels, simulta‐
memory is 8 GB) for the test system simulation, a host PC neous faults, evolving faults, and composite faults. More‐
(Intel Core i7-4770 @ 3.40 GHz with 12 GB RAM and 64- over, the test has also been conducted for noise in the mea‐
bit operating system) for running the RT-LAB interface soft‐ surement signal, SE, change in sampling frequency, and
ware, OP5330 DAC (number of channels is 16 and voltage change in the topology of the microgrid. The proposed
range is ±16 V), and mixed domain oscilloscope (Tektronix scheme can efficiently distinguish between faulty and non-
MDO3014 with 4 channels and 100 MHz bandwidth) to re‐ faulty events within two cycles of the supply frequency.
cord the results. The IEEE 13-bus network described in Sec‐ Compared with a recently suggested incremental reactive
tion III has been used for real-time simulation. First, the test power coefficient based scheme, the performance of the pro‐
model is created on the host PC in MATLAB/Simulink. Be‐ posed scheme is superior. The proposed scheme has also
fore actually linking with the OPAL-RT simulator, the test been validated using a real-time simulation platform devel‐
system must be able to execute properly in the Simulink en‐ oped using OPAL-RT. Based on the obtained results, it can
vironment first. The test model is divided into three subsys‐ be concluded that the proposed scheme is reliable, accurate,
tems: master, slave, and console. The master and slave sub‐ selective, and discriminative.
systems are responsible for the computing components of
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Om Hari Gupta received the B. Tech. degree in electrical and electronics
Energy Systems, vol. 92, pp. 156-166, Nov. 2017.
engineering from UP Technical University, Lucknow, India, in 2007, the
[22] O. H. Gupta and M. Tripathy, “Universal pilot relaying scheme for se‐
M. Tech. degree in power electronics & ASIC design from Motilal Nehru
ries and shunt-compensated lines,” IET Generation, Transmission &
National Institute of Technology, Allahabad, India, in 2011, and the Ph. D.
Distribution, vol. 12, no. 4, pp. 799-806, Feb. 2018.
degree in electrical engineering from Indian Institute of Technology Roor‐
[23] C. Yu, Y. Huang, and J. Jiang, “A full- and half-cycle DFT-based tech‐
kee, Roorkee, India, in 2017. From March 2017 to June 2017, he was a Vis‐
nique for fault current filtering,” in Proceedings of IEEE International
iting Researcher with the Ontario Tech University, Oshawa, Canada. Since
Conference on Industrial Technology, Via del Mar, Chile, Mar. 2010,
pp. 859-864. 2018, he has been an Assistant Professor with the Electrical Engineering De‐
[24] K. Dubey and P. Jena, “Impedance angle-based differential protection partment, National Institute of Technology, Jamshedpur, India. He is a Se‐
scheme for microgrid feeders,” IEEE Systems Journal, vol. 15, no. 3, nior Member of IEEE and a Reviewer of the journal IEEE Transactions on
pp. 3291-3300, Jul. 2020. Power Delivery, Electric Power Components and Systems, and International
[25] M. E. Erezzaghi and P. A. Crossley, “The effect of high resistance Journal of Electrical Power & Energy Systems. His research interests in‐
faults on a distance relay,” in Proceedings of IEEE PES General Meet‐ clude power system protection, microgrid, renewable-based distributed gen‐
ing, Toronto, Canada, Jul. 2003, pp. 2128-2133. eration, and electric power quality.
[26] M. A. Jarrahi and H. Samet, “Modal current and cumulative sum
based fault detection approach in transmission lines,” International Om P. Malik received the National Diploma degree in electrical engineer‐
Journal of Emerging Electric Power Systems, vol. 19, no. 6, p. ing and the M.E. degree in electrical machine design from University of Ro‐
20180037, Oct. 2018. orkee, Roorkee, Uttarakhand, India, in 1952 and 1962, respectively, the Ph.D.
[27] E. Sortomme, S. S. Venkata, and J. Mitra, “Microgrid protection using degree in electrical engineering from the University of London, London, U.K.,
communication-assisted digital relays,” IEEE Transactions on Power in 1965, and the D. I. C. degree from the Imperial College of Science and
Delivery, vol. 25, no. 4, pp. 2789-2796, Oct. 2010. Technology, London, U. K., in 1965. In 1968, he joined the University of
[28] N. K. Sharma and S. R. Samantaray, “A composite magnitude-phase Calgary, Calgary, Canada, where he is currently a Professor Emeritus with
plane of impedance difference for microgrid protection using synchro‐ the Department of Electrical and Computer Engineering. He is a Fellow of
phasor measurements,” IEEE Systems Journal, vol. 15, no. 3, pp. the Engineering Institute of Canada, the Canadian Academy of Engineering,
4199-4209, Jun. 2020. and the Institution of Electrical Engineers. He is also actively involved in
[29] T. Gush, S. B. A. Bukhari, R. Haider et al., “Fault detection and loca‐ IFAC and is currently the Chair of the IFAC Technical Committee on Power
tion in a microgrid using mathematical morphology and recursive least Plants. He is the author of three books and more than 450 articles. He is a
square methods,” International Journal of Electrical Power & Energy Life Fellow of IEEE and he was an Editor of Canadian Journal of Electrical
Systems, vol. 102, pp. 324-331, Nov. 2018. and Computer Engineering. His research interests include power system pro‐
[30] Z. Chen, X. Pei, M. Yang et al., “A novel protection scheme for in‐ tection, distributed power generation, artificial intelligence, circuit breakers,
verter-interfaced microgrid (IIM) operated in islanded mode,” IEEE battery management systems, capacitor switching and compensation.