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    This document contains a 25 question test on microprocessors and microcontrollers. It covers topics like ARM architecture, instruction sets, registers, addressing modes, and assembly language instructions. Sample questions test knowledge of acronyms, flag settings, operating modes, and writing simple assembly code. The test aims to evaluate understanding of basic concepts in computer engineering related to microprocessor and microcontroller systems.

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    SuddenTest Solution

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    This document contains a 25 question test on microprocessors and microcontrollers. It covers topics like ARM architecture, instruction sets, registers, addressing modes, and assembly language instructions. Sample questions test knowledge of acronyms, flag settings, operating modes, and writing simple assembly code. The test aims to evaluate understanding of basic concepts in computer engineering related to microprocessor and microcontroller systems.

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    This document contains a 25 question test on microprocessors and microcontrollers. It covers topics like ARM architecture, instruction sets, registers, addressing modes, and assembly language instructions. Sample questions test knowledge of acronyms, flag settings, operating modes, and writing simple assembly code. The test aims to evaluate understanding of basic concepts in computer engineering related to microprocessor and microcontroller systems.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    23 views3 pages

    SuddenTest Solution

    Uploaded by

    jannatin176
    This document contains a 25 question test on microprocessors and microcontrollers. It covers topics like ARM architecture, instruction sets, registers, addressing modes, and assembly language instructions. Sample questions test knowledge of acronyms, flag settings, operating modes, and writing simple assembly code. The test aims to evaluate understanding of basic concepts in computer engineering related to microprocessor and microcontroller systems.

    Copyright:

    © All Rights Reserved
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    of 3

    CSE3103: Microprocessor and Microcontroller

    Computer Science and Engineering, University of Dhaka,


    Class Test 1
    Marks : 25
    Time: 40 Minutes
    February 23, 2023

    [Answer All the Following Questions]

    1. Abbreviate the terms: (i) IBM, (ii) CISC, (iii) DARPA, (iv) ARM, (v) NPU

    • Answer: (i) IBM: International Business Machines, (ii)Complex instruction


    set computer, (iii)DARPA: Defense Advanced Research Project Agency, (iv)
    Advanced RISC Machine, (v) NPU: Neural Processing Unit

    2. What is the value of Zero (Z) flag after the instruction: SUB AX,AX

    • (i) Set (ii) Cleared (iii) Unknown (iv) None of the above

    3. If you add positive number plus negative number the over flow flag will be set if:

    • (i) The result is negative (ii) The result is positive (iii) The result is zero (iv) There
    is no over flow when adding ( ve) (-ve) numbers

    4. How many registers does ARM have?

    • (i) four (ii) sixteen (iii)thirty two (iv) thirty seven

    5. How many operating modes does ARM have?

    • (i) four (ii) sixteen (iii) seven (iv) thirty seven

    6. When the processor is executing in ARM state, then all instructions are ˙˙˙˙˙˙˙˙˙˙˙˙˙˙ wide

    • (i) 8 bits (ii) 16 bits (iii) 32 bits (iv) 64 bits

    7. How many arithmetic shift operators does ARM have?

    • (i) 1 (ii) 2 (iii) 3 (iv) 4

    8. Which one of the following architecture has fewer number instructions?

    • (i) RISC (ii) CISC (iii) Both (i) and (ii) (iv) None

    9. The branch with link, software interrupt, and general branch instructions are the ˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙
    instructions

    1
    Assignment 03 Computer Science & Engineering, University of Dhaka page 2

    • (i) Branch (ii) Data Processing (iii) ARM (iv) None

    10. The ARM processors supports ˙˙˙˙˙˙˙˙˙˙˙˙ bytes

    • (i) 8-bit signed & unsigned (ii) 16-bit signed & unsigned (iii) 32-bit signed & unsigned
    (iv) All of the above

    11. What is the standard form of NVIC?

    • (i) Nested Vectored Internal Controller (ii) Nested Vectored Interface Controller (iii)
    Nested Vectored Interrupt Controller (iv) None of the above

    12. The ARM and thumb instruction set and java byte codes are ˙˙˙˙˙˙˙˙˙˙˙ instruction set

    • (i) Java (ii) ARM (iii) Jazelle (iv) Thumb

    13. What is the standard form of APSR?

    • (i) ARM Program Status Register (ii) Application Program Status Register (iii)
    Advanced Program Status Register (iv) Anonymous Program Status Register

    14. The address space in ARM is

    • (i)216 (ii) 28 (iii) 232 (iv) 264

    15. The address system supported by ARM system

    • (i)Little Endian (ii) Big Endian (iii) X-Little Endian, (iv) Both (i) & (ii)

    16. Each instruction in ARM machine is encoded into ˙˙˙˙˙˙ word

    • (i) 2 byte (ii) 3 byte (iii) 4 byte (iv) 8 byte

    17. What will happen when CR is 0

    • (i) nPRIV (ii) FPCA (iii) SPSEL (iv) None

    18. Which of the following is configurable option in STM 32 NUCLEO-F446RE

    • (i) Data Watchpoint and Trace Unit (DWT) (ii) FPU (iii) NVIC (iv) Systick
    Timer

    19. Which interrupt has the highest priority

    • (i) SVCall (ii) HardFault (iii) NMI (iv) SysTick

    20. List out the seven operating modes of ARM processor.

    • Answer: SVC, FIQ, IRQ, Abort, Undef, System, User

    21. Mention the content of the registers after the execution of the instruction POP R4

    • Answer: R4=memory[R13]
    R13=R13+4
    Assignment 03 Computer Science & Engineering, University of Dhaka page 3

    22. Mention the content of the registers after the execution of the instruction
    0x1012 : MOV R0, PC .

    • Answer: R0=)x1016

    23. Write down the set of instructions to disable all exceptions except NMI and Hard faults.

    • Answer:
    MOVS R0, #1
    MSR PRIMASK, R0

    24. Give an example that will set the N and V flags.

    • Answer: 231 − 1 + 1 = 231


    N ZCV = 1001

    25. Write an assembly language to add two signed numbers.

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