Analog VLSI Circuits

E3 238
Differential Amplifier
❑ References:
• BR – Design of Analog CMOS Integrated Circuits by Behzad Razavi
• A-H: CMOS analog circuit design by Allen and Holdberg
Single-ended vs. differential signaling
• Single-ended signal
̶ Any voltage signal requires a reference – single-ended signal reference is DC
voltage
̶ Typically, in includes both biasing and the signal (time-varying) component
𝑉𝑖𝑛 = 𝑉𝑑𝑐 + 𝑉𝑠𝑖𝑔𝑛𝑎𝑙
̶ More naturally occurring; e.g., sensors, photodiodes
• Differential signal
̶ Requires two inputs, signal is referred to each other, i.e., difference
̶ 𝑉𝑠𝑖𝑔𝑛𝑎𝑙 = 𝑉𝑖𝑛1 − 𝑉𝑖𝑛2
̶ Biasing information can be common to both signals 𝑉𝐶𝑀 = 𝑉𝑖𝑛1 + 𝑉𝑖𝑛2 Τ2
̶ 𝑉𝑖𝑛1 = 𝑉𝐶𝑀 + 𝑉𝑠𝑖𝑔𝑛𝑎𝑙 Τ2, 𝑉𝑖𝑛2 = 𝑉𝐶𝑀 − 𝑉𝑠𝑖𝑔𝑛𝑎𝑙 Τ2,
̶ Not natural, but extremely beneficial
IISc, Analog VLSI Circuits E3 238 2
 Sensitivity to VCM (1)
• Single-ended circuits are sensitive to VCM
VCM has “right” value – output is ok

Simple or “pseudo” differential circuit –

practically two single-ended circuits together VCM is too low – output is “clipped” at VDD
IISc, Analog VLSI Circuits E3 238 3
Ref: BR
Sensitivity to VCM (2)
• In differential circuits, VCM is supported by bias current source, has
reduced impact on output

VCM-VGS0
Current source absorbs VCM variation
IISc, Analog VLSI Circuits E3 238 4
Ref: BR
Differential gain analysis
• Half-circuit analysis – depends on the fact that current source output
is AC ground
Voltage gain 𝐴𝐷𝑀 = 𝑔𝑚 𝑟𝑑𝑠 ||𝑅𝐷

AC ground, as there is no variation

in voltage (for small Vin)
IISc, Analog VLSI Circuits E3 238 5
Ref: BR
Common-mode analysis

IISc, Analog VLSI Circuits E3 238 6

Ref: BR
Common mode gain & rejection
• Common mode gain – similar to gain of degenerate CS stage
𝑔𝑚 𝑅𝐷 𝑅𝐷
𝐴𝐶𝑀 = ≅
1 + 2 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆𝑆 𝑅𝑆𝑆
• Common mode rejection: for current source with large output
resistance RSS, 𝐴𝐶𝑀 can be quite low

𝐴𝐷𝑀
• Controversial Common Mode Rejection Ratio (CMRR) =
𝐴𝐶𝑀
𝐴𝐷𝑀
̶ A more meaningful definition, CMRR = (will discuss later..)
𝐴𝐶𝑀−𝐷𝑀

IISc, Analog VLSI Circuits E3 238 7

Input common mode range

• ICMR: Range of common mode voltage

for which differential pair functions
• Lower bound: limited by current mirror minimum headroom
̶ 𝑉𝑃 = 𝑉𝑖𝑛,𝐶𝑀 − 𝑉𝐺𝑆1 , From current mirror, 𝑉𝑃 > 𝑉𝑂𝐷3
̶ Hence, 𝑉𝑖𝑛,𝐶𝑀 > 𝑉𝐺𝑆1 + 𝑉𝑂𝐷3
• Upper bound: Limited by output common mode voltage
̶ Output common mode voltage 𝑉𝑜𝑢𝑡,𝐶𝑀 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷
̶ For M1/M2 to remain in saturation, 𝑉𝐺𝐷 = 𝑉𝑖𝑛,𝐶𝑀 − 𝑉𝑜𝑢𝑡,𝐶𝑀 < 𝑉𝑇
̶ Hence 𝑉𝑖𝑛,𝐶𝑀 < 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 + 𝑉𝑇

IISc, Analog VLSI Circuits E3 238 8

Ref: BR
Maximum output swing
• Maximum output voltage 𝑉𝑜𝑢𝑡,𝑚𝑎𝑥 = 𝑉𝐷𝐷
• Minimum output voltage 𝑉𝑜𝑢𝑡,𝑚𝑖𝑛 = 𝑉𝑖𝑛,𝐶𝑀 − 𝑉𝑇
• Output voltage swing: 𝑉𝑠𝑤𝑖𝑛𝑔 = 𝑉𝐷𝐷 − 𝑉𝑖𝑛,𝐶𝑀 + 𝑉𝑇

• Output swing is maximized for lowest 𝑉𝑖𝑛,𝐶𝑀

• Maximum output swing 𝑉𝑠𝑤𝑖𝑛𝑔,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑂𝐷3 − 𝑉𝑂𝐷1

IISc, Analog VLSI Circuits E3 238 9

Ref: BR
Differential pair with MOS load
• Instead of RD, active load provides much higher gain
̶ Typically, 𝑟𝑂 ≫ 𝑅𝐷 and consumes much less area
• Output impedance 𝑅𝑜𝑢𝑡 = 𝑟𝑂1 ||𝑟𝑂3
• Differential voltage gain 𝐴𝐷𝑀 = 𝑔𝑚1 𝑟𝑂1 ||𝑟𝑂3
• Note: Vb needs to set so that current through the MOS load is equal
to ISS
̶ Common mode gain from Vb to Vout is quite high, 𝐴𝐶𝑀−3 = 𝑔𝑚3 𝑟𝑂3
̶ Output common mode is sensitive to value of Vb
̶ Look ahead: Common mode feedback loop (CMFB) to control Vb and set
Vout,CM
IISc, Analog VLSI Circuits E3 238 10
Ref: BR
Cascode differential pair
• To increase gain – use cascode
• Output resistance
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 𝑔𝑚3 𝑟𝑂3 || 𝑟𝑂7 𝑔𝑚5 𝑟𝑂5
• Gain 𝐴𝑉 = 𝑔𝑚1 𝑅𝑜𝑢𝑡

• Drawback
̶ Input common mode range limited
̶ Output swing limited

IISc, Analog VLSI Circuits E3 238 11

Ref: BR
Benefits of differential circuits (1)
1. Reduced sensitivity to common mode signal/bias variations
̶ Already discussed
2. Simpler biasing
̶ Single ended circuits will require accurate voltage biasing (CS amplifier stage)
̶ Differential amplifier will require current sources that are easier to design
3. Peak-to-peak swing of differential circuit is twice that of single-
ended circuits – Allows larger signal to noise/distortion ratio in low
voltage headroom design
̶ Single-ended Vpeak-peak ~ V0 < VDD
̶ Differential V+max ~ V0, V-max ~ -V0 ⇒ Vpeak-peak ~ 2V0

IISc, Analog VLSI Circuits E3 238 12

Benefits of differential circuits (2)
• Higher immunity to supply noise

• Direct couple of VDD to SE output (gain 1)

• Differential output cancels VDD coupling
to the first order, residual coupling –
Power Supply Rejection (PSR)

• Immunity to digital signal coupling

̶ Best practice: Reduce parasitic capacitance to digital lines, Differential lines
make parasitic capacitances equal by careful layout
̶ Differential signal gives immunity to common mode
disturbance through capacitive coupling Digital signal
IISc, Analog VLSI Circuits E3 238 13
Ref: BR
Op-amp – “shortest review”
• A popular type of op-amp: Differential input, single-ended output
̶ Large input impedance
̶ Large gain
• Applications
̶ Amplifier
̶ Buffer (unity gain amplifier)
̶ Adder, subtractor
̶ Low pass, high pass filters

IISc, Analog VLSI Circuits E3 238 14

Ref: BR
Operational Amplifier (Op-amp) vs.
Operational Transconductoance Amplifer (OTA)
• OTA
̶ High output impedance
̶ Effective model: 𝐼𝑜𝑢𝑡 = 𝐺𝑚 𝑉𝑖𝑛1 − 𝑉𝑖𝑛2 with
large output impedance 𝑅𝑜𝑢𝑡
̶ Intrinsic voltage gain 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡
̶ Issue: Gain depends on load resistance 𝑅𝐿
• Loaded gain: 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡 ||𝑅𝐿
• For small 𝑅𝐿 gain drops significantly
̶ Works well for capacitive load
• Opamp: OTA followed by I-to-V stage
• Buffered Op-amp: Op-amp with output
buffer to drive required load impedance

IISc, Analog VLSI Circuits E3 238 15

Ref: BR
 OTA 1: Diff pair with current load

Not symmetric
⇒ Cannot apply half-
circuit approach

• Single-ended OTA uses a current load (𝐼𝐿 = 𝐼𝑆𝑆 Τ2)

𝑉𝑖𝑛 𝑔𝑚2
• To obtain 𝐺𝑚 , AC short the output to VDD, 𝐼𝑜𝑢𝑡 = 𝑔𝑚2 = 𝐺𝑚 𝑉𝑖𝑛 , → 𝐺𝑚 =
2 2
1
• To obtain 𝑅𝑜𝑢𝑡 , short input. 𝑅𝑜𝑢𝑡 = 1 + 𝑔𝑚2 𝑟𝑂2 ||𝑟𝑂1 + 𝑟𝑂2 | 𝑟𝑂4 = 2𝑟𝑂2 |𝑟𝑂4
𝑔𝑚1
𝑔𝑚2
• Voltage gain 𝐴𝑣 = 2𝑟𝑂2 || 𝑟𝑂4
2
IISc, Analog VLSI Circuits E3 238 16
Ref: BR
 OTA 2: Differential pair with active load

Iout

• As VGS2 decreases ⇒ ID2 decreases ⇒ Iout increases

• As VGS1 increases ⇒ ID1 increases ⇒ ID3 increases
• As VGS2 decreases ⇒ ID2 decreases ⇒ Iout increases • M3 and M4 are current mirrors
• Can we reuse current from M1? • ⇒ ID3 increases ⇒ ID4 increases ⇒ Iout increases
• Two paths to increase Iout
IISc, Analog VLSI Circuits E3 238 17
Ref: BR
5 Transistor OTA: Simplest OTA
• M1 and M2 are not symmetric
▪ 𝑉𝐷𝑆,𝑀1 ≠ 𝑉𝐷𝑆,𝑀2
▪ 𝑟𝑂1 ≠ 𝑟𝑂2
• We are anyway going to use P as
an AC ground

IISc, Analog VLSI Circuits E3 238 18

Small signal model (1)
Small signal model for
M1 and M2

Small signal model for

M3 and M4

Simplified Small signal

model for M3 and M4

IISc, Analog VLSI Circuits E3 238 19

Small signal model (2)
𝐷1 = 𝐷3

1
𝑉3 = −𝑔𝑚1 𝑉1 𝑟𝑂1 || ||𝑟
𝑔𝑚3 𝑂3

𝐷2 = 𝐷4

𝑉𝑜𝑢𝑡 = − 𝑔𝑚2 𝑉2 + 𝑔𝑚4 𝑉3 𝑟𝑂2 ||𝑟𝑂4

1
= − 𝑔𝑚2 𝑉2 − 𝑔𝑚4 𝑔𝑚1 𝑉1 𝑟𝑂1 || ||𝑟 𝑟𝑂2 ||𝑟𝑂4
𝑔𝑚3 𝑂3
IISc, Analog VLSI Circuits E3 238 20
Solution of 5 Transistor OTA
𝑉𝑑𝑚
• For differential signal 𝑉1 = −𝑉2 =
2
• Identical differential input pair 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚,𝐼𝑛
• Identical differential load pair 𝑔𝑚3 = 𝑔𝑚4 = 𝑔𝑚,𝐿
𝑉𝑑𝑚 1
• 𝑉𝑜𝑢𝑡 = 𝑔𝑚,𝐼𝑛 1 + 𝑔𝑚,𝐿 𝑟𝑂1 || ||𝑟𝑂3 𝑟𝑂2 ||𝑟𝑂4
2 𝑔𝑚,𝐿

• 𝑅𝑜𝑢𝑡 = 𝑟𝑂2 ||𝑟𝑂4

𝑔𝑚,𝐼𝑛 1
• 𝐺𝑚 = 1 + 𝑔𝑚,𝐿 𝑟𝑂1 || ||𝑟𝑂3 ≈ 𝑔𝑚,𝐼𝑛
2 𝑔𝑚,𝐿

• 𝐴𝑣 ≈ 𝑔𝑚,𝐼𝑛 𝑟𝑂2 ||𝑟𝑂4

IISc, Analog VLSI Circuits E3 238 21

Intuitive analysis

• Total transconductance
𝑔𝑚1 𝑔𝑚2
𝐺𝑚 = + = 𝑔𝑚
2 2
• Resistance at output
𝑅𝑜𝑢𝑡 = 𝑟𝑂2 ||𝑟𝑂4

IISc, Analog VLSI Circuits E3 238 22

Ref: A-H
Intuitive analysis of cascode amplifier

• Total transconductance
𝑔𝑚1 𝑔𝑚2
𝐺𝑚 = + = 𝑔𝑚
2 2
• Resistance at output
𝑅𝑜𝑢𝑡 = 𝑔𝑚6 𝑟𝑂6 𝑟𝑂2 ||𝑔𝑚8 𝑟𝑂8 𝑟𝑂4

• Voltage gain 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡

IISc, Analog VLSI Circuits E3 238 23

How is the output voltage set? Unity gain Buffer
• Input voltage range: 𝑉𝑜𝑑5 + 𝑉𝐺𝑆1 ≤ 𝑉𝑖𝑛 ≤ 𝑉𝐷𝐷 − 𝑉𝐺𝑆3 + 𝑉𝑇1
• Output voltage range: 𝑉𝑜𝑑5 + 𝑉𝑜𝑑2 ≤ 𝑉𝑜𝑢𝑡 ≤ 𝑉𝐷𝐷 − 𝑉𝑜𝑑4

• Vout = VDD-VGS3 for perfectly symmetric (ideal) devices

• Almost never achieved in practice
• Vout swings between 2Vod and VDD

• Works fine for mismatched devices

• Mismatch results as input offset
voltage

IISc, Analog VLSI Circuits E3 238 Ref: BR 24