Department of Information

Technology
2023-24

Laboratory Manual

Subject

Assembly Language Programming (3IT08)

Prepared by

Mr. Nagesh B.Mapari

Paramhansa Ramkrishna Maunibaba Shikshan Sanstha‘s,

Anuradha Engineering College, Chikhli
Dist-Buldana (M.S.) 443201
Affiliated to Sant Gadge Baba Amravati University, Amravati.
Phone: (07264) – 243274//242063/242580Fax
No. 07264 –243278
Website: www.aecc.ac.in
 Index
Page
Sr. No. Title
No.
1. Vision and Mission statement of the Institute and Program
2. Program Educational Objective (PEOs)
3. Program Outcomes (POs)
4. Program Specific Outcomes (PSOs)
5. Course (Practical)
6. University Scheme
7. Course Learning Objective
8. Course Content
9. List of Experiment
10. Specific Course Outcomes
11. Aim of the Lab Manual
12. Experiment No.
a .Title/Aim
b .Objective
c. Algorithm
d. Sample code
f. Output/Result
i. Quiz/Objective type question/Viva-voce
13. Regular Assessment of Experiment during the practical
session

Assembly Language Programming (3IT07) Page 2

 Paramhansa Ramkrishna Maunibaba Shikshan Sanstha’s
Anuradha Engineering College, Chikhli
Dist-Buldana(M.S.) 443201

CERTIFICATE

This is to certify that, Mr / Ms

Enrollment No. Roll No. of B.E. (IT)
Semester Third , has satisfactorily completed the term work of the subject
Assembly Language Programming (3IT08), prescribed by Sant Gadge Baba
Amravati University, Amravati, during the academic term 2022-23.

Date :

Signature of the faculty Head of Department

Assembly Language Programming (3IT07) Page 3

1. Mission & Vision statements

 Mission & Vision statement of the Institute:

VISION
To make AEC the best in terms of excellence in education,research,
service to industry and society.

MISSION
To provide the finest environment for teaching, learning,research,
innovation and character building.

 Mission & Vision statement of the Department of Information Technology:

VISION
To produce high quality IT Engineers to suite industry,Organizations
and society needs.

MISSION

To equip with elegant ambiance for teaching, learning,

research, innovation and moral development.

2. Program Education Objectives (PEOs)

1. Preparation - To provide students with a solid foundation in mathematical, scientific and

engineering fundamentals required to solve engineering problems and also to pursue
higher studies.
2. Core Competition - To prepare students for a successful career with effective
communication skills, teamwork skills and work with values that meet the needs of Multi-
national Companies.
3. Breadth - To train students with good scientific and engineering breadth so as to
comprehend, analyze, design, and create novel products and solutions for the real life
problems.
4. Awareness - To promote awareness to students in social concern problems and
introduce them to professional ethics and codes of professional practice.
5. Learning Environment - To provide students a sound foundation in the latest
achievements in technologies, R & D and to gain knowledge in multidisciplinary aspects
by projects and industrial training.

Assembly Language Programming (3IT07) Page 4

3. Program Outcomes (POs)

Program Outcomes (POs)

PO1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
PO2 Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO3 Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
PO4 Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis
of the information to provide valid conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
PO9 Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations,and give and receive
clear instructions.
PO11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one‘s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.

PO12 Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technologicalchange.

Assembly Language Programming (3IT07) Page 5

4. Program Specific Outcome (PSOs)

Program Specific Outcome

(PSOs)
PSO1 Professional Skills: The ability to research, understand and implement computer programs in
the areas related to algorithms, system software, multimedia, web design, big data analytics,
and networking for efficient analysis and design of computer-based systems of varying
complexity.
PSO2 Problem-Solving Skills: The ability to apply standard practices and strategies in software
project development using open-ended programming environments to deliver a quality
product for business success.
PSO3 Successful Career and Entrepreneurship: The ability to employ modern computer languages,
environments, and platforms in creating innovative career paths, to be an entrepreneur, and a
zest for higher studies.

5. Course (Practical) Title : Assembly Language Programming - Lab.

Course Code : 3IT08

Instructor In-charge : Mr.A.SChhajed

Compulsory/ Elective : Compulsory

Course Assessment: Term work : Performance

Examinations : Internal Practical Exam - Performance &
Viva
The Semester end Practical Examination
conducted by SGBAU, Amravati.

Grading Policy:
Practical Marks : 25- Internal Marks-Performance & Viva
25- Marks External Exam and Viva

50 – Total Marks

Assembly Language Programming (3IT07) Page 6

6. University Scheme:

Teaching Scheme Examination Scheme

Hours /
Theory Practical
Week
Max.

Hours/Week
Marks

Theory Paper
Credits

Min. Passing
Subject Code

Min. Passing
Total

Max. Marks
Duration of
Paper (Hr.)

Max. Marks
Assessment
Tutorial
Lecture
Sr. No.

College

Marks
Total

Total
Marks
P/D
Subject

External

Internal
THEORY
01 8IT0 Assembly
3 Language 10
4 - - 4 4 3 80 20 40 - - - -
Programming 0

PRACTICALS
06 3IT0 Assembly
8 Language - - 2 4 1 - - - - - 25 25 50 25
Programming
- Lab
Total 10
4 - 2 8 5 50
0

3IT08 Assembly Language Programming Laboratory: Minimum Eight

experiments/programming assignments must be completed based on the 3 IT 04syllabus covering
each of the units.

7. Course Learning Objective

On the completion of this laboratory course, the students will be able to:
 i. Analyze the architecture of the Intel 8085 microprocessor for its various
applications.
ii. Develop simple arithmetic programs.
iii. Use the addressing modes and timing diagram for executing programs
efficiently
iv. Develop assembly language program using stack and subroutine for various
applications
v. Interface peripheral devices with 8085 microprocessor

Assembly Language Programming (3IT07) Page 7

8. Course Contents:

Microprocessor 8086 architecture-BIU and EU, pin configuration, Software model of 8086
microprocessor. Memory addresses space and data organization. Data types. Segment registers,
UNIT-I
memory segmentation. IP & Data registers, Pointer, Index registers. Memory addresses
generation, Maximum and Minimum Modes.
8086 Instruction set overview, addressing modes. 8086 instruction formats. 8086 programming:
Integer instructions and computations: Data transfer instructions, Arithmetic instructions, and
UNIT-II
logical instructions. Shift and rotate instructions and their use in 8086 programming

8086 programming: 8086 flag register and Flag control instructions control flow and jump
instructions, Loops & loop handling instructions. Stack related instructions. 8086 I/O Address
UNIT-III
space. Subroutines and related instructions, Concept of Macros and their types. 8086
programming using these instructions
Memory system design: Address decoding techniques, static- RAM interfacing, Dynamic
-RAM (DRAM): refreshing techniques, interfacing and DRAM controllers; direct memory access
UNIT-IV (DMA). Interfacing Chips- SRAM and EPROM with 8086, 8237 DMA: pin diagram, internal
organization, modes of operation
8086 I/O: Types of input output, isolated I/O interface, input output data transfers, I/O
instructions and bus cycles. Programmable Peripheral Interface 8255 PPI: pin diagram, internal
UNIT-V organization, modes of operation. Programmable Interval Timer / Counter 8253: pin diagram,
internal organization, modes of operation
8086 Interrupts types, priority and instructions. Interrupt vector table, External hardware-
interrupt interface signals & interrupts sequence. Software interrupts, Non-maskable interrupts.
UNIT-VI
Programmable Interrupt Controller 8259: pin diagram, internal organization, modes of
operation.

TEXT-BOOK:
1. Avtar Singh & Walter A. Triebel: The 8088 and 8086 Microprocessors, Programming, Interfacing,
Software, Hardware, and Applications, PHI, 2003.
2. K.M Bhurchandi, ―Advanced Microprocessor and Peripherals Architecture, Programming and
Interfacing‖, Tata Mc Graw Hill , 2006.
3. Ray & Bhurchandi: Advanced Microprocessors & Peripherals (TMH).
4. Liu Gibson: Microcomputer Systems: The 8086/8088 Family- Architecture, Programming And Design , PHI)
REFERENCE BOOKS :
1. Barry B. Brey : The Intel Microprocessor Architecture, Programming & Interfacing (6/e)(PHI)
2. John P Uffenbeck, ―8086/8088 Families: Designing, Programming and Interfacing‖. Prentice Hall
3. D. V. Hall: Microprocessors and Interfacing, TMH

Assembly Language Programming (3IT07) Page 8

 9. List of Experiment:

EXPERIMENT NO.
EXPERIMENT DESCRIPTION
01 Study of Editor, Assembler, Linker and Debugger.
02 Study architecture and software model of 8088/8086microprocessor.
03 Write a TASM program to perform arithmetic operation.
E.g. ADD,SUB,MUL,DIV.
04 Write TASM program for (DX)  7(AX)  5(BX)  (BX)/8
05 Write a TASM program to move block of data from oneplace to another.
06 Write a TASM program for factorial number (N!) .
07 Write a TASM program to perform linear search.
08 Write a TASM program to perform bubble sort.
09 Write a TASM program that display character on monitorby using interrupt 21H
10 To study minimum mode, maximum mode of8088/8086.

10. Specific Course Outcomes:

Upon the completion of Assembly language programming practical course, the studentwill be
able to:
Introduction to 8086 microprocessor.
what are the different categories of addressing mode? Different types of instruction.
Fundamental of 8086 programming.
Explain different types of memories.
Discuss different types of I/O.
Explain need of interrupt? Different types of interrupt

11. Aim of the Lab manual: This manual is designed for the Second Year (3rd Semester)
students of Information Technology. The objective of this lab is introduces the concepts and
methods required for the construction of large software intensive systems. It aims to develop a
broad understanding of the hardware interface. It aims to set these techniques in an appropriate
engineering and management context.

Assembly Language Programming (3IT07) Page 9

 EXPERIMENT NO: 01

Aim: Study of Editor, Assembler, Linker and Debugger.

Theory:

Assembly language has several benefits:

 Speed: Assembly language programs are generally the fastest programs around.
 Space : Assembly language programs are often the smallest.
 Capability: You can do things in assembly which are difficult or impossible inHLLs.
 Knowledge: Your knowledge of assembly language will help you write better
programs, even when using HLLs.

EDITOR:
You must use an editor to enter the program into a file. The process of using the editor (editing)
is a basic form of word processing. This skill has no relevance to programming. TASM and LINK
commands to translate it to machine code so that it may be executed as follows:
If you have syntax errors, you will get error messages at this point. You then have to edit your
program, correct them and repeat the above command; otherwise proceed to the link command,
pressing Return in response to prompts for file names from tasm or link.

Assembly Language Programming (3IT07) Page 10

ASSEMBLER:

An assembler is a program that takes basic computer instructions and converts them into a
pattern of bits that the computer's processor can use to perform its basic operations. Some
people call these instructions assembler language and others use the term assembly language.We
use Turbo TASM and LINK programs for assembling and linking 8086 assembly language
programs. TASM program files should have names with the extension (3 characters after period)
asm.

LINKER:
In computer science, a linker or link editor is a computer program that takes one or more
object files generated by a compiler (assembler) and combines them into a single executable file,
library file, or another object file.

DEBUGGER:
In computers, debugging is the process of locating and fixing or bypassing bugs (errors) in
computer program code or the engineering of a hardware device. To debug a program or
hardware device is to start with a problem, isolate the source of the problem,and then fix it.

Results :

Date Signature Practical In-charge

:

Assembly Language Programming (3IT07) Page 11

 Experiment no: 2

Aim: Study architecture and software model of 8088/8086 microprocessor.

Theory:
The processor is partitioned into two logical units:
a) Bus Interface Unit (BIU) b) Execution Unit (EU).
The role of the EU is to execute instruction, whereas the BIU delivers instruction and data to
EU. The EU contains Arithmetic Logic Unit(ALU), Control Unit(CU) and number of
registers. This feature enables the EU to execute instructions and perform arithmetic and logical
operations.
The most important function of BIU is to manage the bus control unit, segment registers
instruction queue. The BIU controls the busses that transfer data to the EU, to memory, and to
external input/output devices, whereas the segment registers control the memory addressing.
Another function of the BIU is to provide access to instructions, because the instructions for a
program that is executing are kept in memory, the BIU must access

Assembly Language Programming (3IT07) Page 12

instruction from memory and place them in an instruction queue, which varies in size depending
on the processor. This feature enables the BIU to look ahead and prefetch instructions, so that
there is always a queue of instructions ready to execute.
The EU and BIU work in parallel, with the BIU keeping one step ahead. The EU notifies the BIU
when it needs access to data in memory or I/O devices. Also the EU request machine code
instructions from the BIU instruction queue. The top instruction is the currently executable one,
and while the EU is occupied executing an instruction, the BIU fetch another instruction from
memory. This fetching overlaps with execution and speeds up processing.
Registers
Registers are 8, 16, or 32-bit high speed storage locations directly inside the CPU, designed to
be accessed at much higher speed than conventional memory. The CPU has an internal data bus
that is generally twice as wide as its external data bus.
Data Registers: The general purpose registers, are used for arithmetic and data movement.
Each register can be addressed as either 16-bit or 8 bit value. Example, AX register is a 16-bit
register, its upper 8-bit is called AH, and its lower 8-bit is called AL. Bit 0 in AL corresponds to
bit 0 in AX and bit 0 in AH corresponds to bit 8 in AX.

Instructions can address either 16-bit data register as AX, BX, CX, and DX or 8-bit register
as AL, AH, BL, BH, CL, CH, Dl, and DH. If we move 126FH to AX then AL would
immediately 6FH and AH = 12H.
* Each general purpose register has special attributes:
1- AX (Accumulator): AX is the accumulator register because it is favored by the CPU for
arithmetic operations. Other operations are also slightly more efficient when performed using
AX

2- BX (Base): the BX register can hold the address of a procedure or variable. Threeother
registers with this ability are SI, DI and BP. The BX register can also perform arithmetic and
data movement.
3- CX (Counter): the CX register acts as a counter for repeating or looping instructions.These
instructions automatically repeat and decrement CX.
4- DX (Data): the DX register has a special role in multiply and divide operation. When
multiplying for example DX hold the high 16 bit of the product.

Assembly Language Programming (3IT07) Page 13

 Figure 2.1: Pipelined architecture of the 8088/8086.

Assembly Language Programming (3IT07) Page 14

 Figure 2.2: Register in 8086/8088 processor

* Segment Registers: the CPU contain four segment registers, used as base location for
program instruction, and for the stack.
1- CS (Code Segment): The code segment register holds the base location of allexecutable
instructions (code) in a program.
2- DS (Data Segment): the data segment register is the default base location forvariables.
The CPU calculates their location using the segment value in DS.
3- SS (Stack Segment): the stack segment register contain the base location of thestack.
4- ES (Extra Segment): The extra segment register is an additional base location for
memory variables.
* Index registers: index registers contain the offset of data and instructions. The term offset
refers to the distance of a variable, label, or instruction from its base segment. The index
registers are:
1- BP (Base Pointer): the BP register contain an assumed offset from the stack segment
register, as does the stack pointer. The base pointer register is often used by asubroutine to locate
variables that were passed on the stack by a calling program.
2- SP (Stack Pointer): the stack pointer register contain the offset of the top of the stack. The
stack pointer and the stack segment register combine to form the complete address of the top of
Assembly Language Programming (3IT07) Page 15
the stack.
3- SI (Source Index): This register takes its name from the string movement instruction, in
which the source string is pointed to by the source index register.
4- DI (Destination Index): the DI register acts as the destination for string movement
instruction.
Status and Control register:
1- IP (Instruction Pointer): The instruction pointer register always contain the offset ofthe
next instruction to be executed within the current code segment. The instruction pointer and the
code segment register combine to form the complete address of thenext instruction.
2- The Flag Register: is a special register with individual bit positions assigned to showthe
status of the CPU or the result of arithmetic operations.
There two basic types of flags: (control flags and status flags)
1- Control Flags: individual bits can be set in the flag register by the programmer to
control the CPU operation , these are
- The Direction Flag (DF): affects block data transfer instructions, such as MOVS, CMPS,

SCAS. The flag values are 0 = up and 1 = down.

- The Interrupt flag (IF): dictates whether or not a system interrupt can occur. Such as
keyboard, disk drive, and the system clock timer. A program will sometimes briefly disable the
interrupt when performing a critical operation that cannot be interrupted. The flag values are 1
= enable, 0 = disable.
- The Trap flag (TF): Determine whether or not the CPU is halted after each instruction. When
this is set, a debugging program can let a programmer to enter single stepping (trace) through a
program one instruction at a time. The flag values are 1 = on, 0 = off. The flag can be set by
INT 3 instruction.
2- Status Flags: The status flags reflect the outcomes of arithmetic and logical operations
performed by the CPU, these are:
- The Carry Flag (CF): is set when the result of an unsigned arithmetic operation is too large to
fit into the destination for example, if the sum of 71 and 99 where stored in the 8-bit register AL,
the result cause the carry flag to be 1. The flag values = 1 = carry, 0 = no carry.
- The Overflow (OF): is set when the result of a signed arithmetic operation is too wide (too
many bits) to fit into destination. 1 = overflow, 0 = no overflow.
- Sign Flag (SF): is set when the result of an arithmetic of logical operation generates a
Assembly Language Programming (3IT07) Page 16
 negative result, 1= negative, 0 = positive.
- Zero Flag (ZF): is set when the result of an arithmetic of logical operation generates a result
of zero, the flag is used primarily by jump or loop instructions to allow branching to a new
location in a program based on the comparison of two values. The flag value = 1 = zero, & 0 =
not zero.
- Auxiliary Flag: is set when an operation causes a carry from bit 3 to bit 4 (or borrow from bit
4 to bit 3) of an operand. The flag value = 1 = carry, 0 = no carry.
- Parity Flag: reflect the number of 1 bits in the result of an operation. If there is an even
number of bit, the parity is even. If there is an odd number of bits, parity is odd. This
flag is used by the OS to verify memory integrity and by communication software to verify the
correct transmission of data.

Figure 1.3 Software model of the 8088/8086 microprocessor

Result: Hence we successfully studied architecture and software model of 8088/8086

microprocessor.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 17

 Experiment no: 3
Aim: Write a TASM program to perform arithmetic operation. E.g. ADD, SUB, MUL, DIV etc.

Theory:
Variables
Variable is a memory location. For a programmer it is much easier to have some value be kept
in a variable named "var1" then at the address 5A73:235B, especially when you have 10 or more
variables.
Our compiler supports two types of variables: BYTE and WORD.
Syntax for a variable declaration:
name DB value
name DW value

DB - stays for Define Byte.

DW - stays for Define Word.

name - can be any letter or digit combination, though it should start with a letter. It‘s possible to
declare unnamed variables by not specifying the name (this variable will have an address but no

name).

value - can be any numeric value in any supported numbering system (hexadecimal,binary, or
decimal), or "?" symbol for variables that are not initialized.

Arrays
Arrays can be seen as chains of variables. A text string is an example of a byte array,each
character is presented as an ASCII code value (0..255).
Here are some array definition examples:

a DB 48h, 65h, 6Ch, 6Ch, 6Fh, 00h

b DB 'Hello', 0

b is an exact copy of the a array, when compiler sees a string inside quotes it automatically
converts it to set of bytes. This chart shows a part of the memory where these arrays are
declared:

Assembly Language Programming (3IT07) Page 18

Constants
Constants are just like variables, but they exist only until your program is compiled (assembled).
After definition of a constant its value cannot be changed. To define constants EQU directive is
used:
name EQU < any expression >
For example:

k EQU 5
MOV AX, k
The above example is functionally identical to code:MOV
AX, 5

You can access the value of any element in array using square brackets, for example:MOV AL,
a[3]
You can also use any of the memory index registers BX, SI, DI, BP, for example:MOV
SI, 3
MOV AL, a[SI]
If you need to declare a large array you can use DUP operator.The
syntax for DUP:
number DUP ( value(s) )
number - number of duplicate to make (any constant value).value -
expression that DUP will duplicate.

for example:
c DB 5 DUP(9)
is an alternative way of declaring:c
DB 9, 9, 9, 9, 9
one more example:d
DB 5 DUP(1, 2)

Assembly Language Programming (3IT07) Page 19

is an alternative way of declaring:
d DB 1, 2, 1, 2, 1, 2, 1, 2, 1, 2

Of course, you can use DW instead of DB if it's required to keep values larger then 255, or
smaller then -128. DW cannot be used to declare strings.
To view arrays you should click on a variable and set Elements property to array size. In
assembly language there are not strict data types, so any variable can be presented as an array.

Mnemonic Meaning Format Operation Flag Affected

ADD Addition ADD D, S (S)+(D)(D) OF,SF,ZF,AF,PF,CF
Carry(CF)
INC Increment INC D (D) +1 (D) OF,SF,ZF,AF,PF
SUB Subtract SUB D,S (D)–(S)(D) OF,SF,ZF,AF,PF,CF
Borrow(CF)

When two bytes are multiplied -The multiplicand is in the AL register, and the multiplier is a
byte in the memory or in another register. The product is in AX. High-order 8 bits of the product
is stored in AH and the low-order 8 bits are stored in AL.

When two one-word values are multiplied -

The multiplicand should be in the AX register, and the multiplier is a word in memory oranother
register. For example, for an instruction like MUL DX, you must store the multiplier in DX and
the multiplicand in AX.

The resultant product is a doubleword, which will need two registers. The high-order (leftmost)
portion gets stored in DX and the lower-order (rightmost) portion gets storedin AX.

Assembly Language Programming (3IT07) Page 20

 When the divisor is 1 byte -

The dividend is assumed to be in the AX register (16 bits). After division, the quotientgoes to the
AL register and the remainder goes to the AH register.

When the divisor is 1 word –

The dividend is assumed to be 32 bits long and in the DX:AX registers. The high-order 16
bits are in DX and the low-order 16 bits are in AX. After division, the 16-bit quotient goes to the
AX register and the 16-bit remainder goes to the DX register.

Result: Hence we have executed program successfully.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 21

 Experiment no: 4

Aim: Write TASM program for (DX)  7(AX)  5(BX)  (BX)/8using

shift and arithmatic instruction.
Theory:
The set of shifting and rotation instructions is one of the most useful set in any processor‘s
instruction set. They simplify really complex tasks to a very neat and concise algorithm. The
following shifting and rotation operations are available in our processor.
Mnemonic Meaning Format Operation Flags
Affected
SAL/SHL arithmeti SAL/SHL D, Shift the D left by OF, CF
c left/shift Count the number of bit
logical positions equal to
left count and fill the
vacated bits
positions on the
right with zeros

SHR Shift SHR D, Count Shift the D right OF, CF

logical by the number ofbit
right position equalto
count and fill the
vacated bit
positions on the left
with zeros

SAR Shift SAR D, Count Shift the D right OF,SF, ZF,

arithmeti by the number of AF,
c bit positions equal PF, CF
right to count and fill
the vacated bit
positions on the
left with the
original most
significant bit
Assembly Language Programming (3IT07) Page 22
Shift Logical Right (SHR)
The shift logical right operation inserts a zero from the left and moves every bit one position to
the right and copies the rightmost bit in the carry flag. Imagine that there is a pipe filled to
capacity with eight balls. The pipe is open from both ends and there is a basket at the right end
to hold anything dropping from there. The operation of shift logical right is to force a white ball
from the left end. The operation is depicted in the following illustration.

White balls represent zero bits while black balls represent one bit. Sixteen bit shifting is done the
same way with a pipe of double capacity.
Shift Logical Left (SHL) / Shift Arithmetic Left (SAL)
The shift logical left operation is the exact opposite of shift logical right. In this operation the
zero bit is inserted from the right and every bit moves one position to its left with the most
significant bit dropping into the carry flag. Shift arithmetic left is just another name for shift
logical left. The operation is again exemplified with the following

illustration of ball and pipes.

Shift Arithmetic Right (SAR)

A signed number holds the sign in its most significant bit. If this bit was one a logical right
shifting will change the sign of this number because of insertion of a zero from theleft. The sign of
a signed number should not change because of shifting.
The operation of shift arithmetic right is therefore to shift every bit one place to the right with a
copy of the most significant bit left at the most significant place. The bit dropped from the right is
caught in the carry basket. The sign bit is retained in this operation. The operation is further
illustrated below.

Assembly Language Programming (3IT07) Page 23

The left shifting operation is basically multiplication by 2 while the right shifting operation is
division by two. However for signed numbers division by two can be accomplished by using shift
arithmetic right and not shift logical right. The left shift operation is equivalent to multiplication
except when an important bit is dropped from the left. The overflow flag will signal this
condition if it occurs and can be checked with JO. For division by 2 of a signed number logical
right shifting will give a wrong answer for a negative number as the zero inserted from the left
will change its sign. To retain the sign flag and still effectively divide by two the shift arithmetic
right instruction mustbe used on signed numbers.
Rotate Right (ROR)
In the rotate right operation every bit moves one position to the right and the bit dropped from
the right is inserted at the left. This bit is also copied into the carry flag.

The operation can be understood by imagining that the pipe used for shifting has been molded
such that both ends coincide. Now when the first ball is forced to move forward, every ball moves
one step forward with the last ball entering the pipe from its other end occupying the first ball‘s
old position. The carry basket takes a snapshot of this ball leaving one end of the pipe and
entering from the other.

Rotate Left (ROL)

In the operation of rotate left instruction, the most significant bit is copied to the carry flag and is
inserted from the right, causing every bit to move one position to the left. It is the reverse of the
rotate right instruction. Rotation can be of eight or sixteen bits. The following illustration will
make the concept clear using the same pipe and balls example.

Assume that all numbers are small enough so that shifting to the left does not generate an
overflow. Further we will accept the truncation error due to shifts to the right.

Assembly Language Programming (3IT07) Page 24

 Program:
MOV DX,AX ;(DX)  (AX)
MOV CL,3
SHL DX,CL
SUB DX,AX
MOV SI,BX ;(SI)  5(BX)
MOV CL,2
SHL SI,CL
ADD SI,BX
SUB DX,SI ;(DX)  7(AX)  5(BX)
MOV SI,BX ;(SI)  (BX)/8
MOV CL,3
SAR SI,CL
SUB DX,SI ;(DX)  7(AX)  5(BX)  (BX)/8
MOV AX, DX ;(AX)  7(AX)  5(BX)  (BX)/8

Result: Hence we have executed program (DX)  7(AX)  5(BX)  (BX)/8Using

shift and arithmatic instruction.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 25

 Experiment no: 5
Aim: Write a TASM program to move block of data from one place to another.Theory:
Compare Instruction
There is an instruction included instruction set which can be used to compare two 8-bitnumber or 16-bit
numbers. It is the compare (CMP) instruction. The operands can

reside in a storage location in memory, a register within the MPU.

Mnemonic Meaning Format Operation Flags Affected
CMP Compare CMP D,S D-S CF,AF,OF,PF,S
F

Destination Source
Register Register
Register Memory
Memory Register
Register Immediate
Memory Immediate
Accumulator Immediate

The process of comparison performed by the CMP instruction is basically a subtraction

operation. The source operand is subtracted from the destination operand. However the result of
this subtraction is not saved. Instead, based on the result the appropriate flagsare set or reset.

Assembly Language Programming (3IT07) Page 26

 Program:
; program to move a block of N bytes of data starting at offset address BLK1ADDR to
;another block starting at offset address BLK2ADDR. Assume that both blocks are inthe
; same data segment, whose starting point is defined by the data segment address
;DATASEGMADDR.

.MODEL SMALL
.DATA

MOV AX, DATASEGADDR

MOV DS, AX
MOV SI, BLK1ADDR
MOV DI,
BLK2ADDR MOV
CX, N
NXTPT: MOV AH,
[SI] MOV [DI], AH
INC SI
INC DI
DEC
CX
JNZ NXTPT

Result: Hence we have successfully transfer block from one place to another.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 27

 Experiment no: 6
Aim: Write a TASM program for factorial number (N!).
Theory:
JUMP Instruction
The purpose of a jump instruction is to alter the execution path of instructions in the program.
The code segment register and instruction pointer keep track of the next instruction to be
executed. Thus a jump instruction involves altering the contents of these registers. In this way,
execution continues at an address other than that of the next sequential instruction. That is, a
jump occurs to another part of the program.
There two type of jump instructions:
a. Unconditional jump.
b. Conditional jump.
In an unconditional jump, no status requirements are imposed for the jump to occur. That
is, as the instruction is executed, the jump always takes place to change the execution sequence.
See Figure 16
On the other hand, for a conditional jump instruction, status conditions that exist at the moment
the jump instruction is executed decide whether or not the jump will occur. If this condition or
conditions are met, the jump takes place, otherwise execution continues with the next sequential
instruction of the program. The conditions that can be referenced by a conditional jump
instruction are status flags such as carry (CF),

parity (PF), and overflow (OF). See Figure 17

Assembly Language Programming (3IT07) Page 28

 Mnemonic Meaning Format Operation Flags Affected
JCC Conditional Jcc operand If the specific condition cc is None
jump true, the jump to the address
specified by the operand is
initiated, otherwise the next
instruction is executed

The following table lists some of the conditional jump instructions:

Instruction Meaning
JAE/JNB Jump if above or equal jump if not below
JB/JNAE Jump if below/jump if not above or equal
JC Jump if carry
JCXZ Jump if CX is zero
JE/JZ Jump if equal/jump if zero
JNC Jump if not carry
JNE/JNZ Jump if not equal/ jump if not zero
JNO Jump if not overflow
JNP/JPO Jump if parity/jump if parity odd
JNS Jump if not sign
JO Jump if overflow
JP/JPE Jump if parity/jump if parity Even
JS Jump if sign

Program:
; N! = 1*2*3*4...*(N-1)*N
; Also note that 0! = 1! = 1
MOV AL,1H ; Initial value of result MOV
CL,0H ; Start multiplying number
MOV DL,N ; Last number for multiplicationNXT:
CMP CL,DL ; Skip if done
JE DONE
INC CL ; Next multiplying number MUL
CL ; Result  Result * numberJMP NXT ;
Repeat
DONE: MOV [FACT],AL ; Save the result

Result: Hence we have successfully executed Factorial number program.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 29

 Experiment no: 7

Aim: Write a TASM program to perform bubble sort.

Theory:

Sorting can be ascending or descending like if the largest number comes at the top,
followed by a smaller number and so on till the smallest number the sort will be called
descending. The other order starting with the smallest number and ending at the largest is called
ascending sort. This is a common problem and many algorithms have been developed to solve it.
One simple algorithm is the bubble sort algorithm.
In this algorithm we compare consecutive numbers. If they are in required order
e.g. if it is a descending sort and the first is larger than the second, then we leave them as it is
and if they are not in order, we swap them. Then we do the same process for the next two
numbers and so on till the last two are compared and possibly swapped. A complete iteration is
called a pass over the array. We need N passes at least in the simplest algorithm if N is the
number of elements to be sorted. A finer algorithm is to check if any swap was done in this pass
and stop as soon as a pass goes without a swap. The array is now sorted as every pair of
elements is in order.

For example if our list of numbers is 60, 55, 45, and 58 and we want to sort them in ascending
order, the first comparison will be of 60 and 55 and as the order will be reversed to 55 and 60.
The next comparison will be of 60 and 45 and again the two will be swapped. The next
comparison of 60 and 58 will also cause a swap. At the end of first pass the numbers will be in
order of 55, 45, 58, and 60. Observe that the largest number has bubbled down to the bottom.
Just like a bubble at bottom of water. In the next pass 55 and 45 will be swapped. 55 and 58 will
not be swapped and 58 and 60 will also not be swapped. In the next pass there will be no swap as
the elements are in order
i.e. 45, 55, 58, and 60. The passes will be stopped as the last pass did not cause any swap. The
application of bubble sort on these numbers is further explained with the following illustration.

Assembly Language Programming (3IT07) Page 30

Program:
; Write an alp to sort in ascending order using bubble sort algorithm
; a given set of byte sized unsigned numbers in memory.The sorted
; elements should replace the original unsorted elements in memory.

Assembly Language Programming (3IT07) Page 31

 ; name bubblesort
;title ascending order using bubble sort
.model small
.stack 64
.data
a db 34h,78h,56h,47h
si_ze dw $-a ;si_ze=no of elements
.code
bubsort:
mov ax,@data
mov ds,ax mov
bx,si_ze
dec bx ;bx=no of passes needed to complete sorting(n-1)
outlup:
mov cx,bx ;cx=no of comparisions to be performed in a passmov si,0
inlup:
mov al,a[si]
inc si
cmp al,a[si]
jb go_on xchg
al,a[si] mov
a[si-1],al
go_on:
loop inlup ;dec cx,until cx=0
dec bx
jnz outlup
int 3 ;breakpoint interrupt
align 16
end bubsort

Result: Hence we have successfully executed Bubble sort.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 32

 Experiment no: 8
Aim: Write a TASM program to perform linear search.

Theory:

In computer science, linear search or sequential search is a method for finding a particular
value in a list that checks each element in sequence until the desired element is found or the list is
exhausted. The list need not be ordered.

Linear search is the simplest search algorithm; it is a special case of brute-force search. Its worst
case cost is proportional to the number of elements in the list. Its expected cost is also
proportional to the number of elements if all elements are searched equally. If the list has more
than a few elements and is searched often, then more complicated search methods such as binary
search or hashing may be appropriate. Those methods have faster search times but require
additional resources to attain that speed.

; Write an 8086 alp to search for a given 8 bit field using linear
; Search in an array of records with 2 fields. The searchkey is the
; first byte of the record. Message should be displayed on CRT
; indicating whether the search was a success or a failure. If it is a
; ; ; success case, the position of the record in the array is to be
; displayed.title linear search on an array of records
.model small
.stack 64
.data
array db 55h,22h,33h,55h,45h,11h,66h,44hlen
dw ($-array)/2
scrkey equ 66h
asc1 equ (scrkey/10h)+'0' asc2
equ (scrkey mod 10h)+'0'
msgsuc db 'Record with first byte as ',asc1,asc2db '
Found at position: '
result db ?,0dh,0ah,'$'
failmsg db 'Record with first byte as ',asc1,asc2db '
Not found ',0dh,0ah,'$'
.code
main:
mov ax,@data
mov ds,ax mov
cx,len mov bx,0
mov al,scrkey
again:
Assembly Language Programming (3IT07) Page 33
 cmp al,array[bx]
je sucmsg
inc bx
inc bx
loop again
failure:
lea dx,failmsg
jmp display
sucmsg:
ror bx,1
inc bx ;position=(bx/2)+1
add bl,'0'
mov result,bl
lea dx,msgsuc
display:
mov ah,09h
int 21h mov
ah,4chint
21h
end main

Result: Hence program executed successfully.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 34

€

Experiment no: 9
Aim: Write a TASM program that display character on monitor by using interrupt 21H.

Theory
Interrupts
Interrupts can be seen as a number of functions. These functions make the programming much
easier, instead of writing a code to print a character you can simply call the interrupt and it will
do everything for you. There are also interrupt functions that work with disk drive and other
hardware. We call such functions software interrupts.
Interrupts are also triggered by different hardware, these are called hardware interrupts.
Currently we are interested in software interrupts only.

To make software interrupt there is an INT instruction, it has very simple syntax:INT
value
Where value can be a number between 0 to 255 (or 0 to 0FFh). generally we will use
hexadecimal numbers. You may think that there are only 256 functions, but that is not correct.
Each interrupt may have sub-functions.
To specify a sub-function AH register should be set before calling interrupt.
Each interrupt may have up to 256 sub-functions (so we get 256 * 256 = 65536 functions). In
general AH register is used, but sometimes other registers maybe in use. Generally other
registers are used to pass parameters and data to sub-function.
The following example uses INT 10h sub-function 0Eh to type a "Hello!" message. This function
displays a character on the screen, advancing the cursor and scrolling the screen as necessary.
Interrupts introduce temporary breakage in the program flow, sometimes programmed (software
interrupts) and un-programmed at other times (hardware interrupts). By hooking interrupts
various system functionalities can be controlled. The interrupts reserved by the processor and
having special functions in 8088 are listed below:
• INT 0, Division by zero
Meaning the quotient did not fit in the destination register. This is a bit different as this interrupt
does not return to the next instruction, rather it returns to the same instruction that generated it, a
DIV instruction of course. Here INT 0 is automatically generated by a DIV when a specific
situation arises, there is no INT 0 instruction.
• INT 1, Trap, Single step Interrupt
This interrupt is used in debugging with the trap flag. If the trap flag is set the Single Step

Assembly Language Programming (3IT07) Page 35

Interrupt is generated after every instruction. By hooking this interrupt a debugger can get
control after every instruction and display the registers etc. 8088 was the first processor

that has this ability to support debugging.

• INT 2, NMI-Non Maskable Interrupt
Real interrupts come from outside the processor. INT 0 is not real as it is generated from inside.
For real interrupts there are two pins in the processor, the INT pin and the NMI pin. The
processor can be directed to listen or not to listen to the INT pin. Consider a recording studio,
when the recording is going on, doors are closed so that no interruption occurs, and when there
is a break, the doors are opened so that if someone is waiting outside can come it. However if
there is an urgency like fire outside then the door must be broken and the recording must not be
catered for. For such situations is the NMI pin which informs about fatal hardware failures in
the system and is tied to interrupt 2. INT pin can be masked but NMI cannot be masked.
• INT 3, Debug Interrupt
The only special thing about this interrupt is that it has a single byte opcode and not a two byte
combination where the second byte tells the interrupt number. This allows it to replace any
instruction whatsoever. It is also used by the debugger and will be discussed in detail with the
debugger working.
• INT 4, Arithmetic Overflow, change of sign bit
The overflow flag is set if the sign bit unexpectedly changes as a result of a mathematical or
logical instruction. However the overflow flag signals a real overflow only if the numbers in
question are treated as signed numbers. So this interrupt is not automatically generated but as a
result of a special instruction INTO (interrupt on overflow) if the overflow flag is set. Otherwise
the INTO instruction behaves like a NOP (no operation).
These are the five interrupts reserved by Intel and are generally not used in our operations.
INT 21h / AH=1 - read character from standard input, with echo, result is stored in AL.
if there is no character in the keyboard buffer, the function waits until any key is pressed.

example:

mov ah, 1
int 21h

INT 21h / AH=2 - write character to standard output.

entry: DL = character to write, after execution AL = DL.
Assembly Language Programming (3IT07) Page 36
example:

mov ah, 2
mov dl, 'a'
int 21h

INT 21h / AH=5 - output character to printer.

entry: DL = character to print, after execution AL = DL.

example:

mov ah, 5
mov dl, 'a'
int 21h
INT 21h / AH=6 - direct console input or output.

parameters for output: DL = 0..254 (ascii code)

parameters for input: DL = 255

for output returns: AL = DL

for input returns: ZF set if no character available and AL = 00h, ZF clear if character
available.
AL = character read; buffer is cleared.
example:
mov ah, 6
mov dl, 'a'
int 21h ; output character.
mov ah, 6
mov dl, 255
int 21h ; get character from keyboard buffer (if any) or set ZF=1.
INT 21h / AH=7 - character input without echo to AL.
if there is no character in the keyboard buffer, the function waits until any key is pressed.

example:
mov ah, 7
int 21h
INT 21h / AH=9 - output of a string at DS:DX. String must be terminated by '$'.

example:
org 100h
mov dx, offset msg
mov ah, 9
int 21h
ret
msg db "hello world $"
Assembly Language Programming (3IT07) Page 37
 INT 21h / AH=0Ah - input of a string to DS:DX, fist byte is buffer size, second byte is number of
chars actually read. this function does not add '$' in the end of string. to print using INT 21h /
AH=9 you must set dollar character at the end of it and start printing from address DS:DX + 2.
example:
org 100h
mov dx, offset buffer
mov ah, 0ah
int 21h
jmp print
buffer db 10,?, 10 dup(' ')

print:
xor bx, bx
mov bl, buffer[1] mov
buffer[bx+2], '$'
mov dx, offset buffer + 2
mov ah, 9
int 21h
re

Program:
; prog1.asm: displays the character ‗a‘ on the screen
.model small
.stack 100h
.code
start:
mov dl, ‗a‘ ; store ascii code of ‗a‘ in dl
mov ah, 2h ; ms-dos character output functionint
21h ; displays character in dl register
mov ax, 4c00h ; return to ms-dosint
21h
end start
Result: Hence program executed successfully.

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 38

 Experiment no: 10
Aim: To study minimum mode, maximum mode of 8088/8086

Theory:
The INTEL 8086 is the first 16-bit processor released by INTEL in the year 1978. 8086 is packed
in a 40 pin DIP and requires a 5 Volt supply. 8086 microprocessor has a much more powerful
instruction set along with the architectural developments which

imparted substantial programming flexibility and improvement in speed over the 8-bit
microprocessors.
The peripheral chips designed earlier for 8085 were compatible with microprocessor 8086 with
slight or no modifications. Though there is a considerable difference between the memory
addressing techniques of 8085 and 8086, the memory interfacing technique similar, but includes
the use of a few additional signals. The clock requirements are also different as compared to
8085, but the overall minimal system organization of 8086 is similar to that of a general 8-bit
microprocessor.
The 8086 does not have internal clock circuit. The 8086 requires an external asymmetric clock
source with 33% duty cycle. The 8284 clock generator is used to generate the required clock for
8086. The maximum internal clock of 8086 is 5 MHz. The other versions of 8086 with different
.clock rates are 8086-1, 8086-2 and 8086-4 with maximum internal clock frequency of 10MHz,
8MHz and 4MHz respectively.
The 8086 uses a 20-bit address to access memory and hence it can directly address upto one
megabytes (220 = 1 Mega) of memory space. The one megabytes (1 Mb) of addressable memory
space of 8086 are organized as two memory banks of 512 kilobytes each (512 kb + 512 kb 1Mb).
The memory banks are called even (or lower) bank and odd (or upper) bank. The address line A 0
is used to select even bank and the control signal BHE is used to select odd bank.

For accessing I/O mapped devices, the 8086 uses a separate 16-bit address, and so the 8086 can
generate 64k (216) I/O addresses. The signal M /IO is used to differentiate the memory and I/O
addresses. For memory address the signal M /IO is asserted high and

for I/O address the signal M /IO is asserted low by the processor.
The 8086 can operate in two modes, and they are minimum mode and maximum mode. The mode
is decided by a signal at MN/MX pin. When the MN/MX is tied high, it works in minimum mode
and the system is called uniprocessor system. When MN / MX is tied low, it works in maximum
Assembly Language Programming (3IT07) Page 39
mode and the system is called multiprocessor system. Usually the pin MN/ MX is permanently
tied to low or high so that the 8086 system can work in any one of the two modes. The 8086 can
work with 8087 coprocessor in maximum mode. In this mode an external bus controller 8288 is
required to generate bus control signals

The 8086 has two family of processors. They are 8086 and 8088. The 8088 uses 8-bit data bus
externally but 8086 uses 16-bit data bus externally. The 8086 access memory in words but 8088
access memory in bytes. The IBM designed its first personal computer (PC) using INTEL 8088
microprocessor as CPU.

PIN OUT SIGNALS AND FUNCTIONS OF 8086

The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10 MHz,
packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or
multiprocessor configurations to achieve high performance. The pin configuration is shown in
Fig. 1.1. Some of the pins serve a particular function in minimum mode (single processor mode)
and others function in maximum mode (multiprocessor mode) configuration.

The 8086 signals can be categorized in three groups. The first are the signals having common
functions in minimum as well as maximum mode, the second are the signals which have special
functions for minimum mode and the third are the signals having

Assembly Language Programming (3IT07) Page 40

special functions for maximum mode.

The following signal descriptions are common for both the minimum and maximummodes.

AD15 -- AD0 These are the time multiplexed memory I/O address and data lines. Address

Assembly Language Programming (3IT07) Page 41

 remains
Here T2, on the and
Tfloat linesTduring
3, T4 to
T1clock
w are the
state,states
while thea data is availableTon thewait
datastate.
bus during
These Tlines
2,T3, are
Tw and T 4.
high and a tristate during interruptofacknowledge
machine cycle. w is a
and local bus hold acknowledge active
cycles.

A19/S6, A18/S5, A17/S4, A16/S3 These are the time multiplexed address and status lines. During T1,
these are the most significant address lines for memory operations. During I/O operations, these
lines are low. During memory or I/O operations, status information is available on those lines for
T2, T3, Tw and T4. The status of the interrupt enable flag bit (displayed on S5) is updated at the
beginning of each clock cycle. The S4 and S3 combinedly indicate which segment register is
presently being used for memory accesses as shown in Table 1.1. These lines float to tri-state off
(tristated) during the local bus hold acknowledge. The status line S6 is always low (logical). The
address bits are separated from the status bits using latches controlled by the ALE signal.
Table 1.1
S4 S3 Indications
0 0 Alternate Data
0 1 Stack
1 0 Code or none
1 1 Data

BHE / S7-Bus High Enable/Status The bus high enable signal is used to indicate
the transfer of data over the higher order (D15—D8) data bus as shown in Table 1.2. It goes low
for the data transfers over D15—D8 and is used to derive chip selects of odd address memory
bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles,
whenever a byte is to be transferred on the higher byte of the data bus. The status information is
available during T2, T3 and T4. The signal is active low and is tristated during ‗hold‘. It is low
during T1 for the first pulse of the interrupt acknowledge cycle.
Table 1 .2
BHE A0 Indications
0 0 Whole Word
0 1 Upper byte from or to odd
address
1 0 Lower byte from or to even
address
1 1 None

Bus High Enable/Status

 RD-Read Readsignal, when low, indicates the peripherals that the processor is performing a
memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read
cycle. The signal remains tristated during the ‗hold acknowledge‘.

READY This is the acknowledgement from the slow devices or memory that they have completed
the data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086. The signal is active high.

INTR- Interrupt Request This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by
resetting the interrupt enable flag. This signal is active highand internally synchronized.

TEST This input is examined by a ‗WAIT‘ instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is synchronized
internally during each clock cycle on leading edge of clock.

NMI-Non-maskable Interrupt This is an edge-triggered input which causes a Type2 interrupt.

The NMI is not maskable internally by software. A transition from low to high initiates the
interrupt response at the end of the current instruction. This input is internally synchronized.

RESET This input causes the processor to terminate the current activity and start execution
from FFFF0H. The signal is active high and must be active for at least four clock cycles. It
restarts execution when the RESET returns low. RESET is also internallysynchronised.

CLK-Clock Input The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency for
different 8086 versions is from 5MHz to 10MHz.

Vcc +5V power supply for the operation of the internal circuit.GND

ground for the internal circuit.

MN/ MX The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode.
The following pin functions are for the minimum mode operation of 8086.

M / I/O -Memory/IO This is a status line logically equivalent to S2 in maximum mode. When it is
low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation. This line becomes, active in the previous T4 and remains
active till final T4 of the current cycle. It is tristated during localbus ―hold acknowledge‖.

INTA -Interrupt Acknowledge This signal is used as a read strobe for interrupt acknowledge
cycles. In other words, when it goes low, it means that the processor has accepted the interrupt.
It is active low during T2, T3, and Tw of each interrupt acknowledge cycle.

ALE-Address Latch Enable This output signal indicates the availability of the valid address on
the address/data lines, and is connected to latch enable input of latches. This signal is active
high and is never tristated.

DT / R-Data Transmit/Receive This output is used to decide the direction of data flow through
the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high
and when the processor is receiving data, this signal is low. Logically, this is equivalent to S1 in
maximum mode. Its timing is the same as M/ I/O. This is tristated during ‗hold acknowledge‘.

DEN-Data Enable This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. DEN is
tristated during ‗hold acknowledge‘ cycle.

HOLD, HLDA-Hold /Hold Acknowledge When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access. The processor, after receiving the
HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock
cycle after completing the current bus (instruction) cycle. At the same time, the processor floats
the local bus and control lines. When the processor detects the HOLD line low, it lowers the
HLDA signal. HOLD is an asynchronous input, and it should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release
the local bus during T4 provided:
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or operating on an odd
address).
3. The current cycle is not the first acknowledge of an interrupt acknowledgesequence.
4. A Lock instruction is not being executed.

The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, S0 - Status Lines These are the status lines which reflect the type of operation, being
carried out by the processor. These become active during T4 of the previous cycle and remain
active during T1 and T2 of the current bus cycle. The status lines return to passive state during T3
of the current bus cycle so that they may again become active for the next bus cycle during T4.
Any change in these lines during T3 indicates the starting of a new cycle, and return to passive
state indicates end of the bus cycle. Thesestatus lines are encoded in Table 1.3.
Table 1 .3

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write memory
1 1 1 Passive
 This outputpin indicates thatother system busmasters will beprevented from the
system bus, while the LOCK signal is low. The LOCK signal is activated by the prefix
instruction and remains active until the completion of the next instruction. This floats to tri-state
off during ―hold acknowledge‖. When the CPU is executing a critical instruction which requires
the system bus, the LOCK prefix instruction ensures that other processors connected in the
system will not gain the control of the bus. The 8086, while executing the prefixed instruction,
asserts the bus lock signal output, which may be connected to an external bus controller.

QS1, QS0-Queue Status These lines give information about the status of the code prefetch
queue. These are active during the CLK cycle after which the queue operation is performed.
These are encoded as shown in Table 1.4.
Table 1 .4

QS1 QS2 Indication

0 0 No operation
0 1 First byte of Opcode from the
queue
1 0 Empty queue
1 1 Subsequent byte from the queue

This modification in a simple fetch and execute architecture of a conventional microprocessor

offers an added advantage of pipelined processing of the instructions. The 8086 architecture has
a 6-byte instruction prefetch queue. Thus even the largest (6- bytes) instruction can be prefetched
from the memory and stored in the prefetch queue. This results in a faster execution of the
instructions. In 8085, an instruction (opcode and operand) is fetched, decoded and executed and
only after the execution of this instruction, the next one is fetched. By prefetching the instruction,
there is a considerable speeding up in instruction execution in 8086. This scheme is known as
instruction pipelining.

At the starting the CS: IP is loaded with the required address from which the execution is At the
starting the CS: IP is loaded with the required address from which the execution is to be started.
Initially, the queue will be empty and the microprocessor starts a fetch operation to bring one
Assembly Language Programming (3IT07) Page 46
 byte (the first byte) of instruction code, if the CS: IP address is odd or two bytes at a time, if the
CS: IP address is even. The first byte is a complete opcode in case of some instructions (one byte
opcode instruction) and it is a part of opcode, in case of other instructions (two byte long opcode
instructions), the remaining part of opcode may lie in the second byte. But invariably the first
byte of an instruction is an opcode. These opcodes along with data are fetched and arranged in
the queue. When the first byte from the queue goes for decoding and interpretation, onebyte in the
queue becomes empty and subsequently the queue is updated. The microprocessor does not
perform the next fetch operation till at least two bytes of the instruction queue are emptied. The
instruction execution cycle is never broken for fetch operation. After decoding the first byte, the
decoding circuit decides whether the instruction is of single opcode byte or double opcode byte.
If it is single opcode byte, the next bytes are treated as data bytes depending upon the decoded
instruction length, otherwise, the next byte in the queue is treated as the second byte of the
instruction opcode. The second byte is then decoded in continuation with the first byte to decide
the instruction length and the number of subsequent bytes to be treated as instruction data. The
queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU
only if at least two bytes of the queue are empty and the EU may be concurrently executing the
fetched instructions.

Result : Hence we have studied minimum mode, maximum mode of 8088/8086

Date Signature Practical In-charge

Assembly Language Programming (3IT07) Page 47

13. Regular Assessment of Experiment during the practical session

Roll. Name 0f Student Total Viva Tota

No. Experiments Mark Mark l
s s (25)
(Grade A =2, Grade B = 1 Mark) (20) (05)

1 2 3 4 5 6 7 8 9 10

Date

Date: Signature
Practical In-charge

Assembly Language Programming (3IT07) Page 48