DSD TA

Submitted By Group 3

Name Roll Number

Mokshada Girdhar Daga 23
Muskan Asudani 24
Sanchi Joshi 27
Gunjan Kela 30
Harsh Taori 32

Problem Statement:- Implement a UART Receiver (Universal Asynchronous Receiver-Transmitter)

communication system between two FPGA boards. Demonstrate sending and receiving messages.

Introduction to UART
UART means Universal Asynchronous Receiver Transmitter Protocol. UART is used for serial communication from the name
itself we can understand the functions of UART, where U stands for Universal which means this protocol can be applied to any
transmitter and receiver, and A is for Asynchronous which means one cannot use clock signal for communication of data
and R and T refers to Receiver and Transmitter hence UART refers to a protocol in which serial data communication will
happen without clock signal.
UART is established for serial communication
UART is a Universal Asynchronous Receiver Transmitter protocol that is used for serial communication. Two wires are
established here in which only one wire is used for transmission whereas the second wire is used for reception. Data format
and transmission speeds can be configured here. So, before starting with the communication define the data format and
transmission speed. Data format and transmission speed for communication will be defined here and we do not have a clock
over here that’s why it is referred to as asynchronous communication with UART protocol.

Code:-
module uart_reciever(

input i_Clock,

input i_Rx_Serial,

output o_Rx_DV,

output [7:0] o_Rx_Byte

);

parameter CLKS_PER_BIT=30;

parameter s_IDLE = 3'b000;

parameter s_RX_START_BIT = 3'b001;

parameter s_RX_DATA_BITS = 3'b010;

parameter s_RX_STOP_BIT = 3'b011;

parameter s_CLEANUP = 3'b100;

reg r_Rx_Data_R = 1'b1;

reg r_Rx_Data = 1'b1;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total

reg [7:0] r_Rx_Byte = 0;

reg r_Rx_DV = 0;

reg [2:0] r_SM_Main = 0;

// Purpose: Double-register the incoming data.

// This allows it to be used in the UART RX Clock Domain.

// (It removes problems caused by metastability)

always @(posedge i_Clock)

begin

r_Rx_Data_R <= i_Rx_Serial;

r_Rx_Data <= r_Rx_Data_R;

end

// Purpose: Control RX state machine

always @(posedge i_Clock)

begin

case (r_SM_Main)
s_IDLE :

begin

r_Rx_DV <= 1'b0;

r_Clock_Count <= 0;

r_Bit_Index <= 0;

if (r_Rx_Data == 1'b0) // Start bit detected

r_SM_Main <= s_RX_START_BIT;

else

r_SM_Main <= s_IDLE;

end

// Check middle of start bit to make sure it's still low

s_RX_START_BIT :

begin

if (r_Clock_Count == (CLKS_PER_BIT-1)/2)

begin

if (r_Rx_Data == 1'b0)

begin
r_Clock_Count <= 0; // reset counter, found the middle

r_SM_Main <= s_RX_DATA_BITS;

end

else

r_SM_Main <= s_IDLE;

end

else

begin

r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= s_RX_START_BIT;

end

end // case: s_RX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles to sample serial data

s_RX_DATA_BITS :

begin

if (r_Clock_Count < CLKS_PER_BIT-1)

begin
r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= s_RX_DATA_BITS;

end

else

begin

r_Clock_Count <= 0;

r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;

// Check if we have received all bits

if (r_Bit_Index < 7)

begin

r_Bit_Index <= r_Bit_Index + 1;

r_SM_Main <= s_RX_DATA_BITS;

end

else

begin

r_Bit_Index <= 0;

r_SM_Main <= s_RX_STOP_BIT;

end
end

end // case: s_RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

s_RX_STOP_BIT :

begin

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)

begin

r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= s_RX_STOP_BIT;

end

else

begin

r_Rx_DV <= 1'b1;

r_Clock_Count <= 0;

r_SM_Main <= s_CLEANUP;

end

end // case: s_RX_STOP_BIT

// Stay here 1 clock

s_CLEANUP :

begin

r_SM_Main <= s_IDLE;

r_Rx_DV <= 1'b0;

end

default :

r_SM_Main <= s_IDLE;

endcase

end

assign o_Rx_DV = r_Rx_DV;

assign o_Rx_Byte = r_Rx_Byte;

endmodule // uart_rx

Explanation of the code

1. Module Declaration:

 uart_reciever is a module with clock input (i_Clock), serial input (i_Rx_Serial), and two outputs (o_Rx_DV and
o_Rx_Byte).

2. Parameters:

 CLKS_PER_BIT: Represents the number of clock cycles per bit.

 s_IDLE, s_RX_START_BIT, s_RX_DATA_BITS, s_RX_STOP_BIT, s_CLEANUP: These are states in a finite state
machine (FSM) for UART reception.

3. Registers:

 r_Rx_Data_R and r_Rx_Data: These registers double-register the incoming serial data to handle metastability
issues.

 r_Clock_Count: Counts the number of clock cycles.

 r_Bit_Index: Keeps track of the current bit being received (0 to 7 for 8 data bits).

 r_Rx_Byte: Holds the received byte.

 r_Rx_DV: Output register indicating whether the received data is valid.

4. Always Blocks:

 Double-registering Data:

 always @(posedge i_Clock): Triggered on the positive edge of the clock.

 r_Rx_Data_R is updated with the current value of i_Rx_Serial.

 r_Rx_Data is updated with the previous value of r_Rx_Data_R.

  State Machine:

 always @(posedge i_Clock): Triggered on the positive edge of the clock.

 Implements a finite state machine to control the reception process.

 s_IDLE (Idle State):

 Resets some registers and checks for the start bit. If start bit detected, transitions to
s_RX_START_BIT.

 s_RX_START_BIT (Start Bit Detection):

 Checks the middle of the start bit to ensure it's still low. If yes, transitions to s_RX_DATA_BITS;
otherwise, back to s_IDLE.

 s_RX_DATA_BITS (Receive Data Bits):

 Waits for CLKS_PER_BIT-1 clock cycles to sample serial data.

 Stores each bit in r_Rx_Byte.

 Transitions to the next bit or s_RX_STOP_BIT if all bits received.

 s_RX_STOP_BIT (Receive Stop Bit):

 Waits for CLKS_PER_BIT-1 clock cycles for the stop bit to finish.

 Sets r_Rx_DV to indicate valid data and transitions to s_CLEANUP.

 s_CLEANUP:

 Stays here for 1 clock cycle, then transitions back to s_IDLE and resets r_Rx_DV.

5. Assign Statements:
  assign o_Rx_DV = r_Rx_DV;: Connects the internal signal r_Rx_DV to the output signal o_Rx_DV.

 assign o_Rx_Byte = r_Rx_Byte;: Connects the internal signal r_Rx_Byte to the output bus o_Rx_Byte.

In summary, this module implements a UART receiver using a finite state machine. It synchronizes with the incoming serial data,
detects the start bit, receives data bits, checks the stop bit, and outputs the received byte when valid.

Code Output:-

The code is designed to receive serial data and output a valid byte (o_Rx_Byte) along with a data valid signal (o_Rx_DV). The
output signals will reflect the received data when a valid byte has been successfully received. Let's break down the expected
behavior:

 o_Rx_DV (Data Valid Signal):

 It will be asserted (1) when a complete byte has been received, including start and stop bits.

 It will be deasserted (0) at all other times.

 o_Rx_Byte (Received Byte):

 It will hold the received 8-bit data when o_Rx_DV is asserted.

 It should be considered valid only when o_Rx_DV is asserted.

The actual output values for o_Rx_DV and o_Rx_Byte will depend on the serial data input (i_Rx_Serial) and the configuration of
the UART sender. If the received data follows the UART protocol with correct start and stop bits, the module will recognize the
byte and assert o_Rx_DV with the valid byte present in o_Rx_Byte. Otherwise, o_Rx_DV will remain deasserted, and o_Rx_Byte
should not be considered valid.

Please note that the behavior also depends on the clock signal (i_Clock) and the configuration of CLKS_PER_BIT. If the clock
frequency and CLKS_PER_BIT are properly set for the baud rate of the incoming serial data, the module should be able to
correctly receive and interpret the data.