DIGITAL SYSTEM FUNDAMENTALS (ECE421)

COURSE / CODE
DIGITAL ELECTRONICS FUNDAMENTAL (ECE422)

COUNTERS

One common requirement in digital circuits is counting, both forward and backward. Digital clocks and
watches are everywhere, timers are found in a range of appliances from microwave ovens to VCRs,
and counters for other reasons are found in everything from automobiles to test equipment. Although
there many variations on the basic counter, they are all fundamentally very similar.
Counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide
variety of designs exist:

1. Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state
flip-flops
2. Synchronous counter – all state bits change under control of a single clock
3. Decade counter – counts through ten states per stage
4. Up–down counter – counts both up and down, under command of a control input
5. Ring counter – formed by a shift register with feedback connection in a ring
6. Johnson counter – a twisted ring counter
7. Cascaded counter

Each is useful for different applications. Usually, counter circuits are digital in nature, and count in
binary, or sometimes binary coded decimal (BCD). Many types of counter circuit are available as
digital building blocks, for example a number of chips in the 4000 series implement different counters.

Asynchronous Counters
This type of counter
produces a prescribed
sequence of states upon the
application of clock pulses.
The clock pulse triggers the
first flip-flop, and the output
of the next flip-flop is used
to trigger the next flip-flop,
and so on.

There is not much of design steps required, since the flip-flops are all in the toggle mode, that is, J = K
= ‘1’.
Shown below is a two-bit asynchronous binary counter. For the flip-flops, the SET and CLR inputs are
set to ‘0’ and the flip flops are using negative edge trigger clock.

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Exercises:
a) What would be the counting sequence if the output is taken from the Q output?
b) What would be the counting sequence (Q1Q0) if the clock for the second flip-flop is taken from
the Q output?

Shown below is a three-bit asynchronous binary counter. For the flip-flops, the SET and CLR inputs
are set to ‘0’ and the flip flops are using positive edge trigger clock.

Exercise 1: What would be the count if the output is taken from the Q output?

Exercise 2:
a) Design an asynchronous counter using JK flip-flop that count up 0-1-2-3-4-5-6-7.
b) Design an asynchronous counter using T flip-flop that count down 7-6-5-4-3-2-1-0.
c) Design an asynchronous counter using D flip-flop that count up 0-1-2-3-4-5-6-7.

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Exercise 3: For the following asynchronous counters, determine the count sequence.

Exercise 3: What is the count if the JK flip-flops is negative edge triggered? What is the count if the JK
flip-flops is positive edge triggered?

Exercises:
a) Design an asynchronous counter that counts 0-1-2-3-4-5 continuously. Draw the circuit
diagram using T flip-flops and show its timing diagram.
b) Design an asynchronous counter that counts 5-4-3-2-1-0 continuously. Draw the circuit
diagram using D flip-flops and show its timing diagram.

BCD or Decade Counter

A BCD counter or decade counter can be constructed from a straight asynchronous binary counter by
terminating the "ripple-through" counting when the count reaches decimal 9 (binary 1001). Since the
next toggle would set the two most significant bits, a NAND gate tied from those two outputs to the
asynchronous clear line will start the count over after 9.

Observe that the JK inputs are set to ‘1’ (HIGH), which means the flip-flops are in toggle mode.

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Note: If the CLR and SET is an active HIGH inputs, then the gate used will be a AND gate.

Exercise:
Why are asynchronous counters are called ripple counters?

Disadvantages of Asynchronous Counters:

 An extra “re-synchronizing” output flip-flop may be required.
 To count a truncated sequence not equal to 2n, extra feedback logic is required.
 Counting a large number of bits, propagation delay by successive stages may become undesirably
large. This delay gives them the nickname of “Propagation Counters”.
 Counting errors occur at high clocking frequencies.
 Synchronous Counters are faster and more reliable as they use the same clock signal for all flip-
flops.

Synchronous Counters
The output bit of the counter change state simultaneously, with no ripple. The design is such that the
clock inputs for all the flip-flops are connected together, so that each and every flip-flop receives the
exact same clock pulse at the exact same time.

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Now, the question is, what need to be done with the J and K inputs if the output is to be counting in a
certain sequence?

Design procedures of Synchronous Counters

Example: To design a synchronous counter that counts 1,2,3,5,7, …

1. Problem specifications 1 2
Highest count = 7, meaning requires 3 flip flops (7 = 1112)
Call it flip-flop A, B, C. 3
7
2. Draw the State Diagram. The arrow indicates a clock pulse and the
5
counter changes state.

3. Construct the State Table. The unused states can be assigned as don’t care (x means don’t care
state) or any state in the sequence.

Present Present
Next State Next State
State State
Count ABC Count ABC
0 000 x x
1 001 2 010
2 010 3 011
3 011 5 101
4 100 x x
5 101 7 111
6 110 x x
7 111 1 001

The unused states 0, 4 and 6 since it is not in the counting sequence is assigned as ‘don’t care’.

4. Flip-Flop Excitation Table (Textbook Method)

Requires the flip-flop excitation map, in this case the JK flip-flop.

Present State Next State

JA KA JB KB JC KC
ABC ABC
000 x x x x x x x
001 010 0 x 1 x x 1
010 011 0 x x 0 1 x
011 101 1 x x 1 x 0
100 x x x x x x x
101 111 x 0 1 x x 0
110 x x x x x x x
111 001 x 1 x 1 x 0

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5. Flip-flop excitation maps.
Since the flip-flop has two inputs J and K, separate map is drawn for each input.

AB AB
C 00 01 11 10 C 00 01 11 10
0 x 0 x x 0 x x x x
1 0 1 x x 1 x x 1 0

JA=BC KA=B
AB AB
C 00 01 11 10 C 00 01 11 10
0 x x x x 0 x 0 x x
1 1 x x 1 1 x 1 1 x

JB=1 KB=C
AB AB
C 00 01 11 10 C 00 01 11 10
0 x 1 x x 0 x x x x
1 x x x x 1 1 0 0 0

JC=1 KC= AB

6. Implementation of the
counter using JK flip-flops.
Complete the circuit.

Note: The textbook method is tedious and may cause errors during the preparation of the excitation
table, also the desired flip-flop excitation map must be available during the process for reference. The
flip-flop excitation maps also are then drawn for both inputs separately (for JK and SR flip-flops),
adding to the complexity. If the same counter is to be implemented with a different flip-flop, say D
flip-flop, the whole process is repeated using D flip-flop excitation map.

The Universal Map Method

This method will simplify the process of designing a counter. It is simpler,
almost error free, requires only one flip-flop excitation and can be used for
all flip-flops without the need to repeat the process.

1. Excitation Map
Make similar maps as K-map, one for each state. Then fill up for
each state according to the following symbols, there is no need for
the flip-flop excitation map.

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 Present State Next State FLIP- FLIP- FLIP-
ABC ABC FLOP A FLOP B FLOP C

000 x x x x
001 010 0 α β
010 011 0 1 α
011 101 α β 1
100 x x x x
101 111 1 α 1
110 x x x x
111 001 β β 1

AB AB AB
C 00 01 11 10 C 00 01 11 10 C 00 01 11 10
0 x 0 x x 0 x 1 x x 0 x α x x
1 0 α β 1 1 α β β α 1 β 1 1 1

Flip-flop A Flip-flop B Flip-flop C

2. Flip-Flop input expressions (Flip-flops excitations)
The rule for reading the input expressions for the JK flip flop is as follows:
For J input: must read all α, optional read β, 1, x, but must not read 0.
For K input: must read all β, optional read α, 0, x, but must not read 1.
Thus, giving:
JA=BC JB=1 JC=1
KA=B KB=C KC= AB

If the counter is to be redesigned using D flip-flop, there is no need to draw the excitation map again.
Use the same excitation map in step 4, and the input excitation for the D flip-flops can be found using
the following rules. This is the main advantage of using the Universal map method as compared to the
textbook method.

For example, to implement the counter using D flip-flops, then by referring to the flip-flop excitation
map above and following the rules for D flip-flop:
DA= ABC  AB DB= B  C DC= A  B

Exercise 1: Determine the flip flop excitation for the counter if T flip flops were used.

Exercise 2:
a) Design a synchronous counter that counts 0-1-2-3-4-5-6-7 continuously using JK flip-flops.
Draw the circuit diagram.

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 b) Design a synchronous counter that counts 7-6-5-4-3-2-1-0 continuously using T flip-flops. Draw
the circuit diagram.

Exercise 3:
a) Design a synchronous counter that counts 1-5-2-6-0 continuously using D flip-flops. Draw the
circuit diagram. The unused states is taken as ‘don’t care’.
b) Design a synchronous counter that counts 1-5-2-6-0 continuously using JK flip-flops. Draw the
circuit diagram. The unused must jump to state 0.

Exercise 4:
Verify that the synchronous counter below is a 3 bit up counter as shown by the timing diagram.

Exercise 5:
What does the following circuit do? Determine its output.

Up-Down Counters
Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but
there is another more “Universal” type of counter that can count in both directions either Up or Down
depending on the state of their input control pin and these are known as Bidirectional Counters.
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Bidirectional counters, also known as Up/Down counters, are capable of counting in either direction
through any given count sequence and they can be reversed at any point within their count sequence
by using an additional control input as shown below.
The design of the up-down counter is the same as the design of universal synchronous counter as
shown above except that there is now an input to the counter which controls the counting sequence.

PRESENT NEXT
UP/*DOWN QA QB QC QA QB QC
1 0 0 0 0 0 1
1 0 0 1 0 1 0
1 0 1 0 0 1 1
1 0 1 1 1 0 0
1 1 0 0 1 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1
1 1 1 1 0 0 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 1 0 0
0 1 1 0 1 0 1
0 1 1 1 1 1 0

Exercise 1: Show the design of the 3 bit up-down counter above using Universal Map method.

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used for the storage or the
transfer of data in the form of binary numbers.
This sequential device loads the data present on its inputs and then moves or “shifts” it to its output
once every clock cycle, hence the name Shift Register.

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A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit,
either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the
output from one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either the left
or the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is usually
determined by the number of bits to be stored with the most common being 8-bits (one byte) wide
constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore commonly used
inside calculators or computers to store data such as two binary numbers before they are added
together, or to convert the data from either a serial to parallel or parallel to serial format. The
individual data latches that make up a single shift register are all driven by a common clock ( Clk )
signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or
“RESET” as required. Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:
 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit
at a time in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.
 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register,
and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a
shift register can be presented graphically as:
Also, the directional movement of the data through a shift
register can be either to the left, (left shifting) to the right,
(right shifting) left-in but right-out, (rotation) or both left
and right shifting within the same register thereby making
it bidirectional. In this tutorial it is assumed that all the data
shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift

Register

4-bit Serial-in to Parallel-out Shift

Register
The operation is as follows. Let’s assume
that all the flip-flops ( FFA to FFD ) have
just been RESET ( CLEAR input ) and
that all the outputs QA to QD are at logic
level “0” i.e., no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still
remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again
to logic “0” giving us one data pulse or 0-1-0.
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The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH
to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been
“shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC (QC) and so on until
the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0”
because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this
is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This
data value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The truth
table and following waveforms show the propagation of the logic “1” through the register from left to
right as follows.

Basic Data Movement Through a Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1) are stored in the register
and will remain there provided clocking of the register has stopped. In practice the input data to the
register may consist of various combinations of logic “1” and “0”. Commonly available SIPO IC’s
include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read directly in a
parallel form from the outputs QA to QD, this time the data is allowed to flow straight through the
register and out of the other end. Since there is only one output, the DATA leaves the shift register one
bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three connections,
the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which
is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic
circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what’s the point of a SISO
shift register if the output data is exactly
the same as the input data. Well this type
of Shift Register also acts as a temporary
storage device or it can act as a time delay
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device for the data, with the amount of time delay being controlled by the number of stages in the
register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC’s include
the 74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one
above. The data is loaded into the register in a parallel format in which all the data bits enter their
inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out
sequentially in the normal shift-right mode from the register at Q representing the data present
at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note
that with this type of data register a clock pulse is not required to parallel load the register as it is
already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register
converts parallel data, such as an 8-
bit data word into serial format, it
can be used to multiplex many
different input lines into a single
serial DATA stream which can be
sent directly to a computer or
transmitted over a communications
line. Commonly available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift register
also acts as a temporary storage device or as a time delay device similar to the SISO configuration
above. The data is presented in a parallel format to the parallel input pins PA to PD and then
transferred together directly to their respective output pins QA to QA by the same clock pulse. Then
one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is
shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four
configurations as it has only three connections, the
parallel input (PI) which determines what enters
the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register,
this type of register also acts as a temporary
storage device or as a time delay device, with the
amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of
register there are no interconnections between the individual flip-flops since no serial shifting of the
data is required.

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Universal Shift Register
Today, there are many high speed bi-directional “universal” type Shift Registers available such as the
TTL 74LS194, 74LS195 or the CMOS
4035 which are available as 4-bit
multi-function devices that can be
used in either serial-to-serial, left
shifting, right shifting, serial-to-
parallel, parallel-to-serial, or as a
parallel-to-parallel multifunction
data register, hence the name
“Universal”.
These universal shift registers can
perform any combination of parallel
and serial input to output
operations but require additional
inputs to specify desired function and to pre-load and reset the device.
A commonly used universal shift register is the TTL 74LS194 as shown below.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory storage or for the delay of information such
as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or
parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to
the left or right for multiplication or division.

Ring Counters

In the previous shift register discussion above, we saw that if

we apply a serial data signal to the input of a Serial-in to Serial-
out Shift Register, the same sequence of data will exit from the
last flip flop in the register chain.
This serial movement of data through the resister occurs after a
preset number of clock cycles thereby allowing the SISO register
to act as a sort of time delay circuit to the original input data signal.
But what if we were to connect the output of this shift register back to its input so that the output from
the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop
circuit that “recirculates” the same bit of DATA around a continuous loop for every state of its
sequence, and this is the principal operation of a Ring Counter.
Then by looping the output back to the input, (feedback) we can convert a standard shift register
circuit into a ring counter. Consider the circuit below.

4-bit Ring Counter

The synchronous Ring Counter example above, is pre-set so that exactly one data bit in the register is
set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly applied
to all the flip-flops together in order to “RESET” their outputs to a logic “0” level and then a
“PRESET” pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are applied.
This then places a single logic “1” value into the circuit of the ring counter.

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So on each successive clock pulse, the counter
circulates the same data bit between the four
flip-flops over and over again around the “ring”
every fourth clock cycle. But in order to cycle the
data correctly around the counter we must first
“load” the counter with a suitable data pattern as
all logic “0’s” or all logic “1’s” outputted at each
clock cycle would make the ring counter invalid.
This type of data movement is called “rotation”,
and like the previous shift register, the effect of
the movement of the data bit from left to right through a ring counter can be presented graphically as
follows along with its timing diagram:

Rotational Movement of a Ring Counter

Since the ring counter example shown above has four distinct states, it is also known as a “modulo-4”
or “mod-4” counter with each flip-flop output having a frequency value equal to one-fourth or a
quarter (1/4) that of the main clock frequency.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences
through before repeating itself and a ring counter can be made to output any modulo number. A
“mod-n” ring counter will require “n” number of flip-flops connected together to circulate a single
data bit providing “n” different output states.
For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require
sixteen flip-flops. However, as in our example above, only four of the possible sixteen states are used,
making ring counters very inefficient in terms of their output state usage.

Johnson Ring Counter

The Johnson Ring Counter or “Twisted Ring
Counters”, is another shift register with
feedback exactly the same as the
standard Ring Counter above, except that this
time the inverted output Q of the last flip-flop
is now connected back to the input D of the
first flip-flop as shown below.
The main advantage of this type of ring
counter is that it only needs half the number
of flip-flops compared to the standard ring
counter then its modulo number is halved. So

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a “n-stage” Johnson counter will circulate a single data bit giving sequence of 2n different states and
can therefore be considered as a “mod-2n counter”.

4-bit Johnson Ring Counter

This inversion of Q before it is fed back to input D causes the counter to “count” in a different way.
Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit
counter, “0001”(1), “0010”(2), “0100”(4), “1000”(8) and repeat, the Johnson counter counts up and then
down as the initial logic “1” passes through it to the right replacing the preceding logic “0”.
A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1” thereby producing
an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern continually
repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”, “0001”, “0000” and this is
demonstrated in the following table below.

Truth Table for a 4-bit Johnson Ring Counter

As well as counting or rotating data around a

continuous loop, ring counters can also be used to
detect or recognize various patterns or number values
within a set of data. By connecting simple logic gates
such as the AND or the OR gates to the outputs of the
flip-flops the circuit can be made to detect a set number
or value.
Standard 2, 3 or 4-stage Johnson Ring Counters can
also be used to divide the frequency of the clock signal
by varying their feedback connections and divide-by-3 or divide-by-5 outputs are also available.
For example, a 3-stage Johnson Ring Counter could be used as a 3-phase, 120 degree phase shift
square wave generator by connecting to the data outputs at A, Band NOT-B.
The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used as a
synchronous decade counter/divider circuit.
Other combinations such as the smaller 2-stage circuit which is also called a “Quadrature”
(sine/cosine) Oscillator or Generator can be used to produce four individual outputs that are each 90
degrees “out-of-phase” with respect to each other to produce a 4-phase timing signal as shown below.

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2-bit Quadrature Generator

As the four outputs, A to D are phase shifted by 90

degrees with regards to each other, they can be used
with additional circuitry, to drive a 2-phase full-step
stepper motor for position control or the ability to
rotate a motor to a particular location as shown
below.

Stepper Motor Control

2-phase (unipolar) Full-Step Stepper Motor

Circuit

The speed of rotation of the Stepper Motor will

depend mainly upon the clock frequency and
additional circuitry would be require to drive
the “power” requirements of the motor.

Cascaded Counters
Just as parallel combinational logic devices can be expanded to create a wider parallel device, counters
can be cascaded to create counters with higher moduli, or ranges of count values. How counters are
cascaded depends upon the basic counter type.

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Asynchronous Cascaded Counters
Because all but the first flip-flop in an asynchronous counter uses an output of the preceding counter
as its clock, you can cascade asynchronous counters by simply connecting the MSB output of one
counter to the clock of the next. In effect, this is how you create a 4-bit counter with the 74LS93. If the
counter you wish to cascade has N bits and the added counter has M bits, the new counter will have
(N + M) bits and a maximum count of 2N+M.

Synchronous Cascaded Counters

Cascading a synchronous counter requires more care than cascading an asynchronous counter. The
counter being added to the existing counter circuit shares the same clock line but must increment its
count ONLY when the preceding counter “rolls over” from its terminal count back to 0. Most IC
counters like the 74HC163 have a terminal or maximum count signal to enable the next counter, but if
this is not the case, the cascaded counter design must include the decoding logic to provide one.

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