Date: 25-09-2023

Experiment – 6

Objective:
To write a VHDL program to implement Up Counter
Resources Required:
Hardware Requirement: Computer System
Software Requirement: XILINX ISE Design Suite 14.7 Software
Evaluation Board: Spartan 3AN starter kit
Device: XC3S700N
Theory:
A counter is a device which stores (and sometimes displays) the number of times
a particular event or process has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting purpose, they can
count specific event happening in the circuit. For example, in UP counter a
counter increases count for every rising edge of clock. Not only counting, a
counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also be designed with the help of flip flops. They
are used as frequency dividers where the frequency of given pulse waveform is
divided. Counters are sequential circuit that count the number of pulses can be
either in binary code or BCD form. The main properties of a counter are timing
, sequencing , and counting. Counter works in two modes: Up counter and
Down counter. Counters are sequential logic devices that follow a predetermined
sequence of counting states which are triggered by an external clock (CLK)
signal. The number of states or counting sequences through which a particular
counter advances before returning once again back to its original first state is
called the modulus (MOD). In other words, the modulus (or just modulo) is the
number of states the counter counts and is the dividing number of the counter.
The decade counter has four outputs producing a 4-bit binary number, it receives
an input clock pulse, one by one, and counts up from 0 to 9 repeatedly.

Application:
1. Digital Clocks: Up counters are widely used in digital clock circuits to keep
track of time. With each clock pulse, the counter increments, allowing it to
generate the time in hours, minutes, and seconds.
2.Traffic Light Controllers: Up counters are employed in traffic light control
systems to sequence the timing of traffic lights. Each count corresponds to a
specific state in the traffic light sequence, helping regulate traffic flow..
Truth Table:

VHDL Code:
Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Upcounter_114 is
Port ( clk : in STD_LOGIC;
C : inout integer:=0);
end Upcounter_114;
architecture Behavioral of Upcounter_114 is
begin
process (clk)
begin
if(clk'event and clk='1')
then if (C<=C+1; else if(c=9)
then c<=0;
end if;
end if;
end if;
end process;
end Behavioral;
Output and Observation:

Fig:6.1 RTL Schematic of 4-bit UpCounter

Fig:6.2 Circuit Diagram of 4-bit UpCounter

Fig:6.3 Internal Logic gate circuit diagram of 4-bit UpCounter.
 Fig:6.4 Behavioral Simulation Result at time period 1-microsecond and
frequency 1-MHz. The output result is satisfying the truth table. No time
delay is observed in this case.

Fig:6.5 Post Route Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. Time delay
of 10.13ns is observed in this case.
 Fig:6.6 Timing Details of 4-bit UpCounter

Results:
VHDL codes of 4-bit UpCounter has been implemented and simulated
successfully. Resulting output is satisfying the truth table of 4-bit up Counter.
Observed time delay is 4.7ns from timing details and 10.13ns from post route
simulation.
Date: 9-10-2023
Experiment – 7

Objective:
Write a VHDL Program to generate the 1010 sequence detector. The
overlapping patterns are allowed.
Resources Required:
Hardware Requirement: Computer System
Software Requirement: XILINX ISE Design Suite 14.7 Software
Evaluation Board: Spartan 3AN starter kit
Device: XC3S700N
Theory:
A sequence detector is a digital circuit or algorithm designed to identify the
presence or absence of a specific sequence of binary bits in a stream of input
data. It is commonly used in digital signal processing, communication systems,
and control systems. The sequence detector monitors the input stream and
produces an output when the specified sequence is detected. There are two
primary types of sequence detectors: synchronous and asynchronous.
Synchronous Sequence Detector:
In a synchronous sequence detector, the detection process is synchronized with
a clock signal. The input stream is sampled at specific clock intervals, and the
detection logic operates based on these clocked samples. The most common type
of synchronous sequence detector is the Finite State Machine (FSM), which uses
a set of states and transitions to recognize sequences.
Asynchronous Sequence Detector:
An asynchronous sequence detector, on the other hand, doesn't rely on a clock
signal for sampling. It continuously monitors the input and triggers the detection
logic whenever the specified sequence is identified. Asynchronous detectors are
often simpler than synchronous ones but may be more susceptible to noise and
timing variations.
 Fig:7.1 Schematic of a clocked synchronous state machine (Moore
Machine).
A sequential circuit’s behavior can be shown in a state diagram. The state diagram
for our sequence detector is shown below. Each circle represents a state and the
arrows show the transitions to the next state. Inside each circle are the state name
and the value of the output. Along each arrow is the input value that corresponds
to that transition. A sequence detector accepts as input a string of bits: either 0 or
1. Its output goes to 1 when a target sequence has been detected. There are two
basic types: overlap and non-overlap. In a sequence detector that allows overlap,
the final bits of one sequence can be the start of another sequence.
Example: 11011 detector with overlap X 11011011011 Z 00001001001
11011 detector with no overlap Z 00001000001

Fig:7.2 Sequence Detector state diagram.

Applications: 1. Communication Systems: Sequence detectors are used in
communication systems to identify specific patterns or sequences intransmitted
data. For example, in data communication protocols, a sequence detector may
be employed to recognize the start or end of a message.

2.Error Detection and Correction: In digital systems, sequence detectors can

be used for error detection and correction. By detecting predefined patterns, the
system can identify and correct errors in the transmitted data.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity seq_det is
port( clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic );
end seq_det;
architecture Behavioral of seq_det is
type state_type is (s0,s1,s2,s3);
signal state : state_type := s0;
begin
process(clk, reset)
begin if( reset = '1' )
then output <= '0';
state <= s0;
elsif ( clk' event and clk='1' ) then
when s0 =>
output <= '0';
if ( input = '0' ) then state <= s0;
else state <= s1;
end if;
when s1 => if ( input = '0' ) then state <= s2;
output<='0';
else state <= s1;
output<='0';
end if;
when s2 => if ( input = '0' ) then state <= s0;
output<='0';
else state <= s3;
output<='0';
end if;
when s3 => output<='1';
if ( input = '0' ) then state <= s1;
else state <= s2;
output <= '1';
end if;
when others => NULL;
end case;
end if;
end process;
end Behavioral;
Output and Observation:

Fig:7.3 RTL Schematic of Sequence-Detector

 Fig:7.4 Circuit Diagram of Sequence-Detector

Fig:7.5 Internal Logic gate circuit diagram of Sequence-Detector.

 Fig:7.6 Behavioral Simulation Result at time period 1-microsecond and
frequency 1-MHz. The output result is satisfying the truth table. No time
delay is observed in this case.

Fig:7.7 Post Route Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. Time delay
of 10.42ns is observed in this case.
 Fig:7.8 Timing Details of Sequence-Detector

Results:
VHDL codes of Sequence-Detector has been implemented and simulated
successfully. Resulting output is satisfying the truth table of Sequence-Detector.
Observed time delay is 4.677ns from timing details and 10.42ns from post route
simulation.
Date: 16-10-2023
Experiment – 8

Objective:
Write a VHDL code to implement serial to parallel of 4 bit binary number.
Resources Required:
Hardware Requirement: Computer System
Software Requirement: XILINX ISE Design Suite 14.7 Software
Evaluation Board: Spartan 3AN starter kit
Device: XC3S700N
Theory:
Serial-to-parallel conversion is a process in digital electronics where a series of
bits are converted from a serial (one bit at a time) format to a parallel (multiple
bits at a time) format. To convert a 4-bit number from serial to parallel, you
typically need a shift register. Here's a basic explanation of the process:
Serial-to-Parallel Conversion of a 4-Bit Number:
Process:
1. Serial Input:The 4-bit serial input is fed into the first bit of the shift register.
2. Shift Operation:
- On each clock pulse, the contents of the shift register are shifted to the right.
- The serial input bit is loaded into the leftmost (most significant) bit of the
shift register.
3. Shift Cycle:
- After four clock pulses, all four bits of the serial input will be loaded into the
shift register.
4. Parallel Output:
- At this point, the parallel output is available at the four output taps of the
shift register.
- The bits at each output tap represent the 4-bit parallel representation of the
serial input.
Example:
Let's say we have the 4-bit serial input "1101". The process would be as follows:
- Clock 1: Shift register = "0111" (shifted right, new bit loaded at the left).
- Clock 2: Shift register = "1011".
- Clock 3: Shift register = "1101".
- Clock 4: Shift register = "1110".
After four clock pulses, the 4-bit parallel output is "1110".
- The speed of the clock pulses determines the rate at which the serial bits are
loaded into the shift register.
- The shift register needs to be designed for serial-to-parallel conversion, with
the appropriate clock and control signals.
This process is commonly used in various applications, including serial
communication protocols, where data is transmitted serially but needs to be
processed in parallel by the receiving device.ns.

Fig:8.1 4-bit Serial-in to Parallel-out Shift Register

Fig:8.2 Basic Data Movement Through A Shift Register:

Applications: 1. Data Communication Interfaces: Serial-to-parallel
conversion is crucial in communication protocols such as RS-232 and USB,
allowing data received serially to be processed in parallel, facilitating efficient
communication between devices.
2. Memory Systems and Microcontroller Interfaces: In computer systems,
serial-to-parallel conversion is used to interface with memory systems, enabling
the parallel transfer of data. It is also employed in microcontroller applications
for efficient handling of serially transmitted data from sensors or external
devices.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo_114 is
port( y:inout std_logic_vector( 3 downto 0);
x: in std_logic;
clr:in std_logic; clk:in std_logic);
end sipo_114;
architecture Behavioral of sipo_114 is
begin
process(clk)
begin
if(clr='1')
then y<="0000";
elsif(clk'event and clk='1')
then y(3)<=x;
y(2)<=y(3);
y(1)<=y(2);
y(0)<=y(1);
end if;
end process;
end Behavioral;
Output and Observation:

Fig:8.3 RTL Schematic of Serial-to-parallel of 4 bit binary number

Fig:8.4 Circuit Diagram of Serial-to-parallel of 4 bit binary number

 Fig:8.5 Behavioral Simulation Result at time period 1-microsecond and
frequency 1-MHz. The output result is satisfying the truth table. No time
delay is observed in this case.

Fig:8.6 Post Route Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. Time delay
of 8.736ns is observed in this case.
 Fig:8.7 Timing Details of 4-bit serial-to-parallel-converter

Results:
VHDL codes of 4-bit serial-to-parallel-converter has been implemented and
simulated successfully. Resulting output is satisfying the truth table of 4-bit
serial-to-parallel-converter. Observed time delay is 5.558ns from timing details
and 8.736ns from post route simulation.
Date: 23-10-2023
Experiment – 9

Objective:
Write a VHDL program to perform parallel to serial transfer of 4 bit binary
number.
Resources Required:
Hardware Requirement: Computer System
Software Requirement: XILINX ISE Design Suite 14.7 Software
Evaluation Board: Spartan 3AN starter kit
Device: XC3S700N
Theory:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/
serial-out shift registers do plus input data to all stages simultaneously. The
parallel-in/ serial-out shift register stores data, shifts it on a clock by clock basis,
and delays it by the number of stages times the clock period. In addition, parallel-
in/ serial-out really means that we can load data in parallel into all stages before
any shifting ever begins. This is a way to convert data from a parallel format to a
serial format. By parallel format we mean that the data bits are present
simultaneously on individual wires, one for each data bit as shown below. By
serial format we mean that the data bits are presented sequentially in time on a
single wire or circuit as in the case of the “data out” on the block diagram below.

Fig:9.1 Parallel-in-serial-out shift registers with 4 stages.

Applications: 1.Bit serial operations can be performed quickly through device

iteration
2. Iteration (a purely combinational approach) is expensive (in terms of # of
transistors, chip area, power, etc).
3. A sequential approach allows the reuse of combinational functional units
throughout the multi-cycle operation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity piso_114 is
port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC );
end piso_114;
architecture piso_arc of piso_114 is
begin
piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then temp := (others=>'0');
elsif (load='1') then temp := din ;
elsif (rising_edge (clk)) then dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;
end piso_arc;
Output and Observation:

Fig:9.2 RTL Schematic of Parallel-in-serial-out shift registers

Fig:9.3 Circuit Diagram of Parallel-in-serial-out shift registers

 Fig:9.4 Internal Logic gate circuit diagram of Parallel-in-serial-out shift
registers.

Fig:9.5 Behavioral Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. No time
delay is observed in this case.

Fig:9.6 Post Route Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. Time delay
of 7.873ns is observed in this case.
 Fig:9.7 Timing Details of 4-bit serial-to-parallel-converter

Results:
VHDL codes of parallel to serial transfer of 4 bit binary number has been
implemented and simulated successfully. Resulting output is satisfying the truth
table of parallel to serial transfer of 4 bit binary number. Observed time delay is
5.531ns from timing details and 7.873ns from post route simulation.
Date: 5-11-2023
Experiment – 10

Objective:
Write a program to design a 2 bit ALU containing 4 arithmetic & 4 logic
operations.
Resources Required:
Hardware Requirement: Computer System
Software Requirement: XILINX ISE Design Suite 14.7 Software
Evaluation Board: Spartan 3AN starter kit
Device: XC3S700N
Theory:
The Arithmetic Logic Unit (ALU) is a crucial component within a computer's
central processing unit (CPU) responsible for executing arithmetic and logic
operations on binary data. It performs fundamental operations like addition,
subtraction, multiplication, division, and logical comparisons. The ALU operates
based on control signals from the CPU, directing it to execute specific tasks.
Applications:
1.Data Processing: The ALU is at the core of data processing in computers,
handling numerical calculations and logical operations necessary for executing
programs.
2.Cryptography: ALUs are used in cryptographic algorithms to perform
complex mathematical operations required for secure communication,
encryption, and decryption.
3.Graphics Processing: In graphics processing units (GPUs), specialized ALUs
handle parallel processing tasks related to rendering and manipulating graphical
images and video.
4.Scientific Computing: ALUs are crucial in scientific simulations and
calculations, where intricate mathematical operations are required for modeling
physical phenomena, conducting simulations, and analyzing data.
VHDL Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

en ty ALU_114 is

port( inputA,inputB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

output:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0) );

end ALU_114;

architecture alu_114 of ALU_114 is

begin

PROCESS(inputA,inputB,sel)

BEGIN

case sel is

when "000" => output<=inputA+inputB;

when "001" => output<=inputA-inputB;

when "010" => output<=inputA-1;

when "011" => output<=inputA+1;

when "100" => output<=inputA and inputB;

when "101" => output<=inputA or inputB;

when "110" => output<=not inputA;

when "111" => output<=inputA xor inputB;

when others => output<=NULL;

end case;

END PROCESS;

end alu_114;
Output and Observation:

Fig:10.1 RTL Schematic of ALU

Fig:10.2 Circuit Diagram of ALU

 Fig:10.3 Internal Logic gate circuit diagram of ALU.

Fig:10.4 Behavioral Simulation Result at time period 1-microsecond and

frequency 1-MHz. The output result is satisfying the truth table. No time
delay is observed in this case.
Fig:10.5 Post Route Simulation Result at time period 1-microsecond and
frequency 1-MHz. The output result is satisfying the truth table. Time delay
of 7.873ns is observed in this case.

Fig:10.6 Timing Details of ALU

Results:
VHDL codes of ALU has been implemented and simulated successfully.
Resulting output is satisfying the truth table of different operations of ALU.
Observed time delay is 11.303ns from timing details and 8.68ns from post route
simulation.
 HARDWARE DESCRIPTION LAB FILE
SUBJECT-CODE: ECLR 71

SUBMITTED BY: SUBMITTED TO:

Sameer Khan DR. TRAILOKYA
12015114 NATH SASAMAL
ECA2 ASSISTANT PROFESSOR
7th SEMESTER

ELECTRONICS AND COMMUNICATION

ENGINEERING DEPARTMENT, NIT
KURUKSHETRA
 INDEX

Serial Aim Date Remarks

No:
1 Write a VHDL program to implement 3:8 decoder. 7-08-2023

2 Write a VHDL program to implement 8:1 14-08-2023

multiplexerusing behavioral modeling.
3 Write a VHDL program to implement a 1:8 14-08-2023
Demultiplexer using behavioural modelling.
4 Write VHDL program to implement 4 bit 21-08-2023
addition/subtraction
5 Write a program to implement 4- bit Comparator. 28-08-2023
6 To write a VHDL program to implement Up 25-09-2023
Counter.
7 Write a VHDL Program to generate the 1010 9-10-2023
sequence detector. The overlapping patterns are
allowed.
8 Write a VHDL code to implement serial to parallel 16-10-2023
of 4 bit binary number.
9 Write a VHDL program to perform parallel to serial 23-10-2023
transfer of 4 bit binary number
10 Write a program to design a 2 bit ALU containing 4 6-11-2023
arithmetic & 4 logic operations