Intelligent Gate Drivers For Future Power Converters

3484 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO.
3, MARCH 2022
Intelligent Gate Drivers for Future Power Converters

Jochen Henn , Student Member, IEEE, Christoph Lüdecke , Student Member, IEEE,
Michael Laumen , Student Member, IEEE, Steffen Beushausen , Student Member, IEEE,
Sven Kalker , Student Member, IEEE, Christoph H. van der Broeck , Member, IEEE,
Georges Engelmann , and Rik W. de Doncker , Fellow, IEEE
Abstract—This article gives insights into recent developments in I. INTRODUCTION

the field of power semiconductor gate drivers that exhibit intelli-
OWER electronic converters are applied to a wide range of
gent features. Such features are active switching transient control
and optimization of overshoots, electromagnetic interference, and
switching losses. Additionally, these aspects are providing safe
P low- and medium-voltage applications. They are key en-
abling technologies for renewable energies, the next-generation
operation at fast and extreme switching instances and short-circuit grid infrastructure, and electric traction systems [1]–[3]. In the
events. Furthermore, integrated sensing capabilities that extract
thermal response as well as state-of-health data constitute an intel-
light of this development, concepts for future power electronic
ligent gate driver. During the last decade, researchers transformed converters are needed to boost efficiency and reduce weight and
gate drivers from simple amplifiers to intelligent control units. In- costs, while providing a safe and reliable operation. One path in
telligent implies in this context that the driver can gather informa- this direction utilizes multiphysics design optimization of power
tion and adapt its operation behavior to changing conditions. This converters [4], [5]. Taking into account electric, magnetic, ther-
includes detecting and clearing fault states, electrical and thermal
management, and additionally in situ detection of aging effects.
mal, and mechanical constraints of newest devices and materials
Furthermore, this article identifies challenges and opportunities provides a large number of degrees of freedom for designing bet-
that arise with intelligent operation of wide-bandgap semicon- ter topologies [6], thermal management systems [7], [8], power
ductors. Future applications of semiconductor devices demand a modules [9], [10], and passive components [11]. Another path
high level of integration and utilization that can only be achieved toward next-generation power converters explores new monitor-
by safe operation within but close to their electrical and thermal
limits. Intelligent gate drivers provide a unique manipulability that
ing and control features, as they play a more and more important
enables high-performance and secure operation through extracting role for yielding high power densities. Traditionally, this in-
and using information about the switching process and the power cludes the system-level monitoring and control measures, e.g.,
module. voltage and current control [12], torque control [13], thermal
Index Terms—Active gate driver, electromagnetic emission control [14]–[16], and application-dependent control [17], [18].
(EME), electromagnetic interference (EMI), power electronics, A key enabler for these developments is the integration of
short-circuit (SC) protection, silicon carbide (SiC) MOSFET, Si sensing circuits, control features, and improved active gate driv-
insulated-gate bipolar transistor (IGBT), wide bandgap (WBG). ing topologies into intelligent gate drivers [19]–[21]. They are
the primary focus of this article, and Fig. 1 summarizes their role
in an intelligent gate driver. In the following subsections, a brief
Manuscript received March 22, 2021; revised June 30, 2021; accepted August introduction into the three topics of driver topologies, protection
29, 2021. Date of publication September 14, 2021; date of current version circuits, and thermal management is given.
November 30, 2021. This work was supported in part by the German Federal
Ministry of Education and Research (BMBF) through the following projects:
SiCnifikant under Grant 16EMO0304, RobKom under Grant 16EMO0375, A. Driver Topologies
ZuLeSELF under Grant 16EMO0324, and SiCmodul under Grant 16EMO0256,
and in part by the Flexible Electrical Networks Research Campus, Project 2: The major task of traditional gate drivers is to act as a power
Equipment and Network Technologies for Medium-Voltage DC Applications
under Grant FKZ03SF0489. Recommended for publication by Associate Editor amplifier for the power semiconductor device during turn-ON
Z. Zhang. (Corresponding author: Jochen Henn.) and turn-OFF transitions. Traditional gate drivers for silicon (Si)
Jochen Henn, Christoph Lüdecke, Michael Laumen, Sven Kalker, Georges metal–oxide semiconductor field–effect transistors (MOSFETs)
Engelmann, and Rik W. de Doncker are with the Institute for Power Electronics
and Electrical Drives (ISEA), RWTH Aachen University, 52056 Aachen, Ger- and insulated-gate bipolar transistors (IGBTs) are typically de-
many (e-mail: [email protected]; [email protected] signed for a specific device, power module, and application [22].
aachen.de; [email protected]; [email protected] They ensure that the turn-ON and turn-OFF transitions do not
aachen.de; [email protected]; [email protected]).
Steffen Beushausen is with the Institute for Power Generation and Storage lead to critical voltages and currents and operate the devices
Systems (PGS), RWTH Aachen University, 52056 Aachen, Germany (e-mail: with acceptable speed and switching losses [10]. However, the
[email protected]). identical control of power devices independent of the operation
Christoph H. van der Broeck was with the Institute for Power Electronics
and Electrical Drives (ISEA), RWTH Aachen University, 52056 Aachen, Ger- points, i.e., current, voltage, and temperature, can hardly unveil
many. He is now with FEV Europe GmbH, 52078 Aachen, Germany (e-mail: their full potential. This is because many operation points allow
[email protected]). a fast operation of the device within its safe operating area
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TPEL.2021.3112337. (SOA) as well as electromagnetic emission (EME), while some
Digital Object Identifier 10.1109/TPEL.2021.3112337 operation points require more careful device control [23], [24].
0885-8993 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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HENN et al.: INTELLIGENT GATE DRIVERS FOR FUTURE POWER CONVERTERS 3485
Fig. 1. Illustration of features of an intelligent gate driver. Here, power modules are the link between sensing components and gate driver topologies. The
intelligent control block contains methods that close the feedback loop and, thus, provide intelligence to the driver.
Especially, with the rise of silicon carbide (SiC) and gallium proposed in recent years [29], [30]. Consequently, this article
nitride (GaN) power devices, this is becoming a critical issue, as investigates the requirements for future intelligent device protec-
their switching speed provides huge potential for highly efficient tion schemes and illustrates effective implementation examples.
and compact converters, but they must be firmly controlled to
prevent hazardous device operation and electromagnetic inter-
ference (EMI). Thus, there is a strong on-going trend to smart C. Monitoring and Diagnostics
gate drivers that can vary their gate control strategy as a function A rather new role for gate driver circuitry is the integra-
of the operation point. This includes the ability to adjust the tion of monitoring and diagnostics features. Latest research
switching behavior in between switching cycles as well as during on power module integrated monitoring [31]–[33] shows that
the transients. Intelligent control of switching transients can future intelligent gate drivers are an effective tool to bring
increase efficiency [20] and limit current and voltage overshoots, monitoring and diagnostics solutions into an application. These
but also supports active mitigation of EMI [25] as well as thermal include temperature sensing solutions that can prevent overload
cycles [26]. Furthermore, gate drivers that individually control operation [34] and enable active thermal management [15], [35],
the gates of parallel devices enable active electrical and thermal e.g., on the basis of temperature sensors [34], [36], temperature-
balancing of paralleled power devices, as demonstrated in [27]. sensitive electrical parameters (TSEPs) [37]–[39] as well as
This, in return, creates more degrees of freedom in the power temperature-sensitive optical parameters (TSOPs) [40], [41].
module design, as asymmetries in the layout can be actively In addition, degradation-sensitive parameters can be extracted
compensated [28]. Therefore, one key objective of this article that allow determining the severity of bond wire lift-offs or
is to discuss and analyze adaptive gate driver topologies and gate-oxide degradation. Furthermore, a gate driver is excellently
device control methods that are essential for next-generation suited to integrate device self-sensing features [42] that are able
power converters. to extract thermal response properties of power modules, e.g.,
thermal impedances, and to detect degradation of material inter-
faces [43]. Device self-sensing, which can be excellently inte-
B. Protection Circuits grated in future gate drivers, excites the power device with small-
Typically, gate drivers for Si IGBTs and MOSFETs are equipped signal loss excitation and extracts the temperature response
with additional protection features, such as undervoltage lock to identify delaminations of the device or the substrate [44].
out, dead-time insertion, overcurrent and short-circuit-current Thus, this article also focuses on requirements for gate-driver-
handling, and parasitic turn-ON protection [22]. However, many integrated monitoring solutions and related applications.
well-known protection methods cannot be applied to mod- The rest of this article is organized as follows. After this
ern power devices, such as SiC and GaN devices. Their introduction, the requirements of modern gate drivers are ana-
dynamic electrothermal characteristics and fast switching ca- lyzed, and intelligent features such as paralleling and balancing
pability make an effective fast short-circuit (SC) protection multiple devices, control, protection, and monitoring of semi-
challenging. Thus, alternative protection schemes have been conductors are presented in Section II. Section III presents gate
3486 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 3, MARCH 2022
driver topologies that can be used for adaptive device control TABLE I
SI VERSUS SIC MOSFETS, EXEMPLARY 1200-V MODULES
and manipulation of switching transitions as depicted in Fig. 1 AND DISCRETE DEVICES
on the left. Consequently, Section IV discusses methods and
circuits providing protection for the semiconductor devices from
overcurrent and SC events. Section V presents recent methods of
monitoring and thermal management of semiconductor devices,
where gate drivers are involved in exciting a thermal response
and extract the respective parameters from the devices. Before
the conclusion, in Section VI, the key points that are important
for developing and employing future intelligent gate drivers and Low du/dt values for the discrete TO-247-4 SiC are calculated from the data sheets and
in research and commercial adoption using the findings of this can be exceeded in real applications [25].
article are laid out. Finally, Section VII concludes this article.
II. REQUIREMENTS FOR FUTURE APPLICATIONS high-side gate driver [55]. Although recent gate driver power
supplies are designed with minimized coupling capacitances
This section discusses key requirements for next-generation Ccoupling , the increase in slope steepness leads to higher CM
gate drivers. It illustrates how the application of wide-bandgap disturbance currents ICM . Additionally, the increase in power
(WBG) semiconductor devices and the need for low-cost highly demand of control units and sensing circuits inside of gate drivers
efficient Si converters force gate drivers into transformation to minimizes the available commercial solutions [56]–[58]. An
intelligent highly integrated systems. The key objectives for this example calculation for CM currents due to parasitic coupling
transformation have been identified to be the following: capacitances in isolated supplies is presented in (1)–(3). The
1) enabling of faster switching devices voltage slopes of devices 4–6 from Table I range from 16 kV/µs
a) optimized semiconductor structures and new materials for the Si IGBT over 49.23 kV/µs up to 125 kV/µs for the SiC
result in decreased rise and fall times and, thus, reduce MOSFETs and are used to estimate the disturbance current. The
losses [45]–[47]; coupling capacitance used in the following calculations is taken
2) better device utilization from a recently presented commercially available auxiliary gate
a) conventional drivers waste electrical and thermal po- drive transformer [56] that is able to fulfill the higher power
tential of existing technologies, which can be exploited demand of intelligent drivers
by intelligent features [48];
3) higher electromagnetic compatibility (EMC) du
ICM,max = Ccoupling · (1)
a) the need for cost and volume effective converters drives dt
the demand of EME-optimized designs [49]; ICM,Si,max = 7.5 pF · 16 kV/µs = 120 mA (2)
4) critical condition detection and handling
a) by improving detection and handling approaches, ICM,SiC,max = 7.5 pF · 125 kV/µs = 0.94 A. (3)
semiconductor switches can be optimized for usage
In addition to the higher CM disturbance current amplitudes, the
closer to their SOA;
switching frequency is increased, thus increasing the root-mean-
5) lifetime prediction and enhancement
square value of the CM noise. Therefore, special care has to be
a) Sensing of degradation-sensitive parameters allows an
taken while designing the power delivery and communication
optimization of operating parameters [50], [51].
paths of the gate driver.
Intelligent gate driver solutions can address these objectives
2) Higher Bandwidth: Lower or zero external gate resis-
by effectively exploiting the individual potential of various semi-
tances and a decreased amount of gate charge compared to Si
conductors [52] and integration technologies [4], [5] by applying
devices lead to shorter gate charging times and less attenuation
more efficient real-time computation and control abilities [53]
of oscillations. In return, a more dedicated gate loop with an
as well as novel sensing and protection features [37], [40], [41].
optimized impedance has to be implemented to allow stable
After reviewing the basic functionality, this section provides an
operation of the semiconductor devices in the event of extreme
overview on intelligent features that create smart gate drivers.
switching transitions. Table I lists three half-bridge modules
and three discrete devices of similar current ratings and equal
A. Basic Functions
packages to compare Si and SiC characteristics for the gate loop
The application of next-generation high-power MOSFETs bandwidth requirement analysis. In general, faster switching
changes the requirements for basic driver functions such as transitions cause an increased du/dt that, in turn, induces greater
common-mode (CM) immunity and higher output bandwidth. currents in parasitic capacitances of the semiconductor device.
1) CM Immunity: Higher switching speeds of modern semi- The gate loop can cause oscillations that are excited in the
conductor devices result in higher drain source voltage tran- switching event, if the parasitic inductances of the gate loop are
sients (du/dt). Therefore, drivers have to be designed with an too large. Additional excitation may be caused by disturbances
increased CM immunity in mind. This can be achieved by either that are introduced by a fast shifting potential due to a common
improving the resilience or the impedance in the CM path as current path for gate and load current in semiconductor devices
is presented in [54] or reducing the coupling capacitance of the without a kelvin source contact [65]. To protect the gate from
parasitic turn-ON situations that would cause an SC or overvolt- Manufacturing tolerances for both the dies and the packaging
ages at the gate that would damage the semiconductor, the gate lead to different voltage rise and fall times when connecting
loop impedance has to be considered. power semiconductors in series. Several solutions exist to create
Therefore, in the light of the adaption of WBG semiconduc- an active voltage balancing during the switching transitions of
tors, special care has to be taken in designing the layout and gate Si IGBTs and WBG devices.
loop impedance of a gate driver. In [69], an improved active clamping circuit utilizing a status
feedback is introduced. The status feedback signal is used to
adjust delays between the individual gate drive signals of the
B. Intelligent Features series-connected IGBTs to provide a synchronous turn-OFF and,
Modern semiconductors and power modules exhibit superior hence, improved voltage sharing.
properties that can hardly be unleashed with state-of-the-art A digital gate drive proposed in [70] samples the voltage
driver integrated circuits (ICs) and topologies. Thus, in recent slew rates of serialized IGBTs during turn-OFF. The turn-OFF
years, many technological features have been investigated that process itself is divided into several stages, and for each stage,
address the limitations. The following section introduces these the turn-OFF speed of the serialized IGBTs is compared to be able
features. to adjust the drive speed for the subsequent stage. Ultimately,
1) Device Utilization and Parallelization/Serialization: To a synchronized turn-OFF is achieved with improved voltage
increase their current carrying capacity, MOSFETs are connected sharing.
in parallel, as it provides a higher production yield to use several An IGBT serialization with active voltage control is proposed
small MOSFETs than a single large one [66]. in [71] and [72]. With active voltage control, both the collector–
This is done both with discrete components and with in- emitter voltage of each IGBT and the voltage slew rate itself
dividual dies in power modules. A disadvantage of MOSFETs are controlled to predefined values. As each IGBT in series is
connected in parallel is that unevenly distributed losses lead controlled to the same waveform, a good balancing is achieved
to different temperatures and, thus, to different aging phenom- enabling a serialization.
ena. In addition, the module must be derated to ensure that In [73]–[75], approaches using current-source gate drivers are
each MOSFET remains in its SOA. Different losses of paralleled proposed to synchronize the switching of the serialized devices
MOSFETs can be caused, for example, by different component for SiC MOSFETs as well as GaN high-electron-mobility transis-
characteristics or by asymmetries in the electrical parasitics of tors (HEMTs). Either a constant gate current or an additional
the commutation cell. With conventional gate drivers, it is not gate current injection is used to minimize a difference between
possible to influence the losses of the individual MOSFETs. With the voltage waveforms of the devices.
intelligent gate drivers, it is possible to allow each individual 2) Overshoot Optimization: Conventional push–pull driver
MOSFET to be utilized within its performance limit and eliminate stages use a gate resistor designed for the worst-case operating
the need to derate the load current capability. For manufacturers, point. This limits the voltage overshoots to be within the SOA
the component characteristics of the individual MOSFETs are during switching operations, for example. This wastes the po-
known after production. By simulating the switching cell, it is tential of modern power semiconductors as their capability for
possible to determine the parasitic elements of the switching faster switching and, thus, lower switching losses in the partial
cell. With these data, an open-loop approach can be used to load range is not addressed. In [20] and [48], a gate driver
balance the temperatures of the paralleled MOSFETs. As an is presented, which enables the gate resistance to be varied
example, in [28], a gate driver is presented that drives each during the switching process. Compared to a reference push–
gate of parallel-connected MOSFETs individually and delays the pull driver stage, the switching losses are reduced by up to
respective gate signals by a few tenths of nanoseconds to achieve 69% without exceeding the overshoots generated by a reference
equal switching losses in all MOSFETs. driver. In [76], a gate driver is presented which controls the
In [67], a closed-loop solution is presented to balance the gate–source voltage to influence the overshoot of MOSFETs.
losses of the individual MOSFETs. The current mismatch is mea- Some manufacturers have adopted similar techniques and offer
sured with a circuit, and the driver adjusts the delay of the gate commercially available gate drivers that are capable of limiting
signals accordingly. The disadvantage of this closed-loop control the switching overshoots [77], [78].
is that the switching cell has to be adapted for the feedback 3) Open-Loop Voltage and Current Transient Control: With
signal. du/dt control, the rate of rise or fall of the voltage across a power
Another solution is presented in [68]. To balance the currents semiconductor device can be limited to a certain value. The
of the parallel connected MOSFETs, the gate–source voltages are limitation of the absolute value for the du/dt benefits the lifetime
used as feedback signal. Although this does not change the of electromagnetic components, respectively, the insulation of
switching cell, this variant offers only limited possibilities to the windings, connected to a voltage-sourced converter [79],
eliminate asymmetries caused by the geometric structure of the [80]. Additionally, using di/dt control, the reverse recovery
switching cell. current in the diodes of a half-bridge configuration can be
In addition to the current balancing for parallelization, voltage controlled. The current and voltage rise times determine the
balancing for serialization plays an important role in medium- losses of the power semiconductor devices during switching
and high-voltage power converters that require high-voltage events [81]. Furthermore, influencing the switching transients,
switches with ratings above single commercial available devices. the EME can be adjusted according to the specific application
and standards; cf. Section III. Thus, with both du/dt control [94]. The switching loss manipulation ability of the gate drivers
and di/dt control, the switching losses and stress of a power provides an effective manipulated input for active thermal cycle
semiconductor switch as well as the antiparallel diode can be reduction. As an example in [16] and [26], the gate drive circuitry
actively controlled in a converter. However, to achieve the de- with dynamically adjustable gate resistance was developed.
sired behavior, the switch and the diode have to be characterized This can increase or reduce switching losses appropriately to
in a test environment. With the data from the characterization, reduce thermal cycles and, thus, increase the lifetime of power
lookup tables can be implemented on a digital control IC. The modules.
digital control IC then governs the behavior of the gate driver 7) Mitigating Isolation Degradation: Optimized switching
output stage and an open-loop control ensures the desired du/dt cells are a key factor to fully exploit the switching capabilities
and di/dt. Open-loop control approaches are suitable for almost of WBG devices. For this, the loop inductance is minimized in
any switching speed grade of power semiconductor switches, order to achieve higher switching speeds with reduced voltage
ensuring the desired switching behavior [82]. overshoots. However, steep voltage transients caused by high
4) EME Control: The EMEs can be adjusted by manipulat- switching speeds are known to reduce the lifetime of electri-
ing overshoot, slope characteristics, and the reverse recovery cal machines, transformers, and inductors [95]. Intelligent gate
effect in diodes. In general, EMC is achieved by a combination drivers offer a variable gate drive that actively influences the
of attenuating the transmission and limiting the creation of switching process of the power semiconductor. Thus, they allow
EME. Attenuation is accomplished by using filters in power for an operating-point-dependent selection of the gate profile
paths [83]–[86] or increasing the resilience of sensitive circuits to get the lowest possible losses while limiting the voltage
by shielding and zoning [87]. In applications that rely on stable steepness to the requirements of the connected devices.
high-bandwidth communication and low weight and volume, 8) Protection: Device protections are necessary in case of
a balance between cooling capability and EMI filter size is internal or external faults, e.g., SCs of the output. Low inductive
needed, because efficient and fast switching causes EME across switching cells and the low resistance of WBG devices lead
a broader frequency spectrum, which, in turn, affects the filter to a fast increase of the device current especially for the case of
size. As discussed in previous research [25], losses and EME internal faults. Intelligent gate drivers with overcurrent detection
can be adjusted dynamically during a converter operation. The times of less than 100 ns protect the power devices from overload
control mode can be divided into closed- and open-loop control. conditions. In addition, soft turn-OFF functions of the gate driver
In general, it is difficult to sense EME of a WBG converter for a prevent overvoltage conditions during clearing of fault events.
control feedback during the switching process of the converter Protection features of intelligent gate drivers also cover pre-
but has been achieved for Si in [88] and GaN in [89]. As an alter- cautions against parasitic turn-ON of the power MOSFETs. Al-
native, the feedback for a closed-loop controller can be provided though the Miller capacitance is much smaller compared to Si
for the next switching instance by low-cost sensors and, thus, devices, the risk of parasitic turn-ON is increased due to high
create a semi-open-loop control [90]. Future research may yield voltage and current transients and lower threshold voltages of
integrated feedback loops with delays in the subnanosecond WBG devices [96]. Thus, the driver must provide a safe gate
region, which can be suitable for closed control loops of SiC drive during the OFF-state of the MOSFET, e.g., through a negative
devices in high-voltage environments. voltage and a low-inductive/resistive gate path.
5) Sensing and Diagnostics: The higher demands on relia-
bility and lifetime of power electronic systems lead to a need for
III. DRIVER TOPOLOGIES FOR INTELLIGENT DEVICE CONTROL
highly accurate and spatially resolved temperature and degra-
dation information [32], [43]. To achieve this, the driver can This section discusses the gate driver topologies on the left
simultaneously serve as a sensor and evaluation unit [91]. The in Fig. 1. They enable intelligent control of turn-ON and turn-
driver enables the determination of temperature and degradation OFF transitions to meet the requirements that were presented
information via the evaluation of module-integrated sensors in Section II. In comparison to state-of-the-art drivers, which
as well as via the extraction of temperature- and degradation- employ a simple push–pull topology, they enable an adaptive
sensitive parameters. A driver-integrated computing unit can fur- gate voltage control. This way, the shape of the gate voltage
ther process the local sensor information to determine real-time and, in consequence, the transient behavior during a switching
spatially resolved strains and degradation effects in the entire instance of the semiconductor devices can be adjusted.
power module. The resulting condition monitoring system in This section classifies three topology categories: The first
combination with aging models allows predicting the remaining category contains adaptive resistive drivers, which provide a
lifetime of the considered components. Promising approaches possibility to adjust the gate resistance in between or during
for driver-integrated data extraction and evaluation units are switching transients. By including a set of gate resistors in series
presented in Section V. with fast low-power switches, this driver is able to combine the
6) Active Thermal Control: The reliability and lifetime of resistors, thus adapting the behavior.
power electronic systems relate strongly to the thermally in- The second group of drivers achieves the adaption by acting
duced strain in the power electronic module [92]. Reducing as a controlled voltage source, which sources and sinks current
thermal cycles actively, e.g., by applying active thermal manage- according to the input setting. This group is divided into two
ment and control concepts, is an effective method to increase the subclasses. The first one acts as high-bandwidth analog ampli-
reliability and lifetime of power electronic modules [15], [93], fier, which extends an arbitrary gate profile from its input to the
Fig. 2. Simplified active gate driver topologies including a current and (switched-mode) voltage source, as well as an adaptive resistive driver topology.
gate of a semiconductor device. In contrast, the second subclass turn-OFF transient can be adapted for every operating point [26].
behaves in the same way as pulsewidth-modulated power elec- Simplified versions of this class of gate driver are commercially
tronic converters do. This class is chosen to be featured in the available [106], [107], although they lack the flexibility provided
following section. by the prototypes in research.
Finally, adaptive current-source drivers control the current A more intelligent operating scheme of this driver topology
into the gate and, therefore, shape the switching transitions. varies the gate resistance dynamically during the switching
Noteworthy are resonant drivers, which use a combination of process. The gate-resistor value and the turn-ON times of each
inductors and capacitors to store the energy needed and transfer paralleled resistor depend on the operating point. This enables
it into the gate using a resonant tank. These gate driver topolo- a unique control of the turn-ON and turn-OFF dynamics of the
gies are primarily used in ultrahigh-frequency and efficient power device, allowing the mitigation of critical voltage and
switched-mode power supplies of smaller power ratings, where current overshoots that can destroy the switching cell or cause
minimizing gate driver losses is essential to reduce the gate EMI. The adaptive resistive driver provides these features within
drivers’ power demand [97], [98]. Additionally, they do not the SOA of the power device, while it also reduces the switching
provide the capability to adapt their behavior during switching losses, which is not possible using conventional drivers.
instances as the aforementioned classes do. 2) Operating Principle: The operation of the adaptive resis-
Gate driver topologies that allow manipulation of switching tive gate driver is divided in three phases. In the first phase of
instances are the actuators of intelligent gate drivers. Therefore, the switching process, a low gate resistance value is used to
all types of topologies have to be carefully designed to fulfill accelerate the switching process and, thus, reduce the switching
the need of the semiconductor device. The main design goal is losses. In Fig. 3, the first phase for turn-ON starts at time t0 and
to balance the output power and bandwidth of the gate driver, ends before t2 is reached. For turn-OFF, the first phase starts at
because they are in an antiproportional relationship. time t5 and ends before t8 is reached. Before a current or voltage
overshoot occurs during switching, a larger gate resistor is used
in the second phase to slow down the switching process and
A. Adaptive Resistive Driver reduce the overshoot. To reduce the switching losses further and
To influence the switching transients of a semiconductor, to shorten the duration of the gate charging and discharging,
an adaptive resistive driver is presented in the following sec- the gate resistance is reduced in the third phase. The third phase
tions. The driver uses different gate resistors to influence the starts after t2 and ends at t4 for the turn-ON event. For the turn-OFF
switching edges, overshoots, and switching losses. In this and event, the third phase starts after t8 and ends at t10 .
the following sections, first, the driver topology is presented; 3) Exemplary Results for an IGBT Power Module: In Fig. 4,
then, the operating principle and finally experimental results are the comparison of collector–emitter voltage overshoot ÛCE gen-
given. erated with a stepwise driver and with a push–pull driver stage is
1) Topology: Unlike a conventional push–pull driver stage, shown. For the driver design, ÛCE,crit = 520 V and a minimum
the adaptive resistive driver uses multiple resistors for the turn- gate resistor RG,min = 3 Ω are specified. It can be seen that the
ON and turn-OFF events. The driver concept is shown schemat- voltage overshoot ÛCE initially increases with increasing load
ically in the bottom of Fig. 2 and is further explained in [20], current Iload for both drivers. Up to a load current of Iload = 90 A,
[23], [48], and [99]. Similar approaches for SiC MOSFETs and the stepwise driver is used as a pull driver with a gate resistor
IGBTs are described in [82] and [100]–[105]. A basic oper- RG = RG,min = 3 Ω. For larger load currents, an appropriate
ation scheme of this gate driver architecture can adjust the stepwise driver profile is used in order not to exceed the limit
resistance every switching period, such that the turn-ON and value ÛCE,crit .
Fig. 3. Generic turn-ON and turn-OFF transitions.
B. Adaptive Voltage-Source Driver
A different approach is the active manipulation of the gate–

emitter voltage with the gate drive unit (GDU)’s output stage.
When controlling the drive voltage dynamically, the gate current
is manipulated accordingly, and thus, the behavior of the power
semiconductor switch can be controlled.
1) Topology: Different topologies can be utilized in adaptive
voltage-source gate drivers [88], [108]–[110]. In this article, the
switched-mode gate-drive stage is used as an example that is
shown schematically in the center of Fig. 2.
As modern GaN switched-mode power supplies reach higher
Fig. 4. Collector–emitter voltage overshoot using different load currents and and higher switching frequencies and achieve ultrahigh response
driver strategies with an IGBT [20].
times in the range of several tenths of nanoseconds, it is possi-
ble to utilize GaN-based power electronic converters as output
stages for GDUs. The exemplary switched-mode output stage
consists of two GaN HEMTs in a half-bridge configuration
acting as a synchronous buck converter that generates the gate
voltage of a subsequent connected power semiconductor de-
vice [111], [112].
2) Operating Principle: The switched-mode gate-drive
stage allows for three degrees of freedom to influence a power
semiconductor switching transients: a duty cycle, a switching
time for a certain duty cycle, and the number of duty cycle–
switching time pairs. All degrees of freedom can be dynamically
adjusted during the operation of the GDU in an application.
In the following, the operating principle of the driver is
Fig. 5. Turn-OFF losses using different load currents and driver strategies with exemplarily explained using Fig. 3. The driver is connected to an
an IGBT [20].
IGBT working with an inductive load. During turn-ON, the duty
cycle for the drive stage can be lowered prior to the reverse
The reference driver uses a gate resistor RG,ref = 14.2 Ω and recovery process between t1 and t2 to decrease the current
thus only comes close to the limit value ÛCE,crit at the maximum slew rate and, consequently, the peak reverse recovery current.
load current Iload = 300 A. This allows for a high initial current slew rate corresponding
In Fig. 5, the turn-OFF energies Eoff of the respective measure- to low turn-ON losses with a peak reverse recovery current in
ments are shown. It can be seen that, for each measurement point, the boundaries of the SOA for the devices. In addition to the
the stepwise driver generates lower losses than the reference current slew rate, the voltage slew rate can be influenced with a
driver. At a load current of Iload = 200 A, the losses of the change in the duty cycle as well. For the turn-ON, a decrease in
stepwise driver are 51% lower than those of the reference driver, the duty cycle corresponds to an increase in the voltage slew rate
while the collector–emitter voltage overshoot ÛCE stays below and vice versa between t2 and t3 . The turn-OFF transition can be
the critical value ÛCE,crit . influenced in the same way by varying the duty cycle. However,
Fig. 6. Turn-ON of a medium-voltage IGBT with a conventional and a

switched-mode GDU in direct comparison.
Fig. 7. Measurement of UDS of a low-side switch showing the range of
variation achievable with the use of the adaptive current-source driver.
an increase in the duty cycle corresponds to an increase in the

voltage slew rate, whereas it also corresponds to a decrease in
the current slew rate. Thus, different switching parameter pairs reference current for the current mirror. By adjusting the number
need to be set for the different phases of the turn-ON and turn-OFF of output transistors of the current mirror, the maximum amount
transitions to achieve an optimal performance. of output current can be adjusted.
3) Exemplary Results: Fig. 6 shows the turn-ON event for a 2) Operating Principle: The basic operating principle of this
medium-voltage IGBT at 2.4 kV and 1.2 kA with both a con- driver is comparable to an amplifier. A digital voltage waveform
ventional GDU and an switched-mode GDU. When the current created by an FPGA on the input is translated to a current profile
starts to rise, the higher slew rate with the switched-mode GDU and amplified to drive the gate capacitance. The aforementioned
is apparent. Nevertheless, the slew rate is lowered drastically switching profile is only limited by the bandwidth of the output
during the reverse recovery process, thus ensuring that the peak stage and the current carrying capability of the transistors in use.
reverse recovery current is at the same level as the peak of This way, the gate voltage can be manipulated in any way during
the conventional GDU. Subsequently to the peak in reverse a switching transition.
recovery current, the switched-mode GDU speeds up the turn-ON 3) Exemplary Results: This section presents exemplary re-
process, leading to an increase voltage slew rate compared to sults of varying the gate current profile during a turn-ON switch-
the conventional GDU. As the overlap of high currents and ing instance, as presented in Fig. 7. During a measurement at no
high voltages at a semiconductor device produces the switching load, the gate driver adjusts the voltage overshoot of a turn-ON
loss, the mitigation of the overlap time due to higher slew rates transition by adjusting the gate current shortly before the device
benefits the efficiency substantially. is fully turned ON. This results in an increased ON resistance of
Compared to the conventional GDU, using the switched-mode the MOSFET during a very short period and, therefore, attenuates
GDU lowered the turn-ON energy by 20% while still maintaining the oscillation and overshoot while maintaining a fast switching
the same peak reverse recovery current. speed. The voltage slope is as steep as the reference operating
point for 75% of the voltage transition. This results in an in-
C. Adaptive Current-Source Driver creased fall time of 2.6 ns from 12.8 to 15.4 ns. The overshoot
reduces from −106 to −35.9 V in this measurement example.
An additional mode of adapting the gate voltage during
operation can be achieved by adjusting the gate current [75],
[113]–[117]. This method can be applied to Si IGBTs and SiC D. Summary
MOSFETs. To allow arbitrary gate profiles, the adaptive current- The topologies presented in the previous sections provide
source driver needs to be able to translate a highly dynamic input different approaches to adapt the switching behavior of semi-
profile to an output gate current waveform. conductor devices. This is desired to gain an advantage in
1) Topology: The topology of the current-source gate driver the optimization of the switching behavior at a wide range of
can be summarized as depicted in Fig. 2 and described in [25]. operating conditions. As described in Fig. 2, the different drivers
An field-programmable gate array (FPGA) is used to create a make use of either adapting the gate resistance, the gate current,
digital arbitrary switching profile. This is fed through a resistor or the gate voltage. The exemplary results given in each section
ladder to create an analog reference current for the following show the effect of different applications of adaptive gate driver
current mirror. In order to decrease the output impedance of the topologies. The logic functions implemented in each solution are
resistor ladder, a buffer amplifier is inserted. An emitter follower running on FPGAs because they enable easy and precise control
according to the output of the buffer amplifier finally creates the of their digital outputs. A comparison between the topologies
has to be done on a high level because the implementation, The short-circuit withstand time (SCWT) of SiC MOSFETs is
semiconductor technology, and power rating of the applications typically specified to be around 2 µs [121], [122]. However, de-
vary between research prototypes. pendent on the specific gate and dc-link voltages, power modules
The digital character of the adaptive voltage driver stands out may be destroyed by an SC with a duration of 2 µs or lower,
as most efficient. However, this advantage is dependent on the as shown in [123]. Additionally, fully utilizing the potential
availability of ultrafast semiconductor switches and their drivers, of SiC devices through allowing a higher junction temperature
which limit the switching frequency of the driver stage to less and a higher dc-link voltage leads to a further reduction of the
than 50 MHz [118]. This is suitable for devices with rise and SCWT [124]. For GaN HEMTs, an SCWT of only 300 ns to
fall times in the low microsecond range. The adaptive resistive 1 µs is reported [125], [126], with a strong dependence on the
driver is categorized between the digital and analog character dc-link voltage. Finally, the detection must be faster than the
of the switched-mode and adaptive current drivers, as it uses SCWT, because the delay of the signal processing stage and
parallel outputs that can be precisely combined and shifted to turn-OFF time of the power semiconductor device must be taken
obtain the desired output behavior. Finally, the adaptive current into account.
driver acts as an analog amplifier. The driver bandwidth is only
limited by the semiconductors in the drivers power stage, but it
lacks efficiency because of its analog characteristic. B. Detection Methods
In general, the switched-mode voltage driver is suitable for Several detection methods exist that can be used to protect
medium-voltage high-power applications because the semicon- power switches from internal or external faults.
ductor devices will have a slower dynamic behavior and the For IGBTs, gate drivers most commonly use the desaturation
output bandwidth of the driver is high enough. In applications method (e.g., gate driver Infineon 2ED300C17-S) to detect SC
using WBG devices, the adaptive resistive and current drivers are or overcurrent conditions. Commercially available gate drivers
more suitable due to their improved output bandwidth. Here, the also use similar methods that are based on monitoring of the
adaptive resistive driver has a slight advantage in terms of band- ON-state voltage for Si and SiC MOSFETs, e.g., Texas Instruments
width, but the adaptive current driver allows a higher resolution UCC21710. However, as the desaturation method compares
of output currents. All of the mentioned adaptive gate driver the ON-state voltage of the power device to a fixed threshold,
topologies will benefit from integration into an application- compensation methods may be needed to reduce the tempera-
specific integrated circuit (ASIC) as their dynamic behavior will ture influence of the ON-state resistance Rds,on or aging [127].
improve. The challenges in the application of adaptive drivers Furthermore, a high-voltage diode is required for decoupling the
in future converters will be highlighted in Section VI. OFF-state voltage from the detection circuit.
In general, detection speeds of less than 200 ns are possible
when using optimized components [29], [128]–[130].
IV. DEVICE PROTECTION Another fast method with detection times of 150 ns and less
is based on monitoring of the voltage drop across the parasitic
Effective SC detection and handling technologies are key
inductance of a part of the power loop [128], [129], [131]–
components of intelligent gate drivers for next-generation power
[133]. Apart from SC detection, the parasitic inductance can
devices, as depicted in the sensing block of Fig. 1. In addition,
even be used to detect overload conditions using additional
with higher switching speeds, the risk of parasitic turn-ON
filtering [134]. A fast current rise that occurs during a fault
increases, thus requiring techniques to reduce crosstalk. The
condition leads to a voltage drop across the parasitic inductance.
following section presents these technologies.
The faster the current rise, the higher the voltage drop. Thus,
fault conditions and regular switching events can clearly be
distinguished. Power devices and modules with kelvin emitter
A. Requirements of Overcurrent Protection Methods
(IGBT) or kelvin source (MOSFET) offer an easy way to imple-
Overcurrent and SC conditions are critical faults that must be ment this method, because the respective internal inductance
detected to prevent damage to the power switches, capacitors, between emitter/source and kelvin emitter/source can be used.
and magnetic components. Especially, WBG power switches A small drawback is that slowly rising currents, e.g., due to
require fast detection times due to several reasons: First, the chip sensor or control faults, can only be detected during switching
size and, thus, the thermal capacity are smaller than for Si-based events. Thus, a slow current increase during static operation
devices, leading to a faster temperature rise during overcurrent cannot be detected. However, this rare fault type only occurs
conditions. Highly integrated switching cells possess a further for external SCs and, thus, can be detected by an output current
decrease of the thermal capacity due to the very compact layout sensor. Another drawback is the required minimum inductance
of the switching cell and, thus, reduced amount of copper. value to achieve a reliable differentiation between fault cases
Second, the current slope of WBG devices is much steeper and normal switching behavior; modules with extremely low
compared to Si IGBTs or MOSFETs. Third, switching cells for loop inductances (see, e.g., [119] and [120]) are, thus, excluded.
SiC or GaN power switches typically feature very low loop Further methods are the detection with a Rogowski coil in the
inductances to increase switching speed and to limit switching power loop [135], [136] and the usage of shunt resistors in series
overvoltage [119], [120]. The increased switching speed leads to the power devices [137], [138]. The Rogowski coil method
to a faster current rise during fault conditions. is very promising as it achieves very short detection times,
TABLE II
SUMMARY OF OVERCURRENT DETECTION METHODS
Fig. 8. Schematic of the SC detection.
provides intrinsic galvanic isolation, and has no temperature

dependence. Furthermore, as the Rogowski coil outputs the
derivative of the commutation current, it is comparable to the
parasitic inductance method with regard to the bandwidth.
The current information obtained using the Rogowski coil can
even be used by adaptive gate drivers to achieve a closed-loop
control of the switching transient. However, a modification
of the switching cell is required, and, compared to the other
methods, the circuit is rather complex.
The usage of shunt resistors in series to the power devices
allows a very accurate SC and overcurrent detection. For com- lower voltage division ratio than the first divider. Thus, for
mercially available shunts, there is a negligible temperature a constant voltage Udc , the sensing voltage is lower than the
dependence. However, the power losses and the additional in- reference voltage. In addition to the resistive voltage divider,
ductance of the shunt resistor are clear drawbacks of this method. a capacitive voltage divider (Csens,1 , Csens,2 ) with the same
Detection methods using current mirrors [139]–[141] could division ratio is added in parallel to achieve a high bandwidth.
offer high-bandwidth monitoring of the device current as the Otherwise, the parasitic capacitances of the comparator and the
current is monitored directly at chip level. However, they require traces of the printed circuit board would result in a low-pass
power devices with on-chip current mirrors, which are currently behavior of the divider, affecting the detection speed.
not commercially available in SiC devices. As shown in Fig. 8, both voltage dividers are directly con-
Not only focusing on a device level but on a system level nected to the dc-link capacitor Cdc of the converter. Faults, e.g.,
provides the opportunity to detect SCs by monitoring the dc-bus SC events, lead to a fast drop of the dc-link voltage and the
voltage. With detection times of less than 300 ns [142] or even sensing voltage usens . The reference voltage Uref stays constant
below 100 ns [143], these methods allow a fast detection of fault due to the low-pass filter. Thus, the sensing voltage drops below
conditions with low component count. Furthermore, for multi- the reference voltage leading to the comparator changing its
level or multiphase systems, a single monitoring system could be output voltage to high. Depending on the dimensioning of the
used to protect all switches from SC or overcurrent conditions. components and the speed of the comparator, detection times of
A drawback is that during nonswitching operation, SC or over- less than 100 ns are achieved [143].
current events with fast rising currents can be detected only, as Fast SC detection methods are key components of future
otherwise the dc-link voltage does not drop significantly. Similar power converters, because high-speed overcurrent and SC detec-
to the stray inductance method, the dc-link-based detection is not tion methods enable reliable operation even at higher switching
able to detect slowly rising currents during static operation. speeds. As shown in Table II, each detection method has its
In the following, the functioning of the dc-link method as own strengths and weaknesses. Thus, an application-specific
presented in [143] is explained exemplary for the SC detection selection of the detection method is crucial to achieve best
methods. performance.
The circuit depicted in Fig. 8 consists of a comparator and
two voltage dividers: one generates a reference voltage and
C. Protection Methods
the other provides the sensing voltage. The voltage divider for
the reference voltage consists of the two resistors Rref,1 and Detecting and clearing overcurrent conditions as well as SC
Rref,2 that define the voltage ratio of the voltage divider. An faults in short times is crucial to prevent failures of the total
additional capacitor Cref,1 adds a low-pass behavior in order to system. However, instantly turning OFF the devices leads to
get a constant reference voltage. The reference voltage Uref is high overvoltages due to fast-changing currents through par-
connected to the positive input of the comparator. The second asitic inductances of the commutation loop. Instead, the fault
voltage divider (consisting of Rsens,1 and Rsens,2 ) is connected condition needs to be cleared in a way that limits damage to
to the negative input of the comparator and has a slightly other components.
Soft-turn-OFF mechanisms limit the rate of change of the the power conversion process and extract reliability-critical data
current during turn-OFF and, thus, limit the overvoltage. With with minimal delay. Thus, the gate driver is ideally suited for
adapting the gate drive, either through changing the gate current, the implementation of the aforementioned techniques. Electrical
gate voltage, or gate resistance, a soft-turn-OFF can be achieved. circuitry for temperature extraction, which are essential in all
All presented drivers (see Section III) are able to adapt the gate condition monitoring systems, must be implemented as close
drive and, thus, prevent excessive overvoltages. to the power module as possible to maximize accuracy and
interference tolerance [152], [154]. Furthermore, condition and
D. Crosstalk Mitigation aging monitoring methods that rely on system excitation and
response observation benefit from direct driver integration to
Parasitic turn-ON caused by crosstalk between the two devices
minimize lag [44] between smart gate actuation and sensing. The
of a half-bridge is a major problem especially for WBG devices.
same applies to active thermal management systems, which have
It occurs during turn-ON of one power switch, as fast voltage
to adapt the operating strategy, e.g., by adjusting the switching
transients lead to a current flowing into the gate of the other
behavior, with as little delay as possible in order to optimize
switch. When a device turns ON, the voltage across the device
system conditions, e.g., utilization [8] or service life [16], based
will drop fast, hence causing a voltage increase across of the
on extracted condition data. In the following, the procedures
other switch. This leads to charging of the drain–source capac-
for condition and aging monitoring as well as active thermal
itance Cds and gate–drain capacitance Cgd . However, charging
management are presented, and a case is made for why their
the miller capacitance Cgd causes a current flowing into the
implementation on future smart gate drivers is imperative.
gate, thus increasing the gate–source voltage. If the gate–source
voltage rises above the threshold voltage, the device turns ON
leading to an SC of the half bridge. As the typical threshold A. Driver-Integrated Temperature and Degradation Sensing
voltages of WBG are lower than those of Si-based devices,
The availability of temperature and degradation information
the parasitic turn-ON is of greater concern. High-temperature
in the gate driver allows direct intervention in system operation
operation furthermore increases the risk due to the negative
with minimal delay, e.g., to avoid overtemperature or compo-
temperature coefficient (NTC) of the threshold voltage [96].
nent failure, and serves as input for more complex condition
Although manufacturers try to reduce crosstalk by minimizing
monitoring systems. However, for accurate and real-time con-
the gate–drain capacitance [144], preventing parasitic turn-ON
dition monitoring of power electronics, junction temperature
requires thorough design of the gate driver. First, decreasing
information of the switching semiconductors must be extracted
the turn-OFF resistance increases ruggedness as the voltage drop
with high accuracy, high bandwidth, high signal-to-noise ratio,
caused by currents flowing into the gate is reduced. In addition
and minimal lag. Applicable temperature sensing approaches are
to the resistive voltage drop, the inductive voltage drop needs
module-integrated physical sensors [34], [36] as well as the ex-
to be considered. In general, the total impedance of the path
traction of TSEPs [152] and TSOPs [40], [155]. These methods
between the gate driver and the device should be minimized,
have in common that the sensors and parameters can usually be
e.g., by using a low gate resistor and a layout with short and wide
accessed directly via the terminals of the power module. While
traces [145]. However, using a low gate resistance also influences
complexity differs, all methods require extraction circuitry to
the turn-OFF switching waveforms. To avoid influencing the
convert the temperature-sensitive variable or parameter into a
switching behavior, a low-impedance path can also be achieved
usable electrical signal. To avoid interference and lag in the
by using an additional clamping circuit. The clamping circuit
measurement, the extraction circuit must thereby be placed as
either shortens the gate and the source [146] or virtually enlarges
close as possible to the terminals of the module, rendering the
the gate charge by introducing an additional capacitance [147].
gate driver particularly suitable for accommodating the circuit.
Additional crosstalk mitigation methods focus on adapting the
When selecting the temperature sensing approach and de-
gate voltage. Gate drivers with bipolar voltage supply that offer
signing the corresponding driver-integrated extraction circuit,
a negative turn-OFF voltage increase the margin to the threshold
the specific characteristics of each approach must be consid-
voltage and, thus, reduce the chance of parasitic turn-ON [148].
ered [156]. The most commonly used physical temperature
However, negative voltages may reduce lifetime of the gate
sensors are NTC thermistors. Due to its low susceptibility to
oxide [144], [149]. Concepts that dynamically change the gate–
interference, slow transients, and high temperature sensitivity,
source voltage either by using three or more voltage levels [19],
the extraction circuit of NTC sensors can be implemented rela-
[150] or by using a resonant gate drive circuit [151] only use
tively simple compared to other sensing approaches. However,
negative gate voltages during switching events, thus reducing
the bandwidth of the NTC temperature information is limited
the impact on the gate oxide while preventing parasitic turn-ON.
by the distance, in which the sensors are placed from the power
semiconductors [34].
V. MONITORING AND THERMAL MANAGEMENT
TSEPs, such as ON-state voltage [157], peak gate current [39],
Reliability-critical applications of power electronic systems gate-plateau level [37], or the turn-ON delay [21], directly reflect
require monitoring of thermal response [53], [152] and state of the temperature sensitivity of the power device, e.g., threshold
health of relevant components [32], [153] as well as reliability- voltage, transconductance gain, and internal gate resistance.
oriented active thermal management [16], [33], [93]. Due to its This in situ access to temperature data inside the power module
proximity to the power module, the gate driver can manipulate enables temperature measurement with a higher bandwidth than
Several known TSEPs show a temperature and a degradation

dependence. While this circumstance renders the use of TSEPs
as a single temperature sensor less attractive, it allows degra-
dation sensing by decoupling the influence of temperature and
component aging on the TSEP. This decoupling can be achieved
by the simultaneous extraction of several TSEPs with differ-
ent degradation sensitivities [154], [160]. Besides the auxiliary
use of TSEPs for degradation detection, the gate driver can
also extract parameters that are strongly influenced by aging
processes, so-called degradation-sensitive electrical parameters
(DSEPs). Examples for DSEPs are the bond wire resistance
for the detection of bond wire lift-offs [161] as well as the
threshold voltage, gate-plateau voltage, gate-plateau time [162],
and gate leakage current [149] for the detection of gate-oxide
Fig. 9. Electroluminescence of an SiC MOSFET body diode.
degradation.P2.4, P3.1
B. Utilizing Sensing Data for Monitoring

physical sensors. However, TSEPs often inherently come with
short available extraction times, low temperature sensitivity, The presented driver-integrated temperature and degradation
and low signal-to-noise ratios [37], [154]. This implies that for sensing methods allow us to detect and response to overtempera-
TSEPs, the need for minimum signal transmission distances and tures and critical component aging at single points in the power
module proximity of the extraction circuitry increases, reinforc- module with low delay. However, single-point measurements
ing the need for circuit integration in the gate driver. are not sufficient to provide spatially resolved information on
While this article only gives a limited overview of TSEPs for the temperature and degradation condition of the entire module,
the purpose of demonstrating their potential as part of a smart which is necessary for highly accurate and localized monitoring
gate driver, there are several other parameters that have been of aging effects. For this purpose, multiphysics models and
discussed in greater scope and detail in previous publications, control algorithms can be implemented, which can extract 3-D
such as the articles presented in [152], [154], and [158]. distributed temperature information in real time. Based on this
Similar to TSEPs, TSOPs offer high bandwidths, due to spatially resolved temperature information, methods can be
their direct dependence on semiconductor junction temperature. implemented to separate and localize degradation effects by ex-
TSOPs have the advantage over TSEPs of intrinsic galvanic tracting aging-dependent parameters through specific system ex-
isolation due to optical signal transmission. Since the isolation citation. Since system excitation and response monitoring must
is already integrated in the signal path to the gate driver, the be performed with as little delay as possible, it is advantageous
extraction circuit does not need to be additionally isolated from to implement the temperature and aging condition monitoring
the rest of the driver circuitry, and the transmission and extraction system directly on the gate driver’s computing hardware. How-
circuitry is less susceptible to interference. The electrolumines- ever, to enable real-time spatial temperature and aging monitor-
cence of SiC MOSFETs, which is shown in Fig. 9, is a promising ing on gate-driver-integrated hardware, mathematical reduction
example of a TSOP [40], [155]. It allows the extraction of both techniques must be applied to the employed models [92].
temperature and current information using multiple photodiodes To increase the accuracy of pure model-based temperature
in combination with artificial intelligence methods [41]. determination, the condition monitoring methods can be ex-
Compared to physical sensors, it should be noted that for tended by an observer structure. It combines extracted junction
TSEPs as well as for TSOPs, the performance or applicability of temperature data with compact real-time models to provide
such temperature-sensitive parameters can vary significantly for more accurate estimates of temperatures and device losses. The
different semiconductor technologies. While some parameters, need for observers is mainly related to the high inaccuracy of
such as ON-state voltage, threshold voltage, internal gate resis- device loss estimation, which arises from the difficulty of loss
tance, and turn-ON delay, are suitable for different semiconductor model calibration [163]. Using a thermal observer structure, as
technologies, such as Si, SiC, or GaN devices, temperature sen- shown in Fig. 10, the inaccurate loss model can be compen-
sitivity and implementation effort can vary widely [21], [159]. sated, and thus, a precise loss and temperature estimation can
Furthermore, there are parameters that can only be applied to a be achieved [53]. This is realized by compensating the error
specific semiconductor technology, such as the evaluation of the between temperature sensor values and the output of the thermal
electroluminescence spectrum of SiC devices [40], [155]. From model of the sensor positions and thus determining the loss error.
these constraints, it can be deduced that there can be no one- Furthermore, the observer structure can be used to separately
fits-all solution for junction temperature sensing on future gate and locally determine aging processes of the power electronic
drivers, but that it must be adapted to the specific semiconductor system in real time. First, degradation-related parameter drifts
technology in the same way as the other driver functions. of the multiphysical models can be determined and assigned
Besides temperature extraction, the driver can also be used to specific aging processes utilizing the observer and adaptive
to obtain information about the state of component degradation. control methods, such as model reference adaptive systems [43].
One possible goal of active thermal control is to increase

the overload capability of three-phase inverters. Due to the
frequency dependence of the thermal impedance, the thermal
headroom of the power semiconductors in inverter systems is
strongly dependent on its operating point. Thus, active control
can increase the peak current depending on the operating point
without exceeding the maximum permissible junction tempera-
ture [8].
Furthermore, active thermal control can reduce thermal cy-
cling, which strongly contributes to the degradation of sys-
tem components [164], [165]. For this purpose, either the loss
Fig. 10. Thermal observer structure for loss and spatial temperature estima- dissipation of the semiconductors, e.g., by manipulating the
tion [53]. switching behavior [15], [16], [51], [94], [166] or the modulation
scheme [167], [168], or the convection of the system [169], [170]
can be controlled. Other applications of active thermal control
include balancing of paralleled semiconductors [27], [171] and
redistribution of thermal load to multiple system components,
such as for modular [172] and multilevel converters [173]. By
integrating the active thermal control directly into the gate driver,
the operational and lifetime optimization can be performed not
only quickly but also independently of control tasks coming
from a higher control level.
It has been shown that condition monitoring systems and
active thermal management are essential for reliability-critical
applications and must be part of a future smart gate driver. On
the one hand, temperature extraction circuits must be integrated
directly on the driver to achieve sufficient bandwidth, accuracy,
and noise immunity. On the other hand, condition and aging
diagnostic systems and active thermal control need to be imple-
Fig. 11. Degradation sensing using thermal impedance [44]. mented on the driver, as they must be able to manipulate the
converter operation in real time and with minimal delay.
Second, a resonant feedback path can be added to the observer to VI. CHALLENGES IN THE APPLICATION OF
extract thermal impedance information using minimal-invasive INTELLIGENT DRIVERS
periodic loss excitation [44] that can be provided by the active The previous sections describe requirements, topologies, and
gate driver architectures presented in this article. Various aging intelligent features that were developed in recent years. In order
effects, such as delamination and convection reduction, affect to make use of these developments or improve their behavior,
different frequency ranges of thermal impedance and can, thus, a number of challenges have to be met to allow adoption in
be separately extracted. The exemplary influence of different general use. Table III gives an overview over the research that
aging processes on thermal impedance for an Infineon Hybrid- has been reviewed and classifies it into the main objectives that
pack 2 IGBT power module is shown in Fig. 11. These meth- were identified in Section II. Additionally, the main challenges
ods benefit from integrated gate driver implementation because are grouped by their applications and laid out in the following
single-point temperature extraction, observer-based condition subsections: active gate driver topologies, device protection, and
monitoring, and aging diagnosis by system excitation can inter- monitoring and thermal management.
operate with minimal delay and interference.
A. Active Gate Driver Topologies
C. Active Thermal Control Gate drivers that are able to shape the voltage and current
Active thermal control allows influencing the thermal state via transitions are limited by their output bandwidth, drive strength,
operating manipulation to optimize system behavior and extend and knowledge of the characteristics of the switching instance.
operating life. The control system relies on highly accurate, Depending on the topology, there is a tradeoff between the
spatially resolved, and lag-free thermal information, which a output bandwidth and the drive strength. In addition, the par-
thermal monitoring system as presented above can provide. It is asitics of the gate loop will limit the bandwidth of the active
particularly useful to integrate the active thermal control along gate driver. Another limitation for the output bandwidth stems
with the required condition monitoring system on the gate driver, from the availability of ultrafast drivers for the semiconductor
since this allows the direct influence on the system operation, devices used in the drive stage of the gate drivers and ultrafast
such as switching behavior, with minimal delay. semiconductor devices for the drive stage itself.
TABLE III
OVERVIEW OF REVIEWED RESEARCH TO SUMMARIZE AND SORT REFERENCES CONTAINING SOLUTIONS TO THE OBJECTIVES THAT WERE IDENTIFIED IN SECTION II
For an open-loop approach for the control of switching tran- reliability must be minimized. Integrating detection circuits into
sients, a characterization of the driver for each operating point ICs will provide advantages regarding component count, cost,
of the power semiconductor device is required. However, due and space requirements. However, it must be ensured that the
to tolerances in the manufacturing process, each die or power overcurrent level and the detection time can be parameterized
semiconductor device has a slightly different behavior compared easily. Using fast detection circuits, the manufacturers could
to each other. This leads to a deviation from the optimal behavior reduce the SC withstand time of the power devices, thus lead-
established with the driver for the reference device and neces- ing to possible improvements of the switching and conduction
sitates a characterization for each die or device. A closed-loop behavior in normal operation and exploiting the full potential of
approach is capable of mitigating the variation in die or device the devices.
behavior, still achieving the desired performance. However, the 2) Crosstalk Mitigation: Parasitic turn-ON is a major concern
sensing of the controlled variables with sufficient bandwidth is for fast switching power semiconductor devices. In addition
a challenge, especially for WBG power semiconductors. to optimizing the layout of the switching cell and the gate
Therefore, integration efforts and gate loop design to increase driving circuit, crosstalk mitigation is achieved by adapting the
the bandwidth and improvement of sensing solutions are in driver output. Preventing parasitic turn-ON is often achieved
the focus of development. Even though most of the advanced by lowering the turn-OFF voltage during the turn-OFF phase to
functionality is handled through signal processing and can be achieve a higher margin to the threshold voltage. However, this
integrated into an ASIC, depending on the topology, additional leads to additional stress to the power devices, in particular the
passive components need to be placed close to the gate terminal. gate oxide. This affects the lifetime of the switches negatively,
Hence, a good gate loop layout stays imperative. especially for higher junction temperatures. Thus, crosstalk miti-
gation circuits have to be designed in a way that parasitic turn-ON
prevention is just achieved, resulting in minimum impact on the
B. Protection Circuits device lifetime. Additional challenges arise for SiC MOSFETs, as
Future power electronic converters need fast and reliable the bias temperature instability leads to a drift of the threshold
detection circuits that ensure safe operation of the power devices. voltage.
1) Overcurrent Protection: Overcurrent and SC protection
circuits need to detect and clear critical conditions of the power
semiconductors. The major development effort lies in increasing C. Monitoring and Thermal Management
the reliability while providing very fast response times. For this, For an effective future driver, integration of monitoring meth-
the circuits must be able to clearly distinguish between normal ods, and active thermal management systems, various challenges
switching events and faults without being influenced by external need to be addressed.
parameters like the junction temperature of the power device. 1) Sensing: Highly accurate and high-bandwidth junction
Furthermore, the influence of manufacturing differences of the temperature sensing, e.g., by TSEP extraction, is often charac-
power semiconductors or the switching cell on the detection terized by short extraction times, low temperature sensitivities,
and low signal-to-noise ratios, especially for WBG devices. As with WBG power devices, e.g., effective overcurrent and SC
a result, driver-integrated extraction circuitry often relies on protection, active EME mitigation, and integrated temperature
high-performance components, high part count, and stringent sensing via electrical and optical device properties. We show
EMC requirements. Thus, a focus of future investigations must how different gate driver technologies are applied to yield similar
lie on the exploration of robust but streamlined sensing methods optimization objectives in specific applications, e.g., highly inte-
as well as the development of integrated extraction circuits. grated automotive power electronics and stationary high-power
Furthermore, TSEPs and TSOPs often have not only the applications. Additionally, future gate drivers integrate device
desired sensitivity to temperature but also strong sensitivities self-sensing capabilities that enable state-of-health monitoring
to other variables such as device current, dc-link voltage, and and diagnosis of power electronic devices and packages. Further-
component degradation. For highly accurate sensor performance more, we identify future challenges that need to be addressed to
over the entire lifetime, detailed sensitivity analysis of the enable adoption of intelligent gate drivers in industrial practice.
temperature-sensitive parameters is of great importance, allow- Ultimately, adaptive gate drivers allow a variety of operation
ing the identified influences to be taken into account in the enhancements. First, their basic feature enables actively con-
evaluation. However, this circumstance also offers the possibility trolling switching transients according to an external input. Sec-
for a single driver-integrated extraction circuit to simultaneously ond, employing intelligent gate drivers allows operating power
determine not only temperature but also other quantities of devices safely at higher currents and voltages with smaller de-
interest, as has already been exemplarily shown in [155]. This sign margin. Moreover, active gate drivers compensate package
combined sensing approach reduces the number of module- imbalances and, thus, enable parallelization and serialization of
integrated sensors and, thus, costs and space requirements. multiple devices. Finally, thermal management of power devices
The multiple sensitivities of TSEPs/TSOPs lead to an in- by loss modulation leads to thermal cycle reduction and prolongs
creased calibration effort of these sensing methods. Therefore, the lifetime of semiconductor devices.
efficient calibration methods and their integration into the manu-
facturing processes of semiconductors and power modules have
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power modules,” IEEE Trans. Emerg. Sel. Topics Power Electron., to be Jochen Henn (Student Member, IEEE) received the
published, doi: 10.1109/JESTPE.2021.3063305. M.Sc. degree in electrical engineering from RWTH
[157] F. Stella, G. Pellegrino, E. Armando, and D. Dapra, “On-line junction Aachen University, Aachen, Germany, in 2017.
temperature estimation of SiC power MOSFETs through on-state volt- He joined the Institute for Power Electronics and
age mapping,” IEEE Trans. Ind. Appl., vol. 54, no. 4, pp. 3453–3462, Electrical Drives, RWTH Aachen University, in 2017.
Jul./Aug. 2018. His research interests include the field of power
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ment of power semiconductor devices by thermo-sensitive electrical bandgap semiconductors, and electromagnetic emis-
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pp. 3081–3092, Jun. 2012.
Christoph Lüdecke (Student Member, IEEE) re- Christoph H. van der Broeck (Member, IEEE) re-
ceived the M.Sc. degree in electrical engineering ceived the B.Sc., M.Sc., and Ph.D. degrees in elec-
from RWTH Aachen University, Aachen, Germany, trical engineering from RWTH Aachen University,
in 2015. Aachen, Germany, in 2010, 2013, and 2018, respec-
Since 2016, he has been a Research Associate tively.
with the Institute for Power Electronics and Electri- Between 2011 and 2013, he was with AixControl
cal Drives, RWTH Aachen University. His research GmbH, Aachen. From 2011 to 2012 and from 2017
interests include active gate drivers for wide-bandgap to 2018, he was a Fulbright and DAAD Scholar
devices and power electronic converters for automo- with the Wisconsin Electric Machine and Power
tive applications. Electronic Consortium, University of Wisconsin–
Madison, Madison, WI, USA. After completing his
Ph.D. degree, he became a Chief Engineer and Head of the Reliable Power
Electronics Group, Institute for Power Electronics and Electrical Drives, RWTH
Aachen University. In 2020, he joined FEV Europe GmbH, Aachen, as a Senior
Technical Specialist for power electronics and electrical drives. He has authored
more than 40 technical articles. His research interests include multiphysics
modeling, monitoring and control of power electronics, and drive systems.
Dr. van der Broeck is the recipient of two IEEE Prize Paper Awards.
Michael Laumen (Student Member, IEEE) received
the M.Sc. degree in electrical engineering from
RWTH Aachen University, Aachen, Germany, in
2015.
Since 2016, he has been a Research Associate
with the Institute for Power Electronics and Electrical
Drives, RWTH Aachen University, and became a Georges Engelmann received the Diploma and
group leader of the power electronics group in 2019. Ph.D. degrees in electrical engineering from RWTH
His research interests include high-temperature gate Aachen University, Aachen, Germany, in 2012 and
drivers and measurement electronics, especially for 2018, respectively.
automotive power electronic converters. From 2013 to 2019, he was a Research Associate
with the Institute for Power Electronics and Electrical
Drives, RWTH Aachen University, where he has been
a Group Leader of the Power Electronics Group since
2017. His research interests include power semicon-
ductor switching characterization and gate drivers for
wide-bandgap devices.
Steffen Beushausen (Student Member, IEEE) re-

ceived the B.Sc., M.Sc., and Ph.D. degrees in
electrical engineering from RWTH Aachen Univer-
sity, Aachen, Germany, in 2013, 2015, and 2021,
respectively.
He joined the Institute for Power Generation and Rik W. de Doncker (Fellow, IEEE) received
Storage Systems, E.ON Energy Research Center, the Ph.D. degree in electrical engineering from
RWTH Aachen University, in 2016. His research Katholieke Universiteit Leuven, Leuven, Belgium, in
interests include power electronics. 1986.
He was a Visiting Associate Professor with the
University of Wisconsin, Madison, WI, USA, in 1987,
a Senior Scientist with GE CR&D, New York, NY,
USA, in 1988, and the VP Technology of SPCO in
1994, developing world’s first medium-voltage static
transfer switch. Since October 1996, he has been a
Professor with RWTH Aachen University, Aachen,
Germany, leading the Institute for Power Electronics and Drives. He became the
Sven Kalker (Student Member, IEEE) received the Director of the E.ON Energy Research Center, RWTH Aachen University, in
B.Sc. and M.Sc. degrees in electrical engineering 2006 and founded the Institute for Power Generation and Storage Systems. He
from RWTH Aachen University, Aachen, Germany, leads the RWTH CAMPUS Cluster Sustainable Energy and the BMBF Flexible
in 2014 and 2017, respectively. Electrical Networks Research CAMPUS.
Since December 2017, he has been a Research Dr. de Doncker has been a member of the German National Platform for
Associate with the Institute for Power Electronics E-Mobility since 2010, the French VEDECOM since 2017, and the German
and Electrical Drives, RWTH Aachen University, and Academy of Science and Technology since 2016. He is a recipient of the
assumed leadership of the Reliable Power Electron- IEEE IAS Outstanding Achievements Award and the IEEE PES Nari Hingorani
ics Group in September 2020. His research interests Custom Power Award in 2008, the Newell Power Electronics Field Award in
include reliability, modeling, and sensing of power 2013, the IEEE PELS H. Owen Outstanding Service Award in 2014, RWTH
electronic systems. Fellow status in 2015, and the IEEE Gold Medal in Power Engineering in 2020.

Intelligent Gate Drivers For Future Power Converters

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Intelligent Gate Drivers For Future Power Converters

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3484 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO.

Intelligent Gate Drivers for Future Power Converters

Abstract—This article gives insights into recent developments in I. INTRODUCTION

Fig. 3. Generic turn-ON and turn-OFF transitions.

B. Adaptive Voltage-Source Driver

A different approach is the active manipulation of the gate–

Fig. 6. Turn-ON of a medium-voltage IGBT with a conventional and a

an increase in the duty cycle corresponds to an increase in the

Fig. 8. Schematic of the SC detection.

provides intrinsic galvanic isolation, and has no temperature

Several known TSEPs show a temperature and a degradation

B. Utilizing Sensing Data for Monitoring

One possible goal of active thermal control is to increase

Steffen Beushausen (Student Member, IEEE) re-

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