UM8762 - FELib - PSD - Parameters - User - Manual - Rev.2

CAEN
Tools for Discovery

n Electronic Instrumentation
DACMa u
UM8762
FELib PSD Parameters User Manual

Description of the FELib Parameters for the PSD Firmware of
Digitizers 2.0
Rev. 2 - November 24th, 2022
Purpose of this User Manual
This document contains the description of the FELib parameters related to the DPP-PSD
firmware of the Digitizer 2.0 series.
Change Document Record

Date Revision Changes
July 1st, 2022 00 Initial release
September 23rd, 2022 01 Corrected some parameters name typos. Modified description of the
parameters WaveAnalogProbe0 and WaveAnalogProbe1 and
WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2,
WaveDigitalProbe3.
November 24th, 2022 02 Corrected LVDSMode parameter and Decoded Endpoints description.
Symbols, Abbreviated Terms, and Notations

ADC Analog to Digital Converter
DAQ Data Acquisition
DAW Dynamic Acquisition Window
DPP Digital Pulse Processing
GPO General Purpose Output
LVDS Low-voltage Differential Signaling
PCB Printed Board Circuit
PHA Pulse Height Analysis
PSD Pulse Shape Discrimination
PUC Product Unlock Code
TTT Trigger Time Tag
ZLE Zero Length Encoding
Reference Documents
[RD1] DS7783 – 2740/2745 Digitizer Data Sheet
[RD2] GD7897 – 2740/2745 Digitizers User Guide
https://www.caen.it/support-services/documentation-area/
Manufacturer Contact
CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. +39.0584.388.398 Fax +39.0584.388.959
www.caen.it | [email protected]
© CAEN SpA – 2022
Limitation of Responsibility
If the warnings contained in this manual are not followed, Caen will not be responsible for damage caused by
improper use of the device. The manufacturer declines all responsibility for damage resulting from failure to comply
with the instructions for use of the product. The equipment must be used as described in the user manual, with
particular regard to the intended use, using only accessories as specified by the manufacturer. No modification or
repair can be performed.
Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or
otherwise, without the prior written permission of CAEN spa.
The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies. CAEN spa reserves the right to modify its products specifications without giving any notice;
for up to date information please visit www.caen.it.
MADE IN ITALY: We remark that all our boards have been designed and assembled in Italy. In a challenging
environment where a competitive edge is often obtained at the cost of lower wages and declining working conditions,
we proudly acknowledge that all those who participated in the production and distribution process of our devices were
reasonably paid and worked in a safe environment (this is true for the boards marked "MADE IN ITALY", while we
cannot guarantee for third-party manufactures).
CAEN Electronic Instrumentation
Index
Purpose of this User Manual ...................................................................................................................... 2
Change Document Record .......................................................................................................................... 2
Symbols, Abbreviated Terms, and Notations .......................................................................................... 2
Reference Documents.................................................................................................................................. 2
Manufacturer Contact .................................................................................................................................. 2
Limitation of Responsibility ........................................................................................................................ 3
Index ........................................................................................................................................ 4
Figures ..................................................................................................................................... 6
1 Introduction ..................................................................................................................... 8
1.1.1 ChDeadtimeMonitor ..............................................................................................................................................9
1.1.2 ChTriggerCnt .........................................................................................................................................................9
1.1.3 ChSavedEventCnt.................................................................................................................................................9
1.1.4 ChWaveCnt ............................................................................................................................................................9
2 Parameters .................................................................................................................... 11
2.1 Digitizer general parameters ........................................................................................................11
2.1.1 CupVer ..................................................................................................................................................................11
2.1.2 FPGA_FwVer .......................................................................................................................................................11
2.1.3 FwType .................................................................................................................................................................11
2.1.4 ModelCode ...........................................................................................................................................................11
2.1.5 PBCode ................................................................................................................................................................11
2.1.6 ModelName ..........................................................................................................................................................12
2.1.7 FormFactor ...........................................................................................................................................................12
2.1.8 FamilyCode ..........................................................................................................................................................12
2.1.9 SerialNum .............................................................................................................................................................12
2.1.10 PCBrev_MB ....................................................................................................................................................12
2.1.11 PCBrev_PB .....................................................................................................................................................12
2.1.12 License ............................................................................................................................................................13
2.1.13 LicenseStatus .................................................................................................................................................13
2.1.14 LicenseRemainingTime.................................................................................................................................13
2.1.15 NumCh ............................................................................................................................................................13
2.1.16 ADC_Nbit ........................................................................................................................................................13
2.1.17 ADC_SamplRate ............................................................................................................................................13
2.1.18 InputRange .....................................................................................................................................................14
2.1.19 InputType ........................................................................................................................................................14
2.1.20 Zin ....................................................................................................................................................................14
2.1.21 IPAddress, Netmask, Gateway ....................................................................................................................14
2.1.22 ClockSource ...................................................................................................................................................14
2.1.23 EnClockOutP0 ................................................................................................................................................15
2.1.24 EnClockOutFP ................................................................................................................................................15
2.2 Acquistion, Trigger and VETO parameters ................................................................................16
2.2.1 StartSource ..........................................................................................................................................................16
2.2.2 GlobalTriggerSource ...........................................................................................................................................16
2.2.3 WaveTriggerSource ............................................................................................................................................17
2.2.4 EventTriggerSource ............................................................................................................................................17
2.2.5 ChannelsTriggerMask ........................................................................................................................................18
2.2.6 WaveSaving .........................................................................................................................................................18
2.2.7 TrgOutMode .........................................................................................................................................................18
2.2.8 GPIOMode ...........................................................................................................................................................19
2.2.9 BusyInSource.......................................................................................................................................................19
2.2.10 SyncOutMode .................................................................................................................................................20
2.2.11 BoardVetoSource ...........................................................................................................................................21
2.2.12 BoardVetoWidth .............................................................................................................................................21
2.2.13 BoardVetoPolarity ..........................................................................................................................................21
2.2.14 ChannelVetoSource.......................................................................................................................................21
2.2.15 ADCVetoWidth ...............................................................................................................................................22
2.2.16 RunDelay.........................................................................................................................................................22
2.2.17 EnAutoDisarmAcq..........................................................................................................................................22
2.2.18 LedStatus ........................................................................................................................................................22
2.2.19 AcquisitionStatus............................................................................................................................................23
UM8762 – FELib PSD Parameters User Manual rev. 2 4

2.2.20 MaxRawDataSize ..........................................................................................................................................23
2.2.21 EnDataReduction ...........................................................................................................................................23
2.2.22 EnStatEvents ..................................................................................................................................................23
2.2.23 VolatileClockOutDelay...................................................................................................................................24
2.2.24 PermanentClockOutDelay ............................................................................................................................24
2.3 Waveform Inspector parameters .................................................................................................25
2.3.1 WaveDataSource ................................................................................................................................................25
2.3.2 ChRecordLengthS, ChRecordLengthT ............................................................................................................25
2.3.3 WaveResolution ..................................................................................................................................................25
2.3.4 WaveAnalogProbe0 and WaveAnalogProbe1 ................................................................................................26
2.3.5 WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3 .................................26
2.3.6 ChPreTriggerS, ChPreTriggerT ........................................................................................................................26
2.4 Service parameter ..........................................................................................................................27
2.4.1 TestPulsePeriod ..................................................................................................................................................27
2.4.2 TestPulseWidth ...................................................................................................................................................27
2.4.3 TestPulseLowLevel .............................................................................................................................................27
2.4.4 TestPulseHighLevel ............................................................................................................................................27
2.4.5 IOlevel ...................................................................................................................................................................27
2.4.6 TempSensAirIn, TempSensAirOut, TempSensCore, TempSensFirstADC, TempSensLastADC,
TempSensHottestADC, TempSensADC0, TempSensADC1,…, TempSensADC7, TempSensDCDC ................28
2.4.7 VInSensDCDC, VOutSensDCDC .....................................................................................................................28
2.4.8 IOutSensDCDC ...................................................................................................................................................28
2.4.9 FreqSensCore .....................................................................................................................................................28
2.4.10 DutyCycleSensDCDC ...................................................................................................................................28
2.4.11 SpeedSensFan1, SpeedSensFan2 .............................................................................................................28
2.4.12 ErrorFlagMask, ErrorFlagDataMask............................................................................................................29
2.4.13 ErrorFlags .......................................................................................................................................................29
2.4.14 BoardReady ....................................................................................................................................................29
2.5 Individual trigger parameters .......................................................................................................30
2.5.1 ITLAMainLogic, ITLBMainLogic ........................................................................................................................30
2.5.2 ITLAMajorityLev, ITLBMajorityLev ....................................................................................................................31
2.5.3 ITLAPairLogic, ITLBPairLogic ...........................................................................................................................31
2.5.4 ITLAPolarity, ITLBPolarity ..................................................................................................................................31
2.5.5 ITLConnect ...........................................................................................................................................................31
2.5.6 ITLAMask, ITLBMask .........................................................................................................................................32
2.5.7 ITLAGateWidth, ITLBGateWidth .......................................................................................................................32
2.6 LVDS parameters ............................................................................................................................33
2.6.1 LVDSMode ...........................................................................................................................................................33
2.6.2 LVDSDirection .....................................................................................................................................................33
2.6.3 LVDSIOReg .........................................................................................................................................................33
2.6.4 LVDSTrgMask .....................................................................................................................................................33
2.7 Front Panel LEMO DAC parameters ............................................................................................35
2.7.1 DACoutMode .......................................................................................................................................................35
2.7.2 DACoutStaticLevel ..............................................................................................................................................35
2.7.3 DACoutChSelect .................................................................................................................................................35
2.8 Input signal conditioning parameters .........................................................................................36
2.8.1 VGAGain (2745 digitizers only) .........................................................................................................................36
2.8.2 EnOffsetCalibration .............................................................................................................................................36
2.8.3 ChEnable ..............................................................................................................................................................36
2.8.4 SelfTrgRate ..........................................................................................................................................................36
2.8.5 ChStatus ...............................................................................................................................................................37
2.8.6 DCOffset ...............................................................................................................................................................37
2.8.7 GainFactor............................................................................................................................................................37
2.8.8 ADCToVolts .........................................................................................................................................................37
2.8.9 TriggerThr .............................................................................................................................................................38
2.8.10 Pulse Polarity ..................................................................................................................................................38
2.9 Event Selection and Coincidence parameters ..........................................................................39
2.9.1 EnergySkimLowDiscriminator............................................................................................................................39
2.9.2 EnergySkimHighDiscriminator ...........................................................................................................................39
2.9.3 EventSelector.......................................................................................................................................................39
2.9.4 WaveSelector.......................................................................................................................................................39
2.9.5 EventNeutronReject ............................................................................................................................................39
2.9.6 WaveNeutronReject ............................................................................................................................................40
2.9.7 CoincidenceMask ................................................................................................................................................40
5 UM8762 – FELib PSD Parameters User Manual rev. 2

2.9.8 AntiCoincidenceMask .........................................................................................................................................40
2.9.9 CoincidenceLengthT, CoincidenceLengthS ....................................................................................................40
2.10 DPP-PSD parameters .....................................................................................................................41
2.10.1 ADCInputBaselineAvg ...................................................................................................................................41
2.10.2 AbsoluteBaseline ...........................................................................................................................................42
2.10.3 ADCInputBaselineGuardT, ADCInputBaselineGuardS ............................................................................42
2.10.4 SmoothingFactor ............................................................................................................................................42
2.10.5 ChargeSmoothing ..........................................................................................................................................43
2.10.6 TimeFilterSmoothing .....................................................................................................................................43
2.10.7 TriggerFilterSelection ....................................................................................................................................43
2.10.8 CFDDelayS, CFDDelayT ..............................................................................................................................43
2.10.9 CFDFraction ...................................................................................................................................................44
2.10.10 TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS .........................................................................44
2.10.11 TriggerHysteresis ...........................................................................................................................................45
2.10.12 PileupGap .......................................................................................................................................................45
2.10.13 GateLongLengthT, GateLongLengthS ........................................................................................................46
2.10.14 GateShortLengthT, GateShortLengthS ......................................................................................................47
2.10.15 GateOffsetT, GateOffsetS ............................................................................................................................47
2.10.16 LongChargeIntegratorPedestal ....................................................................................................................47
2.10.17 ShortChargeIntegratorPedestal ...................................................................................................................47
2.10.18 EnergyGain .....................................................................................................................................................47
2.10.19 NeutronThreshold ..........................................................................................................................................48
2.10.20 ChRealtimeMonitor ........................................................................................................................................48
2.10.21 ChDeadtimeMonitor .......................................................................................................................................48
2.10.22 ChTriggerCnt ..................................................................................................................................................48
2.10.23 ChSavedEventCnt .........................................................................................................................................49
2.10.24 ChWaveCnt.....................................................................................................................................................49
3 Commands .................................................................................................................... 50
3.1 Reset .................................................................................................................................................50
3.2 ClearData ..........................................................................................................................................50
3.3 ArmAcquisition ...............................................................................................................................50
3.4 DisarmAcquisition ..........................................................................................................................50
3.5 SwStartAcquisition .........................................................................................................................50
3.6 SwStopAcquisition .........................................................................................................................50
3.7 SendSWTrigger ...............................................................................................................................50
3.8 ReloadCalibration ...........................................................................................................................50
4 Endpoints ...................................................................................................................... 51
4.1 Parameters .......................................................................................................................................51
4.1.1 ActiveEndpoint .....................................................................................................................................................51
4.2 Raw Endpoints ................................................................................................................................51
4.2.1 Raw .......................................................................................................................................................................51
4.3 Decoded Endpoints ........................................................................................................................54
4.3.1 DPPPSD ...............................................................................................................................................................54
4.3.2 Statistics ...............................................................................................................................................................55
5 Flags............................................................................................................................... 57
5.1 High Priority .....................................................................................................................................57
5.2 Low Priority .....................................................................................................................................57
6 Technical Support ........................................................................................................ 58
Figures
Figure 1: Individual Trigger logic scheme........................................................................................................................................30
Figure 2: Baseline calculation as managed by the DPP‐PSD algorithm. ...................................................................................41
Figure 3: Example of smoothing over four samples. The input samples are averaged over four samples and replaced in
the smoothed samples by the mean value. ....................................................................................................................................42
Figure 4: Implementation of the Constant Fraction Discriminator. The input signal is first inverted to have a positive
arming threshold, then attenuated by a factor f, then inverted again and delayed. The resulting signal has its zero-
crossing corresponding to the set fraction f. ...................................................................................................................................44
Figure 5: Trigger Hysteresis in DPP‐PSD firmware. Any other triggers are inhibited after the over‐threshold until the input
reaches the value of half the threshold. ...........................................................................................................................................45

Figure 6: Pile‐up definition. ................................................................................................................................................................46
Figure 7: Long and short gate graphic position with respect to a couple of input pulses. The blue pulse has a longer tail 46
Figure 8: 2D scatter plot of PSD parameter vs Energy in a neutron‐gamma application. On the left the 2D plot before the
cut, on the right the plot after the cut on Neutron Threshold . ......................................................................................................48
Figure 9: 27xx digitizer general event structure. ............................................................................................................................51
Figure 10: Event aggregate in Individual Trigger Mode. ...............................................................................................................52
Figure 11: Start Run event structure. ...............................................................................................................................................52
Figure 12: DPP-PSD firmware Raw Data structure. ......................................................................................................................52
Figure 13: Stop Run word event structure. .....................................................................................................................................54

1 Introduction
CAEN Waveform digitizers x27xx introduce a new approach in the access to the firmware parameters with respect to
the previous generation V17xx, DT57xx and N67xx. Indeed, while in the previous generation x17xx the approach was
based on the direct exposition of the single firmware register, the new generation of digitizer provides an abstraction
of the register in the form of library parameters much easier to understand and use.
This new approach is meant to simplify the things for those users that are required to build their own DAQ system and
software and so need to access to the digitizer firmware parameters.
CAENFELib and CAENDig2Lib are the two libraries provided to the user.
Both are downloadable from the CAEN website and includes, in their own installation folder, the related SDK, demo
codes and documentation codes to be used to start user’s custom software development.
CAENFELib can be used to control and acquire data from the new generation CAEN digitizers. This library is just an
interface and does not include support to any digitizer family. In order to use a digitizer, the user must first install the
respective underlying library.
Existing implementation is the CAENDig2Lib (for VX2740 and other second-generation digitizers).
The following manual includes a description of the CAENFELib related to the DPP-PSD firmware and it is structured as
follows.
In the Parameters chapter the description of each single parameter is included in this form:
Parameter name
Level: Mode: Type: UoM: Min: (if present) Max: (if present)
Description of the parameter
Value
Returned value or Allowed values with the corresponding description if required.
Level: indicates the level at which the parameter is applied. It can be Channel (CH) or Digitizer (DIG), LVDS or VGA
Mode: indicates if the parameter is read-only (R) or read/write (R/W).
Type: indicates the parameter type (STRING, NUMBER, ENUM). Type doesn’t correspond to any C-type, all
CAENDig2Lib parameters are float or string.
UoM: indicates the Unity of Measurement of the parameter (if any).
Min: indicates the minimum allowed value (if present)
Max: indicated the maximum allowed value (if present)
The user should note that the CAENFELib, always works with string parameters but then they have to be interpreted in
the proper way according to the Type field.
Parameters must be used in the CAENFELib_Set/GetValue() function with the correct path form:
• For CH parameters: /ch/ChannelNumber/par/ParameteName. Parameters may be set simultaneously in
multiples channels by selecting the interval separated by “..“. E.g. /ch/0..8/par/ParameterName.
• For DIG parameters: /par/ParameterName
• For LVDS parameters: /lvds/Index/par/ParameteName. Parameters may be set simultaneously in multiples
indexes by selecting the interval separated by “..“. E.g. /lvds/0..3/par/ParameterName. Index is [0,1,2,3].
• For VGA parameters: /vga/Index/par/ParameteName. Parameters may be set simultaneously in multiples
indexes by selecting the interval separated by “..“. E.g. /vga/0..3/par/ParameterName. Index is [0,1,2,3].

In the ChRealtimeMonitor
Level: CH Mode: R Type: NUMBER UoM: 524288 ns
RealTime measured by the FPGA, incremented with step of 524288 ns. Reading this parameter updates the values of
ChDeadtimeMonitor, ChTriggerCnt, ChSavedEventCnt and ChWaveCnt.
Value
32-bit value expressed in clock cycles.
1.1.1 ChDeadtimeMonitor
DeadTime measured by the FPGA, incremented with step of 524288 ns. Updated when reading ChRealtimeMonitor.
Value
1.1.2 ChTriggerCnt
Level: CH Mode: R Type: NUMBER UoM: 1 cnt
Counter of channel triggers (24 bit), measured by FPGA. Updated when reading ChRealtimeMonitor.
Value
Eg. 1000.
1.1.3 ChSavedEventCnt
Counter of channel saved events, measured by FPGA (24 bit). Updated when reading ChRealtimeMonitor.
Value
Eg. 1000.
1.1.4 ChWaveCnt
Counter of channel events with waveform, measured by FPGA (24 bit). Updated when reading ChRealtimeMonito.
Value
Eg. 1000.
Commands chapter the description of each single command is included in this form:
Command name
Level:
Description of the command
Level: indicates the level at which the command is applied. It can be Channel (CH) or Digitizer (DIG).
Commands must be used in the CAENFELib_SendCommand() function with the correct path form:
• For CH commands: /ch/ChannelNumber/cmd/CommandName. Commands may be sent simultaneously to
multiples channel by selecting the interval separated by “..“. E.g. /ch/0..8/cmd/CommandName.
• For DIG commands: /cmd/CommandName.

In the Endpoints chapter the description of each single command is included in this form:
EndPoint name
Description of the EndPoint
Supported Fields
Default Data Format
Supported Fields: indicates which fields are supported, their native type, dimension and description.
Default Data Format: shows the corresponding format.
In the Flags chapter the description of each flag provided by the DPP_PSD firmware as additional event-wise
information is included in this form:
Flag name
Table with flag corresponding bit, name and description.
Future manual releases will include also additional schemes and guidelines about how to correlate the CAENFELib
parameter to implement specific functionalities.

2 Parameters
2.1 Digitizer general parameters
2.1.1 CupVer
Level: DIG Mode: R Type: STRING
CUP version currently in use in format “YYYYMMDDNN” there YYYY is the year, MM the month, DD the day and NN a
progressive daily index of the release.
Value
E.g “2021101800”
2.1.2 FPGA_FwVer
Build version of the FPGA firmware currently in use.
Value
E.g TBD
2.1.3 FwType
Level: DIG Mode: R Type: ENUM
Firmware type.
Value
Option Description
DPP_PHA DPP PHA firmware
DPP_ZLE DPP ZLE firmware
DPP_PSD DPP PSD firmware
DPP_DAW DPP DAW firmware
DPP_OPEN Open DPP firmware
Scope Scope firmware
2.1.4 ModelCode
CAEN model code.
Value
E.g. WV2740XAAAAA.
2.1.5 PBCode
CAEN piggyback product code.
Value
E.g. WA40BXAAAAAA.

2.1.6 ModelName
CAEN model name.
Value
E.g. V2740.
2.1.7 FormFactor
CAEN digitizer form factor.
Value
Option Description
0 VME
1 VME64X
2 DT
2.1.8 FamilyCode
Level: DIG Mode: R Type: NUMBER
CAEN family code. For example, 2740 indicates all versions of the XX2740 (VME, VME64X, desktop, SE/DIFF, etc.).
Value
E.g. 2740
2.1.9 SerialNum
CAEN serial number.
Value
E.g. 12741.
2.1.10 PCBrev_MB
PCB Revision of the Mother Board.
Value
E.g. 1
2.1.11 PCBrev_PB
PCB Revision of the Piggyback.
Value
E.g. 1

2.1.12 License
PUC (Product Unlock Code) for DPP firmware.
Value
E.g. 626C40509DD07C7880CEA247.
2.1.13 LicenseStatus
License status. Use web interface to manage the license. See [RD2].
Value
“Licensed” or “Not Licensed”.
2.1.14 LicenseRemainingTime
Level: DIG Mode: R Type: NUMBER UoM: SECONDS
Remaining time to automatic run stop in case of not licensed or invalid license. A reboot is required to start a new
acquisition.
Value
Countdown from 30 minutes.
2.1.15 NumCh
Number of input channels.
Value
E.g 64
2.1.16 ADC_Nbit
Number of bits of the ADCs.
Value
E.g. 16
2.1.17 ADC_SamplRate
Level: DIG Mode: R Type: NUMBER UoM: MS/s
Sampling rate of the ADCs.
Value
E.g. 125 MS/s

2.1.18 InputRange
Level: DIG Mode: R Type: NUMBER UoM: Vpp
Input dynamic range.
Value
E.g. 2 (Vpp).
2.1.19 InputType
Single ended or differential input type.
Value
Option Description
0 Single ended
1 Differential
2.1.20 Zin
Level: DIG Mode: R Type: NUMBER UoM: Ohm
Input impedance in Ohm.
Value
E.g. 50 Ω.
2.1.21 IPAddress, Netmask, Gateway

IPv4 network settings for the ethernet link. Useful to get the ethernet IPv4 when connected by USB.
Value
E.g. IP Address 10.105.252.100, Netmask 255.255.0.0, Gateway 10.105.254.254
2.1.22 ClockSource
Level: DIG Mode: R/W Type: ENUM
This is the source of the system clock. Multiple options are not allowed.
Value
Option Description
Internal Local oscillator, 62.5 MHz
FPClkIn Front Panel Clock input
P0ClkIn Clock from P0 VME backplane (not implemented)
Link Clock recovery from Ethernet or Optical Link (not implemented)
DIPswitchSel Clock source decided by dip switches on the board (not implemented)

2.1.23 EnClockOutP0
Enable clock output on P0 connector for the backplane propagation of the clock.
Value
Option Description
True Clock output on the P0 is enabled
False Clock output on the P0 is disabled
2.1.24 EnClockOutFP
Enable clock output on Front Panel for the daisy chain propagation of the clock between multiple boards.
Value
Option Description
True Clock output on the front panel is enabled
False Clock output on the front panel is disabled

2.2 Acquistion, Trigger and VETO parameters

2.2.1 StartSource
Defines the source for the start of run. Multiple options are allowed, separated by “|”.
Value
Option Description
EncodedClkIn Start from CLK-IN/SYNC connector on the front panel. This is a 4-pin connector
(LVDS signals) used to propagate the reference clock (typ. 62.5 MHz) and a Sync
signal. The rising edge of the Sync starts the acquisition, that lasts until the Sync
returns low (falling edge).
SINlevel Start from SIN (1=run, 0=stop)
SINedge Start from SIN (rising edge = run; stop from SW)
SWcmd Start from SW (see SwStartAcquisition)
LVDS Start from LVDS (see LVDSMode)
P0 Start from P0 (backplane)
2.2.2 GlobalTriggerSource
Defines the source for the Global Trigger, which is the signal that saves the events in the memory buffers. Multiple
options are allowed, separated by “|”.
Value
Option Description
TrgIn Front Panel TRGIN
P0 Trigger from P0 (backplane)
SwTrg Software trigger (see SendSWTrigger)
LVDS LVDS trgin (see LVDSMode)
ITLA Internal Trigger Logic A: combination of channel self-triggers (see ITLAMainLogic, ITLBMainLogic)
ITLB Internal Trigger Logic B: combination of channel self-triggers
ITLA_AND_ITLB Second level Trigger logic making the AND of ITL A and B
ITLA_OR_ITLB Second level Trigger logic making the OR of ITL A and B
EncodedClkIn Encoded CLK-IN trigger (not implemented)
GPIO Front Panel GPIO
TestPulse Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)

2.2.3 WaveTriggerSource
Level: CH Mode: R/W Type: ENUM
Allows to set the trigger source for the waveform. Setting this parameter means to get an event including the
waveform and the associated time stamp and energy information.
Value
Option Description
ITLB Internal Trigger Logic B can generate a trigger for a waveform
ITLA Internal Trigger Logic A can generate a trigger for a waveform
GlobalTriggerSource Acquisition Trigger Source (the same of the Scope mode) can generate a
trigger for a waveform
TRGIN External TRGIN can generate a trigger for a waveform
ExternalInhibit Inhibit can generate a trigger for a waveform
ADCUnderSaturation ADC Undersaturation can generate a trigger for a waveform
ADCOversaturation ADC Oversaturation can generate a trigger for a waveform
SWTrigger Software Trigger can generate a trigger for a waveform
ChSelfTrigger Channel self-trigger can generate a trigger for a waveform
Ch64Trigger One (or more) channel self-trigger can generate a trigger for a waveform
Disabled No trigger source enabled for the waveform
2.2.4 EventTriggerSource
Allows to set the trigger source for a Time-Energy (T-E) event. Setting this parameter means to get an event including
time stamp and energy information.
Value
Option Description
ITLB Internal Trigger Logic B can generate a trigger for a T-E event
ITLA Internal Trigger Logic A can generate a trigger for a T-E event
GlobalTriggerSource Acquisition Trigger Source (the same of the Scope mode) can generate a trigger
for for a T-E event
TRGIN External TRGIN can generate a trigger for a T-E event
SWTrigger Software Trigger can generate a trigger for a T-E event
ChSelfTrigger Channel self-trigger can generate a trigger for a T-E event
Ch64Trigger One (or more) channel self-trigger can generate a trigger for a T-E event
Disabled No trigger source enabled for the T-E event

2.2.5 ChannelsTriggerMask
Level: CH Mode: R/W Type: STRING
Allows to set the mask over 64 bits to generate a channel trigger. It can be used to trigger a channel using a trigger
coming from another channel.
It also allows to set the mask over 64 bits to enable the channel to participate in the coincidence logic defined in
CoincidenceMask and AntiCoincidenceMask (option Channel64Trg).
Value
64-bit enable mask, each bit representing a channel.
2.2.6 WaveSaving
Allows to save waveforms always or on request only.
Value
Option Description
Always Waveforms are always saved
On Request Waveforms are saved on request
2.2.7 TrgOutMode
Selects the signal that is routed to the TRGOUT output. Multiple options are not allowed.
Value
Option Description
Disabled TrgOutMode is disabled.
TRGIN Propagation of Front Panel TRGIN (TRGOUT is a replica, with some delay, of the
TRGIN signal)
P0 Propagation of P0 trigger (not implemented yet)
ITLA Internal Trigger Logic A: combination of channel self-triggers (see
ITLAMainLogic, ITLBMainLogic)
ITLA_AND_ITLB Second level Trigger logic making the AND of ITL A and B
EncodedClkIn Propagation of the Encoded CLK-IN trigger (not implemented yet)
Run Propagation of the RUN signal (acquisition start/stop), before applying the
delay given by the RunDelay parameter.
RefClk Monitor of the 62.5 MHz clock (used for phase alignment)
Busy Busy of the board
Fixed0 0
Fixed1 1
SyncIn SyncIn signal
SIN SIN signal
GPIO GPIO signal
AcceptTrg Accepted Triggers signal

Option Description
TrgClk Trigger Clock signal
2.2.8 GPIOMode
Select the signal that is routed to the GPIO, when this is used as output. Multiple options are not allowed. The GPIO on
the front panel is a bidirectional signal that can used in three different ways:
1) as independent board output (each board drives its own GPIO)
2) as a shared input for the boards: the signal is driven high (= 1) or low (= 0) by an external source and connected in
“short circuit” among multiple boards using “T” connectors at the inputs. The GPIO is not internally terminated, thus it
is necessary to put a 50Ω terminator at the end of the line (last “T” of the chain)
3) as a shared bidirectional line, making a “wired OR”. One or more boards can simultaneously drive the signal high (=
1). If no board drives the GPIO, it remains low (= 0). All boards can read back the signal. It is necessary to put a 50Ω
terminator at both ends of the line (first and last “T” of the chain). This mode ca be used to generate, for instance, the
global Busy and Veto logic for multiple boards.
Value
Option Description
Disabled GPIOMode is disabled.
TrgIn Propagation of Front Panel TRGIN (GPIO is a replica, with some delay, of the
TRGIN signal)
P0 Propagation of P0 trigger
SIN Propagation of SIN
ITLA Internal Trigger Logic A: combination of channel self-triggers (see ITLAMainLogic,
ITLBMainLogic)
ITLA_AND_ITL Second level Trigger logic making the AND of ITL A and B
B
EncodedClkIn Propagation of the Encoded CLK-IN trigger (not implemented)
Run Propagation of RUN
RefClk Monitor of the 62.5 MHz clock (used for phase alignment)
Busy Busy of the board
Fixed0 0
Fixed1 1
2.2.9 BusyInSource
In a multi-board system, it might be necessary to prevent one board to accept a new trigger while another board is full
and thus unable to accept the same trigger. For this reason, each board can generate a Busy signal to notify that it is
unable to get a new trigger. If the busy/veto mechanism has some latency, it is advisable generate the busy slightly
before the digitizer become full. For this purpose, it is possible to assert the busy output when the acquisition memory
reaches a programmable level of occupancy.
The OR of the busy signals is typically used to stop the global trigger. It is possible to get the individual busy signals
from each board and make an external OR logic or connect the boards with cables to propagate the Busy along the
chain. Each board makes an OR between its internal busy and the busy input signal coming from the previous board,
thus having a global Busy at the end of the line. This parameter defines the source of the Busy Input.

Value
Option Description
SIN Busy input from SIN on front panel
GPIO Busy input coming from GPIO on front panel, used as a simple input. It is also
possible to use GPIO as a wired OR (bidirectional), as described in GPIOMode. In
this mode, the Busy line goes high as soon as one board drives it high. All the
boards can read the Busy line and use it as a veto for the trigger (see
BoardVetoSource)
Disabled The Busy is given by the Internal Busy only (Memory full or almost full)
2.2.10 SyncOutMode
In a multi-board system, it can be useful to propagate a synchronous signal together with the clock (to synchronize the
start of the run, for example) on CLK OUT front panel connector [RD1]. This parameter defines which signal must be
sent out. Multiple options are not allowed.
Value
Option Description
Disabled SyncOutMode is disabled
SyncIn SyncIn signal (if provided with clkIn on CLK IN connector [RD1])
IntClk Internal 62.5 MHz clock
Run Propagation of RUN

2.2.11 BoardVetoSource
Defines the source for the Veto, which is the signal that inhibits the acquisition trigger. Multiple options are allowed,
separated by “|”. The VETO signal can be either active high or low, depending on the BoardVetoPolarity parameter.
When active low, it acts as a GATE for the trigger. It is possible to stretch the duration of the VETO by means of the
parameter.
Value
Option Description
SIN SIN on the front panel
GPIO GPIO on the front panel (used as input)
P0 P0 (signal from the backplane)
EncodedClkIn Encoded CLK-IN veto (not implemented)
Disabled VETO is always OFF
2.2.12 BoardVetoWidth
Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 34359738360
Whatever is the source of the VETO signal, it is possible to stretch the duration of the veto up to a given time by means
of a re-triggerable monostable. Expressed in ns. When 0, the monostable is disabled and the veto lasts as long as the
selected source is active
Value
E.g. 2000 ns
2.2.13 BoardVetoPolarity
Defines the polarity of the Veto.
Value
Option Description
ActiveHigh Veto is active high. The signals acts as an “Inhibit” for the trigger
ActiveLow Veto is active low. The signals acts as a “Gate” the trigger
2.2.14 ChannelVetoSource
Allows to set the veto for each channel; it can be external (which means one of the veto options in the previous table),
or it can be on a channel base.
Value
Option Description
BoardVeto Enables board veto
ADCOverSaturation Enables veto due to ADC oversaturation
ADCUnderSaturation Enables veto due to ADC undersaturation
Disabled Any channel veto source is disabled

2.2.15 ADCVetoWidth
Level: CH Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 524280
It is the width of the ADC veto (undersaturation and oversaturation width) expressed in ns.
Value
E.g. 2000 ns
2.2.16 RunDelay
When the start of run is controlled by a RUN signal that is propagated in daisy chain between the boards (for instance
through the ClkIn-ClkOut or SIN-GPIO sync chain), it is necessary to compensate for the propagation delay and let the
boards to start exactly at the same time. The Run Delay parameter allow the start of the acquisition to be delayed by a
given number of clock cycles with respect to the rising edge of the RUN signal. Assuming that the propagation delay is 2
cycles, the RunDelay setting will be 0 for the last board in the chain, 2 for the previous one, and so on up 2*(NB-1) for
the first one.
Value
E.g. 20 ns
2.2.17 EnAutoDisarmAcq
When enabled, the Auto Disarm option disarms the acquisition at the stop of run. When the start of run is controlled
by an external signal, this option prevents the digitizer to restart without the intervention of the software.
Value
Option Description
True The acquisition is automatically disarmed after the stop. It is therefore necessary
to rearm the digitizer (with the relevant command sent by the software) before
starting a new run.
False The acquisition is not disarmed after the stop. Multiple transition of the start
signal will produce multiple runs.
2.2.18 LedStatus
Get a 32-bit word representing the LEDs status of the digitizer.
Value
Bit Number Name
0 LED_JESD_Y_PASS
1 LED_JESD_H_PASS
2 LED_DDR4_0_PASS
3 LED_DDR4_1_PASS
4 LED_DDR4_2_PASS
5 LEDFP_FAIL
6 LEDFP_NIM
7 LEDFP_TTL
8 LEDFP_DTLOSS
9 LEDFP_DTRDY
10 LEDFP_TRG

Bit Number Name
11 LEDFP_RUN
12 LEDFP_PLL_LOCK
13 LEDFP_CLKOUT
14 LEDFP_CLKIN
15 LEDFP_USB
16 LEDFP_SFP_SD
17 LEDFP_SFP_ACT
18 LEDFP_ACT
19-31 Not Used
2.2.19 AcquisitionStatus
Get a 32-bit word representing the acquisition status of the digitizer.
Value
Bit Number Name
0 Armed
1 Run
2 Run_mw
3 Jesd_Clk_Valid
4 Busy
5 PreTriggerReady
6 LicenceFail
7-31 Not Used
2.2.20 MaxRawDataSize
Level: DIG Mode: R Type: NUMBER UoM: byte
Maximum size that can be returned from a single call to GetData from the raw endpoint (see Chap. 4). This parameter
should be read at the end of the configuration.
Value
E.g. 2621440 bytes
2.2.21 EnDataReduction
Level: DIG Mode: R/W Type: STRING
If enabled, events consisting of 2 words are compressed in a single word event.
Value
Option Description
False Data reduction is disabled.
True Data reduction is enabled.
2.2.22 EnStatEvents
If enabled, stats events are generated.

Value
Option Description
False Stats event generation is disabled.
True Stats event generation is enabled.
2.2.23 VolatileClockOutDelay
Level: DIG Mode: R/W Type: NUMBER UoM: ps Min: -18888.888 Max: 18888.888
Sets the delay of the clock output with respect to the input reference clock. When the clock is distributed between
multiple boards in daisy chain (typ. through CLKIN-CLKOUT connectors), this option allows for compensation of the
propagation delay and fine alignment of the clock phases. This setting is directly writing into the PLL registers and is not
permanent. Once the good setting has been found, use the parameter PermanentClockOutDelay to store the delay in
the flash memory and automatically reload it at every power-up.
Value
E.g. 148.148 ps.
2.2.24 PermanentClockOutDelay
Level: DIG Mode: R/W Type: NUMBER UoM: ps Min: -18888.888 Max: 18888.888
Sets the Value
Option Description
False Data reduction is disabled.
True Data reduction is enabled.
EnStatEvents
If enabled, stats events are generated.
Value
Option Description
False Stats event generation is disabled.
True Stats event generation is enabled.
VolatileClockOutDelay, stores the value into the filesystem and makes it permanent.
When read, it returns the value of the delay stored in the filesystem, that may differ from the one currently applied, if
volatile. Steps of 74.074 ps
Value
E.g. 148.148 ps.

2.3 Waveform Inspector parameters

2.3.1 WaveDataSource
In normal mode, the acquired waveform represents a sequence of ADC samples, resulting from the A/D conversion of
the analog input. For test purposes, it is possible to replace the ADC data with internal data generators.ù
Value
Option Description
ADC_DATA Data from the ADC (normal operating mode)
ADC_TEST_TOGGLE Set the ADC to produce a Toggle signal
ADC_TEST_RAMP Set the ADC to produce a Ramp signal
ADC_TEST_SIN Set the ADC to produce a Sinusoidal signal
IPE (not implemented)
Ramp Data from a ramp generator (16 bit: 6 most significant bit for the channel
codification + 10 bit for the Ramp signal)
SquareWave Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)
ADC_TEST_PRBS
2.3.2 ChRecordLengthS, ChRecordLengthT

Level: CH Mode: R/W Type: NUMBER UoM: sample/ns Min: 4/32 Max: 8100/64800
The waveform size. Integer representing the number of samples (“S” option) or the time in ns (“T” option). The actual
size of the waveform will be automatically rounded to the closest allowed value. It is possible to get the exact size by
reading back the parameter. The record length in time depends on wave resolution.
Value
E.g. 32000
2.3.3 WaveResolution
Allows to set the waveform resolution.
Value
Option Description
Res8 8ns
Res16 16ns
Res32 32ns
Res64 64ns

2.3.4 WaveAnalogProbe0 and WaveAnalogProbe1

Allows to set the analog signal for the analog probe 0 and 1.
Value
Option Description
ADCInput, ADC input probe
ADCInputBaseline ADC input baseline probe
CFDFilter Constant Fraction Discriminator filter probe
2.3.5 WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2,

WaveDigitalProbe3
Allows to select the logical signal for digital probe 0, 1, 2 and 3.
Value
Option Description
Trigger Trigger probe
CFDFilterArmed Constant Fraction Discriminator Filter Armed probe
ReTriggerGaurd ReTrigger Guard probe
ADCInputBaselineFreeze ADC Input Baseline Freeze probe
ADCInputOverthreshold ADC Input Overthreshold probe
ChargeReady Charge Ready probe
LongGate Long Gate probe
PileUpTrigger Pile Up Trigger probe
ShortGate Short Gate probe
ChargeOverRange Integrated Charge Over Range probe
ADCSaturation ADC Saturation probe
ADCInputNegativeOverthre ADC Input Negative Overthreshold probe
shold
2.3.6 ChPreTriggerS, ChPreTriggerT

Level: CH Mode: R/W Type: NUMBER UoM: sample/ns Min: 4/32 Max: 1000/8000
Number of samples coming before the position of the trigger in the waveform (i.e. size of the pre-trigger window).
Value
E.g. 800/3200.

2.4 Service parameter

2.4.1 TestPulsePeriod
The Test Pulse is a programmable square wave that can be used as an internal periodic trigger (mainly for test
purposes) or to generate a logic test pulse (TTL or NIM) on the TRGOUT and GPIO outputs. The actual value will be
rounded to 8 ns.
Value
E.g 1000 ns.
2.4.2 TestPulseWidth
Width (i.e. the time the signal stays high = 1) of the test pulse in nanoseconds (ns). The actual value will be rounded to
8 ns. See TestPulsePeriod.
Value
E.g 1000 ns.
2.4.3 TestPulseLowLevel
Level: DIG Mode: R/W Type: NUMBER UoM: ADC counts Min: 0 Max: 65535
Low level of the test pulse. See TestPulsePeriod.
Value
E.g. 0.
2.4.4 TestPulseHighLevel
Level: DIG Mode: R/W Type: NUMBER UoM: ADC counts Min: 0 Max: 65535
High level of the test pulse. See TestPulsePeriod.
Value
E.g. 10000.
2.4.5 IOlevel
Sets the electrical logic level of the LEMO I/Os (TRGIN, SIN, TRGOUT, GPIO). NOTE: TRGIN and SIN are 50 Ω terminated,
GPIO and TRGOUT require 50 Ω termination at the receiver.
Value
Option Description
NIM NIM logic (0=0V, 1=-0.8V, that is -16mA)
TTL Low Voltage TLL logic (0=0V, 1=3.3V)

2.4.6 TempSensAirIn, TempSensAirOut, TempSensCore, TempSensFirstADC,

TempSensLastADC, TempSensHottestADC, TempSensADC0,
TempSensADC1,…, TempSensADC7, TempSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Celsius degrees Min: 0 Max: null
Various sensors monitoring the temperature of the incoming (TempSensAirIn) and outcoming (TemSensAirOut) air flow
of the board, at the FPGA core (TempSensCore), at the first, the last and the ottest ADC component
(TempSensFirstADC, TempSensLastADC, TempSensHottestADC), at the first and second ADC sensor (TempSensADC0,
TempSensADC1,.., TemSensADC7), and at the DC-DC converter (TempSensDCDC). The resolution is 0.1 °C.
Value
E.g. 40.7 (°C).
2.4.7 VInSensDCDC, VOutSensDCDC

Level: DIG Mode: R Type: NUMBER Units: Volts Min: 0 Max: null
Sensors monitoring the input and output voltage of the DC-DC converter. The resolution is 0.001 V
Value
E.g. 4.997 (V).
2.4.8 IOutSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Ampere Min: 0 Max: null
Sensor monitoring the DC-DC converter current. The resolution is 0.001 A.
Value
E.g. 7.570 (A).
2.4.9 FreqSensCore
Level: DIG Mode: R Type: NUMBER Units: Hertz Min: 0 Max: null
Frequency of the DCDC converter. The resolution is 0.1 Hz.
Value
E.g. 800 (Hz).
2.4.10 DutyCycleSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Percentage Min: 0 Max: null
Duty cycle of the DCDC converter. The resolution is 0.1 %.
Value
E.g. 14.8 (%).
2.4.11 SpeedSensFan1, SpeedSensFan2

Level: DIG Mode: R Type: NUMBER Units: Rpm Min: 0 Max: null
Sensors monitoring the fan speed (desktop modules only). The resolution is 1 rpm.
Value
E.g. 2700 (rpm).

2.4.12 ErrorFlagMask, ErrorFlagDataMask

There are several error sources in the digitizer, mainly coming from the internal health monitoring system
(temperature, current, etc..), but also from FPGA data consistency checking and others. All these errors can be
combined into a error flag mask through a masked OR, programmed by this parameter. The ErrorFlagMask drives the
relevant LED on the front panel, while ErrorFlagDataMask drives the error flag bit in the event.
Value
32-bit integer, where each bit meaning is explained in the table below. Other bits currently unused.
Bit Description
0 power_fail
1 board_init_fault
2 si5341_unlock
3 si5395_unlock
4 LMK04832_unlock
5 jesd_unlock
6 ddr_pl_bank0_calib_fail
7 ddr_pl_bank1_calib_fail
8 ddr_ps_calib_fail
9 fpga_config_fail
10 bic_error
11 adc_overtemp
12 air_overtemp
13 fpga_overtemp
14 dcdc_overtemp
15 clkin_miss
16 adc_shutdown
2.4.13 ErrorFlags
Reads the status of the error flags.
Value
See ErrorFlagMask, ErrorFlagDataMask fields.
2.4.14 BoardReady
Check if there is any error set in ErrorFlags.
Value
Option Description
True True means ErrorFlags is zero
False Otherwise

2.5 Individual trigger parameters

2.5.1 ITLAMainLogic, ITLBMainLogic
Each channel of the digitizer feature a digital Constant Fraction Discriminator (CFD with programmable fraction, delay
and threshold (see CFDFraction, CFDDelayS, CFDDelayT and TriggerThr) able to self-trigger on the input pulses and
generate a self-trigger signal. In PSD Mode, the channels acquire independently, so the channel self-trigger is used
locally to acquire a waveform. The trigger threshold is then referred to the CFD filter, and the threshold crossing arms
the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the CFD trace on the
signal inspector.
It is also possible to combine all the self-triggers of the board (64 lines in the case of the V2740/2745), according to a
specific trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to
feed, for instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex
trigger schemes (see GlobalTriggerSource and TrgOutMode). Therefore, the ITLs can either generate the local
acquisition trigger, common to all the channels, for the acquisition of the waveform, or propagate the signal outside,
through the TRGOUT, thus making it possible to combine triggers of multiple boards in an external trigger logic, that
eventually feeds back the TRGIN of the digitizers.
Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self-
triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 self-
triggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable
gate generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).
ITL Mask: 64 bit
PairMode: AND, OR, NONE
ITL Mode: AND, OR, MAJ
SELF-TRG[0]
PAIR
LOGIC
SELF-TRG[1]
Width in ns (0 = Linear)
SELF-TRG[2]
Retriggerable: True, False
PAIR
LOGIC Polarity: DIRECT, INVERTED
SELF-TRG[3]
ENABLE MASK
MAIN
ITLOUT
TRG GATE POLARITY
LOGIC
SELF-TRG[62]
PAIR
SELF-TRG[63] LOGIC
Figure 1: Individual Trigger logic scheme.
Value
Option Description
OR ITLOUT = masked OR of channel self-triggers
AND ITLOUT = masked AND of channel self-triggers
Majority ITLOUT = masked Majority of channel self-triggers

2.5.2 ITLAMajorityLev, ITLBMajorityLev

Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 1 Max: 63
Defines the majority level of the Main Logic of the ITL A and B. The majority output is calculated at every clock cycle
and it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycles and
MajLev is the programmed majority level. NOTE: when the Pair Logic is used to combine the self-triggers two by two
(AND/OR), each pair produces two identical signals that will be counted twice in the majority level
Value
E.g 10.
2.5.3 ITLAPairLogic, ITLBPairLogic

Pairs of channels can be combined with an OR or AND before feeding the Main trigger Logic. When the AND/OR logic is
applied, the two outputs of the Pair Logic blocks are identical. Please note that they are counted twice in the following
Majority logic. If the Pair Logic is disabled (option “NONE”), the block is transparent, and the two outputs are just a
replica of the inputs.
Value
Option Description
OR Both Pair Logic Outputs = OR of two consecutive self-triggers
AND Both Pair Logic Outputs = AND of two consecutive self-triggers
NONE Outputs = Inputs
2.5.4 ITLAPolarity, ITLBPolarity

Indicate the polarity of the ITLA/ITLB Enable Mask at the input of the ITLB.
Value
Option Description
Direct Polarity of the ITLA/ITLB is direct.
Inverted Polarity of the ITLA/ITLB is inverted.
2.5.5 ITLConnect
Level: CH Mode: R/W Type: STRING Index:[0:63]
Alternative to ITLAMAsk, ITLBMask. Determines if the channel partecipate in ITLA or ITLB.
Value
Option Description
Disabled The channel is disabled.
ITLA The channel participates in ITLA logic block.
ITLB The channel participates in ITLB logic block.

2.5.6 ITLAMask, ITLBMask

Enable Mask at the input of the ITLA/ITLB. Enable Mask at the input of the ITLA/ITLB. The user should pay attention to
the fact that the use of this parameter overwrites the ITLConnect settings. The two cannot be used at the same time.
Value
2.5.7 ITLAGateWidth, ITLBGateWidth

Width of the gate generator at the output of the ITLs. Steps of 8 ns.
Value
E.g 1000 ns

2.6 LVDS parameters

2.6.1 LVDSMode
Level: LVDS Mode: R/W Type: ENUM
The digitizer has 16 LVDS I/Os that can be programmed to be inputs or outputs in groups of 4 (quartets), depending on
the parameter LVDSDirection). Once the direction has been selected, it is possible to select the functionality of the
LVDS lines, individually for each quartet.
Value
Option Description
SelfTriggers Each LVDS line can be assigned to a combination of the 64 self-triggers,
implemented as a masked OR, where the mask is set by the parameter
LVDSTrgMask (16 independent masks, one per LVDS line)
Sync Whatever is the direction of the quartet, the 4 lines are rigidly assigned to
specific acquisition signals:
0=Busy; 1=Veto; 2=Trigger; 3=Run
It is possible to implement a daisy chain distribution of these signals using one
quartet as input and another one as output
IORegister The LVDS lines of the quartet are statically controlled by the parameter
LVDSIOReg. Use the SetValue function to set the relevant LVDS lines when
programmed as output. Use GetValue to read the status of the LVDS lines when
programmed as inputs.
2.6.2 LVDSDirection
Level: LVDS Mode: R/W Type: ENUM
Assigns the direction of a quartet of LVDS I/Os.
Value
Option Description
Input The LVDS lines of the relevant quartet are used as input. The relevant LED on the
front panel is OFF
Output The LVDS lines of the relevant quartet are used as output. The relevant LED on
the front panel lights-up.
2.6.3 LVDSIOReg
Set the status of the LVDS I/O for the quartets that are programmed to be output and Mode = IORegister.
Value
16-bit value representing the status of the LVDS I/Os (either for writing or reading).
2.6.4 LVDSTrgMask
Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask
is set by this parameter. There are 16 independent masks, one per LVDS line. NOTE: the trigger mask assignment does
not imply the LVDS direction and mode settings. It is therefore necessary to set the Direction = Output and Mode =
SelfTriggers to use the Self-Trigger propagation to the LVDS I/Os.
Value

Each independent mask can be set using a string in the format "<mask ID in the range [0, 15]>=<64-bit integer>" as
value. Integers are internally parsed using C++ std::stoul, so you can use 0x prefix for hexadecimal or 0 for octal.
For example:
CAEN_FELib_SetValue(root_handle, "/par/lvdstrgmask", "7=0xf0f0f0f0f0f0f0f0");
Each independent mask can be get by writing the mask ID in the value string that is passed to the
CAEN_FELib_GetValue, and the function will overwrite it with the value.
For example:
char value[256] = "7";
CAEN_FELib_GetValue(root_handle, "/par/lvdstrgmask", value);

2.7 Front Panel LEMO DAC parameters

2.7.1 DACoutMode
Select the signal type to be sent in output on the front panel DAC connector.
Value
Option Description
Static DAC output stays at a fixed level, given by the parameter DACoutStaticLevel
IPE (not implemented)
ChInput The DAC reproduces the input signal received by one input channel, selected by
the parameter DACoutChSelect
MemOccupancy Level of the memory occupancy (not yet implemented)
ChSum The DAC reproduces the “analog” sum of the of all the digitizer inputs.
OverThrSum The DAC output is proportional to the number of channels that are currently
above the threshold
Ramp The DAC output is driven by a 14-bit counter
Sin5MHz The DAC output is a sine wave at 5 MHz with fixed amplitude
Square Square wave with period and width set by TestPulsePeriod and
TestPulseWidth and amplitude between TestPulseLowLevel and
TestPulseHighLevel.
2.7.2 DACoutStaticLevel
Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 0 Max 16383
When the DACoutMode = Static, the DAC generates a static output.
Value
E.g 1000
2.7.3 DACoutChSelect
Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 0 Max 63
When the DACoutMode = ChInput, the DAC reproduces the inputs signal received by a selected channel.
Value
Selected channel index.

2.8 Input signal conditioning parameters

2.8.1 VGAGain (2745 digitizers only)
Level: VGA Mode: R/W Type: NUMBER Index: [0, 1, 2, 3] UoM: dB Min: 0 Max: 40
Sets the gain of the Variable Gain Amplifiers (VGA) in steps of 0.5 dB. The gain is set commonly to a group of 16
channels depending on the Index: Index[0] means CH0-CH15.
Value
E.g. 1 (dB).
2.8.2 EnOffsetCalibration
The input DCoffset that determines the position of the signal baseline (zero volt) is controlled by individual channel
DACs. Due to the tolerance of the components, there is some spread in the offset setting that is compensated by the
offset calibration. This is normally enabled and automatically applied in the firmware of the board. The calibration can
be disabled, mainly when a new calibration has to be calculated.
Value
Option Description
True DC offset calibration is applied (default)
False DC offset calibration is not applied
2.8.3 ChEnable
Allows to enable/disable a channel. If the Run is already set, ch_enable starts the acquisition.
Value
Option Description
True The channel is enabled for the acquisition
False The channel is disabled for the acquisition
2.8.4 SelfTrgRate
Level: CH Mode: R Type: NUMBER
Each channel has a 32-bit counter permanently connected to its self-trigger. This parameter allows to read the channel
self-trigger rate in Hertz (Hz).
Value
Eg. 1000 Hz.

2.8.5 ChStatus
Level: CH Mode: R Type: ENUM
Gets a 32-bit word representing the status of the acquisition.
Value
Bit Description
0 Channel signal delay initialization status (1 = initial delay done)
1 Channel time filter initialization status (1 = time filter initialization done)
2 Channel energy filter initialization status (1 = energy filter initialization done)
3 Channel full initialization status (1 = initialization done)
4 Reserved
5 Channel enable acquisition status (1 = acq enabled)
6 Channel inner run status (1 = run active)
7 Time-energy event free space status (1 = time-energy can be written)
8 Waveform event free space status (1 = waveform can be written)
9 : 31 Not used
2.8.6 DCOffset
Level: CH Mode: R/W Type: NUMBER UoM: percentage Min: 0 Max: 100
A constant DC offset (controlled by a 16-bit DAC) is added to the analog input, individually for each channel, in order to
adjust the position of the signal baseline (that is the “zero volt” of the analog input) within the dynamic range of the
ADC. Because of the tolerance of the components, it is necessary to calibrate the offset DAC. The calibration is done by
factory testing and normally it is not necessary to recalibrate the digitizer. It is however possible to perform a new
calibration. The calibration parameters are stored in the flash memory of the board and loaded at power on. They are
automatically applied by the internal logic every time the parameter DCoffset is written or read. DCoffset expressed as
a float number, in percent of the full scale. When the DC offset is 0, the baseline of the input signal is at 0 ADC counts.
When the DC offset is 100, the baseline of the input signal is at 2 NBIT-1 ADC counts.
Value
E.g 50 %.
2.8.7 GainFactor
Level: CH Mode: R
Read the gain ADC calibration value stored in the internal flash. This value can be used by the user in its own DAQ
software to calibrate the ADC and provide the signal amplitude value in mV units.
Value
E.g 1.010591
2.8.8 ADCToVolts
Level: CH Mode: R Type: NUMBER UoM: Volts
Factor to convert ADC counts to volts. It is a more sophisticated version of the inverse of the GainFactor that takes into
account also the value of the VGAGain (2745 digitizers only). While GainFactor is a fixed value, ADCToVolts provides
the current value to be applied to convert ADC into Volts.
Value
E.g 0.000031

2.8.9 TriggerThr
Level: CH Mode: R/W Type: NUMBER UoM: units Min: 0 Max 8191
Each channel of the digitizer features a Leading Edge and a digital Constant Fraction (TimeFilterSmoothing
TriggerFilterSelection, CFDDelayS, CFDDelayT CFDFraction) and threshold able to self-trigger on the input pulses and
generate a self-trigger signal feeding the internal trigger logics or digitizer outputs. This parameter sets the trigger
threshold. In case of the CFD discriminator the trigger threshold is then referred to the CFD signal itself, and the
threshold crossing arms the event selection. The trigger fires at the zero crossing of the bipolar signal. The user can see
the bipolar trace on the signal inspector. Threshold value in counts is referred to the Time Filter. It is a 13-bit signed
number.
Value
E.g 52.
2.8.10 Pulse Polarity

Allows to set the polarity of the input pulse.
Value
Option Description
Positive Positive polarity
Negative Negative polarity

2.9 Event Selection and Coincidence parameters

2.9.1 EnergySkimLowDiscriminator
Allows to flag events with energy higher than the low skim threshold. 16-bit value.
Value
E.g. 1000.
2.9.2 EnergySkimHighDiscriminator
Allows to flag events with energy lower than the high skim threshold. 16-bit value.
Value
E.g 2000.
2.9.3 EventSelector
Allows to set which events have to be saved.
Value
Option Description
All All events are saved
Pileup Only pileup events are saved
EnergySkim Save only the events in the Energy skim range
2.9.4 WaveSelector
Allows to set which waveform have to be saved.
Value
Option Description
All All waves are saved
Pileup Only pileup waves are saved
EnergySkim Save only waves in the EnergySkim range
2.9.5 EventNeutronReject
Enable Neutron Rejection for Events. See NeutronThreshold.
Value
Option Description
Disabled Neutron rejection for events is disabled.
Enabled Neutron rejection for events is enabled.

2.9.6 WaveNeutronReject
Enable Neutron Rejection for Waves. See NeutronThreshold.
Value
Option Description
Disabled Neutron rejection for waves is disabled.
Enabled Neutron rejection for waves is enabled.
2.9.7 CoincidenceMask
Allows to set the coincidence mask that generates a trigger on the specified channel.
Value
Option Description
Disabled All the coincidence sources are disabled
Ch64Trigger One of the 64 channels can generate a coincidence signal
TRGIN TRGIN can generate a coincidence signal
GlobalTriggerSource Acquisition Trigger can generate a coincidence signal
ITLA ITLA can generate a coincidence signal
ITLB ITLB can generate a coincidence signal
2.9.8 AntiCoincidenceMask
Allows to set the anticoincidence mask that generates a trigger on the specified channel.
Value
Option Description
Disabled All the anticoincidence sources are disabled
Ch64Trigger One of the 64 channels can generate an anticoincidence signal
TRGIN TRGIN can generate an anticoincidence signal
GlobalTriggerSource Acquisition Trigger can generate an anticoincidence signal
ITLA ITLA can generate an anticoincidence signal
ITLB ITLB can generate an anticoincidence signal
2.9.9 CoincidenceLengthT, CoincidenceLengthS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 8/1 Max: 524280/65535
Coincidence window length in nanoseconds (ns) or samples (S). 16-bit value.
Value
E.g 800 ns/100 samples.

2.10 DPP-PSD parameters

2.10.1 ADCInputBaselineAvg
The digitizer continuously receives the input signal and digitizes it. The position of the signal baseline can be adjusted in
the ADC scale to exploit the full dynamics of the digitizer using the DCOffset parameter. The baseline value is an
important parameter of the DPP‐PSD firmware, since its value is used as a reference value for the charge integration of
the input pulses. Moreover, most of the DPP parameters are related to the baseline value, like the trigger threshold.
The user can set either a fixed value for the baseline or let the DPP firmware calculate it dynamically. In the first case
the user must set the baseline value in LSB units through the option Fixed. This value remains fixed for the entire
acquisition run. In the latter case, the firmware dynamically evaluates the baseline as the mean value of N points inside
a moving time window. The user can choose one of the below listed option each of them corresponding to a
predefined number of samples. The baseline is then frozen from few clocks before the gates start, up to the end of the
maximum value between the long gate and the trigger hold‐off (see GateLongLengthT, GateLongLengthS and
TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS)
Figure 2 shows how the baseline calculation and freeze work. The trigger threshold dynamically follows the baseline
variations. Note that in case of overshoots before the charge integration, the baseline can be distorted and the
reference for the trigger threshold might not be accurate. In that case it might be more convenient to use the fixed
baseline value.
Figure 2: Baseline calculation as managed by the DPP‐PSD algorithm.
This parameter allows to set the Number of samples used to average the baseline of the Energy Filter.
Value
Option Description
Fixed Baseline fixed at AbsoluteBaseline value
Low Baseline samples for average = 16
MediumLow Baseline samples for average = 64
MediumHigh Baseline samples for average = 256
High Baseline samples for average = 1024

2.10.2 AbsoluteBaseline
Level: CH Mode: R/W Type: NUMBER UoM: sample Min: 0 Max: 65535
Absolute value of the ADCInput signal baseline.
Value
E.g 32000 samples
2.10.3 ADCInputBaselineGuardT, ADCInputBaselineGuardS

Energy Filter Baseline Evaluation Guard before the integration gate open in nanoseconds (ns) or samples (S).
Value
2.10.4 SmoothingFactor
The smoothing is a moving average filter, where the input samples are replaced by the mean value of the previous n
samples, where n is: 2, 4, 8 and 16 samples. When enabled (see TimeFilterSmoothing), the trigger is applied on the
smoothed samples, thus reducing triggering on noise. Both CFD and LED triggering modes can be used on the
smoothed input. The charge integration is either performed on the input samples and/or on the smoothed samples,
according the ChargeSmoothing parameter.
Figure 3: Example of smoothing over four samples. The input samples are averaged over four samples and replaced in the
smoothed samples by the mean value.
Value
Option Description
1 Smoothing is disabled.
2 Smoothing is done averaging 2 samples.

2.10.5 ChargeSmoothing
Enable/Disable Smoothing factor for the charge evaluation.
Value
Option Description
Enabled Smoothing factor is enabled in the harge evaluation
Disabled Smoothing factor is disabled in the charge evaluation
2.10.6 TimeFilterSmoothing
Enable/Disable Smoothing factor for the time filter.
Value
Option Description
Enabled Smoothing factor is enabled for the time filter.
Disabled Smoothing factor is disabled for the time filter.
2.10.7 TriggerFilterSelection
The DPP‐PSD allows the user to select the pulses according to two methods: leading edge, where a pulse is identified
when its samples crosses a programmable threshold value, or through a digital constant fraction discrimination to have
a better timing information. In both cases once the event is selected, the signal is delayed by a programmable number
of samples (corresponding to the “pre‐trigger” value in ns) to be able to integrate the pulse before the trigger
(“Pre‐Gate”). The gates for charge integration are then generated and received by the charge accumulator before the
signal. While the gates are active, the baseline remains frozen until the last averaged value and its value is used as
charge integration reference. For the whole duration of a programmable “retrigger guard” (see
TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS) value, other trigger signals are inhibited. It is recommended to
set a trigger hold‐off value compatible with the signal width. The baseline remains frozen for the whole trigger hold‐off
duration.
This parameter allows to set the Leading Edge or Constant Fraction Discriminator Filter selection.
Value
Option Description
LeadingEdge Set the Leading Edge discriminator
CFD Set the Constant Fraction discriminator
2.10.8 CFDDelayS, CFDDelayT

The x27xx digitizer running the DPP_PSD firmware discriminates events based on a CFD signal.
The digital CFD signal has been implemented in the classical way except for the input signal inversion. The input
waveform is first inverted, then attenuated by a factor f equal to the desired timing fraction (see CFDFraction) of full
amplitude, then the signal is inverted again and delayed by a time d equal to the time it takes the pulse to rise from the
constant fraction level to the pulse peak; the latest two signals are summed to produce a bipolar pulse, the CFD, and its
zero crossing – corresponding to the fraction f of the input pulse – is taken as the trigger time.

Figure 4: Implementation of the Constant Fraction Discriminator. The input signal is first inverted to have a positive arming
threshold, then attenuated by a factor f, then inverted again and delayed. The resulting signal has its zero-crossing corresponding
to the set fraction f.
The delay of the CFD signal can be defined by the user in the range 32 to 8184 ns. The TriggerThreshold is then
referred to the CFD itself, and the threshold crossing arms the event selection.
The trigger fires at the zero crossing of the derivative signal itself.
Value
E.g. 20 ns/5 samples.
2.10.9 CFDFraction
Level: CH Mode: R/W Type: NUMBER UoM: % Min: 25 Max: 100
CFD Fraction.
Value
E.g. 25%.
2.10.10 TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS

This parameter allows to set a retrigger inhibit guard (in ns or samples). 10-bit value.
Value

2.10.11 TriggerHysteresis
When the input signal is no more over‐threshold, the trigger could fire again in the tail of the pulse, especially in case
the tail contains spikes or noise. The “Trigger Hysteresis” feature inhibits any trigger until the input pulse reaches half
of the threshold value itself. See for a diagram of this feature. This parameters allows to Enable/Disable Trigger
hysteresis mechanism.
Figure 5: Trigger Hysteresis in DPP‐PSD firmware. Any other triggers are inhibited after the over‐threshold until the input reaches
the value of half the threshold.
Value
Option Description
Disabled Trigger hysteresis mechanism is disabled.
Enabled Trigger hysteresis mechanism is enabled.
2.10.12 PileupGap
Level: CH Mode: R/W Type: NUMBER UoM: sample Min: 0 Max: 65535
The DPP‐PSD firmware is mainly designed to work with fast signals like those coming from scintillation detectors
coupled with Photomultiplier Tubes. The relevant output signals do not show long decay tails as in the case of charge
sensitive preamplifiers, and the probability of pile‐up between two pulses is quite low. In particular, the case of a
second pulse sitting on the exponential tail of the previous one is rather rare. However, with the PSD algorithm, it is
important to separate fast and slow components of the light emitted by the scintillation detector. Typically, the fast
component is a quick pulse (few tens of ns) while the slow component is a quite long tail (typically a few μs) having
amplitude much smaller than the fast component. To get the best results in the pulse shape discrimination, it is
necessary to set the “Long Gate” as long as the full duration of the slow component. Under these conditions, most likely
the events in pile‐up occur during the long gate and cause an error in the calculation of the charge of the slow
component. For this reason, it is important to detect these cases.
In the DPP‐PSD firmware, two events are considered in pile‐up when there is a situation of peak‐valley‐peak inside the
same gate, where the gap between the valley and the peak is a programmable value. Referring to Figure 6, when the
peak value is reached the algorithm evaluates the point corresponding to the PileupGap (PUR-GAP) value and gets
ready to detect a pile‐up event (PILE‐UP ARMED). If there is a condition of “valley”, and the input signal overcomes the
PUR‐GAP threshold, then the event is tagged as pile‐up. In the default configuration the firmware does not take any
action and the total charge of the event is evaluated within the gate and saved into memory.

Figure 6: Pile‐up definition.
This parameter allows to set the Peak Gap to identify pile up.
Value
E.g 1000 samples.
2.10.13 GateLongLengthT, GateLongLengthS

The aim of the DPP‐PSD firmware is to perform a charge integration of the input signal and to calculate the PSD factor
performing a double gate integration of the input (Qshort and Qlong). Fig. 2.3 shows the short and long gates position
for two signals of different shapes
Figure 7: Long and short gate graphic position with respect to a couple of input pulses. The blue pulse has a longer tail
than the red one.
This parameter allows to set the Gate Long Length (in ns or samples).
Value

2.10.14 GateShortLengthT, GateShortLengthS

This parameter allows to set the Gate Short Length (in ns or samples).
Value
2.10.15 GateOffsetT, GateOffsetS

This parameter allows to set the Gate Offset with respect to the trigger signal (in ns or samples).
Value
2.10.16 LongChargeIntegratorPedestal
Level: CH Mode: R/W Type: NUMBER UoM: counts Min: 0 Max: 1000
This parameter allows to set the Long Charge Integrator Pedestal. This feature is useful in case of energies close to
zero.
Value
E.g. 300 counts.
2.10.17 ShortChargeIntegratorPedestal
This parameter allows to set the Long Charge Integrator Pedestal. This feature is useful in case of energies close to
zero.
Value
E.g. 300 counts.
2.10.18 EnergyGain
This parameter allows to set the Energy Gain i.e. to rescale the signal charge.
Value
Option Description
x1 Charge value is multiplied x1.

2.10.19 NeutronThreshold
This parameter allows to set the Neutron Energy Threshold for Neutron Discriminator. The FW compare the difference
“Energy Long” – “Energy Short” (i.e. the difference between the charge integrated in the Long gate and in the Short
gate) with the threshold set by this parameter to decide whether the event has to be rejected.
Referring to the example of neutron/gamma discrimination shown in Fig. 2.16, the cut on PSD allows the user to reject
most of the gamma events, thus recording only neutrons and the small amount of gamma overlapping with the
neutrons.
Figure 8: 2D scatter plot of PSD parameter vs Energy in a neutron‐gamma application. On the left the 2D plot before the cut, on the
right the plot after the cut on Neutron Threshold .
Value
E.g. 300 counts.
2.10.20 ChRealtimeMonitor
RealTime measured by the FPGA, incremented with step of 524288 ns. Reading this parameter updates the values of
ChDeadtimeMonitor, ChTriggerCnt, ChSavedEventCnt and ChWaveCnt.
Value
2.10.21 ChDeadtimeMonitor
DeadTime measured by the FPGA, incremented with step of 524288 ns. Updated when reading ChRealtimeMonitor.
Value
2.10.22 ChTriggerCnt
Counter of channel triggers (24 bit), measured by FPGA. Updated when reading ChRealtimeMonitor.
Value
Eg. 1000.

2.10.23 ChSavedEventCnt
Counter of channel saved events, measured by FPGA (24 bit). Updated when reading ChRealtimeMonitor.
Value
Eg. 1000.
2.10.24 ChWaveCnt
Counter of channel events with waveform, measured by FPGA (24 bit). Updated when reading ChRealtimeMonito.
Value
Eg. 1000.

3 Commands
3.1 Reset
Level: DIG
Resets the board. This command sets all registers to the default value and clear data from memories. It does not act on
the communication interfaces, the PLLs and the clocks.
3.2 ClearData
Level: DIG
Clear data from memories. Register’s content is not affected. This command is typically used before starting an
acquisition to guarantee that no data belonging to a previous run is still present in the internal memory of the digitizer.
3.3 ArmAcquisition
Level: DIG
Arms the digitizer to start an acquisition. When the start of run is software controlled, the arming is not implicit in the
start command and it is necessary to use the ArmAcquisition command.
3.4 DisarmAcquisition
Level: DIG
Disarms the acquisition and prevents the digitizer to start a new run (for instance controlled by an external signal
feeding SIN) without the grant of the software. It is possible to set an automatic disarm after the stop of the acquisition
by means of the EnAutoDisarmAcq parameter. However, in order to make the higher level software aware of this
occurrence and allow him to properly manage the Disarm condition, the use of the DisarmAcquistion command is
mandatory even when the EnAutoDisarmAcq parameter is used.
3.5 SwStartAcquisition
Level: DIG
Starts the acquisition, provided that the option SwStart is enabled in the parameter StartSource. This start command
does require a previous arming command.
3.6 SwStopAcquisition
Level: DIG
Forces the acquisition to stop, whatever is the start source.
3.7 SendSWTrigger
Level: DIG
Send a software trigger to the digitizer, provided that the option SwTrg is enabled in the GlobalTriggerSource
parameter.
3.8 ReloadCalibration
Level: DIG
Delete calibration file and reload it from flash or, if invalid, use default calibration.

4 Endpoints
4.1 Parameters
4.1.1 ActiveEndpoint
Level: ENDPOINT FOLDER Mode: R/W Type: ENUM
Defines which endpoint will be used.
Option Description
raw Decode is disabled and ReadData should be made on handle /endpoint/raw
dpppsd Decode is enabled and ReadData should be made on handle /endpoint/dpppsd
4.2 Raw Endpoints

4.2.1 Raw
Path: /endpoint/raw
Raw data. See MaxRawDataSize parameter to get the maximum size that can be returned by a single call to ReadData.
Supported fields
Name Native type Dim. Description
DATA U8 (fixed) 1 Raw data (type conversion not supported)
SIZE SIZE_T 0 Size of data written to DATA
N_EVENTS U32 0 Add N_EVENTS to raw endpoint to get the number
of events in the blob. In case of firmware using
aggregate events (DPP firmwares) it returns the
number of aggregates.
Default data format

[
{ "name": "DATA", "type”: "U8", "dim": 1 },
{ "name": "SIZE", "type”: "SIZE_T"}
]
Data are passed on the network as big-endian 64-bit words. The endianness must be properly adjusted before to start
decoding it.
In all the 27xx digitizer family the most general structure of the events is
Figure 9: 27xx digitizer general event structure.
where
• n. words = N
• format can be:
o 0x1 in case of Common Trigger Mode
o 0x2 in case of Individual Trigger Mode
o 0x3 in case of Special Events
The DPP-PSD belongs to the Individual trigger mode case. In such a mode the event aggregate has the following format

Figure 10: Event aggregate in Individual Trigger Mode.
where
• n. aggregate words = N
• bit 56 ("board fail") is common to all the aggregated events. The size of each aggregated event must be
inferred by the information in the aggregated event itself.
Three event types are present in the data aggregate:

• The Start Run event
• Data events, one per each trigger accepted by the board
• The Stop Run event
The Start Run is a special event composed of four 64-bit words and generated by the board when the acquisition
starts.
The Start Run event is below described:
Figure 11: Start Run event structure.
where
• dec. factor log2 (decimation factor in log2 scale) = 0x0;
• n. traces = 0x1;
• acquisition width = 0x0;
The aggregate event(0), aggregate event (1), …, aggregate event (N-1) can be of three types:
a. single event without waveform sample (W=0)
b. single event with waveform sample (W=1)
c. single word event
Figure 12: DPP-PSD firmware Raw Data structure.
The latter can be used when the data throughput is a concern. Such event type replaces the first one when the
EnDataReduction is enabled.
In the above pictures:
• bit 63 is set on the last header word, despite the presence of the waveform payload. In case of no extra word,
it is set on the second word.
• there are always at least 2 words (i.e. bit 63 on first word is unset).
• the optional waveform payload is present only if the bit 62 on the second word is set.
• in the timestamp field: 1 LSB = 8 ns
• in the fine timestamp field: 1 LSB = 7.8125 ps

• The number of user words must be deduced by bit 63.
When waveform are present, channel record length = N samples (ChRecordLengthS, ChRecordLengthT) so waveform
n. words = N/2.
Sample format is:
• analog probe #0 = bit [0:13]
• digital probe #0 = bit 14
• analog probe #1 = bit [16:29]
Extra word type can be

• Waveform = 0x0
• Time = 0x1
The DPP-PSD extra word Time is in the form
If enabled, these events are sent for statistical purposes only, and does not represent real events. If there is the time
extra word, bit 55 is set on the first word and the second word is meaningless. In the dead time field 1 LSB = 8 ns.
The DPP-PSD extra word Waveform is in the form
If there is the waveform extra word, bit 62 is set on the second word.
The Analog probe info format is:

• analog probe type = bit[0:2]
• is signed = bit 3
• multiplication factor = bit[4:5]
The Analog probe type can be:

• ADC input = 0x0
• Baseline = 0x1
• CFD = 0x2
The Analog probe multiplication factor can be:

• Factor 1 = 0x0
• Factor 4 = 0x1
• Factor 8 = 0x2
• Factor 16 = 0x3
The Digital probe info format is:

• digital probe type = bit[0:3]
The Digital probe type can be:

• Trigger = 0x0
• Time filter armed = 0x1
• Re-trigger guard = 0x2
• Energy filter baseline freeze = 0x3
• Over threshold = 0x4
• Charge ready = 0x5
• Long gate = 0x6
• Event pile up = 0x7
• Short gate = 0x8
• Charge over range = 0x9

• Energy saturation = 0xA
• Negative over threshold = 0xB
The Time resolution (Time res.) is referred to the waveform downsampling, and it can be:
• No downsampling = 0x0
• Downsampling x2 = 0x1
The Stop Run is a special event composed of three 64-bit words and generated at the end of the Run. The Stop Run
event will be read out after all the data events.
The Stop event is below described:
Figure 13: Stop Run word event structure.
where
• Timestamp is the end of run time so the Real Time (1LSB = 8ns)
• Dead time is the dead time of the acquisition (1LSB = 8ns)
4.3 Decoded Endpoints

4.3.1 DPPPSD
Path: /endpoint/dpppsd
Decoded endpoint.
Supported fields
CHANNEL U8 0 Channel (7 bits)
TIMESTAMP U64 0 Timestamp (48 bits)
TIMESTAMP_NS U64 0 Timestamp in nanoseconds (51 bits)
FINE_TIMESTAMP U16 0 Fine timestamp (10 bits)
ENERGY U16 0 Energy (16 bits)
ENERGY_SHORT U16 0 Energy short (16 bits)
FLAGS_LOW_PRIORITY U16 0 Event low priority flags (12 bits). See Low Priority.
FLAGS_HIGH_PRIORITY U8 0 Event high priority flags (8 bits). See High Priority.
TRIGGER_THR U16 0 Trigger threshold (16 bits)
TIME_RESOLUTION U8 0 Time resolution (2 bits):
• No downsampling (0)
• Downsampling x2 (1)
ANALOG_PROBE_1 I32 1 Analog probe #1 (18 bits, signed)
ANALOG_PROBE_1_TYPE U8 0 Analog probe #1 type (4 bits):
• ADC input (0)
• Baseline (9)
• CFD (10)
ANALOG_PROBE_2 I32 1 Analog probe #2 (18 bits, signed)
ANALOG_PROBE_2_TYPE U8 0 Analog probe #2 type. See ANALOG_PROBE_1_TYPE
description.
DIGITAL_PROBE_1 U8 1 Digital probe #1 (1 bit)

DIGITAL_PROBE_1_TYPE U8 0 Digital probe #1 type (5 bits):
• Trigger (0)
• CFD Filter Armed (1)
• Re trigger guard (2)
• ADC Input baseline freeze (3)
• ADC Input overthreshold (20)
• Charge ready (21)
• Long gate (22)
• Pile up trigger (7)
• Short gate (24)
• Energy Saturation (25)
• Charge overrange (26)
• ADC Input negative overthreshold (27)
DIGITAL_PROBE_2_TYPE U8 0 Digital probe #2 type. See DIGITAL_PROBE_1_TYPE
description.

description.

description.
WAVEFORM_SIZE SIZE_T 0 Number of waveform samples, assumed to be equal for

all probes.
BOARD_FAIL BOOL 0 Set if the logical AND between of the ErrorFlag and
ErrorFlagDataMask is not 0. Present in all the events
belonging to the same aggregate. (1 bit)
EVENT_SIZE SIZE_T 0 Total event raw size, useful for statistics.
FLUSH BOOL 0 Flush of the aggregate word. Shared by all the events in
the aggregate. Useful for debug purposes. (1 bit)
AGGREGATE_COUNTER U32 0 Aggregate counter section in the Event Aggregate
structure. Shared by all the events in the aggregate.
Useful for debug purposes. (24 bit)
Default data format

[
{ "name": "CHANNEL", "type": "U8" },
{ "name": "TIMESTAMP", "type": "U64" },
{ "name": "FINE_TIMESTAMP", "type": "U16" },
{ "name": "ENERGY", "type": "U16" },
{ "name": "ENERGY_SHORT", "type": "U16" },
{ "name": "ANALOG_PROBE_1", "type": "I32", "dim": 1 },
{ "name": "ANALOG_PROBE_2", "type": "I32", "dim": 1 },
{ "name": "DIGITAL_PROBE_1", "type": "U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_2", "type": "U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_3", "type": " U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_4", "type": " U8", "dim": 1 },
{ "name": "WAVEFORM_SIZE", "type": "SIZE_T" }
]
4.3.2 Statistics
Path: /endpoint/dpppsd/stats

Decoded endpoint.
The statistics endpoint data are aligned to the data stream obtained from the dpppsd endpoint.
The user should note that the dpppsd endpoint has a buffer of 4096 events, and therefore the statistics endpoint data
could be up to 4096 events ahead of what the user reads from the dpppsd endpoint.
All the time fields are U64 Native type however the information in provided on 48 bit like the single even timestamp
for the fields REAL_TIME, DEAD_TIME and LIVE_TIME while it is provided on 51 bit for the fields REAL_TIME_NS,
DEAD_TIME_NS and LIVE_TIME_NS. All the counts fields are U32 Native type however the information in provided on
24 bit.
Supported fields
REAL_TIME U64 1 Channel real time (in clock steps)
REAL_TIME_NS U64 1 Channel real time (in ns)
DEAD_TIME U64 1 Channel dead time (in clock steps)
DEAD_TIME_NS U64 1 Channel dead time (in ns)
LIVE_TIME U64 1 Channel live time (in clock steps)
LIVE_TIME_NS U64 1 Channel live time (in ns)
TRIGGER_CNT U32 1 Counter of channel triggers
SAVED_EVENT_CNT U32 1 Counter of channel saved events
Default data format

[
{ "name": "REAL_TIME", "type": "U64", "dim": 1 },
{ "name": "DEAD_TIME", "type": "U64", "dim": 1 }
]

5 Flags
5.1 High Priority
Bit Name Description
0 Pile-Up Identifies pile-up events, ie events in which there is a at least one situation
of peak‐valley‐peak inside the integration gate. See PileupGap.
1 Unused -
2 Event saturation Identifies an event in which a saturation of the input dynamics occurred
3 Post saturation event Identifies an event occurred during a the ADCVetoWidth time.
4 Charge overflow event Identifies an event in which an overflow of the integrated charge occurred.
5 SCA selected event Identifies an event falling within the SCA windows (if enabled).
6 Event with fine Identifies an event in which the fine timestamp has been properly
timestamp calculated.
5.2 Low Priority

Bit Name Description
0 Event waveform Identifies a saved waveform because occurred when the external inhibit is
occurrent during active (useful in case of Transistor Reset Preamplifier detector use to see
external inhibit what happens during the reset)
1 Event waveform under- Identifies a saved waveform because under-saturating.
saturation
2 Event waveform over- Identifies a saved waveform because over-saturating.
saturation
3 External trigger Identifies an event triggered by the external trigger from the TRG-IN
connector
4 Global trigger Identifies an event triggered by a global trigger condition.
5 Software trigger Identifies an event triggered by a software trigger.
6 Self trigger Identifies an event triggered by the single channel self trigger.
7 LVDS trigger Identifies an event triggered by the external trigger from the LVDS
connector.
8 64 channel trigger Identifies an event triggered by another (or a combination of other)
channels trigger.
9 ITLA trigger Identifies an event triggered by the ITLA logic.
10 ITLB trigger Identifies an event triggered by the ITLB logic.

6 Technical Support
CAEN makes available the technical support of its specialists for requests concerning the software, hardware,
and eventually board repair. To access the support platform, please follow the steps below:
1. Login at www.caen.it or register a new account.

2. On the MyCAEN+ area, from the “Dashboard” section (www.caen.it/mycaen/dashboard), register your
boards
3. From the “Support” section (www.caen.it/mycaen/support) open a ticket request for the issue you have
found.
4. In case of product repair, a CAEN operator will enable the RMA (Return Merchandise Authorization) form
directly from the support ticket.
Note: only MyCAEN+ accounts can request technical support. If you have a basic account, please insert
 your institutional email: if the domain is in our whitelist, the account is automatically updated to MyCAEN+,
otherwise an operator will take care of the validation within 48 hours .

CAEN
Tools for Discovery
n Electronic Instrumentation
CAEN SpA is acknowledged as the only company in the world providing a complete range of High/Low Voltage Power
Supply systems and Front-End/Data Acquisition modules which meet IEEE Standards for Nuclear and Particle Physics.
Extensive Research and Development capabilities have allowed CAEN SpA to play an important, long term role in this
field. Our activities have always been at the forefront of technology, thanks to years of intensive collaborations with
the most important Research Centres of the world. Our products appeal to a wide range of customers including
engineers, scientists and technical professionals who all trust them to help achieve their goals faster and more
effectively.
CAEN S.p.A. CAEN GmbH CAEN Technologies, Inc.

Via Vetraia, 11 Klingenstraße 108 1 Edgewater Street - Suite 101
55049 Viareggio D-42651 Solingen Staten Island, NY 10305
Italy Germany USA
Tel. +39.0584.388.398 Tel. +49 (0)212 254 4077 Tel. +1.718.981.0401
Fax +39.0584.388.959 Mobile +49 (0)151 16 548 484 Fax +1.718.556.9185
[email protected] Fax +49 (0)212 25 44079 [email protected]
www.caen.it [email protected] www.caentechnologies.com
www.caen-de.com
UM8762 - FELib PSD Parameters User Manual rev. 0 - June 15th, 2022
00107/17:VX2740.MUTX/0
Copyright © CAEN SpA. All rights reserved. Information in this publication supersedes all earlier versions. Specifications subject to change without notice.

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Tools for Discovery

FELib PSD Parameters User Manual

Change Document Record

Symbols, Abbreviated Terms, and Notations

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Returned value or Allowed values with the corresponding description if required.

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2.1.21 IPAddress, Netmask, Gateway

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2.2 Acquistion, Trigger and VETO parameters

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2.3 Waveform Inspector parameters

2.3.2 ChRecordLengthS, ChRecordLengthT

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2.3.4 WaveAnalogProbe0 and WaveAnalogProbe1

2.3.5 WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2,

2.3.6 ChPreTriggerS, ChPreTriggerT

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2.4 Service parameter

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2.4.6 TempSensAirIn, TempSensAirOut, TempSensCore, TempSensFirstADC,

2.4.7 VInSensDCDC, VOutSensDCDC

2.4.11 SpeedSensFan1, SpeedSensFan2

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2.4.12 ErrorFlagMask, ErrorFlagDataMask

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2.5 Individual trigger parameters

PairMode: AND, OR, NONE

ITL Mode: AND, OR, MAJ

Figure 1: Individual Trigger logic scheme.

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2.5.2 ITLAMajorityLev, ITLBMajorityLev

2.5.3 ITLAPairLogic, ITLBPairLogic

2.5.4 ITLAPolarity, ITLBPolarity

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2.5.6 ITLAMask, ITLBMask

2.5.7 ITLAGateWidth, ITLBGateWidth

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2.6 LVDS parameters

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