Micom P40 Agile: Ge Grid Solutions

GE
Grid Solutions
MiCOM P40 Agile

P642, P643, P645
Technical Manual
Transformer Protection IED
Hardware Version: M, P
Software Version: 91
Publication Reference: P64x-TM-EN-4.1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
3 Product Scope 6
3.1 Product Versions 6
3.2 Ordering Options 8
4 Features and Functions 9
4.1 Protection Functions 9
4.2 Control Functions 9
4.3 Measurement Functions 10
4.4 Communication Functions 10
5 Compliance 11
6 Functional Overview 12
Chapter 2 Safety Information 13

2 Health and Safety 16
3 Symbols 17
4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 23
5 Decommissioning and Disposal 24
6 Regulatory Compliance 25
6.1 EMC Compliance: 2014/30/EU 25
6.2 LVD Compliance: 2014/35/EU 25
6.3 R&TTE Compliance: 2014/53/EU 25
6.4 UL/CUL Compliance 25
Chapter 3 Hardware Design 27

2 Hardware Architecture 30
3 Mechanical Implementation 31
3.1 Housing Variants 31
3.2 List of Boards 32
4 Front Panel 33
4.1 Front Panel 33
4.1.1 Front Panel Compartments 33
4.1.2 HMI Panel 34
4.1.3 Keypad 34
4.1.4 USB Port 35
4.1.5 Fixed Function LEDs 36
4.1.6 Function Keys 36
Contents P64x
4.1.7 Programable LEDs 36

5 Rear Panel 37
5.1 Terminal Block Ingress Protection 38
6 Boards and Modules 39
6.1 PCBs 39
6.2 Subassemblies 39
6.3 Main Processor Board 40
6.4 Power Supply Board 41
6.4.1 Watchdog 43
6.4.2 Rear Serial Port 44
6.5 Input Module - 1 Transformer Board 45
6.5.1 Input Module Circuit Description 46
6.5.2 Frequency Response 47
6.5.3 Transformer Board 48
6.5.4 Input Board 49
6.6 Standard Output Relay Board 50
6.7 IRIG-B Board 51
6.8 Fibre Optic Board 52
6.9 Rear Communication Board 53
6.10 Redundant Ethernet Board 54
6.11 RTD Board 56
6.12 CLIO Board 57
6.13 High Break Output Relay Board 59
Chapter 4 Software Design 61

2 Sofware Design Overview 64
3 System Level Software 65
3.1 Real Time Operating System 65
3.2 System Services Software 65
3.3 Self-Diagnostic Software 65
3.4 Startup Self-Testing 65
3.4.1 System Boot 65
3.4.2 System Level Software Initialisation 66
3.4.3 Platform Software Initialisation and Monitoring 66
3.5 Continuous Self-Testing 66
4 Platform Software 68
4.1 Record Logging 68
4.2 Settings Database 68
4.3 Interfaces 68
5 Protection and Control Functions 69
5.1 Acquisition of Samples 69
5.2 Frequency Tracking 69
5.3 Direct Use of Sample Values 69
5.4 Fourier Signal Processing 69
5.5 Programmable Scheme Logic 70
5.6 Event Recording 71
5.7 Disturbance Recorder 71
5.8 Fault Locator 71
5.9 Function Key Interface 71
Chapter 5 Configuration 73
2 Settings Application Software 76
3 Using the HMI Panel 77
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3.1 Navigating the HMI Panel 78

3.2 Getting Started 78
3.3 Default Display 79
3.4 Default Display Navigation 80
3.5 Password Entry 81
3.6 Processing Alarms and Records 82
3.7 Menu Structure 82
3.8 Changing the Settings 83
3.9 Direct Access (The Hotkey menu) 84
3.9.1 Setting Group Selection Using Hotkeys 84
3.9.2 Control Inputs 85
3.10 Function Keys 85
4 Configuring the Data Protocols 87
4.1 Courier Configuration 87
4.2 DNP3 Configuration 88
4.2.1 DNP3 Configurator 89
4.3 IEC 60870-5-103 Configuration 89
4.4 MODBUS Configuration 90
4.5 IEC 61850 Configuration 91
4.5.1 IEC 61850 Configuration Banks 92
4.5.2 IEC 61850 Network Connectivity 92
5 Date and Time Configuration 93
5.1 Using an SNTP Signal 93
5.2 Using an IRIG-B Signal 93
5.3 Using an IEEE 1588 PTP Signal 93
5.4 Without a Timing Source Signal 94
5.5 Time Zone Compensation 94
5.6 Daylight Saving Time Compensation 95
6 Phase Rotation 96
6.1 CT and VT Reversal 96
Chapter 6 Transformer Differential Protection 97

2 Transformer Differential Protection Principles 100
2.1 Through Fault Stability 100
2.2 Bias Current Compensation 100
2.3 Three-phase Transformer Connection Types 101
2.4 Phase and Amplitude Compensation 104
2.5 Zero Sequence Filtering 105
2.6 Magnetising Inrush Restraint 105
2.7 Overfluxing Restraint 106
3 Implementation 107
3.1 Defining the Power Transformer 107
3.2 Selecting the Current Inputs 107
3.3 Phase Correction 108
3.4 Ratio Correction 108
3.5 CT Parameter Mismatch 109
3.6 Setting up Zero Sequence Filtering 110
3.7 Tripping Characteristics 110
3.7.1 High-Set Function 111
3.7.2 Circuitry Fail Alarm 112
3.8 Tripping Characteristic Stability 112
3.8.1 Maximum Bias 112
3.8.2 Delayed Bias 112
3.8.3 Transient Bias 112
3.8.4 CT Saturation Technique 113
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3.8.5 No Gap Detection Technique 113

3.8.6 External Fault Detection Technique 113
3.8.7 Current Transformer Supervision 115
3.8.8 Circuitry Fail Alarm 116
3.9 Differential Biased Trip Logic 117
4 Harmonic Blocking 118
4.1 2nd Harmonic Blocking 118
4.2 2nd Harmonic Blocking Logic 119
4.3 2nd Harmonic Setting Guidelines 119
4.4 5th Harmonic Blocking Implementation 120
4.5 5th Harmonic Setting Guideline 120
4.6 Geomagnetic Disturbances 121
4.7 Overall Harmonic Blocking Logic 121
5 Application Notes 122
5.1 Setting Guidelines 122
5.2 Example 1: Two-winding Transformer - No Tap Changer 123
5.3 Example 2: Autotransformer with Loaded Delta Winding 126
5.4 Example 3: Autotransformer with Unloaded Delta Winding 129
5.5 Setting Guidelines for Short-Interconnected Biased Differential Protection 132
5.6 Setting Guidelines for Shunt Reactor Biased Differential Protection 135
5.7 Setting Guidelines for using Spare CT Inputs 137
5.8 Setting Guidelines for Reference Vector Group 138
5.9 Stub Bus Application 139
5.9.1 Stub Bus Implementation 139
5.9.2 Stub Bus Scheme 140
5.10 Transformer Differential Protection CT Requirements 140
5.10.1 CT Requirements - Transformer Application 140
5.10.2 CT Requirements - Small Busbar Application 141
Chapter 7 Transformer Condition Monitoring 143

2 Thermal Overload Protection 146
2.1 Thermal Overload Implementation 147
2.1.1 Thermal Overload Bias Current 147
2.2 The Thermal Model 148
2.2.1 Top Oil Temperature Caculations 148
2.2.2 Hotspot Caculations 148
2.2.3 Thermal State Measurement 149
2.3 Application Notes 149
2.3.1 Recommendations 149
2.3.2 IEEE Recommendations 150
2.3.3 Data Provided by Transformer Manufacturers 150
3 Loss of Life Statistics 152
3.1 Loss of Life Implementation 152
3.1.1 Loss of Life Calculations 152
3.2.1 LOL Setting Guidelines 154
3.2.2 Example 154
4 Through Fault Monitoring 156
4.1 Through Fault Monitoring Implementation 156
4.2 Through Fault Monitoring Logic 157
4.3.1 TFM Setting Guidelines 157
5 RTD Protection 160
5.1 RTD Protection Implementation 160
5.2 RTD Logic 161
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5.3.1 Setting Guidelines for RTD Protection 161
6 CLIO Protection 162
6.1 Current Loop Input Implementation 162
6.2 Current Loop Input Logic 164
6.3 CLO Implementation 164
6.4.1 CLI Setting Guidelines 166
6.4.2 CLO Setting Guidelines 166
Chapter 8 Restricted Earth Fault Protection 169

2 REF Protection Principles 172
2.1 Resistance-Earthed Star Windings 173
2.2 Solidly-Earthed Star Windings 173
2.3 Through Fault Stability 174
2.4 Restricted Earth Fault Types 174
2.4.1 Low Impedance REF Principle 175
2.4.2 High Impedance REF Principle 176
3 Restricted Earth Fault Protection Implementation 178
3.1 Enabling REF Protection 178
3.3 Low Impedance REF 179
3.3.1 Setting the Bias Characteristic 179
3.3.2 Delayed Bias 180
3.3.3 Transient Bias 180
3.3.4 Restricted Earth Fault Logic 181
3.4 High Impedance REF 181
3.4.1 High Impedance REF Calculation Principles 181
4 Second Harmonic Blocking 183
4.1 REF 2nd harmonic Blocking Logic 183
5.1 Star Winding Resistance Earthed 184
5.2 Low Impedance REF Protection Application 185
5.2.1 Setting Guidelines for Biased Operation 185
5.2.2 Low Impedance REF Scaling Factor 185
5.2.3 Parameter Calculations 186
5.2.4 Dual CB Application with Different Phase CT Ratios 186
5.2.5 Dual CB Application with Same Phase CT Ratios 187
5.2.6 CT Requirements - Low Impedance REF 188
5.3 High Impedance REF Protection Application 189
5.3.1 High Impedance REF Operating Modes 189
5.3.2 Setting Guidelines for High Impedance Operation 190
5.3.3 Use of Metrosil Non-linear Resistors 192
5.3.4 CT Requirements - High Impedance REF 194
Chapter 9 Current Protection Functions 197

2 Overcurrent Protection Principles 200
2.1 IDMT Characteristics 200
2.1.1 IEC 60255 IDMT Curves 201
2.1.2 European Standards 203
2.1.3 North American Standards 204
2.1.4 IEC and IEEE Inverse Curves 206
2.1.5 Differences Between the North american and European Standards 207
2.2 Principles of Implementation 207
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2.2.1 Timer Hold Facility 208

2.3 Magnetising Inrush Restraint 209
3 Phase Overcurrent Protection 211
3.1 Phase Overcurrent Protection for Power Transformers 211
3.2 Phase Overcurrent Protection Implementation 211
3.4 Non-Directional Overcurrent Logic 213
3.5 Directional Element 214
3.5.1 Implementing Directionalisation 215
3.5.2 Directional Overcurrent Logic 216
3.6.1 Setting Guidelines 216
3.6.2 Parallel Feeders 218
4 Voltage Dependent Overcurrent Element 219
4.1 Current Setting Threshold Selection 219
4.2 VCO Implementation 219
4.3 VRO Implementation 220
5 Negative Sequence Overcurrent Protection 222
5.1 NPSOC Protection Implementation 222
5.2 Non-Directional NPSOC Logic 223
5.3.1 Directional NPSOC Logic 224
5.4.1 Setting Guidelines (General) 224
5.4.2 Setting Guidelines (Current Threshold) 224
5.4.3 Setting Guidelines (Time Delay) 225
5.4.4 Setting Guidelines (Directional element) 225
6 Earth Fault Protection 226
6.1 Earth Fault Protection Elements 226
6.2 Non-directional Earth Fault Logic 227
6.3 IDG Curve 227
6.4.1 Residual Voltage Polarisation 228
6.4.2 Negative Sequence Polarisation 229
6.5.1 Setting Guidelines (Non-directional) 230
6.5.2 Setting Guidelines (Directional Element) 231
7 Second Harmonic Blocking 232
7.1 Second Harmonic Blocking Implementation 232
7.2 Second Harmonic Blocking Logic 233
7.3 EF Second Harmonic Blocking Logic 234
Chapter 10 CB Fail Protection 235

2 Circuit Breaker Fail Protection 238
3 Circuit Breaker Fail Implementation 239
3.1 Circuit Breaker Fail Timers 239
3.2 Zero Crossing Detection 240
4 Circuit Breaker Fail Logic 241
5.1 Reset Mechanisms for CB Fail Timers 243
5.2 Setting Guidelines (CB fail Timer) 243
5.3 Setting Guidelines (Undercurrent) 244
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Chapter 11 Voltage Protection Functions 245

2 Undervoltage Protection 248
2.1 Undervoltage Protection Implementation 248
2.2 Undervoltage Protection Logic 249
2.3.1 Undervoltage Setting Guidelines 250
3 Overvoltage Protection 251
3.1 Overvoltage Protection Implementation 251
3.2 Overvoltage Protection Logic 252
3.3.1 Overvoltage Setting Guidelines 253
4 Residual Overvoltage Protection 254
4.1 Residual Overvoltage Protection Implementation 254
4.2 Residual Overvoltage Logic 255
4.3.1 Calculation for Solidly Earthed Systems 255
4.3.2 Calculation for Impedance Earthed Systems 256
5 Negative Sequence Overvoltage Protection 258
5.1 Negative Sequence Overvoltage Implementation 258
5.2 Negative Sequence Overvoltage Logic 258
Chapter 12 Frequency Protection Functions 261

2 Overfluxing Protection 264
2.1 Overfluxing Protection Implementation 264
2.1.1 Time-delayed Overfluxing Protection 265
2.1.2 5th Harmonic Blocking 266
2.1.3 Overfluxing Protection Logic 267
2.2.1 Overfluxing Protection Setting Guidelines 267
3 Frequency Protection 270
3.1 Underfrequency Protection 270
3.1.1 Underfrequency Protection Implementation 270
3.1.2 Underfrequency Protection logic 271
3.1.3 Application Notes 271
3.2 Overfrequency Protection 271
3.2.1 Overfrequency Protection Implementation 271
3.2.2 Overfrequency Protection logic 272
3.2.3 Application Notes 272
Chapter 13 Monitoring and Control 273

2 Event Records 276
2.1 Event Types 276
2.1.1 Opto-input Events 277
2.1.2 Contact Events 277
2.1.3 Alarm Events 277
2.1.4 Fault Record Events 281
2.1.5 Maintenance Events 281
2.1.6 Protection Events 282
2.1.7 Security Events 282
P64x-TM-EN-4.1 vii
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2.1.8 Platform Events 282

3 Disturbance Recorder 283
4 Measurements 284
4.1 Measured Quantities 284
4.1.1 Measured and Calculated Currents 284
4.1.2 Measured and Calculated Voltages 284
4.1.3 Power and Energy Quantities 284
4.1.4 Demand Values 285
4.1.5 Other Measurements 285
4.2 Measurement Setup 285
4.3 Opto-input Time Stamping 285
5 Current Input Exclusion Function 286
5.1 Current Input Exclusion Logic 286
5.2.1 Current Input Exclusion Example 287
6 Circuit Breaker Control 288
6.1 CB Control using the IED Menu 288
6.2 CB Control using the Hotkeys 288
6.3 CB Control using the Function Keys 289
6.4 CB Control using the Opto-inputs 290
6.5 Remote CB Control 290
6.6 CB Healthy Check 291
6.7 CB Control Logic 292
7 Pole Dead Function 293
7.1 Pole Dead Function Implementation 293
7.2 Pole Dead Logic 294
7.3 CB Status Indication 296
Chapter 14 Supervision 297

2 Voltage Transformer Supervision 300
2.1 Loss of One or Two Phase Voltages 300
2.2 Loss of all Three Phase Voltages 300
2.3 Absence of all Three Phase Voltages on Line Energisation 300
2.4 VTS Implementation 301
2.5 VTS Logic 302
3 Current Transformer Supervision 305
3.1 CTS Implementation 305
3.2 CTS Logic 306
4 Trip Circuit Supervision 308
4.1 Trip Circuit Supervision Scheme 1 308
4.1.1 Resistor Values 308
4.1.2 PSL for TCS Scheme 1 309
Chapter 15 Digital I/O and PSL Configuration 313

2 Configuring Digital Inputs and Outputs 316
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3 Scheme Logic 317

3.1 PSL Editor 318
3.2 PSL Schemes 318
3.3 PSL Scheme Version Control 318
4 Configuring the Opto-Inputs 319
5 Assigning the Output Relays 320
6 Fixed Function LEDs 321
6.1 Trip LED Logic 321
7 Configuring Programmable LEDs 322
8 Function Keys 324
9 Control Inputs 325
Chapter 16 Communications 327

2 Communication Interfaces 330
3 Serial Communication 331
3.1 EIA(RS)232 Bus 331
3.2 EIA(RS)485 Bus 331
3.2.1 EIA(RS)485 Biasing Requirements 332
3.3 K-Bus 332
4 Standard Ethernet Communication 334
5 Redundant Ethernet Communication 335
5.1 Supported Protocols 335
5.2 Parallel Redundancy Protocol 335
5.2.1 PRP Application in the Substation 337
5.3 High-Availability Seamless Redundancy (HSR) 337
5.3.1 HSR Multicast Topology 337
5.3.2 HSR Unicast Topology 338
5.3.3 HSR Application in the Substation 339
5.4 Rapid Spanning Tree Protocol 340
5.5 Configuring IP Addresses 341
5.5.1 Configuring the IED IP Address 341
5.5.2 Configuring the REB IP Address 341
5.6 Redundant Ethernet Configurator 342
5.6.1 Connecting the IED to a PC 342
5.6.2 Installing the Configurator 342
5.6.3 Starting the Configurator 343
5.6.4 PRP/HSR Device Identification 343
5.6.5 Selecting the Device Mode 343
5.6.6 PRP/HSR IP Address Configuration 343
5.6.7 SNTP IP Address Configuration 343
5.6.8 Check for Connected Equipment 344
5.6.9 PRP Configuration 344
5.6.10 HSR Configuration 344
5.6.11 Filtering Database 344
5.6.12 End of Session 345
5.7 RSTP Configurator 345
5.7.1 Connecting the IED to a PC 346
5.7.2 Installing the Configurator 346
5.7.3 Starting the Configurator 346
5.7.4 RSTP Device Identification 347
5.7.5 RSTP IP Address Configuration 347
5.7.6 SNTP IP Address Configuration 347
5.7.8 RSTP Configuration 347
5.8 Switch Manager 348
5.8.1 Installation 349
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5.8.2 Setup 350

5.8.3 Network Setup 350
5.8.4 Bandwidth Used 350
5.8.5 Reset Counters 350
5.8.7 Mirroring Function 351
5.8.8 Ports On/Off 351
5.8.9 VLAN 351
5.8.10 End of Session 351
6 Data Protocols 352
6.1 Courier 352
6.1.1 Physical Connection and Link Layer 352
6.1.2 Courier Database 353
6.1.3 Settings Categories 353
6.1.4 Setting Changes 353
6.1.5 Event Extraction 353
6.1.6 Disturbance Record Extraction 355
6.1.7 Programmable Scheme Logic Settings 355
6.1.8 Time Synchronisation 355
6.1.9 Courier Configuration 356
6.2 IEC 60870-5-103 357
6.2.2 Initialisation 358
6.2.4 Configurable IEC 60870-5-103 Signal List 358
6.2.5 Spontaneous Events 359
6.2.6 General Interrogation (GI) 359
6.2.7 Cyclic Measurements 359
6.2.8 Commands 359
6.2.9 Test Mode 359
6.2.10 Disturbance Records 359
6.2.11 Command/Monitor Blocking 360
6.2.12 IEC 60870-5-103 Configuration 360
6.3 DNP 3.0 361
6.3.2 Object 1 Binary Inputs 362
6.3.3 Object 10 Binary Outputs 362
6.3.4 Object 20 Binary Counters 363
6.3.5 Object 30 Analogue Input 363
6.3.6 Object 40 Analogue Output 363
6.3.7 Object 50 Time Synchronisation 363
6.3.8 DNP3 Device Profile 363
6.3.9 DNP3 Configuration 371
6.4 MODBUS 373
6.4.2 MODBUS Functions 373
6.4.3 Response Codes 373
6.4.4 Register Mapping 374
6.4.5 Event Extraction 374
6.4.6 Disturbance Record Extraction 375
6.4.7 Setting Changes 383
6.4.8 Password Protection 383
6.4.9 Protection and Disturbance Recorder Settings 383
6.4.11 Power and Energy Measurement Data Formats 385
6.4.12 MODBUS Configuration 386
6.5 IEC 61850 387
6.5.1 Benefits of IEC 61850 387
6.5.2 IEC 61850 Interoperability 388
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6.5.3 The IEC 61850 Data Model 388

6.5.4 IEC 61850 in MiCOM IEDs 389
6.5.5 IEC 61850 Data Model Implementation 389
6.5.6 IEC 61850 Communication Services Implementation 389
6.5.7 IEC 61850 Peer-to-peer (GOOSE) communications 390
6.5.8 Mapping GOOSE Messages to Virtual Inputs 390
6.5.9 Ethernet Functionality 390
6.5.10 IEC 61850 Configuration 390
6.5.11 Selection of the IEC 61850 Edition 391
6.5.12 IEC 61850 Edition 2 392
7 Read Only Mode 396
7.1 IEC 60870-5-103 Protocol Blocking 396
7.2 Courier Protocol Blocking 396
7.3 IEC 61850 Protocol Blocking 397
7.4 Read-Only Settings 397
7.5 Read-Only DDB Signals 397
8 Time Synchronisation 398
8.1 Demodulated IRIG-B 398
8.1.1 IRIG-B Implementation 399
8.2 SNTP 399
8.3 IEEE 1588 Precision time Protocol 399
8.3.1 Accuracy and Delay Calculation 399
8.3.2 PTP Domains 400
8.4 Time Synchronisation using the Communication Protocols 400
Chapter 17 Cyber-Security 401

1 Overview 403
2 The Need for Cyber-Security 404
3 Standards 405
3.1 NERC Compliance 405
3.1.1 CIP 002 406
3.1.2 CIP 003 406
3.1.3 CIP 004 406
3.1.4 CIP 005 406
3.1.5 CIP 006 406
3.1.6 CIP 007 407
3.1.7 CIP 008 407
3.1.8 CIP 009 407
3.2 IEEE 1686-2013 407
4 Cyber-Security Implementation 409
4.1 Initial Setup 409
5 Roles and Permissions 410
5.1 Roles 410
5.2 Permissions 411
6 Authentication 413
6.1 Authentication Methods 413
6.2 Bypass 413
6.3 Login 414
6.3.1 Front Panel Login 415
6.3.2 MiCOM S1 Login 415
6.3.3 Warning Banner 415
6.3.4 Login Failed 415
6.4 User Sessions 415
6.5 User Locking Policy 416
6.6 Logout 417
6.6.1 Front Panel Logout 417
6.6.2 MiCOM S1 Logout 417
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6.7 Device Users 417

6.8 Password Policy 418
6.9 Change Password 418
6.10 RADIUS 418
6.10.1 RADIUS Users 418
6.10.2 RADIUS Client 419
6.10.3 RADIUS Server Settings 419
6.10.4 RADIUS Accounting 420
6.10.5 RADIUS Client-Server Validation 420
6.11 Recovery 420
6.11.1 Restore to Local Factory Default 420
6.11.2 Password Reset Procedure 421
6.11.3 Access Level DDBs 422
6.12 Disabling Physical Ports 422
6.13 Disabling Logical Ports 423
7 Security Event Management 424
7.1 Security Events: Courier 424
7.2 Syslog 426
7.3 Syslog Client 426
7.4 Syslog Functionality 427
Chapter 18 Installation 429

2 Handling the Goods 432
2.1 Receipt of the Goods 432
2.2 Unpacking the Goods 432
2.3 Storing the Goods 432
2.4 Dismantling the Goods 432
3 Mounting the Device 433
3.1 Flush Panel Mounting 433
3.2 Rack Mounting 433
4 Cables and Connectors 435
4.1 Terminal Blocks 435
4.2 Power Supply Connections 436
4.3 Earth Connnection 436
4.4 Current Transformers 436
4.5 Voltage Transformer Connections 437
4.6 Watchdog Connections 437
4.7 EIA(RS)485 and K-Bus Connections 437
4.8 IRIG-B Connection 437
4.9 Opto-input Connections 437
4.10 Output Relay Connections 437
4.11 Ethernet Metallic Connections 438
4.12 Ethernet Fibre Connections 438
4.13 USB Connection 438
4.14 GPS Fibre Connection 438
4.15 Fibre Communication Connections 438
4.16 RTD Connections 438
4.17 CLIO Connections 439
5 Case Dimensions 440
5.1 Case Dimensions 40TE 440
Chapter 19 Commissioning Instructions 443
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2 General Guidelines 446
3 Commissioning Test Menu 447
3.1 Opto I/P Status Cell (Opto-input Status) 447
3.2 Relay O/P Status Cell (Relay Output Status) 447
3.3 Test Mode Cell 447
3.4 Test Pattern Cell 448
3.5 Contact Test Cell 448
3.6 Test LEDs Cell 448
3.7 Red and Green LED Status Cells 448
3.8 PSL Verificiation 448
3.8.1 Test Port Status Cell 448
3.8.2 Monitor Bit 1 to 8 Cells 448
3.8.3 Using a Monitor Port Test Box 449
4 Commissioning Equipment 450
4.1 Recommended Commissioning Equipment 450
4.2 Essential Commissioning Equipment 450
4.3 Advisory Test Equipment 451
5 Product Checks 452
5.1 Product Checks with the IED De-energised 452
5.1.1 Visual Inspection 452
5.1.2 Current Transformer Shorting Contacts 453
5.1.3 Insulation 453
5.1.4 External Wiring 453
5.1.5 Watchdog Contacts 453
5.1.6 Power Supply 454
5.2 Product Checks with the IED Energised 454
5.2.1 Watchdog Contacts 454
5.2.2 Test LCD 455
5.2.3 Date and Time 455
5.2.4 Test LEDs 455
5.2.5 Test Alarm and Out-of-Service LEDs 456
5.2.6 Test Trip LED 456
5.2.7 Test User-programmable LEDs 456
5.2.8 Test Opto-inputs 456
5.2.9 Test Output Relays 456
5.2.10 RTD Inputs 456
5.2.11 Current Loop Outputs 457
5.2.12 Current Loop Inputs 457
5.2.13 Test Serial Communication Port RP1 457
5.2.14 Test Serial Communication Port RP2 459
5.2.15 Test Ethernet Communication 460
5.3 Secondary Injection Tests 460
5.3.1 Test Current Inputs 460
5.3.2 Test Voltage Inputs 461
6 Setting Checks 462
6.1 Apply Application-specific Settings 462
6.1.1 Transferring Settings from a Settings File 462
6.1.2 Entering settings using the HMI 462
7 IEC 61850 Edition 2 Testing 464
7.1 Using IEC 61850 Edition 2 Test Modes 464
7.1.1 IED Test Mode Behaviour 464
7.1.2 Sampled Value Test Mode Behaviour 464
7.2 Simulated Input Behaviour 465
7.3 Testing Examples 465
7.3.1 Test Procedure for Real Values 466
7.3.2 Test Procedure for Simulated Values - No Plant 466
7.3.3 Test Procedure for Simulated Values - With Plant 467
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7.3.4 Contact Test 468

8 Checking the Differential Element 469
8.1 Using the Omicron Advanced Module 469
9 Protection Timing Checks 472
9.1 Bypassing the All Pole Dead Blocking Condition 472
9.2 Overcurrent Check 472
9.3 Connecting the Test Circuit 472
9.4 Performing the Test 473
9.5 Check the Operating Time 473
10 Onload Checks 474
10.1 Confirm Current Connections 474
10.2 Confirm Voltage Connections 474
10.3 On-load Directional Test 475
11 Final Checks 476
Chapter 20 Maintenance and Troubleshooting 477

2 Maintenance 480
2.1 Maintenance Checks 480
2.1.1 Alarms 480
2.1.2 Opto-isolators 480
2.1.3 Output Relays 480
2.1.4 Measurement Accuracy 480
2.2 Replacing the Device 481
2.3 Repairing the Device 482
2.4 Removing the front panel 482
2.5 Replacing PCBs 483
2.5.1 Replacing the main processor board 483
2.5.2 Replacement of communications boards 484
2.5.3 Replacement of the input module 485
2.5.4 Replacement of the power supply board 485
2.5.5 Replacement of the I/O boards 486
2.6 Recalibration 486
2.7 Cleaning 487
3 Troubleshooting 488
3.1 Self-Diagnostic Software 488
3.2 Power-up Errors 488
3.3 Error Message or Code on Power-up 488
3.4 Out of Service LED on at power-up 489
3.5 Error Code during Operation 490
3.6 Mal-operation during testing 490
3.6.1 Failure of Output Contacts 490
3.6.2 Failure of Opto-inputs 490
3.6.3 Incorrect Analogue Signals 491
3.7 PSL Editor Troubleshooting 491
3.7.1 Diagram Reconstruction 491
3.7.2 PSL Version Check 491
4 Repair and Modification Procedure 492
Chapter 21 Technical Specifications 493

2 Interfaces 496
2.1 Front USB Port 496
2.2 Rear Serial Port 1 496
2.3 Fibre Rear Serial Port 1 496
xiv P64x-TM-EN-4.1
P64x Contents
2.4 Rear Serial Port 2 496

2.5 IRIG-B (Demodulated) 497
2.6 IRIG-B (Modulated) 497
2.7 Rear Ethernet Port Copper 497
2.8 Rear Ethernet Port Fibre 497
2.8.1 100 Base FX Receiver Characteristics 498
2.8.2 100 Base FX Transmitter Characteristics 498
3 Performance of Transformer Differential Protection and Monitoring Functions 499
3.1 Transformer Differential Protection 499
3.2 Matching Factors 499
3.3 Circuitry Fault Alarm 499
3.4 Through Fault Monitoring 500
3.5 Thermal Overload 500
3.6 Low Impedance Restricted Earth Fault 500
3.7 High Impedance Restricted Earth Fault 500
4 Performance of Current Protection Functions 501
4.1 Transient Overreach and Overshoot 501
4.2 Three-phase Overcurrent Protection 501
4.2.1 Three-phase Overcurrent Directional Parameters 501
4.3 Voltage Dependent Overcurrent Protection 501
4.4 Earth Fault Protection 501
4.4.1 Earth Fault Directional Parameters 502
4.5 Negative Sequence Overcurrent Protection 502
4.5.1 NPSOC Directional Parameters 502
4.6 Circuit Breaker Fail Protection 503
5 Performance of Voltage Protection Functions 504
5.1 Undervoltage Protection (P643/5) 504
5.2 Overvoltage Protection 504
5.3 Residual Overvoltage Protection (P643/5) 504
5.4 Negative Sequence Voltage Protection 504
6 Performance of Frequency Protection Functions 505
6.1 Overfrequency Protection 505
6.2 Underfrequency Protection 505
6.3 Overfluxing Protection 505
7 Performance of Monitoring and Control Functions 506
7.1 Voltage Transformer Supervision 506
7.2 Current Transformer Supervision 506
7.3 Pole Dead Protection 506
7.4 PSL Timers 507
8 Measurements and Recording 508
8.1 General 508
8.2 Disturbance Records 508
8.3 Event, Fault and Maintenance Records 508
8.4 Current Loop Inputs/Outputs 508
9 Regulatory Compliance 510
9.1 EMC Compliance: 2014/30/EU 510
9.2 LVD Compliance: 2014/35/EU 510
9.3 R&TTE Compliance: 2014/53/EU 510
9.4 UL/CUL Compliance 510
10 Mechanical Specifications 511
10.1 Physical Parameters 511
10.2 Enclosure Protection 511
10.3 Mechanical Robustness 511
10.4 Transit Packaging Performance 511
11 Ratings 512
11.1 AC Measuring Inputs 512
P64x-TM-EN-4.1 xv
Contents P64x
11.2 Current Transformer Inputs 512

11.3 Voltage Transformer Inputs 512
12 Power Supply 513
12.1 Auxiliary Supply Voltage 513
12.2 Nominal Burden 513
12.3 Power Supply Interruption 513
12.4 Supercapacitor 514
13 Input / Output Connections 515
13.1 Isolated Digital Inputs 515
13.1.1 Nominal Pickup and Reset Thresholds 515
13.2 Standard Output Contacts 515
13.3 High Break Output Contacts 516
13.4 Watchdog Contacts 516
14 Environmental Conditions 517
14.1 Ambient Temperature Range 517
14.2 Temperature Endurance Test 517
14.3 Ambient Humidity Range 517
14.4 Corrosive Environments 517
15 Type Tests 518
15.1 Insulation 518
15.2 Creepage Distances and Clearances 518
15.3 High Voltage (Dielectric) Withstand 518
15.4 Impulse Voltage Withstand Test 518
16 Electromagnetic Compatibility 519
16.1 1 MHz Burst High Frequency Disturbance Test 519
16.2 Damped Oscillatory Test 519
16.3 Immunity to Electrostatic Discharge 519
16.4 Electrical Fast Transient or Burst Requirements 519
16.5 Surge Withstand Capability 519
16.6 Surge Immunity Test 520
16.7 Immunity to Radiated Electromagnetic Energy 520
16.8 Radiated Immunity from Digital Communications 520
16.9 Radiated Immunity from Digital Radio Telephones 520
16.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 520
16.11 Magnetic Field Immunity 521
16.12 Conducted Emissions 521
16.13 Radiated Emissions 521
16.14 Power Frequency 521
Appendix A Ordering Options 523
Appendix B Settings and Signals 525
Appendix C Wiring Diagrams 527
xvi P64x-TM-EN-4.1
Table of Figures
Figure 1: P64x version evolution 7
Figure 2: Functional overview 12
Figure 3: Hardware architecture 30
Figure 4: Exploded view of IED 31
Figure 5: Front panel (60TE) 33
Figure 6: HMI panel 34
Figure 7: Rear view of populated case 37
Figure 8: Terminal block types 38
Figure 9: Example—fitted IP2x shields (cabling omitted for clarity) 38
Figure 10: Rear connection to terminal block 39
Figure 11: Main processor board 40
Figure 12: Power supply board 41
Figure 13: Power supply assembly 42
Figure 14: Power supply terminals 43
Figure 15: Watchdog contact terminals 44
Figure 16: Rear serial port terminals 45
Figure 17: Input module - 1 transformer board 45
Figure 18: Input module schematic 46
Figure 19: Frequency response 47
Figure 20: Transformer board 48
Figure 21: Input board 49
Figure 22: Standard output relay board - 8 contacts 50
Figure 23: IRIG-B board 51
Figure 24: Fibre optic board 52
Figure 25: Rear communication board 53
Figure 26: Redundant Ethernet board 54
Figure 27: RTD board 56
Figure 28: RTD board 57
Figure 29: High Break relay output board 59
Figure 30: High Break contact operation 60
Figure 31: Software Architecture 64
Figure 32: Frequency Response (indicative only) 70
Figure 33: Navigating the HMI 78
Figure 34: Default display navigation 80
Figure 35: Compensation using biased differential characteristic 101
Figure 36: Transformer winding connections - part 1 103
Figure 37: Transformer winding connections - part 2 104
Figure 38: Magnetising inrush phenomenon 105
Table of Figures P64x
Figure 39: Typical overflux current waveform 106

Figure 40: CT parameter mismatch logic diagram 109
Figure 41: Transformer biased tripping characteristic 111
Figure 42: Transient bias characteristic 113
Figure 43: Time to saturation - external AN fault 115
Figure 44: Effect of CTS restrain 116
Figure 45: Bias characteristic with circuitry fail alarm 116
Figure 46: Differential biased trip logic 117
Figure 47: 2nd harmonic blocking process 118
Figure 48: 2nd harmonic blocking logic 119
Figure 49: 5th harmonic blocking process 120
Figure 50: Differential protection blocking mechanisms 121
Figure 51: Triple slope characteristic 123
Figure 52: P642 used to protect a two winding transformer 124
Figure 53: P645 used to protect an autotransformer with loaded delta winding 127
Figure 54: P643 used to protect an autotransformer with unloaded delta winding 130
Figure 55: Unloaded delta – current distribution 131
Figure 56: Single bus differential protection zone 133
Figure 57: Busbar biased differential protection 135
Figure 58: Shunt Reactor single line diagram 136
Figure 59: P643 Using spare CT input for overcurrent protection 138
Figure 60: Stub Bus arrangement 139
Figure 61: Stub Bus Scheme Logic 140
Figure 62: Transformer losses 146
Figure 63: Through-fault alarm logic 157
Figure 64: P645 used to protect an autotransformer with loaded delta winding 158
Figure 65: Connection for RTD thermal probes 160
Figure 66: RTD logic 161
Figure 67: Current loop input ranges 163
Figure 68: Current Loop Input logic 164
Figure 69: Current Loop Output ranges 165
Figure 70: REF protection for delta side 172
Figure 71: REF protection for star side 172
Figure 72: REF Protection for resistance-earthed systems 173
Figure 73: REF Protection for solidly earthed system 173
Figure 74: Low Impedance REF Connection 175
Figure 75: Three-slope REF bias characteristic 175
Figure 76: High Impedance REF principle 176
Figure 77: High Impedance REF Connection 177
Figure 78: REF bias characteristic 180
xviii P64x-TM-EN-4.1
P64x Table of Figures
Figure 79: Low impedance restricted Earth Fault logic 181

Figure 80: REF 2nd harmonic blocking logic 183
Figure 81: Star winding, resistance earthed 184
Figure 82: Percentage of winding protected 185
Figure 83: Low Impedance REF Scaling Factor 185
Figure 84: Low-Z REF for dual CB application with different phase CT ratios 186
Figure 85: Low-Z REF for dual CB application with same phase CT ratios 187
Figure 86: Hi-Z REF protection for a grounded star winding 189
Figure 87: Hi-Z REF protection for a delta winding 190
Figure 88: Hi-Z REF Protection for autotransformer configuration 190
Figure 89: High Impedance REF for the LV winding 191
Figure 90: High Impedance REF CT requirement 195
Figure 91: IEC 60255 IDMT curves 203
Figure 92: IEC standard and very inverse curves 206
Figure 93: IEC Extremely inverse and IEEE moderate inverse curves 206
Figure 94: IEEE very and extremely inverse curves 207
Figure 95: Principle of protection function implementation 208
Figure 96: Magnetising inrush phenomenon 210
Figure 97: Non-directional overcurrent logic diagram 213
Figure 98: Directional overcurrent logic diagram 216
Figure 99: Typical distribution system using parallel transformers 218
Figure 100: Selecting the current threshold setting 219
Figure 101: Modification of current pickup level for voltage controlled overcurrent protection 220
Figure 102: Modification of current pickup level for voltage restrained overcurrent protection 221
Figure 103: Negative Sequence Overcurrent logic - non-directional operation 223
Figure 104: Negative Phase Sequence Overcurrent logic - directional operation 224
Figure 105: Non-directional EF logic (single stage) 227
Figure 106: IDG Characteristic 228
Figure 107: Directional EF logic with neutral voltage polarization (single stage) 229
Figure 108: Directional Earth Fault logic with negative phase sequence polarisation (single 230
stage)
Figure 109: Phase overcurrent 2nd harmonic blocking Logic 233
Figure 110: Earth fault 2nd harmonic blocking Logic 234
Figure 111: Circuit Breaker Fail Logic - part 1 241
Figure 112: Circuit Breaker Fail Logic - part 2 242
Figure 113: CB Fail timing 244
Figure 114: Undervoltage - single and three phase tripping mode (single stage) 249
Figure 115: Overvoltage - single and three phase tripping mode (single stage) 252
Figure 116: Residual Overvoltage logic 255
Figure 117: Residual voltage for a solidly earthed system 256
P64x-TM-EN-4.1 xix
Figure 118: Residual voltage for an impedance earthed system 257

Figure 119: Negative Sequence Overvoltage logic 258
Figure 120: Variable time overfluxing protection characteristic 265
Figure 121: Overfluxing reset characteristic 266
Figure 122: 5th harmonic blocking time delay in PSL 266
Figure 123: Overfluxing protection logic 267
Figure 124: Multi-stage overfluxing characteristic 268
Figure 125: Scheme logic for multi-stage overfluxing characteristic 269
Figure 126: Underfrequency logic (single stage) 271
Figure 127: Overfrequency logic (single stage) 272
Figure 128: Fault recorder stop conditions 281
Figure 129: CT Exclusion logic 286
Figure 130: CT input exclusion - 1.5 CB application 287
Figure 131: CT input exclusion - auxiliary contact connection 287
Figure 132: Hotkey menu navigation 289
Figure 133: Default function key PSL 290
Figure 134: Remote Control of Circuit Breaker 291
Figure 135: CB Control logic 292
Figure 136: Pole Dead logic - P642 294
Figure 137: Pole Dead logic - P643 and P645 295
Figure 138: Forcing CB Closed signals 296
Figure 139: VTS logic (P642 with 2 single-phase VTs) 302
Figure 140: VTS logic (P643 and P645 with 3-phase VTs) 303
Figure 141: CTS restraint region increase 305
Figure 142: CTS logic diagram 306
Figure 143: TCS Scheme 1 308
Figure 144: PSL for TCS Scheme 1 309
Figure 149: Scheme Logic Interfaces 317
Figure 150: Trip LED logic 321
Figure 151: RS485 biasing circuit 332
Figure 152: Remote communication using K-Bus 333
Figure 153: IED attached to separate LANs 336
Figure 154: PRP application in the substation 337
Figure 155: HSR multicast topology 338
Figure 156: HSR unicast topology 339
Figure 157: HSR application in the substation 340
xx P64x-TM-EN-4.1
P64x Table of Figures
Figure 158: IED attached to redundant Ethernet star or ring circuit 340
Figure 159: IED and REB IP address configuration 341
Figure 160: Connection using (a) an Ethernet switch and (b) a media converter 342
Figure 161: Connection using (a) an Ethernet switch and (b) a media converter 346
Figure 162: Control input behaviour 362
Figure 163: Manual selection of a disturbance record 378
Figure 164: Automatic selection of disturbance record - method 1 379
Figure 165: Automatic selection of disturbance record - method 2 380
Figure 166: Configuration file extraction 381
Figure 167: Data file extraction 382
Figure 168: Data model layers in IEC61850 388
Figure 169: Edition 2 system - backward compatibility 393
Figure 170: Edition 1 system - forward compatibility issues 393
Figure 171: Example of Standby IED 394
Figure 172: Standby IED Activation Process 395
Figure 173: GPS Satellite timing signal 398
Figure 174: Timing error using ring or line topology 400
Figure 175: RADIUS server/client communication 418
Figure 176: Rack mounting of products 434
Figure 177: Terminal block types 435
Figure 178: 40TE case dimensions 440
Figure 181: RP1 physical connection 458
Figure 182: Remote communication using K-bus 459
Figure 183: Simulated input behaviour 465
Figure 184: Test example 1 466
Figure 187: Operating Characteristic Diagram 470
Figure 188: Trip Time Test Plane 470
Figure 189: Harmonic Restraint Test Plane 471
Figure 190: Possible terminal block types 482
Figure 191: Front panel assembly 484
P64x-TM-EN-4.1 xxi
xxii P64x-TM-EN-4.1
CHAPTER 1
INTRODUCTION
Chapter 1 - Introduction P64x
2 P64x-TM-EN-4.1
P64x Chapter 1 - Introduction
1 CHAPTER OVERVIEW
This chapter provides some general information about the technical manual and an introduction to the device(s)
described in this technical manual.
This chapter contains the following sections:
Chapter Overview 3
Foreword 4
Product Scope 6
Features and Functions 9
Compliance 11
Functional Overview 12
P64x-TM-EN-4.1 3
2 FOREWORD
This technical manual provides a functional and technical description of General Electric's P642, P643, P645, as
well as a comprehensive set of instructions for using the device. The level at which this manual is written assumes
that you are already familiar with protection engineering and have experience in this discipline. The description of
principles and theory is limited to that which is necessary to understand the product. For further details on general
protection engineering theory, we refer you to General Electric's publication NPAG, which is available online or
from our contact centre.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we
cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be
very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to
provide the information necessary to help you safely specify, engineer, install, commission, maintain, and
eventually dispose of this product. We consider that this manual provides the necessary information, but if you
consider that more details are needed, please contact us.
All feedback should be sent to our contact centre via:
[email protected]
2.1 TARGET AUDIENCE

This manual is aimed towards all professionals charged with installing, commissioning, maintaining,
troubleshooting, or operating any of the products within the specified product range. This includes installation and
commissioning personnel as well as engineers who will be responsible for operating the product.
The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection
systems and associated equipment.
2.2 TYPOGRAPHICAL CONVENTIONS

The following typographical conventions are used throughout this manual.
● The names for special keys appear in capital letters.
For example: ENTER
● When describing software applications, menu items, buttons, labels etc as they appear on the screen are
written in bold type.
For example: Select Save from the file menu.
● Filenames and paths use the courier font
For example: Example\File.text
● Special terminology is written with leading capitals
For example: Sensitive Earth Fault
● If reference is made to the IED's internal settings and signals database, the menu group heading (column)
text is written in upper case italics
For example: The SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are
written in bold italics
For example: The Language cell in the SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the value of a cell's content is
written in the Courier font
For example: The Language cell in the SYSTEM DATA column contains the value English
4 P64x-TM-EN-4.1
2.3 NOMENCLATURE
Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout
the manual. Some of these terms are well-known industry-specific terms while others may be special product-
specific terms used by General Electric. The first instance of any acronym or term used in a particular chapter is
explained. In addition, a separate glossary is available on the General Electric website, or from the General Electric
contact centre.
We would like to highlight the following changes of nomenclature however:
● The word 'relay' is no longer used to describe the device itself. Instead, the device is referred to as the 'IED'
(Intelligent Electronic Device), the 'device', or the 'product'. The word 'relay' is used purely to describe the
electromechanical components within the device, i.e. the output relays.
● British English is used throughout this manual.
● The British term 'Earth' is used in favour of the American term 'Ground'.
P64x-TM-EN-4.1 5
3 PRODUCT SCOPE
The MiCOM P64x range of devices preserve transformer service life by offering fast protection for transformer
faults. Hosted on an advanced IED platform, the P64x products incorporate Current Differential, Restricted Earth
Fault (REF),Thermal, and Overfluxing protection, plus backup protection for uncleared external faults. Further, the
P64x devices provide a range of transformer condition monitoring functions such as Through-fault monitoring,
loss of life statistics, RTD and CLIO protection functionality.
All devices also provide a comprehensive range of additional features to aid with power system diagnosis and fault
analysis.
Model variants cover two and three winding power transformers, with up to five sets of 3-phase CT inputs. Backup
overcurrent protection can be directionalised, if you select the optional 3-phase VT input.
The P64x range consists of three models; the P642, P643, and P645.
● The P642 provides 8 on-board CTs to support two-winding 3-phase power transformers and 1or 2 single-
phase voltage transformers to support directionalisation and a range of voltage-related functions.
● The P643 provides 12 on-board CTs to support three-winding 3-phase power transformers, a single-phase
voltage transformer and an optional three-phase voltage transformer to support directionalisation and a
range of voltage-related functions including undervoltage, overvoltage and residual overvoltage protection.
● The P645 provides 18 on-board CTs to support three-winding 3-phase power transformers and other
applications needing 5 sets of 3-phase current inputs, a single-phase voltage transformer and an optional
three-phase voltage transformer to support directionalisation and a range of voltage-related functions
including undervoltage, overvoltage and residual overvoltage protection.
The difference in model variants are summarised below:
Feature/Variant P642 P643 P645
Case 40TE 60TE/80TE 60TE/80TE
Number of CT Inputs 8 (6 Bias, 2 EF) 12 (9 bias, 3EF) 18 (15 Bias, 3EF)
Number of VT inputs 1 or 2 1 or 4 1 or 4
Number of bias inputs (3-phase CT sets) 2 3 5
Optically coupled digital inputs 8 - 12 16 - 40 16 - 40
Standard relay output contacts 8 - 12 8 - 24 8 - 24
Function keys No 10 10
Undervoltage/Overvoltage/Residual voltage protection No Yes Yes
Underfrequency/Overfrequency protection No Yes Yes
Overfluxing protection 1-phase only 1-phase + 3-phase 1-phase + 3-phase
Programmable LEDs 8 red 18 tri-colour 18 tri-colour
3.1 PRODUCT VERSIONS

Since software version 2, the evolution of the P64x product family has followed two paths as shown below:
6 P64x-TM-EN-4.1
J, K
02
Hardware version K (P645SV) Hardware version J (P642), K (P643/5)

Software version 12 Software version 04
 Hot-Standby Ethernet Failover  Negative Sequence Overvoltage
 Cyber Security  Voltage Controlled Overcurrent
 IEC61850 9-2L Edition 1  Low Impedance REF for autotransformer
 High Impedance REF
 User Alarms
 CT Exclusion
Hardware version M (P645SV)
Software version 20
 IEC61850 9-2LE Edition 2 Hardware version P (P642), M (P643/5)
Software version 05
 Hot-Standby Ethernet Failover
 Cyber Security
 More Disturbance Record channels
Software version 22
 Inclusion of duplicate GOOSE Hardware version P (P642), M (P643/5)
 IRG-B local sync function, for IRIG-B type Software version 06
changes from UTC to local
 New DDBs added to indicate blocked  Extra I/O (40 opto-inputs)
password  2nd harmonic blocking for E/F, REF, POC
 Setting name and DDB signal changes
 Setting range extensions
 Vector Group Reference change
 Changes to default PSL
Software version 90
 IEC 61850 Edition 1 & 2 switching Hardware version P (P642), M (P643/5)
 RBAC Software version 07
 Syslog  Sensitive CT module
 Multi-client RCB  Voltage restraining overcurrent
 Additional fault record data
Hardware version P (P642), M (P643/5)

Software version 21
 IEC 61850 Edition 2
 Fourth neutral current element, derived
 Internal/external CBF initiation
 CB Control including XCBR
 UTC/Local feature in IRIG-B
Hardware version P (P642), M (P643/5)

Software version 91
 IEC 61850 Edition 1 & 2 switching
 RBAC
 Syslog
 Multi-client RCB
V00035
Figure 1: P64x version evolution
P64x-TM-EN-4.1 7
3.2 ORDERING OPTIONS

All current models and variants for this product are defined in an interactive spreadsheet called the CORTEC. This is
available on the company website.
Alternatively, you can obtain it via the Contact Centre at:
[email protected]
A copy of the CORTEC is also supplied as a static table in the Appendices of this document. However, it should only
be used for guidance as it provides a snapshot of the interactive data taken at the time of publication.
This technical manual is applicable to the product version M06
8 P64x-TM-EN-4.1
4 FEATURES AND FUNCTIONS
4.1 PROTECTION FUNCTIONS

The P64x range of devices provides the following protection functions:
ANSI IEC 61850 Protection Function P642 P643 P645
87T LzdPDIF Transformer biased differential protection • • •
64 RefPDIF Low Impedance and High Impedance Restricted Earth Fault protection 2 3 3
49 ThmPTTR Thermal Overload (3 stages) • • •
24 PVPH Single-phase and three-phase V/Hz Overfluxing protection (4 stages) 1 1 (2) 1 (2)
LoL Loss of Life • • •
Thru Through-fault monitoring • • •
RTD RtfPTTR RTDs x 10 PT100 temperature probes (•) (•) (•)
CLIO PTUC Current Loop transducer I/O (4 input / 4 output) (•) (•) (•)
50 OcpPTOC Definite time overcurrent protection (4 stages per winding) • • •
50N EfdPTOC Neutral/Ground Definite time overcurrent protection (4 stages per winding) • • •
51 OcpPTOC IDMT overcurrent protection (2 stages per winding) • • •
51N EfdPTOC Neutral/Ground IDMT overcurrent protection (2 stages per winding) • • •
46 NgcPTOC Negative sequence overcurrent (4 stages per winding) • • •
67 OcpPTOC Directional Phase Overcurrent protection (4 stages per winding) • • •
67N EfdPTOC Directional earth fault overcurrent protection (4 stages per winding) • • •
50BF RBRF CB Failure (Breaker Fail) protection (2 stages per winding) 2 3 5
27 VtpPhsPTUV Undervoltage protection (2 stages) (•) (•)
59 VtpPhsPTOV Overvoltage protection (2 stages) (•) (•)
59N VtpResPTOV Residual Overvoltage protection (2 stages) (•) (•)
47 NgvPTOV Negative sequence overvoltage protection (1 stage) (•) (•) (•)
81U FrqPTUF Underfrequency protection (4 stages) (•) (•)
81O FrqPTOF Overfrequency protection (2 stages) (•) (•)
Note:
If item is enclosed in brackets, this indicates that the feature is an ordering option.
4.2 CONTROL FUNCTIONS
Feature IEC 61850 ANSI

Watchdog contacts
Read-only mode
NERC compliant cyber-security
Function keys (up to 10) FnkGGIO
Programmable LEDs (up to 18) LedGGIO
Programmable hotkeys (2)
Programmable allocation of digital inputs and outputs
Fully customizable menu texts
Circuit breaker control, status & condition monitoring XCBR 52
P64x-TM-EN-4.1 9
Feature IEC 61850 ANSI

Trip circuit and coil supervision
Control inputs PloGGIO1
Power-up diagnostics and continuous self-monitoring
Dual rated 1A and 5A CT inputs
Alternative setting groups (4)
Graphical programmable scheme logic (PSL)
4.3 MEASUREMENT FUNCTIONS
Measurement Function IEC 61850 ANSI

Measurement of all instantaneous & integrated values
MET
(Exact range of measurements depend on the device model)
Disturbance recorder for waveform capture – specified in samples per cycle RDRE DFR
Fault Records
Maintenance Records
Event Records / Event logging Event records
Time Stamping of Opto-inputs Yes Yes
4.4 COMMUNICATION FUNCTIONS

The device offers the following communication functions:
Feature ANSI
NERC compliant cyber-security
Front RS232 serial communication port for configuration 16S
Rear serial RS485 communication port for SCADA control 16S
2nd Additional rear serial communication ports for SCADA control and
16S
teleprotection (fibre and copper) (optional)
Ethernet communication (optional) 16E
Redundant Ethernet communication (optional) 16E
Courier protocol 16S
IEC 61850 Edition 1 or 2 (optional) 16E
IEC 60870-5-103 protocol (optional) 16S
Modbus protocol (optional) 16S
DNP3.0 protocol over serial link (optional) 16S
DNP3.0 protocol over Ethernet (optional) 16E
IRIG-B time synchronisation (optional) CLK
IEEE 1588 PTP (Edition 2 devices only)
10 P64x-TM-EN-4.1
5 COMPLIANCE
The device has undergone a range of extensive testing and certification processes to ensure and prove
compatibility with all target markets. A detailed description of these criteria can be found in the Technical
Specifications chapter.
P64x-TM-EN-4.1 11
6 FUNCTIONAL OVERVIEW
2nd Remote Remote Local

Ethernet Fault records
Comm. port Comm. port Communication
Disturbance
Record
I-HV Measurements
Self monitoring
47
IN-HV
50N/51N 50N/51N
IN-LV EF-1 EF-3 51V 51V
50N/51N 50N/51N DT IDMT
EF-2 EF-4
I-LV
DIFF
Thru CTS
IN-TV
I-TV
virtual
I-TV
Always Available Transformer Differential
BINARY MEASO
CLIO I/O
RTDs MEASI
Protection P64x
Optional or Specific
1. The three-phase VT input is optional.

2. The 27, 59, 59N and VTS functions require the three-phase VT input.
3. The frequency required by the 81 function is obtained from any analog signal but the voltage signals have priority over the current signals.
E00073
Figure 2: Functional overview
12 P64x-TM-EN-4.1
CHAPTER 2
SAFETY INFORMATION
Chapter 2 - Safety Information P64x
14 P64x-TM-EN-4.1
P64x Chapter 2 - Safety Information
1 CHAPTER OVERVIEW
This chapter provides information about the safe handling of the equipment. The equipment must be properly
installed and handled in order to maintain it in a safe condition and to keep personnel safe at all times. You must
be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the
equipment.
Chapter Overview 15
Health and Safety 16
Symbols 17
Installation, Commissioning and Servicing 18
Decommissioning and Disposal 24
Regulatory Compliance 25
P64x-TM-EN-4.1 15
2 HEALTH AND SAFETY

Personnel associated with the equipment must be familiar with the contents of this Safety Information.
When electrical equipment is in operation, dangerous voltages are present in certain parts of the equipment.
Improper use of the equipment and failure to observe warning notices will endanger personnel.
Only qualified personnel may work on or operate the equipment. Qualified personnel are individuals who are:
● familiar with the installation, commissioning, and operation of the equipment and the system to which it is
being connected.
● familiar with accepted safety engineering practises and are authorised to energise and de-energise
equipment in the correct manner.
● trained in the care and use of safety apparatus in accordance with safety engineering practises
● trained in emergency procedures (first aid).
The documentation provides instructions for installing, commissioning and operating the equipment. It cannot,
however cover all conceivable circumstances. In the event of questions or problems, do not take any action
without proper authorisation. Please contact your local sales office and request the necessary information.
16 P64x-TM-EN-4.1
3 SYMBOLS
Throughout this manual you will come across the following symbols. You will also see these symbols on parts of
the equipment.
Caution:
Refer to equipment documentation. Failure to do so could result in damage to the
equipment
Warning:
Risk of electric shock
Warning:
Risk of damage to eyesight
Earth terminal. Note: This symbol may also be used for a protective conductor (earth) terminal if that terminal
is part of a terminal block or sub-assembly.
Protective conductor (earth) terminal
Instructions on disposal requirements
Note:
The term 'Earth' used in this manual is the direct equivalent of the North American term 'Ground'.
P64x-TM-EN-4.1 17
4 INSTALLATION, COMMISSIONING AND SERVICING
4.1 LIFTING HAZARDS

Many injuries are caused by:
● Lifting heavy objects
● Lifting things incorrectly
● Pushing or pulling heavy objects
● Using the same muscles repetitively
Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of
moving the load to avoid manual handling. Use the correct lifting techniques and Personal Protective Equipment
(PPE) to reduce the risk of injury.
4.2 ELECTRICAL HAZARDS
Caution:
All personnel involved in installing, commissioning, or servicing this equipment must be
familiar with the correct working procedures.
Caution:
Consult the equipment documentation before installing, commissioning, or servicing
the equipment.
Caution:
Always use the equipment as specified. Failure to do so will jeopardise the protection
provided by the equipment.
Warning:
Removal of equipment panels or covers may expose hazardous live parts. Do not touch
until the electrical power is removed. Take care when there is unlocked access to the
rear of the equipment.
Warning:
Isolate the equipment before working on the terminal strips.
Warning:
Use a suitable protective barrier for areas with restricted space, where there is a risk of
electric shock due to exposed terminals.
Caution:
Disconnect power before disassembling. Disassembly of the equipment may expose
sensitive electronic circuitry. Take suitable precautions against electrostatic voltage
discharge (ESD) to avoid damage to the equipment.
18 P64x-TM-EN-4.1
Warning:
NEVER look into optical fibres or optical output connections. Always use optical power
meters to determine operation or signal level.
Warning:
Testing may leave capacitors charged to dangerous voltage levels. Discharge
capacitors by reducing test voltages to zero before disconnecting test leads.
Caution:
Operate the equipment within the specified electrical and environmental limits.
Caution:
Before cleaning the equipment, ensure that no connections are energised. Use a lint
free cloth dampened with clean water.
Note:
Contact fingers of test plugs are normally protected by petroleum jelly, which should not be removed.
4.3 UL/CSA/CUL REQUIREMENTS

The information in this section is applicable only to equipment carrying UL/CSA/CUL markings.
Caution:
Equipment intended for rack or panel mounting is for use on a flat surface of a Type 1
enclosure, as defined by Underwriters Laboratories (UL).
Caution:
To maintain compliance with UL and CSA/CUL, install the equipment using UL/CSA-
recognised parts for: cables, protective fuses, fuse holders and circuit breakers,
insulation crimp terminals, and replacement internal batteries.
4.4 FUSING REQUIREMENTS
Caution:
Where UL/CSA listing of the equipment is required for external fuse protection, a UL or
CSA Listed fuse must be used for the auxiliary supply. The listed protective fuse type is:
Class J time delay fuse, with a maximum current rating of 15 A and a minimum DC
rating of 250 V dc (for example type AJT15).
Caution:
Where UL/CSA listing of the equipment is not required, a high rupture capacity (HRC)
fuse type with a maximum current rating of 16 Amps and a minimum dc rating of 250 V
dc may be used for the auxiliary supply (for example Red Spot type NIT or TIA).
For P50 models, use a 1A maximum T-type fuse.
For P60 models, use a 4A maximum T-type fuse.
P64x-TM-EN-4.1 19
Caution:
Digital input circuits should be protected by a high rupture capacity NIT or TIA fuse with
maximum rating of 16 A. for safety reasons, current transformer circuits must never be
fused. Other circuits should be appropriately fused to protect the wire used.
Caution:
CTs must NOT be fused since open circuiting them may produce lethal hazardous
voltages
4.5 EQUIPMENT CONNECTIONS
Warning:
Terminals exposed during installation, commissioning and maintenance may present a
hazardous voltage unless the equipment is electrically isolated.
Caution:
Tighten M4 clamping screws of heavy duty terminal block connectors to a nominal
torque of 1.3 Nm.
Tighten captive screws of terminal blocks to 0.5 Nm minimum and 0.6 Nm maximum.
Caution:
Always use insulated crimp terminations for voltage and current connections.
Caution:
Always use the correct crimp terminal and tool according to the wire size.
Caution:
Watchdog (self-monitoring) contacts are provided to indicate the health of the device
on some products. We strongly recommend that you hard wire these contacts into the
substation's automation system, for alarm purposes.
4.6 PROTECTION CLASS 1 EQUIPMENT REQUIREMENTS
Caution:
Earth the equipment with the supplied PCT (Protective Conductor Terminal).
Caution:
Do not remove the PCT.
Caution:
The PCT is sometimes used to terminate cable screens. Always check the PCT’s integrity
after adding or removing such earth connections.
20 P64x-TM-EN-4.1
Caution:
Use a locknut or similar mechanism to ensure the integrity of stud-connected PCTs.
Caution:
The recommended minimum PCT wire size is 2.5 mm² for countries whose mains supply
is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North
America). This may be superseded by local or country wiring regulations.
For P60 products, the recommended minimum PCT wire size is 6 mm². See product
documentation for details.
Caution:
The PCT connection must have low-inductance and be as short as possible.
Caution:
All connections to the equipment must have a defined potential. Connections that are
pre-wired, but not used, should be earthed, or connected to a common grouped
potential.
4.7 PRE-ENERGISATION CHECKLIST
Caution:
Check voltage rating/polarity (rating label/equipment documentation).
Caution:
Check CT circuit rating (rating label) and integrity of connections.
Caution:
Check protective fuse or miniature circuit breaker (MCB) rating.
Caution:
Check integrity of the PCT connection.
Caution:
Check voltage and current rating of external wiring, ensuring it is appropriate for the
application.
4.8 PERIPHERAL CIRCUITRY
Warning:
Do not open the secondary circuit of a live CT since the high voltage produced may be
lethal to personnel and could damage insulation. Short the secondary of the line CT
before opening any connections to it.
P64x-TM-EN-4.1 21
Note:
For most General Electric equipment with ring-terminal connections, the threaded terminal block for current transformer
termination is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required.
Check the equipment documentation and wiring diagrams first to see if this applies.
Caution:
Where external components such as resistors or voltage dependent resistors (VDRs) are
used, these may present a risk of electric shock or burns if touched.
Warning:
Take extreme care when using external test blocks and test plugs such as the MMLG,
MMLB and P990, as hazardous voltages may be exposed. Ensure that CT shorting links
are in place before removing test plugs, to avoid potentially lethal voltages.
Warning:
Data communication cables with accessible screens and/or screen conductors,
(including optical fibre cables with metallic elements), may create an electric shock
hazard in a sub-station environment if both ends of the cable screen are not connected
to the same equipotential bonded earthing system.
To reduce the risk of electric shock due to transferred potential hazards:
i. The installation shall include all necessary protection measures to ensure that no
fault currents can flow in the connected cable screen conductor.
ii. The connected cable shall have its screen conductor connected to the protective
conductor terminal (PCT) of the connected equipment at both ends. This connection
may be inherent in the connectors provided on the equipment but, if there is any doubt,
this must be confirmed by a continuity test.
iii. The protective conductor terminal (PCT) of each piece of connected equipment shall
be connected directly to the same equipotential bonded earthing system.
iv. If, for any reason, both ends of the cable screen are not connected to the same
equipotential bonded earth system, precautions must be taken to ensure that such
screen connections are made safe before work is done to, or in proximity to, any such
cables.
v. No equipment shall be connected to any download or maintenance circuits or

connectors of this product except temporarily and for maintenance purposes only.
vi. Equipment temporarily connected to this product for maintenance purposes shall be
protectively earthed (if the temporary equipment is required to be protectively
earthed), directly to the same equipotential bonded earthing system as the product.
Warning:
Small Form-factor Pluggable (SFP) modules which provide copper Ethernet connections
typically do not provide any additional safety isolation. Copper Ethernet SFP modules
must only be used in connector positions intended for this type of connection.
22 P64x-TM-EN-4.1
4.9 UPGRADING/SERVICING
Warning:
Do not insert or withdraw modules, PCBs or expansion boards from the equipment
while energised, as this may result in damage to the equipment. Hazardous live
voltages would also be exposed, endangering personnel.
Caution:
Internal modules and assemblies can be heavy and may have sharp edges. Take care
when inserting or removing modules into or out of the IED.
P64x-TM-EN-4.1 23
5 DECOMMISSIONING AND DISPOSAL
Caution:
Before decommissioning, completely isolate the equipment power supplies (both poles
of any dc supply). The auxiliary supply input may have capacitors in parallel, which may
still be charged. To avoid electric shock, discharge the capacitors using the external
terminals before decommissioning.
Caution:
Avoid incineration or disposal to water courses. Dispose of the equipment in a safe,
responsible and environmentally friendly manner, and if applicable, in accordance with
country-specific regulations.
24 P64x-TM-EN-4.1
6 REGULATORY COMPLIANCE
Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file.
6.1 EMC COMPLIANCE: 2014/30/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformity
assessment used to demonstrate compliance with the EMC directive.
6.2 LVD COMPLIANCE: 2014/35/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonized standard(s) or conformity
assessment used to demonstrate compliance with the LVD directive.
Safety related information, such as the installation I overvoltage category, pollution degree and operating
temperature ranges are specified in the Technical Data section of the relevant product documentation and/or on
the product labelling.
Unless otherwise stated in the Technical Data section of the relevant product documentation, the equipment is
intended for indoor use only. Where the equipment is required for use in an outdoor location, it must be mounted
in a specific cabinet or housing to provide the equipment with the appropriate level of protection from the
expected outdoor environment.
6.3 R&TTE COMPLIANCE: 2014/53/EU

Radio and Telecommunications Terminal Equipment (R&TTE) directive 2014/53/EU.
Conformity is demonstrated by compliance to both the EMC directive and the Low Voltage directive, to zero volts.
6.4 UL/CUL COMPLIANCE

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.
The relevant UL file number and ID is shown on the equipment.
P64x-TM-EN-4.1 25
26 P64x-TM-EN-4.1
CHAPTER 3
HARDWARE DESIGN
Chapter 3 - Hardware Design P64x
28 P64x-TM-EN-4.1
P64x Chapter 3 - Hardware Design
1 CHAPTER OVERVIEW
This chapter provides information about the product's hardware design.
Chapter Overview 29
Hardware Architecture 30
Mechanical Implementation 31
Front Panel 33
Rear Panel 37
Boards and Modules 39
P64x-TM-EN-4.1 29
2 HARDWARE ARCHITECTURE
The main components comprising devices based on the Px4x platform are as follows:
● The housing, consisting of a front panel and connections at the rear
● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface
to the front panel HMI (Human Machine Interface)
● A selection of plug-in boards and modules with presentation at the rear for the power supply,
communication functions, digital I/O, analogue inputs, and time synchronisation connectivity
All boards and modules are connected by a parallel data and address bus, which allows the processor module to
send and receive information to and from the other modules as required. There is also a separate serial data bus
for conveying sampled data from the input module to the CPU. These parallel and serial databuses are shown as a
single interconnection module in the following figure, which shows typical modules and the flow of data between
them.
Keypad
Output relay boards Output relay contacts
Processor module
Front panel HMI
LCD
Opto-input boards Digital inputs
LEDs
I/O
Front port
CTs Power system currents
Memory
Interconnection
Flash memory for settings VTs Power system voltages
Backed-up SRAM Analogue Inputs

for records
RS485 modules RS485 communication

Watchdog
contacts Watchdog module
IRIG-B module Time synchronisation
+ LED
Ethernet modules Ethernet communication

Auxiliary
PSU module
Supply Communications
Note: Not all modules are applicable to all products
V00233
Figure 3: Hardware architecture
30 P64x-TM-EN-4.1
3 MECHANICAL IMPLEMENTATION
All products based on the Px4x platform have common hardware architecture. The hardware is modular and
consists of the following main parts:
● Case and terminal blocks
● Boards and modules
● Front panel
The case comprises the housing metalwork and terminal blocks at the rear. The boards fasten into the terminal
blocks and are connected together by a ribbon cable. This ribbon cable connects to the processor in the front
panel.
The following diagram shows an exploded view of a typical product. The diagram shown does not necessarily
represent exactly the product model described in this manual.
Figure 4: Exploded view of IED
3.1 HOUSING VARIANTS

The Px4x range of products are implemented in a range of case sizes. Case dimensions for industrial products
usually follow modular measurement units based on rack sizes. These are: U for height and TE for width, where:
● 1U = 1.75 inches = 44.45 mm
● 1TE = 0.2 inches = 5.08 mm
The products are available in panel-mount or standalone versions. All products are nominally 4U high. This equates
to 177.8 mm or 7 inches.
The cases are pre-finished steel with a conductive covering of aluminium and zinc. This provides good grounding
at all joints, providing a low resistance path to earth that is essential for performance in the presence of external
noise.
The case width depends on the product type and its hardware options. There are three different case widths for
the described range of products: 40TE, 60TE and 80TE. The case dimensions and compatibility criteria are as
follows:
Case width (TE) Case width (mm) Case width (inches)
40TE 203.2 8
P64x-TM-EN-4.1 31
Case width (TE) Case width (mm) Case width (inches)

60TE 304.8 12
80TE 406.4 16
Note:
Not all case sizes are available for all models.
3.2 LIST OF BOARDS

The product's hardware consists of several modules drawn from a standard range. The exact specification and
number of hardware modules depends on the model number and variant. Depending on the exact model, the
product in question will use a selection of the following boards.
Board Use
Main Processor board – 40TE or smaller Main Processor board – without support for function keys
Main Processor board – 60TE or larger Main Processor board – with support for function keys
Power supply board 24/54 V DC Power supply input. Accepts DC voltage between 24 V and 54 V
Power supply board - 48/125 V DC Power supply input. Accepts DC voltage between 48 V and 125 V
Power supply board 110/250 V DC Power supply input. Accepts DC voltage between 110 V and 250 V
Instrument Transformer board Contains the voltage and current transformers
Input board Contains the A/D conversion circuitry
Input board with opto-inputs Contains the A/D conversion circuitry + 8 digital opto-inputs
Opto-input board Contains 8 digital opto-inputs
Output relay board Contains 8 digital output relays
Combined Opto-input / Output relay board Contains 4 digital opto-inputs and 4 digital output relays
IRIG-B board - modulated Interface board for modulated IRIG-B timing signal
IRIG-B - demodulated input Interface board for demodulated IRIG-B timing signal
Fibre optic board Interface board for fibre-based RS485 connection
Fibre optic board + IRIG-B Interface board for fibre-based RS485 connection + demodulated IRIG-B
2nd rear communications board Interface board for RS232 / RS485 connections
2nd rear communications board with IRIG-B input Interface board for RS232 / RS485 + IRIG-B connections
Redundant Ethernet RSTP + PRP + HSR + Failover Redundant Ethernet running RSTP + PRP + HSR + Failover (two fibre pairs), with on-
universal IRIG-B board universal IRIG-B
Redundant Ethernet RSTP + PRP + HSR + Failover Redundant Ethernet running RSTP + PRP + HSR + Failover (two copper pairs), with
universal IRIG-B on-board universal IRIG-B
Single Ethernet RSTP + PRP + HSR + Failover universal Single Ethernet running RSTP + PRP + HSR + Failover (one copper, one multi-mode
IRIG-B fibre), with on-board universal IRIG-B
Output relay output board (8 outputs) Standard output relay board with 8 outputs
RTD board Contains 10 Resistive Temperature Device inputs
CLIO board Contains 4 current loop inputs and 4 current loop outputs
High Break Output Relay Board Output relay board with high breaking capacity relays
32 P64x-TM-EN-4.1
4 FRONT PANEL
4.1 FRONT PANEL

Depending on the exact model and chosen options, the product will be housed in either a 40TE, 60TE or 80TE case.
By way of example, the following diagram shows the front panel of a typical 60TE unit. The front panels of the
products based on 40TE and 80TE cases have a lot of commonality and differ only in that the 40TE front panel
does not include 10 function keys with their associated user-programmable LEDs.
Figure 5: Front panel (60TE)
The front panel consists of:

● Top and bottom compartments with hinged cover
● LCD display
● Keypad
● USB Type B port inside the bottom compartment
● Fixed function LEDs
● Function keys and LEDs (60TE and 80TE models)
● Programmable LEDs
4.1.1 FRONT PANEL COMPARTMENTS

The top compartment contains labels for the:
● Serial number
● Current and voltage ratings.
P64x-TM-EN-4.1 33
The bottom compartment contains:

● USB Type B port
4.1.2 HMI PANEL

The keypad provides full access to the device functionality using a range of menu options. The information is
displayed on the LCD.The LCD is a high resolution monochrome display with 16 characters by 3 lines and
controllable back light.
Figure 6: HMI panel
Note:
As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form.
4.1.3 KEYPAD
The keypad consists of the following keys:
4 arrow keys to navigate the menus (organised around the Enter key)
34 P64x-TM-EN-4.1
An enter key for executing the chosen option
A clear key for clearing the last command
A read key for viewing larger blocks of text (arrow keys now used for
scrolling)
2 hot keys for scrolling through the default display and for control of
setting groups. These are situated directly below the LCD display.
4.1.3.1 LIQUID CRYSTAL DISPLAY

The LCD is a high resolution monochrome display with 16 characters by 3 lines and controllable back light.
4.1.4 USB PORT

The USB port is situated inside the bottom compartment, and is used to communicate with a locally connected PC.
It has two main purposes:
● To transfer settings information to/from the PC from/to the device.
● For downloading firmware updates and menu text editing.
The port is intended for temporary connection during testing, installation and commissioning. It is not intended to
be used for permanent SCADA communications. This port supports the Courier communication protocol only.
Courier is a proprietary communication protocol to allow communication with a range of protection equipment,
and between the device and the Windows-based support software package.
You can connect the unit to a PC with a USB cable up to 5 m in length.
The inactivity timer for the front port is set to 15 minutes. This controls how long the unit maintains its level of
password access on the front port. If no messages are received on the front port for 15 minutes, any password
access level that has been enabled is cancelled.
Note:
The front USB port does not support automatic extraction of event and disturbance records, although this data can be
accessed manually.
Caution:
When not in use, always close the cover of the USB port to prevent contamination.
P64x-TM-EN-4.1 35
4.1.5 FIXED FUNCTION LEDS

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.
● Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is
cleared from the front display. Also the trip LED can be configured as self-resetting.
● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or
maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.
● Out of service (Yellow) is ON when the IED's functions are unavailable.
● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if
the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.
4.1.6 FUNCTION KEYS

The programmable function keys are available for custom use for some models.
Factory default settings associate specific functions to these keys, but by using programmable scheme logic, you
can change the default functions of these keys to fit specific needs. Adjacent to these function keys are
programmable LEDs, which are usually set to be associated with their respective function keys.
4.1.7 PROGRAMABLE LEDS

The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The
programmable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the
programmable LEDs for some models are single-colour (red) only. The single-colour LEDs can be recognised by
virtue of the fact they are large and slightly oval, whereas the tri-colour LEDs are small and round.
36 P64x-TM-EN-4.1
5 REAR PANEL
The MiCOM Px40 series uses a modular construction. Most of the internal workings are on boards and modules
which fit into slots. Some of the boards plug into terminal blocks, which are bolted onto the rear of the unit.
However, some boards such as the communications boards have their own connectors. The rear panel consists of
these terminal blocks plus the rears of the communications boards.
The back panel cut-outs and slot allocations vary. This depends on the product, the type of boards and the
terminal blocks needed to populate the case. The following diagram shows a typical rear view of a case populated
with various boards.
Figure 7: Rear view of populated case
Note:
This diagram is just an example and may not show the exact product described in this manual. It also does not show the full
range of available boards, just a typical arrangement.
Not all slots are the same size. The slot width depends on the type of board or terminal block. For example, HD
(heavy duty) terminal blocks, as required for the analogue inputs, require a wider slot size than MD (medium duty)
terminal blocks. The board positions are not generally interchangeable. Each slot is designed to house a particular
type of board. Again this is model-dependent.
The device may use one or more of the terminal block types shown in the following diagram. The terminal blocks
are fastened to the rear panel with screws.
● Heavy duty (HD) terminal blocks for CT and VT circuits
● Medium duty (MD) terminal blocks for the power supply, opto-inputs, relay outputs and rear
communications port
● MiDOS terminal blocks for CT and VT circuits
● RTD/CLIO terminal block for connection to analogue transducers
P64x-TM-EN-4.1 37
,
Figure 8: Terminal block types
Note:
Not all products use all types of terminal blocks. The product described in this manual may use one or more of the above
types.
5.1 TERMINAL BLOCK INGRESS PROTECTION

IP2x shields and side cover panels are designed to provide IP20 ingress protection for MiCOM terminal blocks. The
shields and covers may be attached during installation or retrofitted to upgrade existing installations—see figure
below. For more information, contact your local sales office or our worldwide Contact Centre.
Figure 9: Example—fitted IP2x shields (cabling omitted for clarity)
38 P64x-TM-EN-4.1
6 BOARDS AND MODULES

Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen
configuration.
6.1 PCBS
A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via
a ribbon cable, and an interface to the rear. This rear interface may be:
● Directly presented to the outside world (as is the case for communication boards such as Ethernet Boards)
● Presented to a connector, which in turn connects into a terminal block bolted onto the rear of the case (as is
the case for most of the other board types)
Figure 10: Rear connection to terminal block
6.2 SUBASSEMBLIES
A sub-assembly consists of two or more boards bolted together with spacers and connected with electrical
connectors. It may also have other special requirements such as being encased in a metal housing for shielding
against electromagnetic radiation.
Boards are designated by a part number beginning with ZN, whereas pre-assembled sub-assemblies are
designated with a part number beginning with GN. Sub-assemblies, which are put together at the production
stage, do not have a separate part number.
P64x-TM-EN-4.1 39
The products in the Px40 series typically contain two sub-assemblies:

● The power supply assembly comprising:
○ A power supply board
○ An output relay board
● The input module comprising:
○ One or more transformer boards, which contains the voltage and current transformers (partially or
fully populated)
○ One or more input boards
○ Metal protective covers for EM (electromagnetic) shielding
The input module is pre-assembled and is therefore assigned a GN number, whereas the power supply module is
assembled at production stage and does not therefore have an individual part number.
6.3 MAIN PROCESSOR BOARD
Figure 11: Main processor board
The main processor board performs all calculations and controls the operation of all other modules in the IED,
including the data communication and user interfaces. This is the only board that does not fit into one of the slots.
It resides in the front panel and connects to the rest of the system using an internal ribbon cable.
The LCD and LEDs are mounted on the processor board along with the front panel communication ports.
The memory on the main processor board is split into two categories: volatile and non-volatile. The volatile
memory is fast access SRAM, used by the processor to run the software and store data during calculations. The
non-volatile memory is sub-divided into two groups:
● Flash memory to store software code, text and configuration data including the present setting values.
● Supercapacitor-backed SRAM to store disturbance, event, fault and maintenance record data.
There are two board types available depending on the size of the case:
● For models in 40TE cases
● For models in 60TE cases and larger
40 P64x-TM-EN-4.1
6.4 POWER SUPPLY BOARD
Figure 12: Power supply board
The power supply board provides power to the unit. One of three different configurations of the power supply
board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply
voltage that will be connected to it.
There are three board types, which support the following voltage ranges:
● 24/54 V DC
● 48/125 V DC or 40-100V AC
● 110/250 V DC or 100-240V AC
The power supply board connector plugs into a medium duty terminal block. This terminal block is always
positioned on the right hand side of the unit looking from the rear.
The power supply board is usually assembled together with a relay output board to form a complete subassembly,
as shown in the following diagram.
P64x-TM-EN-4.1 41
Figure 13: Power supply assembly
The power supply outputs are used to provide isolated power supply rails to the various modules within the unit.
Three voltage levels are used by the unit’s modules:
● 5.1 V for all of the digital circuits
● +/- 16 V for the analogue electronics such as on the input board
● 22 V for driving the output relay coils.
All power supply voltages, including the 0 V earth line, are distributed around the unit by the 64-way ribbon cable.
The power supply board incorporates inrush current limiting. This limits the peak inrush current to approximately
10 A.
Power is applied to pins 1 and 2 of the terminal block, where pin 1 is negative and pin 2 is positive. The pin
numbers are clearly marked on the terminal block as shown in the following diagram.
42 P64x-TM-EN-4.1
Figure 14: Power supply terminals
6.4.1 WATCHDOG
The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output
relay contacts, one normally open and one normally closed. These are used to indicate the health of the device
and are driven by the main processor board, which continually monitors the hardware and software when the
device is in service.
P64x-TM-EN-4.1 43
Figure 15: Watchdog contact terminals
6.4.2 REAR SERIAL PORT

The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial
communications port and is intended for use with a permanently wired connection to a remote control centre for
SCADA communication. The interface supports half-duplex communication and provides optical isolation for the
serial data being transmitted and received.
The physical connectivity is achieved using three screw terminals; two for the signal connection, and the third for
the earth shield of the cable. These are located on pins 16, 17 and 18 of the power supply terminal block, which is
on the far right looking from the rear. The interface can be selected between RS485 and K-bus. When the K-Bus
option is selected, the two signal connections are not polarity conscious.
The polarity independent K-bus can only be used for the Courier data protocol. The polarity conscious MODBUS,
IEC 60870-5-103 and DNP3.0 protocols need RS485.
The following diagram shows the rear serial port. The pin assignments are as follows:
● Pin 16: Earth shield
● Pin 17: Negative signal
● Pin 18: Positive signal
44 P64x-TM-EN-4.1
Figure 16: Rear serial port terminals
An additional serial port with D-type presentation is available as an optional board, if required.
6.5 INPUT MODULE - 1 TRANSFORMER BOARD
Figure 17: Input module - 1 transformer board
The input module consists of the main input board coupled together with an instrument transformer board. The
instrument transformer board contains the voltage and current transformers, which isolate and scale the
analogue input signals delivered by the system transformers. The input board contains the A/D conversion and
digital processing circuitry, as well as eight digital isolated inputs (opto-inputs).
The boards are connected together physically and electrically. The module is encased in a metal housing for
shielding against electromagnetic interference.
P64x-TM-EN-4.1 45
6.5.1 INPUT MODULE CIRCUIT DESCRIPTION
Optical 8 digital inputs Optical

Isolator Isolator
Noise Noise
filter filter
Parallel Bus
Buffer
Transformer
board
VT
or
CT
Serial Serial Link

A/D Converter
interface
VT
or
CT
V00239
Figure 18: Input module schematic
A/D Conversion
The differential analogue inputs from the CT and VT transformers are presented to the main input board as shown.
Each differential input is first converted to a single input quantity referenced to the input board’s earth potential.
The analogue inputs are sampled and converted to digital, then filtered to remove unwanted properties. The
samples are then passed through a serial interface module which outputs data on the serial sample data bus.
The calibration coefficients are stored in non-volatile memory. These are used by the processor board to correct
for any amplitude or phase errors introduced by the transformers and analogue circuitry.
Opto-isolated inputs
The other function of the input board is to read in the state of the digital inputs. As with the analogue inputs, the
digital inputs must be electrically isolated from the power system. This is achieved by means of the 8 on-board
optical isolators for connection of up to 8 digital signals. The digital signals are passed through an optional noise
filter before being buffered and presented to the unit’s processing boards in the form of a parallel data bus.
This selectable filtering allows the use of a pre-set filter of ½ cycle which renders the input immune to induced
power-system noise on the wiring. Although this method is secure it can be slow, particularly for inter-tripping. This
can be improved by switching off the ½ cycle filter, in which case one of the following methods to reduce ac noise
should be considered.
● Use double pole switching on the input
● Use screened twisted cable on the input circuit
46 P64x-TM-EN-4.1
The opto-isolated logic inputs can be configured for the nominal battery voltage of the circuit for which they are a
part, allowing different voltages for different circuits such as signalling and tripping.
Note:
The opto-input circuitry can be provided without the A/D circuitry as a separate board, which can provide supplementary
opto-inputs.
6.5.2 FREQUENCY RESPONSE

With the exception of the RMS measurements, all other measurements and protection functions are based on the
Fourier-derived fundamental component. The fundamental component is extracted by using a 24 sample Discrete
Fourier Transform (DFT). This gives good harmonic rejection for frequencies up to the 23rd harmonic. The 23rd is
the first predominant harmonic that is not attenuated by the Fourier filter and this is known as an ‘Alias’. However,
the Alias is attenuated by approximately 85% by an additional, analogue, ‘anti-aliasing’ filter (low pass filter). The
combined affect of the anti-aliasing and Fourier filters is shown below.
1
Ideal anti-alias filter response
0.8
Real anti-alias filter Fourier response without

0.6 anti-alias filter
response
0.4
Fourier response with
anti-alias filter
0.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Alias frequency
50 Hz 600 Hz 1200 Hz
V00301
Figure 19: Frequency response
For power frequencies that are not equal to the selected rated frequency, the harmonics are attenuated to zero
amplitude. For small deviations of +/-1 Hz, this is not a problem but to allow for larger deviations, frequency
tracking is used.
Frequency tracking automatically adjusts the sampling rate of the analog to digital conversion to match the
applied signal. In the absence of a suitable signal to amplitude track, the sample rate defaults to the selected rated
frequency (Fn). If the a signal is in the tracking range of 45 to 66 Hz, the relay locks onto the signal and the
measured frequency coincides with the power frequency. The outputs for harmonics up to the 23rd are zero. The
device frequency tracks off any voltage or current in the order VA/VB/VC/IA/IB/IC down to 10% Vn for voltage and
5%In for current.
P64x-TM-EN-4.1 47
6.5.3 TRANSFORMER BOARD
Figure 20: Transformer board
The transformer board hosts the current and voltage transformers. These are used to step down the currents and
voltages originating from the power systems' current and voltage transformers to levels that can be used by the
devices' electronic circuitry. In addition to this, the on-board CT and VT transformers provide electrical isolation
between the unit and the power system.
The transformer board is connected physically and electrically to the input board to form a complete input module.
For terminal connections, please refer to the wiring diagrams.
48 P64x-TM-EN-4.1
6.5.4 INPUT BOARD
Figure 21: Input board
The input board is used to convert the analogue signals delivered by the current and voltage transformers into
digital quantities used by the IED. This input board also has on-board opto-input circuitry, providing eight optically-
isolated digital inputs and associated noise filtering and buffering. These opto-inputs are presented to the user by
means of a MD terminal block, which sits adjacent to the analogue inputs HD terminal block.
The input board is connected physically and electrically to the transformer board to form a complete input module.
The terminal numbers of the opto-inputs are as follows:
Terminal Number Opto-input
Terminal 1 Opto 1 -ve
Terminal 2 Opto 1 +ve
Terminal 13 Opto 7 –ve
Terminal 15 Opto 8 –ve
P64x-TM-EN-4.1 49
Terminal Number Opto-input

Terminal 17 Common
Terminal 18 Common
6.6 STANDARD OUTPUT RELAY BOARD
Figure 22: Standard output relay board - 8 contacts
This output relay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts.
The output relay board is provided together with the power supply board as a complete assembly, or
independently for the purposes of relay output expansion.
There are two cut-out locations in the board. These can be removed to allow power supply components to
protrude when coupling the output relay board to the power supply board. If the output relay board is to be used
independently, these cut-out locations remain intact.
The terminal numbers are as follows:
Terminal Number Output Relay
Terminal 1 Relay 1 NO
50 P64x-TM-EN-4.1
Terminal Number Output Relay

Terminal 13 Relay 7 changeover
Terminal 15 Relay 7 common
Terminal 18 Relay 8 common
6.7 IRIG-B BOARD
Figure 23: IRIG-B board
The IRIG-B board can be fitted to provide an accurate timing reference for the device. The IRIG-B signal is
connected to the board via a BNC connector. The timing information is used to synchronise the IED's internal real-
time clock to an accuracy of 1 ms. The internal clock is then used for time tagging events, fault, maintenance and
disturbance records.
IRIG-B interface is available in modulated or demodulated formats.
The IRIG-B facility is provided in combination with other functionality on a number of additional boards, such as:
● Fibre board with IRIG-B
● Second rear communications board with IRIG-B
● Ethernet board with IRIG-B
● Redundant Ethernet board with IRIG-B
There are three types of each of these boards; one type which accepts a modulated IRIG-B input, one type which
accepts a demodulated IRIG-B input and one type which accepts a universal IRIG-B input.
P64x-TM-EN-4.1 51
6.8 FIBRE OPTIC BOARD
Figure 24: Fibre optic board
This board provides an interface for communicating with a master station. This communication link can use all
compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic
RS485 port presented on the power supply terminal block. The metallic and fibre optic ports are mutually exclusive.
The fibre optic port uses BFOC 2.5 ST connectors.
The board comes in two varieties; one with an IRIG-B input and one without:
52 P64x-TM-EN-4.1
6.9 REAR COMMUNICATION BOARD
Figure 25: Rear communication board
The optional communications board containing the secondary communication ports provide two serial interfaces
presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female
connectors, but are configured as DTE ports. This means pin 2 is used to transmit information and pin 3 to receive.
SK4 can be used with RS232, RS485 and K-bus. SK5 can only be used with RS232 and is used for electrical
teleprotection. The optional rear communications board and IRIG-B board are mutually exclusive since they use
the same hardware slot. However, the board comes in two varieties; one with an IRIG-B input and one without.
P64x-TM-EN-4.1 53
6.10 REDUNDANT ETHERNET BOARD
Figure 26: Redundant Ethernet board
This board provides dual redundant Ethernet together with an IRIG-B interface for timing.
Different board variants are available, depending on the redundancy protocol and the type of IRIG-B signal
(unmodulated and modulated). The available redundancy protocols are:
● RSTP (Rapid Spanning Tree Protocol)
● PRP (Parallel Redundancy Protocol)
● HSR (High-availability Seamless Redundancy)
● Failover
There are several variants for this board as follows:

● 100 Mbps redundant Ethernet running RSTP + PRP + HSR + Failover (two fibre pairs), with on-board universal
IRIG-B
● 100 Mbps redundant Ethernet running RSTP + PRP + HSR + Failover (two copper pairs), with on-board
universal IRIG-B
● 100 Mbps redundant Ethernet running RSTP + PRP + HSR + Failover (one copper, one multi-mode fibre), with
on-board universal IRIG-B
The Ethernet and other connection details are described below:
IRIG-B Connector
● Centre connection: Signal
● Outer connection: Earth
Link Fail Connector (Ethernet Board Watchdog Relay)

Pin Closed Open
1-2 Link fail Channel 1 (A) Link ok Channel 1 (A)
2-3 Link fail Channel 2 (B) Link ok Channel 2 (B)
54 P64x-TM-EN-4.1
LEDs
LED Function On Off Flashing
Green Link Link ok Link broken
Yellow Activity Running PRP, RSTP traffic
Optical Fibre Connectors (ST)

Connector RSTP PRP HSR
A RX1 RXA RXA
B TX1 TXA TXA
C RX2 RXB RXB
D TX2 TXB TXB
RJ45 connector
Pin Signal name Signal definition
1 TXP Transmit (positive)
2 TXN Transmit (negative)
3 RXP Receive (positive)
4 - Not used
5 - Not used
6 RXN Receive (negative)
7 - Not used
8 - Not used
P64x-TM-EN-4.1 55
6.11 RTD BOARD
Figure 27: RTD board
The RTD board provides two banks of 15 terminals to support ten RTD inputs, of the type PT100, Ni100, or Ni120,
depending on the product. There are three terminals for each RTD, therefore 30 terminals altogether. The RTD
board fits into slot B or slot C, depending on the model variant.
The terminal numbers of the RTDs are as follows:
Terminal Number RTD connection
Terminal 1 RTD1 wire 1
56 P64x-TM-EN-4.1
Terminal Number RTD connection

6.12 CLIO BOARD
Figure 28: RTD board
The CLIO board provides two banks of 15 terminals to support four current loop inputs and four current loop
outputs. There are three terminals for each input and three for each output, therefore 24 of the terminals are used
altogether. The CLIO board fits into slot B or slot C, depending on the model variant.
The terminal numbers of the current loop inputs and outputs are as follows:
P64x-TM-EN-4.1 57
Terminal Number Current Loop Connection

Terminal 1 CLO1 - 20 mA input
Terminal 3 CLO1 - common input
Terminal 4 Not used
Terminal 8 Not used
Terminal 12 Not used
Terminal 16 CLI1 - 20 mA input
Terminal 18 CLI1 - common input
58 P64x-TM-EN-4.1
6.13 HIGH BREAK OUTPUT RELAY BOARD
Figure 29: High Break relay output board
A High Break output relay board is available as an option. It comprises four normally open output contacts, which
are suitable for high breaking loads.
A High Break contact consists of a high capacity relay with a MOSFET in parallel with it. The MOSFET has a varistor
placed across it to provide protection, which is required when switching off inductive loads. This is because the
stored energy in the inductor causes a high reverse voltage that could damage the MOSFET, if not protected.
When there is a control input command to operate an output contact the miniature relay is operated at the same
time as the MOSFET. The miniature relay contact closes in nominally 3.5 ms and is used to carry the continuous
load current. The MOSFET operates in less than 0.2 ms, but is switched off after 7.5 ms.
When the control input is reset, the MOSFET is again turned on for 7.5 mS. The miniature relay resets in nominally
3.5 ms before the MOSFET. This means the MOSFET is used to break the load. The MOSFET absorbs the energy
when breaking inductive loads and so limits the resulting voltage surge. This contact arrangement is for switching
DC circuits only.
The board number is:
● ZN0042 001
High Break Contact Operation

The following figure shows the timing diagram for High Break contact operation.
P64x-TM-EN-4.1 59
Databus on off
control input
MOSFET operate 7ms 7ms

on on
MOSFET reset
Relay contact
Closed
3.5ms + contact bounce 3.5ms
Load current
V00246
Figure 30: High Break contact operation
High Break Contact Applications

● Efficient scheme engineering
In traditional hard wired scheme designs, High Break capability could only be achieved using external
electromechanical trip relays. Instead, these internal High Break contacts can be used thus reducing space
requirements.
● Accessibility of CB auxiliary contacts
It is common practise to use circuit breaker 52a (CB Closed) auxiliary contacts to break the trip coil current
on breaker opening, thereby easing the duty on the protection contacts. In some cases (such as operation
of disconnectors, or retrofitting), it may be that 52a contacts are either unavailable or unreliable. In such
cases, High Break contacts can be used to break the trip coil current in these applications.
● Breaker fail
In the event of failure of the local circuit breaker (stuck breaker), or defective auxiliary contacts (stuck
contacts), it is incorrect to use 52a contact action. The interrupting duty at the local breaker then falls on the
relay output contacts, which may not be rated to perform this duty. High Break contacts should be used in
this case to avoid the risk of burning out relay contacts.
● Initiation of teleprotection
The High Break contacts also offer fast making, which results in faster tripping. In addition, fast keying of
teleprotection is a benefit. Fast keying bypasses the usual contact operation time, such that permissive,
blocking and intertrip commands can be routed faster.
Warning:
These relay contacts are POLARITY SENSITIVE. External wiring must comply with the polarity
requirements described in the external connection diagram to ensure correct operation.
60 P64x-TM-EN-4.1
CHAPTER 4
SOFTWARE DESIGN
Chapter 4 - Software Design P64x
62 P64x-TM-EN-4.1
P64x Chapter 4 - Software Design
1 CHAPTER OVERVIEW
This chapter describes the software design of the IED.
Chapter Overview 63
Sofware Design Overview 64
System Level Software 65
Platform Software 68
Protection and Control Functions 69
P64x-TM-EN-4.1 63
2 SOFWARE DESIGN OVERVIEW

The device software can be conceptually categorized into several elements as follows:
● The system level software
● The platform software
● The protection and control software
These elements are not distinguishable to the user, and the distinction is made purely for the purposes of
explanation. The following figure shows the software architecture.
Protection and Control Software Layer

Protection Task
Programmable & Fourier signal Protection

fixed scheme logic processing algorithms Fault locator Disturbance
task recorder task
Supervisor task
Records
and control
Protection
settings
Platform Software Layer
Event, fault,
Remote
disturbance,
Settings database communications
maintenance record
Sampling function interfaces
logging
Front panel Local

interface communications
(LCD + Keypad) interfaces
Sample data + digital Control of interfaces to keypad, LCD, LEDs,

logic inputs front & rear ports.
Control of output contacts
and programmable LEDs Self-checking maintenance records
System Level Software Layer

System services (e.g. device drivers) / Real time operating system / Self
-diagnostic software
Hardware Device Layer

LEDs / LCD / Keypad / Memory / FPGA
V00300
Figure 31: Software Architecture
The software, which executes on the main processor, can be divided into a number of functions as illustrated
above. Each function is further broken down into a number of separate tasks. These tasks are then run according
to a scheduler. They are run at either a fixed rate or they are event driven. The tasks communicate with each other
as and when required.
64 P64x-TM-EN-4.1
3 SYSTEM LEVEL SOFTWARE
3.1 REAL TIME OPERATING SYSTEM

The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are
processed in the time available and in the desired order of priority. The operating system also plays a part in
controlling the communication between the software tasks, through the use of operating system messages.
3.2 SYSTEM SERVICES SOFTWARE

The system services software provides the layer between the hardware and the higher-level functionality of the
platform software and the protection and control software. For example, the system services software provides
drivers for items such as the LCD display, the keypad and the remote communication ports. It also controls things
like the booting of the processor and the downloading of the processor code into RAM at startup.
3.3 SELF-DIAGNOSTIC SOFTWARE

The device includes several self-monitoring functions to check the operation of its hardware and software while in
service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.
If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.
The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot-
up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.
3.4 STARTUP SELF-TESTING

The self-testing takes a few seconds to complete, during which time the IED's measurement, recording, control,
and protection functions are unavailable. On a successful start-up and self-test, the ‘Healthy' state LED on the
front of the device is switched on. If a problem is detected during the start-up testing, the device remains out of
service until it is manually restored to working order.
The operations that are performed at start-up are:
1. System boot
2. System software initialisation
3. Platform software initialisation and monitoring
3.4.1 SYSTEM BOOT

The integrity of the Flash memory is verified using a checksum before the program code and stored data is loaded
into RAM for execution by the processor. When the loading has been completed, the data held in RAM is compared
to that held in the Flash memory to ensure that no errors have occurred in the data transfer and that the two are
the same. The entry point of the software code in RAM is then called. This is the IED's initialisation code.
P64x-TM-EN-4.1 65
3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION

The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the
hardware to determine whether the software is still running), starts the real-time operating system and creates
and starts the supervisor task. In the initialization process the device checks the following:
● The status of the supercapacitor
● The integrity of the supercapacitor-backed SRAM that is used to store event, fault and disturbance records
● The operation of the LCD controller
● The watchdog operation
At the conclusion of the initialization software the supervisor task begins the process of starting the platform
software.
3.4.3 PLATFORM SOFTWARE INITIALISATION AND MONITORING

When starting the platform software, the IED checks the following:
● The integrity of the data held in non-volatile memory (using a checksum)
● The operation of the real-time clock
● The optional IRIG-B function (if applicable)
● The presence and condition of the input board
● The analog data acquisition system (it does this by sampling the reference voltage)
At the successful conclusion of all of these tests the unit is entered into service and the application software is
started up.
3.5 CONTINUOUS SELF-TESTING

When the IED is in service, it continually checks the operation of the critical parts of its hardware and software. The
checking is carried out by the system services software and the results are reported to the platform software. The
functions that are checked are as follows:
● The Flash memory containing all program code and language text is verified by a checksum.
● The code and constant data held in system memory is checked against the corresponding data in Flash
memory to check for data corruption.
● The system memory containing all data other than the code and constant data is verified with a checksum.
● The integrity of the digital signal I/O data from the opto-inputs and the output relay coils is checked by the
data acquisition function every time it is executed.
● The operation of the analog data acquisition system is continuously checked by the acquisition function
every time it is executed. This is done by sampling the reference voltages.
● The operation of the optional Ethernet board is checked by the software on the main processor card. If the
Ethernet board fails to respond an alarm is raised and the card is reset in an attempt to resolve the problem.
● The operation of the optional IRIG-B function is checked by the software that reads the time and date from
the board.
● Where fitted, the operation of the RTD board is checked by reading the temperature indicated by the
reference resistors on the two spare RTD channels
● Where fitted, the operation of the CLIO board is checked
In the event that one of the checks detects an error in any of the subsystems, the platform software is notified and
it attempts to log a maintenance record.
If the problem is with the IRIG-B board, the device continues in operation. For problems detected in any other area,
the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds when the functionality is
unavailable.
66 P64x-TM-EN-4.1
A restart should clear most problems that may occur. If, however, the diagnostic self-check detects the same
problem that caused the IED to restart, it is clear that the restart has not cleared the problem, and the device takes
itself permanently out of service. This is indicated by the ‘’health-state’ LED on the front of the device, which
switches OFF, and the watchdog contact which switches ON.
P64x-TM-EN-4.1 67
4 PLATFORM SOFTWARE
The platform software has three main functions:
● To control the logging of records generated by the protection software, including alarms, events, faults, and
maintenance records
● To store and maintain a database of all of the settings in non-volatile memory
● To provide the internal interface between the settings database and the user interfaces, using the front
panel interface and the front and rear communication ports
4.1 RECORD LOGGING

The logging function is used to store all alarms, events, faults and maintenance records. The records are stored in
non-volatile memory to provide a log of what has happened. The IED maintains four types of log on a first in first
out basis (FIFO). These are:
● Alarms
● Event records
● Fault records
● Maintenance records
The logs are maintained such that the oldest record is overwritten with the newest record. The logging function
can be initiated from the protection software. The platform software is responsible for logging a maintenance
record in the event of an IED failure. This includes errors that have been detected by the platform software itself or
errors that are detected by either the system services or the protection software function. See the Monitoring and
Control chapter for further details on record logging.
4.2 SETTINGS DATABASE

The settings database contains all the settings and data, which are stored in non-volatile memory. The platform
software manages the settings database and ensures that only one user interface can modify the settings at any
one time. This is a necessary restriction to avoid conflict between different parts of the software during a setting
change.
Changes to protection settings and disturbance recorder settings, are first written to a temporary location SRAM
memory. This is sometimes called 'Scratchpad' memory. These settings are not written into non-volatile memory
immediately. This is because a batch of such changes should not be activated one by one, but as part of a
complete scheme. Once the complete scheme has been stored in SRAM, the batch of settings can be committed to
the non-volatile memory where they will become active.
4.3 INTERFACES
The settings and measurements database must be accessible from all of the interfaces to allow read and modify
operations. The platform software presents the data in the appropriate format for each of the interfaces (LCD
display, keypad and all the communications interfaces).
68 P64x-TM-EN-4.1
5 PROTECTION AND CONTROL FUNCTIONS

The protection and control software processes all of the protection elements and measurement functions. To
achieve this it has to communicate with the system services software, the platform software as well as organise its
own operations.
The protection task software has the highest priority of any of the software tasks in the main processor board. This
ensures the fastest possible protection response.
The protection and control software provides a supervisory task, which controls the start-up of the task and deals
with the exchange of messages between the task and the platform software.
5.1 ACQUISITION OF SAMPLES

After initialization, the protection and control task waits until there are enough samples to process. The acquisition
of samples on the main processor board is controlled by a ‘sampling function’ which is called by the system
services software.
This sampling function takes samples from the input module and stores them in a two-cycle FIFO buffer. The
sample rate is 24 samples per cycle. This results in a nominal sample rate of 1,200 samples per second for a 50 Hz
system and 1,440 samples per second for a 60 Hz system. However the sample rate is not fixed. It tracks the
power system frequency as described in the next section.
5.2 FREQUENCY TRACKING

The device provides a frequency tracking algorithm so that there are always 24 samples per cycle irrespective of
frequency drift within a certain frequency range (see technical specifications). If the frequency falls outside this
range, the sample rate reverts to its default rate of 1200 Hz for 50 Hz or 1440 Hz for 60 Hz.
The frequency tracking of the analog input signals is achieved by a recursive Fourier algorithm which is applied to
one of the input signals. It works by detecting a change in the signal’s measured phase angle. The calculated value
of the frequency is used to modify the sample rate being used by the input module, in order to achieve a constant
sample rate per cycle of the power waveform. The value of the tracked frequency is also stored for use by the
protection and control task.
The frequency tracks off any voltage or current in the order VA, VB, VC, IA, IB, IC, down to 10%Vn for voltage and
5%In for current.
5.3 DIRECT USE OF SAMPLE VALUES

Most of the IED’s protection functionality uses the Fourier components calculated by the device’s signal processing
software. However RMS measurements and some special protection algorithms available in some products use
the sampled values directly.
The disturbance recorder also uses the samples from the input module, in an unprocessed form. This is for
waveform recording and the calculation of true RMS values of current, voltage and power for metering purposes.
In the case of special protection algorithms, using the sampled values directly provides exceptionally fast response
because you do not have to wait for the signal processing task to calculate the fundamental. You can act on the
sampled values immediately.
5.4 FOURIER SIGNAL PROCESSING

When the protection and control task is re-started by the sampling function, it calculates the Fourier components
for the analog signals. Although some protection algorithms use some Fourier-derived harmonics (e.g. second
harmonic for magnetizing inrush), most protection functions are based on the Fourier-derived fundamental
components of the measured analog signals. The Fourier components of the input current and voltage signals are
stored in memory so that they can be accessed by all of the protection elements’ algorithms.
P64x-TM-EN-4.1 69
The Fourier components are calculated using single-cycle Fourier algorithm. This Fourier algorithm always uses
the most recent 24 samples from the 2-cycle buffer.
Most protection algorithms use the fundamental component. In this case, the Fourier algorithm extracts the power
frequency fundamental component from the signal to produce its magnitude and phase angle. This can be
represented in either polar format or rectangular format, depending on the functions and algorithms using it.
The Fourier function acts as a filter, with zero gain at DC and unity gain at the fundamental, but with good
harmonic rejection for all harmonic frequencies up to the nyquist frequency. Frequencies beyond this nyquist
frequency are known as alias frequencies, which are introduced when the sampling frequency becomes less than
twice the frequency component being sampled. However, the Alias frequencies are significantly attenuated by an
anti-aliasing filter (low pass filter), which acts on the analog signals before they are sampled. The ideal cut-off point
of an anti-aliasing low pass filter would be set at:
(samples per cycle) ´ (fundamental frequency)/2
At 24 samples per cycle, this would be nominally 600 Hz for a 50 Hz system, or 720 Hz for a 60 Hz system.
The following figure shows the nominal frequency response of the anti-alias filter and the Fourier filter for a 24-
sample single cycle fourier algorithm acting on the fundamental component:
1
Ideal anti-alias filter response
0.8
Real anti-alias filter Fourier response without

0.6 anti-alias filter
response
0.4
Fourier response with
anti-alias filter
0.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Alias frequency
50 Hz 600 Hz 1200 Hz
V00301
Figure 32: Frequency Response (indicative only)
5.5 PROGRAMMABLE SCHEME LOGIC

The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to
suit your particular application. This is done with programmable logic gates and delay timers. To allow greater
flexibility, different PSL is allowed for each of the four setting groups.
The input to the PSL is any combination of the status of the digital input signals from the opto-isolators on the
input board, the outputs of the protection elements such as protection starts and trips, and the outputs of the fixed
protection scheme logic (FSL). The fixed scheme logic provides the standard protection schemes. The PSL consists
of software logic gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a programmable delay,
and/or to condition the logic outputs, such as to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front panel of the relay and the output
contacts at the rear.
The execution of the PSL logic is event driven. The logic is processed whenever any of its inputs change, for
example as a result of a change in one of the digital input signals or a trip output from a protection element. Also,
only the part of the PSL logic that is affected by the particular input change that has occurred is processed. This
reduces the amount of processing time that is used by the PSL. The protection & control software updates the logic
delay timers and checks for a change in the PSL input signals every time it runs.
The PSL can be configured to create very complex schemes. Because of this PSL desing is achieved by means of a
PC support package called the PSL Editor. This is available as part of the settings application software MiCOm S1
Agile, or as a standalone software module.
70 P64x-TM-EN-4.1
5.6 EVENT RECORDING

A change in any digital input signal or protection element output signal is used to indicate that an event has taken
place. When this happens, the protection and control task sends a message to the supervisor task to indicate that
an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
When the supervisor task receives an event record, it instructs the platform software to create the appropriate log
in non-volatile memory (backed-up SRAM). The operation of the record logging to backed-up SRAM is slower than
the supervisor buffer. This means that the protection software is not delayed waiting for the records to be logged
by the platform software. However, in the rare case when a large number of records to be logged are created in a
short period of time, it is possible that some will be lost, if the supervisor buffer is full before the platform software
is able to create a new log in backed-up SRAM. If this occurs then an event is logged to indicate this loss of
information.
Maintenance records are created in a similar manner, with the supervisor task instructing the platform software to
log a record when it receives a maintenance record message. However, it is possible that a maintenance record
may be triggered by a fatal error in the relay in which case it may not be possible to successfully store a
maintenance record, depending on the nature of the problem.
For more information, see the Monitoring and Control chapter.
5.7 DISTURBANCE RECORDER

The disturbance recorder operates as a separate task from the protection and control task. It can record the
waveforms of the calibrated analog channels, plus the values of the digital signals. The recording time is user
selectable up to a maximum of 10.5 seconds. The disturbance recorder is supplied with data by the protection and
control task once per cycle, and collates the received data into the required length disturbance record. The
disturbance records can be extracted using application software or the SCADA system, which can also store the
data in COMTRADE format, allowing the use of other packages to view the recorded data.
For more information, see the Monitoring and Control chapter.
5.8 FAULT LOCATOR

The fault locator uses 12 cycles of the analog input signals to calculate the fault location. The result is returned to
the protection and control task, which includes it in the fault record. The pre-fault and post-fault voltages are also
presented in the fault record. When the fault record is complete, including the fault location, the protection and
control task sends a message to the supervisor task to log the fault record.
The Fault Locator is not available on all models.
5.9 FUNCTION KEY INTERFACE

The function keys interface directly into the PSL as digital input signals. A change of state is only recognized when
a key press is executed on average for longer than 200 ms. The time to register a change of state depends on
whether the function key press is executed at the start or the end of a protection task cycle, with the additional
hardware and software scan time included. A function key press can provide a latched (toggled mode) or output
on key press only (normal mode) depending on how it is programmed. It can be configured to individual protection
scheme requirements. The latched state signal for each function key is written to non-volatile memory and read
from non-volatile memory during relay power up thus allowing the function key state to be reinstated after power-
up, should power be inadvertently lost.
P64x-TM-EN-4.1 71
72 P64x-TM-EN-4.1
CHAPTER 5
CONFIGURATION
Chapter 5 - Configuration P64x
74 P64x-TM-EN-4.1
P64x Chapter 5 - Configuration
1 CHAPTER OVERVIEW
Each product has different configuration parameters according to the functions it has been designed to perform.
There is, however, a common methodology used across the entire product series to set these parameters.
Some of the communications setup can only be carried out using the HMI, and cannot be carried out using
settings applications software. This chapter includes concise instructions of how to configure the device,
particularly with respect to the communications setup, as well as a description of the common methodology used
to configure the device in general.
Chapter Overview 75
Settings Application Software 76
Using the HMI Panel 77
Configuring the Data Protocols 87
Date and Time Configuration 93
Phase Rotation 96
P64x-TM-EN-4.1 75
2 SETTINGS APPLICATION SOFTWARE

To configure this device you will need to use the Settings Application Software. The settings application software
used in this range of IEDs is called MiCOM S1 Agile. It is a collection of software tools, which is used for setting up
and managing the IEDs.
Although you can change many settings using the front panel HMI, some of the features cannot be configured
without the Settings Application Software; for example the programmable scheme logic, or IEC61850
communications.
If you do not already have a copy of the Settings Application Software, you can obtain it from General Electric
contact centre.
To configure your product, you will need a data model that matches your product. When you launch the Settings
Application Software, you will be presented with a panel that allows you to invoke the “Data Model Manager”. This
will close the other aspects of the software in order to allow an efficient import of the chosen data model. If you
don’t have, or can’t find, the data model relating to your product, please call the General Electric contact centre.
When you have loaded all the data models you need, you should restart the Settings Application Software and
start to create a model of your system using the “System Explorer” panel.
The software is designed to be intuitive, but help is available in an online help system and also the Settings
Application Software user guide P40-M&CR-SAS-UG-EN-n, where 'Language' is a 2 letter code designating the
language version of the user guide and 'n' is the latest version of the settings application software.
76 P64x-TM-EN-4.1
3 USING THE HMI PANEL

Using the HMI, you can:
● Display and modify settings
● View the digital I/O signal status
● Display measurements
● Display fault records
● Reset fault and alarm indications
The keypad provides full access to the device functionality using a range of menu options. The information is
displayed on the LCD.
Keys Description Function
To change the menu level or change between settings in a

Up and down cursor keys
particular column, or changing values within a cell
To change default display, change between column headings, or

Left and right cursor keys
changing values within a cell
ENTER key For changing and executing settings
For executing commands and settings for which shortcuts have

Hotkeys
been defined
Cancel key To return to column header from any menu cell
Read key To read alarm messages
Function keys (not all models) For executing user programmable functions
P64x-TM-EN-4.1 77
Note:
As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form.
3.1 NAVIGATING THE HMI PANEL

The cursor keys are used to navigate the menus. These keys have an auto-repeat function if held down
continuously. This can be used to speed up both setting value changes and menu navigation. The longer the key is
held pressed, the faster the rate of change or movement.
The navigation map below shows how to navigate the menu items.
Default display Default display

option option
Alarm message
Default display options
Column 00 Subsequent column headings Last Column

System data
Vertical cursor keys move

Horizontal cursor
between setting rows
Row 01 keys move Row 01
Language between values
within a cell
The Cancel key
returns to
column header
Subsequent rows Subsequent rows
V00437
Figure 33: Navigating the HMI
3.2 GETTING STARTED

When you first start the IED, it will go through its power up procedure. After a few seconds it will settle down into
one of the top level menus. There are two menus at this level:
● The Alarms menu for when there are alarms present
● The default display menu for when there are no alarms present.
If there are alarms present, the yellow Alarms LED will be flashing and the menu display will read as follows:
78 P64x-TM-EN-4.1
Alarms / Faults
Present
HOTKEY
Even though the device itself should be in full working order when you first start it, an alarm could still be present,
for example, if there is no network connection for a device fitted with a network card. If this is the case, you can
read the alarm by pressing the 'Read' key.
ALARMS
NIC Link Fail
If the device is fitted with an Ethernet card, you will first need to connect the device to an active Ethernet network
to clear the alarm and get the default display.
If there are other alarms present, these must also be cleared before you can get into the default display menu
options.
3.3 DEFAULT DISPLAY

The HMI contains a range of possible options that you can choose to be the default display. The options available
are:
NERC Compliant banner

If the device is a cyber-security model, it will provide a NERC-compliant default display. If the device does not
contain the cyber-security option, this display option is not available.
ACCESS ONLY FOR

AUTHORISED USERS
HOTKEY
Date and time

For example:
11:09:15
23 Nov 2011
HOTKEY
Description (user-defined)
For example:
Description
MiCOM P14NB
HOTKEY
Plant reference (user-defined)

For example:
P64x-TM-EN-4.1 79
Plant Reference
MiCOM
HOTKEY
Access Level
For example:
Access Level
3
HOTKEY
In addition to the above, there are also displays for the system voltages, currents, power and frequency etc.,
depending on the device model.
3.4 DEFAULT DISPLAY NAVIGATION

The following diagram is an example of the default display navigation. In this example, we have used a cyber-
secure model. This is an example only and may not apply in its entirety to all models. The actual display options
available depend on the exact model.
Use the horizontal cursor keys to step through from one display to the next.
NERC compliant
banner
NERC Compliance NERC Compliance

Warning Warning
System Current
Access Level
Measurements
System Voltage
System Frequency
Measurements
System Power
Plant Reference
Measurements
Description Date & Time
V00403
Figure 34: Default display navigation
If the device is cyber-secure but is not yet configured for NERC compliance (see Cyber-security chapter), a warning
will appear when moving from the "NERC compliant" banner. The warning message is as follows:
80 P64x-TM-EN-4.1
DISPLAY NOT NERC

COMPLIANT. OK?
You will have to confirm with the Enter button before you can go any further.
Note:
Whenever the IED has an uncleared alarm the default display is replaced by the text Alarms/ Faults present. You cannot
override this default display. However, you can enter the menu structure from the default display, even if the display shows
the Alarms/Faults present message.
3.5 PASSWORD ENTRY

Configuring the default display (in addition to modification of other settings) requires level 3 access. You will be
prompted for a password before you can make any changes, as follows. The default level 3 password is AAAA.
Enter Password
1. A flashing cursor shows which character field of the password can be changed. Press the up or down cursor
keys to change each character (tip: pressing the up arrow once will return an upper case "A" as required by
the default level 3 password).
2. Use the left and right cursor keys to move between the character fields of the password.
3. Press the Enter key to confirm the password. If you enter an incorrect password, an invalid password
message is displayed then the display reverts to Enter password. On entering a valid password a message
appears indicating that the password is correct and which level of access has been unlocked. If this level is
sufficient to edit the selected setting, the display returns to the setting page to allow the edit to continue. If
the correct level of password has not been entered, the password prompt page appears again.
4. To escape from this prompt press the Clear key. Alternatively, enter the password using the Password
setting in the SYSTEM DATA column. If the keypad is inactive for 15 minutes, the password protection of the
front panel user interface reverts to the default access level.
To manually reset the password protection to the default level, select Password, then press the CLEAR key instead
of entering a password.
Note:
In the SECURITY CONFIG column, you can set the maximum number of attemps, the time window in which the failed attempts
are counted and the time duration for which the user is blocked.
P64x-TM-EN-4.1 81
3.6 PROCESSING ALARMS AND RECORDS

If there are any alarm messages, they will appear on the default display and the yellow alarm LED flashes. The
alarm messages can either be self-resetting or latched. If they are latched, they must be cleared manually.
1. To view the alarm messages, press the Read key. When all alarms have been viewed but not cleared, the
alarm LED changes from flashing to constantly on, and the latest fault record appears (if there is one).
2. Scroll through the pages of the latest fault record, using the cursor keys. When all pages of the fault record
have been viewed, the following prompt appears.
Press Clear To
Reset Alarms
3. To clear all alarm messages, press the Clear key. To return to the display showing alarms or faults present,
and leave the alarms uncleared, press the Read key.
4. Depending on the password configuration settings, you may need to enter a password before the alarm
messages can be cleared.
5. When all alarms are cleared, the yellow alarm LED switches off. If the red LED was on, this will also be
switched off.
Note:
To speed up the procedure, you can enter the alarm viewer using the Read key and subsequently pressing the Clear key. This
goes straight to the fault record display. Press the Clear key again to move straight to the alarm reset prompt, then press the
Clear key again to clear all alarms.
3.7 MENU STRUCTURE

Settings, commands, records and measurements are stored in a local database inside the IED. When using the
Human Machine Interface (HMI) it is convenient to visualise the menu navigation system as a table. Each item in
the menu is known as a cell, which is accessed by reference to a column and row address. Each column and row is
assigned a 2-digit hexadecimal numbers, resulting in a unique 4-digit cell address for every cell in the database.
The main menu groups are allocated columns and the items within the groups are allocated rows, meaning a
particular item within a particular group is a cell.
Each column contains all related items, for example all of the disturbance recorder settings and records are in the
same column.
There are three types of cell:
● Settings: this is for parameters that can be set to different values
● Commands: this is for commands to be executed
● Data: this is for measurements and records to be viewed, which are not settable
Note:
Sometimes the term "Setting" is used generically to describe all of the three types.
The table below, provides an example of the menu structure:

SYSTEM DATA (Col 00) VIEW RECORDS (Col 01) MEASUREMENTS 1 (Col 02) …
Language (Row 01) "Select Event [0...n]" (Row 01) IA Magnitude (Row 01) …
Password (Row 02) Menu Cell Ref (Row 02) IA Phase Angle (Row 02) …
Sys Fn Links (Row 03) Time & Date (Row 03) IB Magnitude (Row 03) …
… … … …
82 P64x-TM-EN-4.1
It is convenient to specify all the settings in a single column, detailing the complete Courier address for each
setting. The above table may therefore be represented as follows:
Setting Column Row Description
SYSTEM DATA 00 00 First Column definition
Language (Row 01) 00 01 First setting within first column
Password (Row 02) 00 02 Second setting within first column
Sys Fn Links (Row 03) 00 03 Third setting within first column
… … …
VIEW RECORDS 01 00 Second Column definition
Select Event [0...n] 01 01 First setting within second column
Menu Cell Ref 01 02 Second setting within second column
Time & Date 01 03 Third setting within second column
… … …
MEASUREMENTS 1 02 00 Third Column definition
IA Magnitude 02 01 First setting within third column
IA Phase Angle 02 02 Second setting within third column
IB Magnitude 02 03 Third setting within third column
… … …
The first three column headers are common throughout much of the product ranges. However the rows within
each of these column headers may differ according to the product type. Many of the column headers are the
same for all products within the series. However, there is no guarantee that the addresses will be the same for a
particular column header. Therefore you should always refer to the product settings documentation and not make
any assumptions.
3.8 CHANGING THE SETTINGS

1. Starting at the default display, press the Down cursor key to show the first column heading.
2. Use the horizontal cursor keys to select the required column heading.
3. Use the vertical cursor keys to view the setting data in the column.
4. To return to the column header, either press the Up cursor key for a second or so, or press the Clear key
once. It is only possible to move across columns at the column heading level.
5. To return to the default display, press the Up cursor key or the Clear key from any of the column headings. If
you use the auto-repeat function of the Up cursor key, you cannot go straight to the default display from
one of the column cells because the auto-repeat stops at the column heading.
6. To change the value of a setting, go to the relevant cell in the menu, then press the Enter key to change the
cell value. A flashing cursor on the LCD shows that the value can be changed. You may be prompted for a
password first.
7. To change the setting value, press the Up and Down cursor keys. If the setting to be changed is a binary
value or a text string, select the required bit or character to be changed using the horizontal cursor keys.
P64x-TM-EN-4.1 83
8. Press the Enter key to confirm the new setting value or the Clear key to discard it. The new setting is
automatically discarded if it is not confirmed within 15 seconds.
9. For protection group settings and disturbance recorder settings, the changes must be confirmed before
they are used. When all required changes have been entered, return to the column heading level and press
the Down cursor key. Before returning to the default display, the following prompt appears.
Update settings?
ENTER or CLEAR
10. Press the Enter key to accept the new settings or press the Clear key to discard the new settings.
Note:
For the protection group and disturbance recorder settings, if the menu time-out occurs before the changes have been
confirmed, the setting values are discarded. Control and support settings, howeverr, are updated immediately after they are
entered, without the Update settings? prompt.
3.9 DIRECT ACCESS (THE HOTKEY MENU)

It can be an onerous process to configure settings using the HMI panel, especially for settings and commands that
need to be executed quickly or on a regular basis. The IED provides a pair of keys directly below the LCD display,
which can be used to execute specified settings and commands directly.
The functions available for direct access using these keys are:
● Setting group selection
● Control Inputs
These functions are enabled or disabled in the Direct Access cell in the CONFIGURATION column.
3.9.1 SETTING GROUP SELECTION USING HOTKEYS

In some models you can use the hotkey menu to select the settings group. By default, only Setting group 1 is
enabled. Other setting groups will only be available if they are first enabled. To be able to select a different setting
group, you must first enable them in the CONFIGURATION column.
To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD.
The following screen will appear.
¬User32 STG GP®

HOTKEY MENU
EXIT
Use the right cursor keys to enter the SETTING GROUP menu.
¬Menu User01®
SETTING GROUP 1
Nxt Grp Select
Select the setting group with Nxt Grp and confirm by pressing Select. If neither of the cursor keys is pressed within
20 seconds of entering a hotkey sub menu, the device reverts to the default display.
84 P64x-TM-EN-4.1
3.9.2 CONTROL INPUTS

The control inputs are user-assignable functions. You can use the CTRL I/P CONFIG column to configure the control
inputs for the hotkey menu. In order to do this, use the first setting Hotkey Enabled cell to enable or disable any of
the 32 control inputs. You can then set each control input to latched or pulsed and set its command to On/Off,
Set/Reset, In/Out, or Enabled/Disabled.
By default, the hotkey is enabled for all 32 control inputs and they are set to Set/Reset and are Latched.
To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD.
The following screen will appear.
¬User32 STG GP®

HOTKEY MENU
EXIT
Press the right cursor key twice to get to the first control input, or the left cursor key to get to the last control input.
¬STP GP User02®
Control Input 1
EXIT SET
Now you can execute the chosen function (Set/Reset in this case).
If neither of the cursor keys is pressed within 20 seconds of entering a hotkey sub menu, the device reverts to the
default display.
3.10 FUNCTION KEYS

Most products have a number of function keys for programming control functionality using the programmable
scheme logic (PSL).
Each function key has an associated programmable tri-colour LED that can be programmed to give the desired
indication on function key activation.
These function keys can be used to trigger any function that they are connected to as part of the PSL. The function
key commands are in the FUNCTION KEYS column.
The first cell down in the FUNCTION KEYS column is the Fn Key Status cell. This contains a binary string, which
represents the function key commands. Their status can be read from this binary string.
FUNCTION KEYS
Fn Key Status
0000000000
The next cell down (Fn Key 1) allows you to activate or disable the first function key (1). The Lock setting allows a
function key to be locked. This allows function keys that are set to Toggled mode and their DDB signal active
‘high’, to be locked in their active state, preventing any further key presses from deactivating the associated
function. Locking a function key that is set to the Normal mode causes the associated DDB signals to be
permanently off. This safety feature prevents any inadvertent function key presses from activating or deactivating
critical functions.
P64x-TM-EN-4.1 85
FUNCTION KEYS
Fn Key 1
Unlocked
The next cell down (Fn Key 1 Mode) allows you to set the function key to Normal or Toggled. In the Toggle mode
the function key DDB signal output stays in the set state until a reset command is given, by activating the function
key on the next key press. In the Normal mode, the function key DDB signal stays energised for as long as the
function key is pressed then resets automatically. If required, a minimum pulse width can be programmed by
adding a minimum pulse timer to the function key DDB output signal.
FUNCTION KEYS
Fn Key 1 Mode
Toggled
The next cell down (Fn Key 1 Label) allows you to change the label assigned to the function. The default label is
Function key 1 in this case. To change the label you need to press the enter key and then change the text on
the bottom line, character by character. This text is displayed when a function key is accessed in the function key
menu, or it can be displayed in the PSL.
FUNCTION KEYS
Fn Key 1 Label
Function Key 1
Subsequent cells allow you to carry out the same procedure as above for the other function keys.
The status of the function keys is stored in non-volatile memory. If the auxiliary supply is interrupted, the status of
all the function keys is restored. The IED only recognises a single function key press at a time and a minimum key
press duration of approximately 200 ms is required before the key press is recognised. This feature avoids
accidental double presses.
86 P64x-TM-EN-4.1
4 CONFIGURING THE DATA PROTOCOLS

Different protocols can be used with the various ports. The choice of protocol depends on the chosen model. Each
port can support only one protocol at a time. The range of available communication settings depend on which
protocol has been chosen.
Depending on the exact model, the following choices may be available:
● Courier over RS485
● Tunneled Courier over Ethernet
● MODBUS over RS485
● DNP3 over RS485
● DNP3 over Ethernet
● IEC 60870-5-103 over RS485
● IEC61850 over Ethernet
Note:
Not all protocols are available on all products
You configure most of the communication settings using the HMI. Depending on the model, you will also need to
use the settings applications software to carry out some of the configuration, such as the IEC61850 configurator.
Detailed information on configuring the data protocols can be found in the communications chapter.
4.1 COURIER CONFIGURATION

To configure the device:
1. Select the CONFIGURATION column and check that the Comms settings cell is set to Visible.
2. Select the COMMUNICATIONS column.
3. Move to the first cell down (RP1 protocol). This is a non-settable cell, which shows the chosen
communication protocol – in this case Courier.
COMMUNICATIONS
RP1 Protocol
Courier
4. Move down to the next cell (RP1 Address). This cell controls the address of the RP1 port on thje device. Up to
32 IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so
that messages from the master control station are accepted by one IED only. Courier uses an integer
number between 1 and 254 for the Relay Address. It is set to 255 by default, which has to be changed. It is
important that no two IEDs share the same address.
COMMUNICATIONS
RP1 Address
100
5. Move down to the next cell (RP1 InactivTimer). This cell controls the inactivity timer. The inactivity timer
controls how long the IED waits without receiving any messages on the rear port before revoking any
password access that was enabled and discarding any changes. For the rear port this can be set between 1
and 30 minutes.
COMMUNICATIONS
RP1 Inactivtimer
10.00 mins.
P64x-TM-EN-4.1 87
6. If the optional fibre optic connectors are fitted, the RP1 PhysicalLink cell is visible. This cell controls the
physical media used for the communication (Copper or Fibre optic).
COMMUNICATIONS
RP1 PhysicalLink
Copper
7. Move down to the next cell (RP1 Card Status). This cell is not settable. It displays the status of the chosen
physical layer protocol for RP1.
COMMUNICATIONS
RP1 Card Status
K-Bus OK
8. Move down to the next cell (RP1 Port Config). This cell controls the type of serial connection. Select between
K-Bus or RS485.
COMMUNICATIONS
RP1 Port Config
K-Bus
9. If using EIA(RS)485, the next cell (RP1 Comms Mode) selects the communication mode. The choice is either
IEC 60870 FT1.2 for normal operation with 11-bit modems, or 10-bit no parity. If using K-Bus this cell will not
appear.
COMMUNICATIONS
RP1 Comms Mode
IEC 60870 FT1.2
10. If using EIA(RS)485, the next cell down controls the baud rate. Three baud rates are supported; 9600, 19200
and 38400. If using K-Bus this cell will not appear as the baud rate is fixed at 64 kbps.
COMMUNICATIONS
RP1 Baud rate
19200
4.2 DNP3 CONFIGURATION

communication protocol – in this case DNP3.0.
COMMUNICATIONS
RP1 Protocol
DNP3.0
4. Move down to the next cell (RP1 Address). This cell controls the DNP3.0 address of the IED. Up to 32 IEDs can
be connected to one spur, therefore it is necessary for each IED to have a unique address so that messages
from the master control station are accepted by only one IED. DNP3.0 uses a decimal number between 1
and 65519 for the Relay Address. It is important that no two IEDs have the same address.
COMMUNICATIONS
RP1 Address
1
88 P64x-TM-EN-4.1
5. Move down to the next cell (RP1 Baud Rate). This cell controls the baud rate to be used. Six baud rates are
supported by the IED 1200 bps, 2400 bps, 4800 bps, 9600 bps, 19200 bps and 38400 bps. Make sure that
the baud rate selected on the IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
6. Move down to the next cell (RP1 Parity). This cell controls the parity format used in the data frames. The
parity can be set to be one of None, Odd or Even. Make sure that the parity format selected on the IED is
the same as that set on the master station.
COMMUNICATIONS
RP1 Parity
None
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. Move down to the next cell (RP1 Time Sync). This cell affects the time synchronisation request from the
master by the IED. It can be set to enabled or disabled. If enabled it allows the DNP3.0 master to
synchronise the time on the IED.
COMMUNICATIONS
RP1 Time Sync
Enabled
4.2.1 DNP3 CONFIGURATOR

A PC support package for DNP3.0 is available as part of the supplied settings application software (MiCOM S1 Agile)
to allow configuration of the device's DNP3.0 response. The configuration data is uploaded from the device to the
PC in a block of compressed format data and downloaded in a similar manner after modification. The new DNP3.0
configuration takes effect after the download is complete. To restore the default configuration at any time, from
the CONFIGURATION column, select the Restore Defaults cell then select All Settings.
In MiCOM S1 Agile, the DNP3.0 data is shown in three main folders, one folder each for the point configuration,
integer scaling and default variation (data format). The point configuration also includes screens for binary inputs,
binary outputs, counters and analogue input configuration.
If the device supports DNP Over Ethernet, the configuration related settings are done in the folder DNP Over
Ethernet.
4.3 IEC 60870-5-103 CONFIGURATION

communication protocol – in this case IEC 60870-5-103.
COMMUNICATIONS
RP1 Protocol
IEC 60870-5-103
P64x-TM-EN-4.1 89
4. Move down to the next cell (RP1 Address). This cell controls the IEC 60870-5-103 address of the IED. Up to 32
IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so that
messages from the master control station are accepted by one IED only. IEC 60870-5-103 uses an integer
number between 0 and 254 for the address. It is important that no two IEDs have the same IEC 60870 5 103
address. The IEC 60870-5-103 address is then used by the master station to communicate with the IED.
COMMUNICATIONS
RP1 address
162
5. Move down to the next cell (RP1 Baud Rate). This cell controls the baud rate to be used. Two baud rates are
supported by the IED, 9600 bits/s and 19200 bits/s. Make sure that the baud rate selected on the
IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
6. Move down to the next cell (RP1 Meas Period). The next cell down controls the period between
IEC 60870-5-103 measurements. The IEC 60870-5-103 protocol allows the IED to supply measurements at
regular intervals. The interval between measurements is controlled by this cell, and can be set between 1
and 60 seconds.
COMMUNICATIONS
RP1 Meas Period
30.00 s
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. The next cell down (RP1 CS103Blcking) can be used for monitor or command blocking.
COMMUNICATIONS
RP1 CS103Blcking
Disabled
9. There are three settings associated with this cell; these are:
Setting: Description:
Disabled No blocking selected.
When the monitor blocking DDB Signal is active high, either by energising an opto input or control input,
Monitor Blocking reading of the status information and disturbance records is not permitted. When in this mode the device
returns a "Termination of general interrogation" message to the master station.
When the command blocking DDB signal is active high, either by energising an opto input or control input,
Command Blocking all remote commands will be ignored (i.e. CB Trip/Close, change setting group etc.). When in this mode the
device returns a "negative acknowledgement of command" message to the master station.
4.4 MODBUS CONFIGURATION

90 P64x-TM-EN-4.1
3. Move to the first cell down (RP1 protocol). This is a non settable cell, which shows the chosen
communication protocol – in this case Modbus.
COMMUNICATIONS
RP1 Protocol
Modbus
4. Move down to the next cell (RP1 Address). This cell controls the Modbus address of the IED. Up to 32 IEDs
can be connected to one spur, therefore it is necessary for each IED to have a unique address so that
messages from the master control station are accepted by only one IED. Modbus uses a decimal number
between 1 and 247 for the Relay Address. It is important that no two IEDs have the same address.
COMMUNICATIONS
RP1 Address
1
controls how long the IED waits without receiving any messages on the rear port before it reverts to its
default state, including revoking any password access that was enabled. For the rear port this can be set
between 1 and 30 minutes.
COMMUNICATIONS
RP1 Inactivtimer
10.00 mins
supported by the IED 1200 bits/s, 2400 bits/s, 4800 bits/s, 9600 bits/s, 19200 bits/s and 38400 bits/s. Make
sure that the baud rate selected on the IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
COMMUNICATIONS
RP1 Parity
None
8. Move down to the next cell (Modbus IEC Time). This cell controls the order in which the bytes of information
are transmitted. There is a choice of Standard or Reverse. When Standard is selected the time format
complies with IEC 60870-5-4 requirements such that byte 1 of the information is transmitted first, followed
by bytes 2 through to 7. If Reverse is selected the transmission of information is reversed.
COMMUNICATIONS
Modbus IEC Time
Standard
4.5 IEC 61850 CONFIGURATION

You cannot configure the device for IEC 61850 edition 1 using the HMI panel on the product. For this you must use
the IEC 61850 Configurator, which is part of the settings application software. If the device is compatible with
edition 2, however, you can configure it with the HMI. To configure IEC61850 edition 2 using the HMI, you must first
enable the IP From HMI setting, after which you can set the media (copper or fibre), IP address, subnet mask and
gateway address.
P64x-TM-EN-4.1 91
IEC 61850 allows IEDs to be directly configured from a configuration file. The IED’s system configuration
capabilities are determined from an IED Capability Description file (ICD), supplied with the product. By using ICD
files from the products to be installed, you can design, configure and test (using simulation tools), a substation’s
entire protection scheme before the products are installed into the substation.
To help with this process, the settings application software provides an IEC 61850 Configurator tool, which allows
the pre-configured IEC 61850 configuration file to be imported and transferred to the IED. As well as this, you can
manually create configuration files for all products, based on their original IED capability description (ICD file).
Other features include:
● The extraction of configuration data for viewing and editing.
● A sophisticated error checking sequence to validate the configuration data before sending to the IED.
Note:
Some configuration data is available in the IEC61850 CONFIG. column, allowing read-only access to basic configuration data.
4.5.1 IEC 61850 CONFIGURATION BANKS

There are two configuration banks:
● Active Configuration Bank
● Inactive Configuration Bank
Any new configuration sent to the IED is automatically stored in the inactive configuration bank, therefore not
immediately affecting the current configuration.
Following an upgrade, the IEC 61850 Configurator tool can be used to transmit a command, which authorises
activation of the new configuration contained in the inactive configuration bank. This is done by switching the
active and inactive configuration banks. The capability of switching the configuration banks is also available using
the IEC61850 CONFIG. column of the HMI.
The SCL Name and Revision attributes of both configuration banks are available in the IEC61850 CONFIG. column
of the HMI.
4.5.2 IEC 61850 NETWORK CONNECTIVITY

Configuration of the IP parameters and SNTP (Simple Network Time Protocol) time synchronisation parameters is
performed by the IEC 61850 Configurator tool. If these parameters are not available using an SCL (Substation
Configuration Language) file, they must be configured manually.
Every IP address on the Local Area Network must be unique. Duplicate IP addresses result in conflict and must be
avoided. Most IEDs check for a conflict on every IP configuration change and at power up and they raise an alarm
if an IP conflict is detected.
The IED can be configured to accept data from other networks using the Gateway setting. If multiple networks are
used, the IP addresses must be unique across networks.
92 P64x-TM-EN-4.1
5 DATE AND TIME CONFIGURATION

The date and time setting will normally be updated automatically by the chosen UTC (Universal Time Co-
ordination) time synchronisation mechanism when the device is in service. You can also set the date and time
manually using the Date/Time cell in the DATE AND TIME column.
5.1 USING AN SNTP SIGNAL

When using SNTP to maintain the clock, the IED must first be connected to the SNTP server, which should be
energized and functioning.
1. In the DATE AND TIME column, check that either the Primary Source or Secondary Source setting is set to
SNTP.
2. Ensure that the IED is receiving valid time synchronisation messages by checking that the SNTP Status cell
reads Server 1 OK or Server 2 OK.
3. Check that the Act. Time Source cell reads SNTP. This indicates that the IED is using PTP as the source for
its time. Note that If IRIG-B or PTP have been selected as the Primary Source, these must first be
disconnected before the device can switch to SNTP as the active source.
4. Once the IED is using SNTP as the active time source, adjust the time offset of the universal coordinated
time on the SNTP Server equipment, so that local time is displayed.
5. Check that the time, date and month are correct in the Date/Time cell.
5.2 USING AN IRIG-B SIGNAL

When using IRIG-B to maintain the clock, the IED must first be connected to the timing source equipment (usually a
P594/RT430), which should be energized and functioning.
IRIG-B.
2. Ensure the IED is receiving the IRIG-B signal by checking that IRIG-B Status cell reads Active
3. Check that the Act. Time Source cell reads IRIG-B. This indicates that the IED is using IRIG-B as the
source for its time. Note that If SNTP or PTP have been selected as the Primary Source, these must first be
disconnected before the device can switch to IRIG-B as the active source.
4. Once the IED is using IRIG-B as the active time source, adjust the time offset of the universal coordinated
time (satellite clock time) on the satellite clock equipment, so that local time is displayed.
5. Check that the time, date and month are correct in the Date/Time cell. The IRIG-B signal does not contain
the current year so this also needs to be set manually in this cell.
6. If the auxiliary supply fails, the time and date are maintained by the auxiliary battery. Therefore, when the
auxiliary supply is restored, you should not have to set the time and date again. To test this, remove the
IRIG-B signal, and then remove the auxiliary supply. Leave the device de-energized for approximately 30
seconds. On re-energization, the time should be correct.
7. Reconnect the IRIG-B signal.
5.3 USING AN IEEE 1588 PTP SIGNAL

When using IEEE 1588 PTP to maintain the clock, the IED must first be connected to the PTP Grandmaster, which
should be energized and functioning.
PTP.
2. Set the Domain Number setting. The domain defines which clocks the IED will use for synchronisation.
Therefore this number must match the domain used by the other clocks on the network.
P64x-TM-EN-4.1 93
3. Ensure that the IED is receiving valid time synchronisation messages by checking that the PTP Status cell
reads Valid Master.
4. Check that Act. Time Source cell reads PTP. This indicates that the IED is using PTP as the source for its
time. Note that If IRIG-B or SNTP have been selected as the Primary Source, these must first be
disconnected before the device can switch to PTP as the active source.
5. Once the IED is using PTP as the active time source, adjust the time offset of the universal coordinated time
on the Master Clock equipment, so that local time is displayed.
6. Check that the time, date and month are correct in the Date/Time cell.
5.4 WITHOUT A TIMING SOURCE SIGNAL

If the time and date is not being maintained by an IRIG-B, PTP or SNTP signal, in the DATE AND TIME column, ensure
that both the Primary Source and Secondary Source are set to NONE.
1. Check that Act. Time Source cell reads Free Running.
2. Set the date and time to the correct local time and date using the Date/Time cell or the serial protocol.
3. If the auxiliary supply fails, the time and date are maintained by the auxiliary battery. Therefore, when the
auxiliary supply is restored, you should not have to set the time and date again. To test this, remove the
auxiliary supply. Leave the device de-energized for approximately 30 seconds. On re-energization, the time
should be correct.
5.5 TIME ZONE COMPENSATION

The UTC time standard uses Greenwich Mean Time as its standard. Without compensation, the date and time
would be displayed on the device irrespective of its location.
You may wish to display the local time corresponding to its geographical location. You can do this with the settings
LocalTime Enable and LocalTime Offset.
The LocalTime Enable has three setting options; Disabled, Fixed, and Flexible.
With Disabled, no local time zone is maintained. Time synchronisation from any interface will be used to directly
set the master clock. All times displayed on all interfaces will be based on the master clock with no adjustment.
With Fixed, a local time zone adjustment is defined using the LocalTime Offset setting and all non-IEC 61850
interfaces, which uses the Simple Network Time Protocol (SNTP), are compensated to display the local time.
With Flexible, a local time zone adjustment is defined using the LocalTime Offset setting. The non-local and
non-IEC 61850 interfaces can be set to either the UTC zone or the local time zone. The local interfaces are always
set to the local time zone and the Ethernet interface is always set to the UTC zone.
The interfaces where you can select between UTC and Local Time are the serial interfaces RP1, RP2, DNP over
Ethernet (if applicable) and Tunnelled Courier (if applicable). This is achieved by means of the following settings,
each of which can be set to UTC or Local.:
● RP1 Time Zone
● RP2 Time Zone
● DNPOE Time Zone
● Tunnel Time Zone
The LocalTime Offset setting allows you to enter the local time zone compensation from -12 to + 12 hours at 15
minute intervals.
94 P64x-TM-EN-4.1
5.6 DAYLIGHT SAVING TIME COMPENSATION

It is possible to compensate for Daylight Saving time using the following settings
● DST Enable
● DST Offset
● DST Start
● DST Start Day
● DST Start Month
● DST Start Mins
● DST End
● DST End Day
● DST End Month
● DST End Mins
These settings are described in the DATE AND TIME settings table in the configuration chapter.
P64x-TM-EN-4.1 95
6 PHASE ROTATION
The product provides a facility to maintain correct operation of all the protection functions even when the system
is running in a reverse phase sequence. This is achieved by the Phase Sequence setting in the SYSTEM CONFIG
column, and is available for all four setting groups.
You can configure the Phase Sequence setting to Standard ABC or Reverse ABC. This setting does not
perform any internal phase swapping of the analog channels.
The Phase Sequence setting affecs the sequence component calculation as follows (In this example, the positive
and negative sequence currents are shown. The same principle applies to voltages):
Standard ABC
Ī1 = 1/3(ĪA + aĪB +a2ĪC)
Ī2 = 1/3(ĪA + aĪB +a2ĪC)
Reverse ABC
Ī1 = 1/3(ĪA + a2ĪB +aĪC)
Ī2 = 1/3(ĪA + a2ĪB +aĪC)

where a is the operator 1Ð120°
The phase Sequence setting also affects the directional overcurrent protection as follows:
Standard ABC
● Phase A: Use IA and VBC
● Phase B: Use IB and VCA
● Phase C: Use IC and VAB
Reverse ABC
● Phase A: Use IA and -VBC
● Phase B: Use IB and -VCA
● Phase C: Use IC and -VAB
6.1 CT AND VT REVERSAL

The product also provides VT and CT reversal settings (in the SYSTEM CONFIG column), which can be used in
applications where some or all of the voltage or current inputs are temporarily reversed, for example in pump
storage applications. These settings affect the order of the analog channels in the device and are set to emulate
the order of the channels on the power system. So assuming the settings emulate the change in phase
configuration on the power system, all the protection functions will naturally operate as per a standard phase
rotation system. The phase sequence calculations and the protection functions all remain unchanged.
96 P64x-TM-EN-4.1
CHAPTER 6
TRANSFORMER DIFFERENTIAL PROTECTION

Chapter 6 - Transformer Differential Protection P64x
98 P64x-TM-EN-4.1
P64x Chapter 6 - Transformer Differential Protection
1 CHAPTER OVERVIEW

Chapter Overview 99
Transformer Differential Protection Principles 100
Implementation 107
Harmonic Blocking 118
Application Notes 122
P64x-TM-EN-4.1 99
2 TRANSFORMER DIFFERENTIAL PROTECTION PRINCIPLES

Transformer Differential Protection (87T) uses the well-known current differential principle where current entering
the protected equipment is compared with the current leaving the protected equipment. If there is no fault, the
current entering the transformer will be equal to the current leaving the transformer multiplied by the inverse of
the turns ratio. If there is a fault in the transformer zone, the currents will not be equal, which results in a
differential current. This differential current is proportional to the fault current for internal faults, but approaches
zero for any other operating conditions. The IED trips the circuit breakers protecting the transformer when it
detects a minimum level of differential current.
The differential scheme creates a well-defined protection zone between the CT sets protecting the transformer.
Any fault within the differential protection zone is called an internal fault, while any fault outside the differential
protection zone is called an external fault. The protection should operate only for internal faults and be sensitive to
low fault currents. It should also restrain on the highest prospective external faults, providing the CTS accurately
reproduce the primary currents. This is difficult to achieve in practice because the CTs never have identical
saturation characteristics. This will result in a differential current, which could cause undesirable operation.
An external fault, which causes a high current to flow through the transformer, is called a through fault. The
through-fault current will usually be high enough to saturate the CTs. The differences in the saturation
characteristics of the CTs will cause a differential current, which could cause the device to trip unless it is
restrained. The term used to specify the IED's ability to cope with these imperfections is called Through Fault
Stability.
CT saturation is not the only cause of undesirable differential current. Other aspects which need to be considered
by the transformer differential element to avoid maloperation are:
● Phase shift between the transformer primary and secondary currents depending on the vector group
● Transformation ratio
● The zero-sequence current, which flows in the grounded star transformer winding or the grounding
transformer within the differential protection zone
● Tap changer operation to adjust the voltage
● Magnetising inrush current that flows immediately after the transformer energisation or during a voltage
recovery after the clearance of an external fault or when a second transformer is paralleled with the
already energised transformer
● Over excitation of the transformer
2.1 THROUGH FAULT STABILITY

In an ideal world, the CTs either side of a differentially protected system would be identical with identical
characteristics to avoid creating a differential current. However, in reality CTs can never be identical, therefore a
certain amount of differential current is inevitable. As the through-fault current in the primary increases, the
discrepancies introduced by imperfectly matched CTs is magnified, causing the differential current to build up.
Eventually, the value of the differential current reaches the pickup current threshold, causing the protection
element to trip. In such cases, the differential scheme is said to have lost stability. To specify a differential scheme’s
ability to restrain from tripping on external faults, we define a parameter called ‘through-fault stability limit’, which
is the maximum through-fault current a system can handle without losing stability.
2.2 BIAS CURRENT COMPENSATION

To prevent maloperation, compensation is needed for the protection to remain sensitive to internal faults but to
ignore through faults. This is achieved by applying a proportion of the scalar sum of all the currents entering and
exiting the zone. This scalar sum is called bias current.
The bias characteristic changes the operating point of the IED depending on the fault current. At low through-fault
currents, the CT performance is more reliable so a low bias current is needed. Less differential current is then
needed to trip the circuit breakers, allowing greater sensitivity to internal faults. At high through-fault currents, the
100 P64x-TM-EN-4.1
CTs may be close to saturation so a high bias current is needed. More differential current is then needed to trip the
circuit breakers, allowing greater security from external faults and less risk of maloperation.
This is achieved by defining an operating current characteristic. Often a triple slope characteristic is used as shown
below.
High Set Threshold
Operate region
Idiff
K2
Restraint region
K1
Is1
Is2 Ibias
V00664
Figure 35: Compensation using biased differential characteristic
Idiff is the differential current, which is the vector sum of all the current inputs. Ibias is a current which is
proportional to the scalar sum of all currents entering and leaving the zone. The bias current is used to calculate
an operating current. If the differential current calculated by the IED is above the operation current, then the
device will trip (providing no blocking signals are asserted).
The characteristic can be defined by setting certain parameters such as the minimum operating current Is1 (Iset
1), Is2 (Iset 2), K1 and K2. Is1 sets the minimum operating current. Is2 sets the level of bias current at which the
steeper slope sets in. Constants K1 and K2 define the slopes. A High Set Threshold is usually defined, which ensures
the device will operate for very high currents, even if blocking signals are present.
The slope parts of the characteristic curve provide stability for external faults that cause CT saturation. The high
bias current region of the characteristic curve has a steeper slope than the low bias current region in order to
improve the stability even further for high-current external faults. The first slope, K1, compensates for CT errors
and tap changer errors. The second slope, K2, compensates for CT saturation. Is1 should be set above transient
overfluxing and Is2 should be considered as the transformer full load current. The CTs are sized according to the
transformer full load current.
2.3 THREE-PHASE TRANSFORMER CONNECTION TYPES

There are two ways of connecting a three-phase transformer winding:
● Star-connected (sometimes known as Y, or Wye)
● Delta-connected (sometimes known as D or D)
In some transformers, the windings are split at the centre point and terminals are brought out so that they can
also be interconnected. These windings can be zig-zag connected (Z-connected).
The more common connection types are:
● Y-y
● Y-d
● Y-z
● D-d
● D-y
● D-z
To differentiate between the low and high voltage sides of the transformer, a standard convention has been
adopted whereby lower case is used for the low voltage side and upper case is used for the high voltage side.
P64x-TM-EN-4.1 101
Not only can the primary and secondary be connected as a star or a delta, each phase can also be reversed
resulting in a large choice of possible connections. In reality, however, only a few of these are used, because we
generally require that the phase shifts between the primary windings and their secondary counterparts be
consistent. This reduces the common connection types to those shown in the table below.
You will notice that the naming convention specifying the connection type in the first column also has a number
appended to it. This number, called the clock face vector, or vector group number represents the phase shift
between the current in a low voltage winding with respect to its counterpart on the high voltage winding. This
corresponds to the position of the number of a standard clock face. The table and diagram below shows examples
of connections with the clock vectors Midnight, 1 o’ clock, 6 o’ clock and 11 o’clock, which is equivalent to a phase
shift of 0°, -30°, -180° and +30° respectively.
Vector Group Phase shift
Yy0 0°
Dd0 0°
Dz0 0°
Yd1 -30°
Dy1 -30°
Dz1 -30°
Yd5 -150°
Dy5 -150°
Dz5 -150°
Yy6 180°
Dd6 180°
Dz6 180°
Yd11 +30°
Dy11 +30°
Dz11 +30°
102 P64x-TM-EN-4.1
Type HV winding LV winding Winding Connection Phase Shift

YN yn
A2 a2
A1 a1
A2 a2
Yy0 B1 b1 0°
B2 b2
C2 B2 c2 b2 C1 c1
C2 c2
A2 a2 A1 A2 a2 a1
Dd0 C A c a B1 B2 b2 b1 0°
C2 B2 C1 C2 c2 c1
c2 b2
B b
n
A2 a4
A1 A2 a4
a3 a2 a1
Dz0 C A B1 B2 b4 0°
b3 b2 b1
C2 B2 b4 C1 C2 c4
B c4
c3 c2 c1
a2 YN
A2 c A1 A2 a2 a1
a
Yd1 c2 -30°
B1 B2 b2 b1
b
C1 C2 c2 c1
C2 B2 b2
yn
a2
A2
A1 A2 a2 a1
Dy1 A B c2 B2 b2 b1 -30°
B1
C2 B2 C1 C2 c2 c1
C b2
YN n
A2
a4 A1 A2 a4
a3 a2 a1
Yz1 B1 B2 b4 -30°
c4 b3 b2 b1
C2 B2
C1 C2 c4
b4
c3 c2 c1
YN
A2 c2
A1 A2 a1
b a2
Yd5 b2
c -150°
B1 B2 b1
b2
C2 B2 a C1 C2 c1
a2 c2
yn
A2 c2
A1 A2 a2 a1
Dy5 A B
B1 B2 b2 b1 -150°
b2
C2 B2 C1 C2 c2 c1
C
a2
YN n
A2 c4 a3 a2
A1 A2 a4 a1
b4
Yz5 B1 B2 b3 b2
b1 -150°
b4
C2 B2 C1 C2 c4 c3 c2 c1
a4
V03125
Figure 36: Transformer winding connections - part 1
P64x-TM-EN-4.1 103
Type HV winding LV winding Winding Connection Phase Shift

YN yn
A2 b1 c1
A1 A2 a2 a1
Yy6 180°
B1 B2 b2 b1
C2 B2
a1 C1 C2 c2 c1
A2 b1 b c1
A1 A2 a2 a1
Dd6 C A B1 B2 b2 b1 180°
a c
C2 B2 C1 C2 c2 c1
B a1
n
A2
c3 A2 a3 a4 a2 a1
b3
Dz6 C A B2 b3 b4 b2 b1 180°
C2 B2 c C2 c3 c4 c2 c1
B
a3
YN
a2 A1 A2 a2
A2 b a1
Yd11 a b2 B1 B2 b2 30°
b1
c C1 C2 c2
C2 B2 c2 c1
a2 yn
A2
A1 A2 a2 a1
Dy11 A B b2 30°
B1 B2 b2 b1
C2 B2
C C1 C2 c2 c1
c2
YN n
A2 a4
A1 A2 a4 a3 a2
a1
Yz11 B1 B2 b4
b3 b2 30°
b4
b1
C2 B2 c3 c2
C1 C2 c4
c4 c1
V03126
Figure 37: Transformer winding connections - part 2
2.4 PHASE AND AMPLITUDE COMPENSATION

A power transformer is designed to convert voltages. This means the line currents either side of the transformer
are different in magnitude. If identical CTs were used on both sides of the transformer, the differential protection
circuit would be unbalanced, causing a differential current. Obviously, this has to be compensated for. Amplitude
compensation is theoretically arranged by having a suitable turns ratio on the secondary CT. Ideally, selecting CT
ratios that exactly match the inverse of the transformer turns ratio would compensate for the difference in the
transformer current magnitudes. However, the CT ratios associated with available CTs typically do not provide
exact ratio matching. Also for Y-delta or delta-Y connected transformers, the voltage and current magnitudes used
are changed by a factor of Ö3. Further, a phase shift is introduced, meaning the secondary side is out of phase with
the primary side. So further amplitude compensation, as well as phase compensation is required.
Before the advent of numerical IEDs, this compensation was achieved by choosing CTs with appropriate turns
ratios and connection types, and introducing interposing CTs with appropriate connection types. Of course, having
CTs with different turns ratios and connection types on each side of the protected zone exacerbates the CT errors,
therefore increasing the need for good through-fault compensation.
With modern IEDs, it is possible to do a great deal of the compensation in software, so simple Y-connected CTs can
be used on both sides of the transformer irrespective of the connection types. The CTs are chosen such that their
respective turns ratios provide a nominal current usable by the IED (1A or 5A). This in itself provides a certain
amount of amplitude compensation, but there will invariably be a CT ratio mismatch. This mismatch is
compensated for by software in the IED. The device calculates suitable values based on the reference power
rating, transformer voltage ratings, CT ratios and connection type (star or delta) to scale the secondary currents to
a common base.
104 P64x-TM-EN-4.1
2.5 ZERO SEQUENCE FILTERING

An earth fault in a three-phase system will always produce a zero sequence current component. With earthed Y-
connected windings, this zero sequence current flows through the neutral conductor to earth. With delta-
connected windings, this zero sequence current component just circulates around the delta connected windings
(unless an earthing transformer is used). So in the case of a Y-delta transformer, an external fault will cause zero
sequence current to be measured by the Y-side CTs. However, because this zero sequence current is trapped on
the delta side, it is not measured by the delta-side CTs. This could cause maloperation if not compensated for.
Before the advent of numerical IEDs, this was handled by a configuration involving interposing CTs. Numerical
IEDs, however, can do this by filtering out the zero sequence component in software.
2.6 MAGNETISING INRUSH RESTRAINT

Whenever there is an abrupt change of magnetising voltage (e.g. when a transformer is initially connected to a
source of AC voltage), there may be a substantial surge of current through the primary winding called inrush
current.
In an ideal transformer, the magnetizing current would rise to approximately twice its normal peak value as well,
generating the necessary MMF to create this higher-than-normal flux. However, most transformers are not
designed with enough of a margin between normal flux peaks and the saturation limits to avoid saturating in a
condition like this, and so the core will almost certainly saturate during this first half-cycle of voltage. During
saturation, disproportionate amounts of MMF are needed to generate magnetic flux. This means that winding
current, which creates the MMF to cause flux in the core, could rise to a value way in excess of its steady state
peak value. Furthermore, if the transformer happens to have some residual magnetism in its core at the moment
of connection to the source, the problem could be further exacerbated.
The following figure shows the magnetizing inrush phenomenon:
+Fm
Steady state
-Fm
2Fm
Switch on at voltage
zero – No residual flux
V = Voltage, F = Flux, Im = magnetising current, Fm = maximum flux
V03123
Figure 38: Magnetising inrush phenomenon
P64x-TM-EN-4.1 105
The main characteristics of magnetising inrush currents are:

● Higher magnitude than the transformer rated current magnitude
● Containing harmonics and DC offset
● Much longer time constant than that of the DC offset component of fault current
We can see that inrush current is a regularly occurring phenomenon and should not be considered a fault, as we
do not wish the protection device to issue a trip command whenever a transformer is switched on at an
inconvenient point during the input voltage cycle. This presents a problem to the protection device, because it
should always trip on an internal fault. The problem is that typical internal transformer faults may produce
overcurrents which are not necessarily greater than the inrush current. Furthermore, faults tend to manifest
themselves on switch on, due to the high inrush currents. For this reason, we need to find a mechanism that can
distinguish between fault current and inrush current. Fortunately, this is possible due to the different natures of the
respective currents. An inrush current waveform is rich in harmonics, especially 2nd harmonics, whereas an
internal fault current consists only of the fundamental. We can therefore develop a restraining method based on
the 2nd harmonic content of the inrush current. The mechanism by which this is achieved, is called second
harmonic blocking.
2.7 OVERFLUXING RESTRAINT

Sometimes the protected transformer is subject to overfluxing due to temporary overloading with a voltage in
excess of the nominal voltage, or a reduced voltage frequency. For example, when a load is suddenly
disconnected from a power transformer, the voltage at the input terminals of the transformer may rise by 10-20%
of the rated value. Since the voltage increases, the flux also increases. As a result, the transformer steady state
excitation current becomes higher. The resulting excitation current flows in one winding only and therefore
appears as differential current which may rise to a value high enough to operate the differential protection. A
typical differential current waveform during such a condition is as follows.
E03107
Figure 39: Typical overflux current waveform
Such waveforms have a significant 5th harmonic content. We can therefore develop a restraining method based
on the 5th harmonic content of the inrush current. The mechanism by which this is achieved, is called fifth
harmonic blocking.
106 P64x-TM-EN-4.1
3 IMPLEMENTATION
To enable or disable Differential Protection, set Diff Protection in the CONFIGURATION column and Trans Diff in the
DIFF PROTECTION column of the of the relevant settings group.
3.1 DEFINING THE POWER TRANSFORMER

To set up the transformer differential protection you need to define what type of transformer is being protected.
You do this with settings in the SYSTEM CONFIG column.
The P642 only supports two-winding transformers. For the P643 and P645, the Winding Config setting determines
whether the power transformer being protected is a two-winding (HV+LV), or a three-winding (HV+LV+TV)
transformer.
The Winding Type setting determines whether the protected transformer is a conventional transformer or an
autotransformer.
The Ref Power S setting sets the reference power of the protected transformer. This is used as a reference by the
differential function to calculate the ratio correction factors (which incidentally are displayed in the Match Factor
CT cells. The reference power is the maximum MVA rating specified in the transformer nameplate.
You can define each winding as Y (or Star, or Wye), D (delta), or Z (zigzag) in the settings HV connection, LV
Connection and TV connection.
You also need to set the nominal voltage of each winding. You do this with the settings HV Nominal, LV Nominal
and TV Nominal.
To ensure the device can perform vector group correction, you need to enter the vector groups for the LV and TV
windings. You do this by entering the relevant vector group reference (available on the nameplate) using the
settings LV Vector Group and TV Vector Group.
In addition to the LV Vector Group and TV Vector Group settings, there is a setting called Ref Vector Group. This
setting allows you to apply a phase shift to the HV current inputs. In the majority of cases, this would be set to 0,
but there are some specialist applications where you may wish to set the reference vector group to something
other than 0. An application note at the end of this chapter explains why you would want do to this.
Finally, you need to set the phase sequence with the Phase Sequence setting. This will be either standard ABC
or Reverse ACB.
If the phase rotation is changed from ABC to ACB, then the vector group settings need to reflect this change
accordingly. This can be achieved by setting them to be equal to 12 minus the original value. For example a Yd11
transformer has a vector group setting of 11 when the phase sequence is ABC. However if the phase sequence
changes to ACB, then the vector group setting should be set to 1.
Note:
To minimise imbalances due to tap changer operation, current inputs to the differential element should be set according to
the mid-tap position and not the nominal voltage. The Ref Vector Group setting provides a reference vector group to which
all other vector groups are referenced. Typically, this is set to 0°.
3.2 SELECTING THE CURRENT INPUTS

The P642 has two current terminal inputs (T1 and T2), the P643 has up to three terminal current inputs (T1 to T3),
and the P645 has up to five current terminal inputs (T1 to T5).
For the P642, you associate one terminal current input with the HV (High Voltage) winding and the other with the
LV (Low Voltage) winding.
For the P643 and P645 you can choose to associate more than one terminal current input with particular windings.
In cases where more than one terminal CT is associated with a winding, the input to the differential protection
P64x-TM-EN-4.1 107
function uses the vector sum of the current terminal inputs (on a phase by phase basis) as the input to the
calculation for that winding.
You associate these current inputs with the system transformer windings with the settings HV CT Terminals, LV CT
Terminals and TV CT Terminals in the SYSTEM CONFIG column as follows:
Setting P642 P643 P645
00001
00011
001
HV CT Terminals 01 00111
011
01011
01111
10000
11000
100
LV CT Terminals 10 11100
110
11010
11110
00100
01100
TV CT Terminals 010
00110
01110
Where the terminals T1 to T5 correspond to the bits in the binary string as follows (1 = in use, 0 = not in use). The bit
order starts with T1 on the right-hand side. For example:
If a CT is assigned to more than one winding, then an alarm is issued (CT Selection Alm). When this DDB signal is
asserted, the protection is also blocked.
3.3 PHASE CORRECTION

The device automatically carries out phase correction based on the settings made in the SYSTEM CONFIG column.
For a reverse phase rotation (ACB), the device will automatically form a complementary value for the vector group
ID. You can achieve reverse phase rotation by setting the Phase Sequence setting in the SYSTEM CONFIG column.
The device will then automatically form the complementary value of the set vector group ID by subtracting it from
the number 12 (vector group ID = 12 - set ID).
3.4 RATIO CORRECTION

For transformer differential protection, ratio correction is required. The device automatically calculates the ratio
correction factor for each of the current inputs and displays the calculated matching factors in the SYSTEM
CONFIG column.
As well as the parameters of the power transformer itself, which are defined in the SYSTEM CONFIG column, you
need to set up the CT ratios and polarities. You do this in the CT AND VT RATIOS column with the Polarity, Primary
and Secondary settings for all CTs used.
The device then calculates the ratio correction factors as follows:
108 P64x-TM-EN-4.1
S ref I nom ,n
I ref ,n = K amp ,n =
3Vnom , n S ref
3Vnom, n
where:
● Sref = common reference power for all ends
● Iref,n = reference current for the respective CT input
● Kamp,n = amplitude-matching factor for the respective CT input
● Inom,n = primary nominal currents for the respective CT input
● Vnom,n = primary nominal voltage for the respective CT input
The device also checks that the matching factors are within their permissible ranges. The matching factors must
satisfy the condition:
0.05 <= Kamp <= 15 for standard CTs
0.05 <= Kamp <= 20 for sensitive CTs
3.5 CT PARAMETER MISMATCH

The CT parameter (CT Para) mismatch logic implemented in firmware is as follows:
One CT is configured to more than one

winding simultaneously
1 Set CT para mismatch alarm
Winding configuration = HV/LV

&
Reset CT para mismatch alarm
The ratio correction factor (amplitude
matching factor) of any CT is out of range
Winding configuration = HV/LV/TV

&

matching factor ) of the CTs associated with
the HV winding is out of range 1

the LV winding is out of range

the TV winding is out of range &

the TV winding is greater than allowed

the TV winding is out of range Remove the current inputs from
&
the differential calculation
the TV winding is less than 0.05
V03108
Figure 40: CT parameter mismatch logic diagram
P64x-TM-EN-4.1 109
If any of the ratio correction factors in two-winding applications are out of range, the CT para mismatch alarm is
asserted. In multi-winding applications, the alarm is asserted if the ratio correction factor of the CTs associated
with HV or LV windings are out of range or the ratio correction factor of the CTs associated to TV winding is greater
than 15 for standard CTs and 20 for sensitive CTs.
If the ratio correction factor of the CT associated to TV winding is lower than 0.05, this current is removed from the
differential calculation, as shown in the logic diagram.
If the CT para mismatch alarm is asserted the protection is also blocked.
The phase current measured values of the windings of the protected object are always scaled by the relevant
matching factors. These are then available for further processing. Consequently, all threshold values and
measured values refer back to the relevant reference currents rather than to the transformer nominal currents or
the nominal currents of the device.
3.6 SETTING UP ZERO SEQUENCE FILTERING

There are two modes of operation for zero sequence filtering; simple and advanced. You set the operation mode
with the Set Mode setting in the DIFFPROTECTION column.
In simple mode, you cannot disable zero sequence filtering. It is automatically implemented for all earthed
windings. You can define whether a winding is earthed or not with the settings HV Grounding, LV Grounding and
TV Grounding in the SYSTEM CONFIG column. If a setting is set to grounded, zero sequence filtering will always
be implemented for that winding. If set to Ungrounded, it will not be implemented.
In advanced mode, you can enable or disable zero sequence filtering manually using the settings Zero seq filt HV,
Zero seq filt LV and Zero seq filt TV in the DIFF PROTECTION column.
3.7 TRIPPING CHARACTERISTICS

The differential and bias currents for each phase are calculated from the current variables after amplitude and
vector group matching.
The differential current is the vector sum of the CT current inputs as follows:
P642 : I diff , y = I s , y ,CT 1 + I s , y ,CT 2
P643 : I diff , y = I s , y ,CT 1 + I s , y ,CT 2 + I s , y ,CT 3
P645 : I diff , y = I s , y ,CT 1 + I s , y ,CT 2 + I s , y ,CT 3 + I s , y ,CT 4 + I s , y ,CT 5
The bias current is defined as half of the scalar sum of the CT current inputs:
P 642 : I bias , y = 0.5 ⋅  I s , y ,CT 1 + I s , y ,CT 2 

 
P 643 : I bias , y = 0.5 ⋅  I s , y ,CT 1 + I s , y ,CT 2 + I s , y ,CT 3 
 
P 645 : I bias , y = 0.5 ⋅  I s , y ,CT 1 + I s , y ,CT 2 + I s , y ,CT 3 + I s , y ,CT 4 + I s , y ,CT 5 
 
where:
● y is the measured phase (A, B or C)
● Is is the current after the amplitude and vector group are matched.
110 P64x-TM-EN-4.1
The tripping characteristic has two knees. The first knee is dependent on the settings of Is1 and K1. The second
knee is defined by the setting Is2. The lower slope provides stability for low external faults. The higher slope
provides stability for high through fault conditions, since transient differential currents may be present due to
current transformer saturation.
Idiff/Inom
Is-HS2
Is-HS1 Restraint region
K2
Operate region
K1
Is1
TC and CT errors
Is2 Ibias /Inom

V03110
Figure 41: Transformer biased tripping characteristic
Once the differential and bias currents are calculated, the following comparisons are made and an operate/
restrain signal is obtained:
For the flat slope range: 0 ≤ Ibias max ≤ Is1/K1
Idiff ≥ Is1 + transient bias

For the K1 slope range: Is1/K1 ≤ Ibias max ≤ Is2
Idiff ≥ K1.Ibias max + transient bias

For the K2 slope range: Is2 ≤ Ibias max ≤ Is-HS2/K2
Idiff ≥ K1.Is2 + K2(Ibias max - Is2 ) + transient bias
3.7.1 HIGH-SET FUNCTION

The High Set 1 algorithm uses a peak detection method to achieve fast operating times. The peak value is the
largest absolute value of differential current in the latest cycle. Since the High Set 1 algorithm uses a peak
detection method, Is-HS1 is set above the expected highest magnetizing inrush peak to maintain immunity to
magnetizing inrush conditions. For a High Set 1 trip, two conditions must be fulfilled:
● The peak value of the differential current is greater than Is-HS1 setting.
● The bias characteristic is in the operate region.
If the differential current is above the adjustable Is-HS1 threshold, the device will trip if in the Operate region, but
not in the restrain region. However, second harmonic blocking and overfluxing blocking are NOT taken into
account. The High Set 1 resets when the differential and bias currents are in the restraint area.
If the differential current is above the adjustable Is-HS2 threshold, bias current is not taken into account and the
device will trip regardless. As with High Set 1, second harmonic blocking and overfluxing blocking are NOT taken
into account. The High Set 2 element resets when the differential current drops below 0.95*Is-HS2.
P64x-TM-EN-4.1 111
3.7.2 CIRCUITRY FAIL ALARM

The circuitry fail alarm logic requires the following settings:
Circuitry Fail: to enable or disable the function
Is-cctfail: to define the minimum differential threshold
K-cctfail: to define the slope gradient
CctFail Delay: to set a time delay
If the differential current is larger than the Is-cctfail setting and no trip is issued after the time delay has elapsed,
an alarm is issued indicating a CT problem.
3.8 TRIPPING CHARACTERISTIC STABILITY

Conditions such as CT saturation and transient switching operations can cause incorrect operation of differential
elements. To avoid this a number of techniques are employed in this device. These include :
● Maximum and Residual Bias
● Transient Bias
● CT saturation detection (to discriminate between internal and external faults)
● No Gap Detection
● External Fault Detection
● Current Transformer Supervision
● Circuitry Fail Alarm
● Second Harmonic Blocking
● Fifth Harmonic Blocking
3.8.1 MAXIMUM BIAS

The differential and bias currents are calculated on a per phase basis eight times per cycle. A comparison between
differential and bias current is used to determine whether to trip or not. The comparison is made on a per phase
basis using the differential current measured on that phase. However a common bias current is used for all three
phases.. To assure stability, the largest bias current calculated on any phase is used to restrain all phases. This is
referred to as the Maximum Bias.
3.8.2 DELAYED BIAS

To provide further stability when external faults are being cleared, the protection checks for the highest value of
bias current calculated during the previous cycle. If that value is higher than the present value, it is used to restrain
the tripping decision. This is referred to as the Residual Bias. The Residual Bias technique maintains through fault
stability for clearance of external faults.
3.8.3 TRANSIENT BIAS

If there is a sudden increase in the mean-bias measurement, an additional bias quantity (caled Transient Bias) can
be introduced into the bias calculation, on a per-phase basis. Transient Bias is only active for external faults. It can
be enabled or disabled with the Transient Bias setting in the DIFF PROTECTION column.
Transient bias, decays exponentially. The transient bias quantity is added to the operating current calculated at
the maximum bias. Therefore, the following differential current thresholds are available:
Differential threshold phase A = Iop at max bias + transient bias_phase A
Differential threshold phase B = Iop at max bias + transient bias_phase B
Differential threshold phase C = Iop at max bias + transient bias_phase C
112 P64x-TM-EN-4.1
The transient bias technique uses a time decay constant, stability coefficients, and some differential function
settings to provide a dynamic bias characteristic. The following diagram shows the behaviour during an external
fault. For the device to trip, the fundamental of the differential current should be above the operating current at
max bias + transient bias.
1.6
transient bias - phaseA
1.4 Iadiff fundamental
Iop at max bias + transient bias - phaseA

1.2
1
I (pu)
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
t(s)
V03109
Figure 42: Transient bias characteristic
The transient bias function enhances the stability of the differential element during external faults and allows for
the time delay in CT saturation caused by small external fault currents and high X/R ratios.
No transient bias is produced under load switching conditions, or when the CT comes out of saturation.
3.8.4 CT SATURATION TECHNIQUE

During CT saturation the second harmonic content may be high enough to block the low set differential element.
This would result, in the operation of the low set differential element being delayed for some internal faults. The
device includes a CT Saturation Detection technique, which unblocks the low set differential element during
internal faults with heavy CT saturation. This CT saturation detection technique is capable of distinguishing
between magnetising inrush and CT saturation. Therefore the 2nd harmonic blocking will work properly for
magnetising inrush, but will not be asserted for internal faults where CT saturation is an issue. This function is
enabled or disabled with the CT Saturation setting in the DIFF PROTECTION column.
3.8.5 NO GAP DETECTION TECHNIQUE

The No Gap Detection technique detects light CT saturation on a per phase basis. The No Gap Detection technique
unblocks the low set differential element during light CT saturation, allowing the low set differential element to trip
faster. Stability during inrush conditions is maintained, as this technique distinguishes between an inrush and a
saturated waveform. This function is enabled or disabled with the No Gap setting in the DIFF PROTECTION column.
3.8.6 EXTERNAL FAULT DETECTION TECHNIQUE

An External Fault Detection technique has been implemented so that the CT saturation and No gap detection
techniques do not affect the second harmonic blocking during an external fault.
This technique considers the time to saturation, a delta bias start signal, a delta differential start signal and the
ratio of delta differential to delta bias at the time of start. As soon as an external fault occurs, the bias current
P64x-TM-EN-4.1 113
changes, but the differential current only increases after the time to saturation. The external fault detection DDBs
are asserted if the following conditions are fulfilled:
The delta bias start signal is asserted first. The delta bias start signal and the delta differential start signal are
asserted if the delta bias and delta differential currents are greater than 0.65 Is1 respectively.
The time difference between the assertion of the delta bias start signal and the assertion of the delta differential
signal is greater than the time to saturation. The minimum time to saturation is 2.5 ms for a 50 Hz system and 2.08
ms for a 60 Hz system.
The ratio of delta differential to delta bias is smaller than a fixed threshold when the delta bias start signal is
asserted.
The External Fault Detection algorithm is on a per phase basis. If an external fault is detected on phase A, B or C,
signals External fault A, External fault B or External fault C are asserted. The external fault detector resets after 6
seconds from the start or after 25 cycles from the start if the current is less than 0.9Is1.
The following figure shows the time to saturation for an external fault.
114 P64x-TM-EN-4.1
I/KA
-1
IA-1 IB-1 IC-1
I/KA
2.5
0.0
-2.5
-5.0
IA-5 IB-5 IC-5
Time to saturation = 31.5ms

PU
1.0
0.5
0.0
IA-DIFF IB-DIFF IC-DIFF
PU
1.5
1.0
0.5
IA-BIAS IB-BIAS IC-BIAS
V03124
Figure 43: Time to saturation - external AN fault
3.8.7 CURRENT TRANSFORMER SUPERVISION

If the CTS Status setting in the SUPERVISION Column is set to restrain, then upon detection of a CTS condition, and
following the CTS Time Delay, the minimum operating current is raised to the Is-CTS value.
This has the effect of lifting the minimum operate current threshold on the bias characteristic as follows:
P64x-TM-EN-4.1 115
Idiff/Inom
Is-HS2
K2
Operate region
Is-CTS
K1
Is1
TC and CT errors
Is2 Ibias /Inom

V03127
Figure 44: Effect of CTS restrain
3.8.8 CIRCUITRY FAIL ALARM

Under normal operating conditions there should be no differential current (although there might be a small
amount due to CT mismatch). Under conditions such as current transformer (CT) failure or a failure of the CT
circuitry, a small differential current may be seen. This product can monitor the scheme for such conditions with a
dual slope differential characteristic, by enabling the Circuitry Fail setting in the DIFF PROTECTION column. The
characteristic is then defined by the settings Is-cctfail and k-cctfail. By default it is a time-delayed element to
prevent conflict with the tripping characteristic in the event of a genuine transformer fault. But if the ratio of
differential to bias current exceeds the Is-cctfail and k-cctfail settings, but does not exceed the Is1 and k1
settings, for the duration of the Is-cctfail setting, a circuitry fail alarm is raised. The Is-cctfail delay is set to 5
seconds by default.
The level at which the circuitry fail alarm would operate under these circumstances is shown by the red line as
follows:
Idiff/Inom
Is-HS2
K2
Operate region
K-cctfail
Is-CTS
K1
Is1
TC and CT errors
Is-cctfail
Is2 Ibias /Inom

V03128
Figure 45: Bias characteristic with circuitry fail alarm
116 P64x-TM-EN-4.1
3.9 DIFFERENTIAL BIASED TRIP LOGIC

The differential biased trip is affected by both the CT Saturation technique and by the No Gap detection technique.
If the second harmonic blocking is asserted and either the CT Saturation Detection or No Gap detection technique
is asserted, then the biased differential trip is unblocked.
CT Saturation Detection and No Gap detection act independently from 5th harmonic blocking, however. A biased
differential trip will occur only if the fifth harmonic blocking is not asserted and the bias differential start signal is
asserted. The differential biased trip logic is described below.
Cross blocking IA5H Diff Start

Enabled
& Id Bias Start A & Id Bias Trip A
1
1
IA2H Diff Start &
&
CT Saturation A IB5H Diff Start
1
No Gap A & Id Bias Start B & Id Bias Trip B
1
External Fault A
1
IB2H Diff Start &
&
CT Saturation B IC5H Diff Sta rt
1
No Gap B & Id Bias Start C & Id Bias Trip C
External Fault B
1
IC2H Diff Start &
&
CT Saturation C
1
No Gap C &
External Fault C
V03113
Figure 46: Differential biased trip logic
P64x-TM-EN-4.1 117
4 HARMONIC BLOCKING
4.1 2ND HARMONIC BLOCKING

The IED filters the differential current to determine the fundamental (Idiff(fn)) and second harmonic (Idiff(2fn)
current components. The device uses these quantities to produce a blocking signal, which will block the protection
in the event that the second harmonic component exceeds a certain level.
Second harmonic blocking is phase segregated. If the ratio of the second harmonic component to fundamental
component exceeds an adjustable threshold (set by IH2 Diff Set) in two consecutive calculations, a second
harmonic blocking signal is issued for the relevant phase. These are:
IA2H Diff Start (blocking signal for phase A)
IB2H Diff Start (blocking signal for phase B)
IC2H Diff Start (blocking signal for phase C)
If the Cross Blocking setting in the DIFF PROTECTION column is enabled, any one of the phase blocking signals will
block all three phases.
No blocking signal is asserted if the differential current exceeds the set thresholds Is-HS1 or Is-HS2.
The following flow diagram summarises the 2nd harmonic blocking procedure:
Any phase N
Idiff(2 fn)/Idiff(fn) > Setting Counter = 0
Counter + = 1
N
Counter >= 2
Block 1-phase
Drop-off
Low-set diff
Y Block 3-phase
Cross Block enabled
Low-set diff
Return
V03111
Figure 47: 2nd harmonic blocking process
118 P64x-TM-EN-4.1
4.2 2ND HARMONIC BLOCKING LOGIC
Idiffa
Idiffafundamental
fundamental
Low current (hard-coded)

& IA2H Diff Start
IB2H Diff Start

Idiffa 2nd harm / I diffa
Idiffa 2nd fund
harmonic IC2H Diff Start
IH2 Diff Set
Idiffb
Idiffbfundamental
fundamental

&
Idiffb 2nd harm / I diffb

Idiffb 2nd fund
harmonic
IH2 Diff Set
Idiffc
Idiffcfundamental
fundamental

&
Idiffc 2nd harm / Idiffc

Idiffb 2nd fund
harmonic
IH2 Diff Set
V00706
Figure 48: 2nd harmonic blocking logic
4.3 2ND HARMONIC SETTING GUIDELINES

During the energization period, the second harmonic component of the inrush current may be as high as 70%,
depending on the power rating. The second harmonic level may be different for each phase, which is why phase
segregated blocking is available.
If the setting is too low, the 2nd harmonic blocking may prevent tripping during some internal transformer faults. If
the setting is too high, the blocking may not operate for low levels of inrush current which could result in undesired
tripping of the differential element during the energization period. In general, a setting of 15% to 20% is suitable.
When testing the 2nd Harmonic blocking feature using an Omicron harmonic restraint module, it is recommended
that the CT Saturation and No Gap settings are Disabled while keeping Transient Bias either Enabled or
Disabled. However, when the relay is in service it is recommended that the CT Saturation and No Gap settings
are both Enabled. This is to make sure that if an internal fault develops during energisation of the transformer,
the 2nd Harmonic blocking feature does not delay tripping of the differential protection element.
P64x-TM-EN-4.1 119
4.4 5TH HARMONIC BLOCKING IMPLEMENTATION

The IED filters the differential current to determine the fundamental Idiff(fn) and the fifth harmonic component
Idiff(5fn). The device uses these quantities to produce a blocking signal, which will block the protection in the event
that the fifth harmonic component exceeds a certain level.
5th Harmonic blocking can be used to prevent unwanted operation of the low set differential element under
transient overfluxing conditions.
The 5th harmonic blocking threshold is adjustable between 0 - 100% differential current. The threshold should be
adjusted so that blocking will be effective when the magnetizing current rises above the chosen threshold setting
of the low-set differential protection.
Fifth harmonic blocking is phase segregated. If the ratio Idiff(5-fn)/Idiff(fn) exceeds an adjustable threshold (set by
IH5 Diff Set in two consecutive calculations, and if the differential current is larger than 0.1 pu (the minimum
setting of Is1), then the fifth harmonic blocking signal is issued for the relevant phase. The DDB signals are:
IA5H Diff Start (blocking signal for phase A)
IB5H Diff Start (blocking signal for phase B)
IC5H Diff Start (blocking signal for phase C)
No cross blocking is available for 5th harmonic blocking.
No blocking signal is asserted if the differential current exceeds the set thresholds Is-HS1 or Is-HS2.
The following flow diagram summarises the 5th harmonic blocking procedure:
Any phase N
Idiff(5 fn)/Idiff(fn) > Setting Counter = 0
Counter + = 1
N
Counter >= 2
Block 1-phase
Drop-off
Low-set diff
Return
V03112
Figure 49: 5th harmonic blocking process
4.5 5TH HARMONIC SETTING GUIDELINE

In most applications, the default settings will ensure stability of the differential element. If more difficult situations
exist, the 5th harmonic differential current blocking facility may be of use.
A typical setting for Ih(5)%> is 35%.
120 P64x-TM-EN-4.1
4.6 GEOMAGNETIC DISTURBANCES

To offer protection against damage due to persistent overfluxing caused by a geomagnetic disturbance, the 5th
harmonic blocking element can be mapped to an output contact using an associated timer. Operation of this
element could be used to give an alarm to the network control centre. If such alarms are received from a number
of transformers, they could serve as a warning of geomagnetic disturbance so that operators could take some
action to safeguard the power system.
Alternatively this element can be used to initiate tripping in the event of prolonged pick up of a 5th harmonic
measuring element. It is not expected that this type of overfluxing condition would be detected by the AC
overfluxing protection. This form of time delayed tripping should only be applied in regions where geomagnetic
disturbances are a known problem and only after proper evaluation through simulation testing.
4.7 OVERALL HARMONIC BLOCKING LOGIC

The following logic diagram shows how the differential protection blocking mechanism works under conditions of
overfluxing and magnetisation inrush.
Id biased
delay
5th harmonic
Overfluxing detection
& Idiff Trip
Id biased
Trip
2nd harmonic
Inrush detection
& Idiff HS1 Trip
1 Idiff Trip
Idiff HS2 Trip
No Gap detection
1
&
CT Saturation
External Fault
Change Is1 to
Is-CTS in
restraint mode K2
CT Supervision K1
Is1 &
Is2
Idiff > Is-HS1
Idiff > Is-HS2
V03114
Figure 50: Differential protection blocking mechanisms
P64x-TM-EN-4.1 121
5 APPLICATION NOTES
5.1 SETTING GUIDELINES

The differential setting, Configuration/Diff Protection, should be set to Enable.
The basic pick up level of the low set differential element, Is1, is variable between 0.1 pu and 2.5 pu in 0.01
pu steps. The setting will be dependant on the item of plant being protected and by the amount of differential
current that might be seen during normal operating conditions. When the device is used to protect a transformer,
we recommend a setting of 0.2 pu.
When protecting generators and other items of plant, where shunt magnetizing current is not present, a lower
differential setting would be more typical. We recommend 0.1 pu.
The P64x percentage bias calculation is performed 8 times per cycle. A triple slope percentage bias characteristic
is implemented. Both the flat and the lower slope provide sensitivity for internal faults. Under normal operation
steady state magnetizing current and the use of tap changers result in unbalanced conditions and hence
differential current. To accommodate these conditions the initial slope, K1, may be set to 30%. This ensures
sensitivity to faults while allowing for mismatch when the power transformer is at the limit of its tap range and CT
ratio errors. At currents above rated, extra errors may be gradually introduced as a result of CT saturation, Hence,
the higher slope may be set to 80% to provide stability under through fault conditions, during which there may be
transient differential currents due to saturation effect of the CTs. The through fault current, in all but ring bus or
mesh fed transformers, is given by the inverse of the per unit reactance of the transformer. For most transformers,
the reactance varies between 0.05 to 0.2 pu, therefore typical through fault current is given by 5 to 20 In.
The wide matching factor range is provided to allow the designer to trade off between the CT selection and the
scheme sensitivity. This is useful for applications such as busbar protection where a wide range of CT ratios may
be encountered. You should also note that the matching factor check should be carried out for all ends. One end
alone is not sufficient. The maximum sensitivity achieved in this product depends on the type of analog input and
is given in the CT requirements.
Note:
Differential protection alone may not achieve the full sensitivity required, and other protection functions such as REF may
have to be incorporated in conjunction with the differential protection.
The number of biased differential inputs required for an application depends on the transformer and its primary
connections. We recommend, where possible, that a set of biased CT inputs is used for each set of current
transformers. According to IEEE C37.110-2007, separate current inputs should be used for each power source to
the transformer. If the secondary windings of the current transformers from two or more supply breakers are
connected in parallel, under heavy through fault conditions, differential current resulting from the different
magnetizing characteristics of the current transformers flows in the IED. This current only flows through one
current input in the device and can cause maloperation. If each CT is connected to a separate current input, the
total fault current in each breaker provides restraint. You should only connect CT secondary windings in parallel
when both circuits are outgoing loads. In this condition, the maximum through fault level is restricted solely by the
power transformer impedance.
The P64x IED achieves stability for through faults in two ways, both of which are essential for correct relay
operation. The first consideration is the correct sizing of the current transformers. The second is by providing a bias
characteristic as shown below:
122 P64x-TM-EN-4.1
Idiff/Inom
Is-HS2
K2
Operate region
K1
Is1
TC and CT errors
Is2 Ibias /Inom

V03110
Figure 51: Triple slope characteristic
5.2 EXAMPLE 1: TWO-WINDING TRANSFORMER - NO TAP CHANGER

Consider a two-winding power transformer with the following specifications:
● Power rating: 90 MVA Transformer
● Connection type: YNd9
● Voltage specification 132:33 kV.
● HV CT ratio: 400:1
● LV CT ratio: 2000:1
● Percentage reactance: 10%
P64x-TM-EN-4.1 123
90 MVA
132 kV/33 kV
YNd9
400:1 2000:1
A a
B b
C c
Protected zone
Earthing
transformer
B B
Phase & amplitude Phase & amplitude

Correction B B
Correction
+ +
Zero sequence filtering Zero sequence filtering
B B
D D D
P642
V03115
Figure 52: P642 used to protect a two winding transformer
Set the following parameters in the SYSTEM CONFIG column:

Setting in GROUP 1 SYSTEM CONFIG Value
Winding Config HV+LV
Winding Type Conventional
HV CT Terminals 01
LV CT Terminals 10
Ref Power S 90.00 MVA
Ref Vector Group 0
HV Connection Y-Wye
HV Grounding Grounded
HV Nominal 132.0 kV
HV Rating 90.00 MVA
% Reactance 10.00%
LV Vector Group 9
LV Connection D-Delta
LV Grounding Grounded
LV Nominal 33.00 kV
LV rating 90.00 MVA
Phase Sequence Standard ABC
VT Reversal No Swap
124 P64x-TM-EN-4.1

CT1 Reversal No Swap
Vector correction and zero sequence filtering are automatically performed by virtue of the LV Vector Group setting
and the HV Grounding and LV Grounding settings.
The ratio correction factors are calculated as follows:
I nom ,T 1CT 400

K amp ,T 1CT = = = 1.016
S ref 90 ×106
3Vnom, HV 3 ×132 ×103
I nom ,T 2CT 2000

K amp ,T 2CT = = = 1.270
S ref 90 ×106
3Vnom , LV 3 × 33 × 103
where:
● Kamp, T1CT, T2CT = ratio correction factor of T1 CT or T2 CT windings
● Inom, T1CT, T2CT = primary nominal currents of the main current transformers
● Vnom, HV,LV = primary nominal voltage of HV or LV windings
These matching factors are also displayed in the SYSTEM CONFIG column (Match Factor CT1 and Match Factor
CT2)
Now set the current differential parameters as follows:
Setting in GROUP 1 DIFF PROTECTION Value
Trans Diff Enabled
Set Mode Advance
Is1 200.0e-3 PU
K1 30.00%
Is2 1.000 PU
K2 80.00%
tdiff 0s
Is-CTS 1.500 PU
Is-HS1 10.00 PU
HS2 Status Disbled
Zero seq filt HV Enabled
Zero seq filt LV Enabled
IH2 Diff Block Enabled
IH2 Diff Set 20%
Cross Blocking Enabled
CT Saturation Enabled
No Gap Enabled
P64x-TM-EN-4.1 125

IH5 Diff Set 35%
Circuitry Fail Disabled
5.3 EXAMPLE 2: AUTOTRANSFORMER WITH LOADED DELTA WINDING

Consider an autotransformer with the following specifications:
● Power rating: 175/175/30 MVA
● Connection type: YNyn0d1
● Voltage specification: 230/115/13.8 kV.
● TV CT ratio: 2000:5
● HV tap range: +5% / -15% and 19 taps
126 P64x-TM-EN-4.1
175/175/30 MVA
230/115/13.8 kV
YNynd1
+5% / -15% TV
800:5 19 taps 2000:5
HV
a
A
b
B
c
C
Earthing
Protected zone transformer
c
LV
1200:5
B B

Correction Correction
B B
+ +
B B
Phase & amplitude

Correction
B
+
Zero sequence filtering
B
D D D
P645
V03116
Figure 53: P645 used to protect an autotransformer with loaded delta winding
Since the transformer has an on load tap changer on the HV side, the nominal voltage of the HV winding must be
set to the mid tap voltage level. According to the nameplate data, the mid tap voltage is 218.5 kV. The mid tap
voltage can also be calculated as follows:
(5 − 15)
100 +
Mid tap voltage = 2 × 230 = 218.5kV
100

Winding Config HV+LV+TV
Winding Type Auto
P64x-TM-EN-4.1 127

HV CT Terminals 00001
LV CT Terminals 10000
TV CT Terminals 00100
Ref Vector Group 0
HV Connection Y-Wye
HV Grounding Grounded
HV Nominal 218.50 kV
HV Rating 175.00 MVA
% Reactance 10.00%
LV Vector Group 0
LV Connection Y-Wye
LV Grounding Grounded
LV Nominal 115.00 kV
LV rating 145.00 MVA
TV Vector Group 1
TV Connection D-Delta
TV Grounding Grounded
TV Nominal 13.800 kV
TV rating 30.00 MVA
VT Reversal No Swap
The device calculates the ratio correction factors as follows:
I nom ,T 1CT 800

K amp ,T 1CT = = = 1.730
S ref 175 ×106
3Vnom, HV 3 × 218.5 ×103
I nom ,T 5CT 1200

K amp ,T 5CT = = = 1.366
S ref 175 × 106
3Vnom , LV 3 ×115 ×103
I nom ,T 3CT 2000

K amp ,T 3CT = = = 0.273
S ref 175 ×106
3Vnom ,TV 3 × 13.8 ×103
128 P64x-TM-EN-4.1
where:
● Kamp, T1CT, T2CT, T3CT = ratio correction factor of T1 CT, T2 CT, or T3 windings
Inom, T1CT, T2CT, T3CT = primary nominal currents of the main current transformers
● Vnom, HV, LV, TV = primary nominal voltage of HV, LV, or TV windings
These matching factors are also displayed in the SYSTEM CONFIG column (Match Factor CT1 and Match Factor
CT2)
Trans Diff Enabled
Set Mode Advance
Is1 200.0e-3 PU
K1 30.00%
Is2 1.000 PU
K2 80.00%
tdiff 0s
Is-CTS 1.500 PU
Is-HS1 10.00 PU
HS2 Status Disabled
Zero seq filt HV Enabled
Zero seq filt LV Enabled
Zero seq filt TV Enabled
IH2 Diff Set 20%
No Gap Enabled
IH5 Diff Set 35%
5.4 EXAMPLE 3: AUTOTRANSFORMER WITH UNLOADED DELTA WINDING

Consider an autotransformer with the following specifications:
● Power rating: 175/175/30 MVA
● Connection type: YNyn0d1
● Voltage specification: 230/115/13.8 kV.
● Neutral CT ratio: 1200:5
● HV taps at +5% and -15%
The winding configuration is set to HV + LV + TV. The CT on the HV line side is connected to T1 CT, the CT on the HV
neutral side is connected to T2 CT, and the CT on the LV side is connected to T3 CT.
P64x-TM-EN-4.1 129
175 /175 /30 MVA

230 /115 /13.8 kV
YNynd1
+5% / -15%
19 taps 1200 :5
LV
1200 :5 a
HV
A b
B c
1200 :5
Protected
zone
B B

Correction B B
Correction
+ +
B B
Phase & amplitude

Correction B
+
B
D D D
P643
V03117
Figure 54: P643 used to protect an autotransformer with unloaded delta winding

Winding Type Auto
HV CT Terminals 001
LV CT Terminals 100
TV CT Terminals 010
Ref Vector Group 0
HV Connection Y-Wye
HV Grounding Ungrounded
HV Nominal 230.0 kV
HV Rating 175.00 MVA
% Reactance 10.00%
LV Vector Group 0
130 P64x-TM-EN-4.1

LV Connection Y-Wye
LV Grounding Ungrounded
LV Nominal 230.00 kV
LV rating 175.00 MVA
TV Vector Group 0
TV Connection Y-Wye
TV Grounding Ungrounded
TV Nominal 230.0 kV
TV rating 175.0 MVA
VT Reversal No Swap
It is preferable to have the ratio correction factors equal to or close to 1.
Applying Kirchoff's law, assume that the full load current is flowing, that an equivalent source is connected to the
HV winding and that an equivalent load is connected to the LV winding. The current distribution is as follows:
S 175 ×106
I FLC − HV = = = 439 A
3Vnom , HV 3 × 230 ×103
S 175 ×106
I FLC − LV = = = 878 A
3Vnom, LV 3 × 115 ×103
175/175/30 MVA
230 /115 /13.8 kV
YNynd1
230 kV - +5%/-15% - 19 taps
a 878 Ð0°
439 Ð0° 439 Ð0° A
Equivalent b 878 Ð-120°
load
439 Ð-120° 439 Ð-120° B
c 878 Ð-240°
439 Ð-120° 439 Ð120° C
1200:5
1200:5 1200:5
V03118
Figure 55: Unloaded delta – current distribution
P64x-TM-EN-4.1 131
The reference power is set to 175 MVA and the nominal voltage in HV, LV and TV windings is set to 230 kV. In this
application, you do not need to consider the mid tap voltage, even though, there is an on load tap changer on the
HV side.
The device calculates the ratio correction factors as follows:
I nom,T 1CT 1200

K amp ,T 1CT = K amp ,T 2CT = K amp ,T 3CT = = = 2.73
S ref 175 × 106
3Vnom 3 × 230 × 103
Trans Diff Enabled
Set Mode Advance
Is1 200.0e-3 PU
K1 20.00%
Is2 1.000 PU
K2 80.00%
tdiff 0s
Is-CTS 1.500 PU
Is-HS1 10.00 PU
HS2 Status Disabled
Is-HS2 32.00 PU
Zero seq filt HV Disabled
Zero seq filt LV Disabled
Zero seq filt TV Disabled
IH2 Diff Set 20%
No Gap Enabled
IH5 Diff Set 35%
The differential element does not protect the tertiary winding. Unloaded delta-connected tertiary windings are
often not protected. If protection is required, the delta winding can be earthed at one point through a current
transformer used to provide instantaneous overcurrent protection for the tertiary winding.
5.5 SETTING GUIDELINES FOR SHORT-INTERCONNECTED BIASED DIFFERENTIAL

PROTECTION
The P645 can be used to protect busbars. Consider the five feeders - single bus scheme and its differential
protection zone shown below:
132 P64x-TM-EN-4.1
B
Phase & amplitude Circuit Breaker 1
Correction
B
+
B
B
B
Correction
+
B
B
Correction
B
+
B
B
Correction
B
+
B
B
B
Correction
+
B
115kV
D D D
P645
V03119
Figure 56: Single bus differential protection zone
Assume that feeder CTs 1 to 5 are connected to inputs T1 to T5 respectively.

HV CT Terminals 01111
LV CT Terminals 10000
Ref Power S 145.0 MVA*
Ref Vector Group 0
HV Connection Y-Wye
HV Grounding Ungrounded**
HV Nominal 115.0 kV***
HV Rating 145.0 MVA****
% Reactance 10.00%
LV Vector Group 0
LV Connection Y-Wye
LV Grounding Ungrounded**
LV Nominal 115.0 kV***
LV rating 145.00 MVA****
P64x-TM-EN-4.1 133

TV Vector Group 0
TV Connection Y-Wye
TV Grounding Ungrounded**
TV Nominal 115.0 kV***
TV rating 145.0 MVA****
Note:
* This is the maximum load (including overloads) that would be handled by the busbar.
Note:
** This disables the zero sequence filters.
Note:
*** This is the system voltage.
Note:
**** This setting has no impact on the differential protection. It is used by other functions such as the thermal and through-
fault monitoring elements which are not required for busbar protection.

Trans Diff Enabled
Set Mode Advance
Is1 1.200 PU
K1 20.00%
Is2 400.0e-3 PU
K2 80.00%
tdiff 0s
Is-CTS 1.500 PU
Is-HS1 10.00 PU
HS2 Status Disabled
IH2 Diff Block Disabled
Circuitry Fail Enabled
Is-cctfail 100.0e-3 PU
K-cctfail 10.00%
Cctfail Delay 5.000 s
134 P64x-TM-EN-4.1
Note:
Set the Circuitry Fail alarm to Enabled and set K-cctfail to 15% to allow the maximum composite error of 10% that may be
introduced by class 10P current transformers. Is-cctfail is typically set between 5 to 20% to prevent CT noise and differential
current caused by load imbalance. This element is typically delayed by 5 s.
Note:
CT supervision should be used to prevent maloperation if there is an open circuited CT secondary. The CTS feature can be
used to desensitize the biased differential protection. To do this, raise the differential current pickup setting Is1 to the value of
Is-CTS.
Idiff/Inom
4
3.8
3.6
3.4 K2 = 80%
3.2
3
2.8
2.6 Is-CTS
2.4
2.2
2
1.8
1.6
1.4 Is1
1.2
1
0.8
0.6
0.4
0.2 Is-cctfail > 10%
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Ibias/Inom
P64x cctfail CT error Is-CTS
V03120
Figure 57: Busbar biased differential protection
5.6 SETTING GUIDELINES FOR SHUNT REACTOR BIASED DIFFERENTIAL PROTECTION

Shunt reactors are commonly used in the power system to compensate for the capacitive reactance of long
transmission lines. Shunt reactors are inductive loads that are used to absorb reactive power to reduce the over
voltages generated by line capacitance.
One of the main difficulties with shunt reactor protection is that the protection IED may maloperate during iron-
core reactor energization and de-energization. A shunt reactor is typically switched in and out regularly depending
on the power system load. The iron-core shunt reactor energization current contains a DC offset with a long time
constant (up to 1 second) and low frequency components. These current waveforms cause a certain level of flux in
the CT magnetic core. During normal reactor operation the current is generally the nominal current, which is not
high enough to reduce the flux level in the CT. In the next switch in operation, the flux may either increase or
decrease depending on the point o on the wave when energization occurs. The regular switching in and out of the
reactor causes CT saturation; therefore, we recommend that the current transformers on both sides of the reactor
have similar excitation characteristics to reduce the risk of maloperations. A high impedance differential scheme is
generally better than a low impedance differential scheme, because it is not affected by CT saturation.
P64x-TM-EN-4.1 135
As per IEEE C37.109-2006 the properties of shunt reactors can be summarized as follows:
● Dry air-air core type reactors: no magnetizing inrush during energization as there is no iron core. The peak
current during energization might be as high as 2 Ö2Inominal due to transient offset. Air core type reactors
are normally used up to 34.5 kV and often installed on the transformer tertiary winding.
● Oil-immersed type reactors: the gapped iron-core type might experience severe energizing inrush. The
coreless type experiences less severe magnetizing inrush.
Consider the following shunt reactor:
Busbar A Busbar B
T1 CT T2 CT
400 :5 400:5
Bk 1 Bk 2 Bk 3
500 kV
163 .3 MVA
T3 CT
1000 :1
V03121
Figure 58: Shunt Reactor single line diagram
The bias differential element in the P643 would be used to protect the reactor. In a reactor application the low set
differential element Is1, should be set between 10%-15%. Inrush current in a shunt reactor does not appear as a
differential current like that which appears in a transformer, unless the CT saturates after some time due to long
DC time constant. Though the level of second harmonic in many cases can be relatively high, there are many
cases with no or very low content of harmonics in the differential current. Since the level of 2nd harmonic is small
in shunt reactors compared with transformers, the high set 1 differential element, Is-HS1, can be set to 250% of
the reactor current at rated voltage.
Winding Config HV+LV
HV CT Terminals 011
LV CT Terminals 100
Ref Vector Group 0
HV Connection Y-Wye
HV Grounding Ungrounded
HV Nominal 500.0 kV
HV Rating 163.3 MVA
% Reactance 40.00%
136 P64x-TM-EN-4.1

LV Vector Group 0
LV Connection Y-Wye
LV Grounding Ungrounded
LV Nominal 115.0 kV
LV rating 163.3 MVA
VT Reversal No Swap

Trans Diff Enabled
Set Mode Simple
Is1 100.0e-3 PU
K1 30.00%
Is2 1.000 PU
K2 80.00%
tdiff 0s
Is-CTS 1.500 PU
Is-HS1 2.500 PU
HS2 Status Disabled
Cross blocking Enabled
CT Saturation Disabled
No Gap Disabled
5.7 SETTING GUIDELINES FOR USING SPARE CT INPUTS

The P643 and P645 can be configured to protect transformers for differential protection and the unused CT inputs
can be used to protect other circuits. For example the P643 can use 2 of the 3 phase CT inputs to provide
differential protection of a 2 winding transformer by setting Winding Config to HV+LV and the unused 3rd 3
phase current input can be used to provide overcurrent protection on another circuit such as an auxiliary
transformer, as shown below:
P64x-TM-EN-4.1 137
V03122
Figure 59: P643 Using spare CT input for overcurrent protection
5.8 SETTING GUIDELINES FOR REFERENCE VECTOR GROUP

The following table shows how to set the zero sequence filter for the different Ref Vector Group options.
Ref Vector Group Zero seq filt HV setting Zero seq filt LV setting Zero seq filt TV setting
0 Enabled Disabled Disabled
1 Disabled Disabled Enabled
2 Enabled Enabled Disabled
In the majority of applications, the reference vector group setting Ref Vector Group is set to 0. However there are
occasional applications where it may be desirable to set it to a value other than 0.
One example is to increase the sensitivity for phase-to-phase faults where it is used to protect a YNyn0
transformer. In this scenario, the P64x would normally apply a -30° phase shift to both HV and LV windings due to
the way it works. However, by setting the reference vector group to 1, the device knows it does not have to apply a
-30° shift in its calculations, thus increasing its sensitivity to phase-to-phase faults.
138 P64x-TM-EN-4.1
5.9 STUB BUS APPLICATION

When a winding isolator is open (e.g. for maintenance purposes), a section of energized line, called the stub, could
be left unprotected. In the diagram below, we see that the HV winding disconnector is open and there is a fault in
the stub zone, which needs to be protected against.
HV TV
LV
Isolator
open signal
P645
V00696
Figure 60: Stub Bus arrangement
We do not want the standard differential protection or low impedance REF protection to operate, as this may have
repercussions on the rest of the system. In this case, Stub Bus protection should be used, when available. Stub Bus
protection is achieved by using the isolator status , applying this to an opto-input and combining it with a phase
overcurrent element (linked to the relevant winding) to provide a trip signal for the relevant circuit breakers.
5.9.1 STUB BUS IMPLEMENTATION

When the protection is used in one and half breaker busbar topology and the disconnector of any of the three
windings of the transformer is open, the differential and low impedance REF elements related to this winding are
affected.
The differential and low impedance REF protection elements should not trip for a stub bus fault and should be
blocked on a per winding basis.
5.9.1.1 STUB BUS ACTIVATION

The Stub Bus active signals HV StubBus Act, LV StubBus Act and TV StubBus Act are asserted when the
appropriate conditions are met to activate Stub Bus for the relevant winding. A fast under current DDB signal,
available on a per winding basis along with the isolator status, should be used to assert the respective Stub Bus
active signal. The fast under current DDB will become asserted if the current measured falls below the I< Current
Set of the relevant CBF element. For the fast undercurrent DDBs, I< Current Set represents a percentage of the CT
secondary nominal current (In). CBF does not need to be activated for the fast under current DDB to assert.
5.9.1.2 STUB BUS DIFFERENTIAL BLOCKING

When a Stub Bus active signal is asserted for a winding, the current of the respective winding is not considered in
the calculation of the differential and bias currents. The differential trip is not blocked however, and should be
blocked on the winding with Stub Bus active only (it should remain unblocked on the other windings). For example,
if a fault occurs within the differential zone and the HV Stub Bus is active, the differential element should only trip
the breakers connected to the LV and TV sides of the transformer. In this case, blocking of the HV winding
differential trip in can be achieved via the PSL logic.
Low impedance REF protection is blocked internally on a per winding basis by the fixed scheme logic. For example,
if HV StubBus Act is activated, then HV low impedance REF is blocked.
In applications where the protection is per differential scheme, the Stub Bus protection cannot be used since the
differential protection trip will be blocked each time any Stub Bus is activated.
P64x-TM-EN-4.1 139
5.9.1.3 STUB BUS TRIPPING

You can protect the Stub Bus zone by a non-directional DT phase overcurrent element with a delay time set to zero
second. To issue a Stub Bus trip, the overcurrent element and the relevant Stub Bus active DDB signals must both
be high. You can configure the Stub Bus tripping scheme in PSL.
5.9.2 STUB BUS SCHEME
Idiff Trip
Blocking 100
Idiff Trip
& Dwell Output R4
0
HV UndCurrent Activation
& S
89 a Q HV StubBus Act
Input L1 R
89b
&
Input L2
HV StubBus Trip
100
Tripping Output R1
& Dwell
POC 1 I>3 Trip
0
This example applies to the HV element only . The LV and TV elements follow the same principles .
In this example , the following applies :
 The differential trip output is connected to output relay 4

 The HV Stub bus trip output is connected to output relay 1
 The HV stage 3 phase overcurrent element is used
 The 89 a contact is connected to opto -input 1
 The 89 b contact is connected to opto -input 2
V03129
Figure 61: Stub Bus Scheme Logic
5.10 TRANSFORMER DIFFERENTIAL PROTECTION CT REQUIREMENTS

The CT requirements detailed below are applicable to both standard CTs and sensitive CTs.
5.10.1 CT REQUIREMENTS - TRANSFORMER APPLICATION

We strongly recommend Class X or Class 5P current transformers for transformer differential protection
applications.
The current transformer knee-point voltage requirements are based on the following settings:
Parameter Description Value
This sets the minimum differential current threshold required for the transformer differential
Is1 0.2 pu
protection to trip.
This defines the bias current threshold at which the second slope of the bias current
Is2 1 pu
characteristic becomes active.
K1 This setting defines the gradient of the first slope in the bias current characteristic. 30%
K2 This setting defines the gradient of the second slope in the bias current characteristic. 80%
This setting defines the first High set threshold on the bias current characteristic. This setting
Is-HS1 10 pu
is only used in advanced mode.
This setting defines the second High set threshold on the bias current characteristic. This
Is-HS2 32 pu
setting is only used in advanced mode.
Transient Bias This setting enables or disables the transient bias factor Enabled
140 P64x-TM-EN-4.1

Zero seq filt HV This setting enables or disables zero sequence filtering on the HV winding Enabled
Zero seq filt LV This setting enables or disables zero sequence filtering on the LV winding Enabled
Zero seq filt TV This setting enables or disables zero sequence filtering on the TV winding Enabled
IH2 Diff Set This setting defines the second harmonic blocking threshold. 20%
This setting enables or disables cross blocking (cross blocking is where a 2nd harmonic
Cross blocking Enabled
blocking signal from any one phase, blocks all three phases).
CT Saturation This setting enables or disables CT saturation detection. Enabled
No Gap This setting enables or disables CT Gap detection. Enabled
IH5 Diff Set This setting defines the fifth harmonic blocking threshold. 35%
The following table provides the maximum sensitivity and its corresponding matching factor for different CT types:
Matching factor for typical setting
CT Type Max. sensitivity Permitted Matching Factor range
Is1 = 0.02 pu
Standard 43 mA 0.05 - 15 4.65
Sensitive 13 mA 0.05 - 20 15.38
A series of external faults were simulated to determine the CT requirements for the differential function, by using a
state of the art Real Time Digital Simulation system (RTDS). We performed these tests with different X/R ratios, CT
burdens, fault currents, fault types and points on the current waveform.
To achieve through-fault stability, the K dimensioning factor must comply with the following expressions:
System Conditions K Kneepoint voltage (VK)

In < IF <= 40In VK => 16In(RCT + 2RL + Rr) (earth fault)
16
5 <= X/R <= 20 VK => 16In(RCT + RL + Rr) (phase fault)
40In < IF <= 64In VK => 30In(RCT + 2RL + Rr) (earth fault)
30
17
34
where:
● VK = kneepoint voltage
● K = CT dimensioning factor
● In = rated current
● RCT = resistance of CT secondary winding
● RL = resistance of a single lead from device to current transformer
● Rr = resistance of any other protection devices sharing the current transformer
● IF = maximum external fault level
5.10.2 CT REQUIREMENTS - SMALL BUSBAR APPLICATION

We strongly recommend Class X or Class 5P current transformers for this application.
The current transformer knee-point voltage requirements are based on the following settings:
P64x-TM-EN-4.1 141

This sets the minimum differential current threshold required for the transformer differential
Is1 1.2 pu
protection to trip.
This defines the bias current threshold at which the second slope of the bias current
Is2 0.4 pu
characteristic becomes active.
K1 This setting defines the gradient of the first slope in the bias current characteristic. 20%
K2 This setting defines the gradient of the second slope in the bias current characteristic. 80%
This setting defines the first High set threshold on the bias current characteristic. This setting
Is-HS1 10 pu
is only used in advanced mode.
This setting defines the second High set threshold on the bias current characteristic. This
Is-HS2 Disabled
setting is only used in advanced mode.
Transient Bias This setting enables or disables the transient bias factor Enabled
Zero seq filt HV This setting enables or disables zero sequence filtering on the HV winding Disabled
Zero seq filt LV This setting enables or disables zero sequence filtering on the LV winding Disabled
Zero seq filt TV This setting enables or disables zero sequence filtering on the TV winding Disabled
IH2 Diff Set This setting defines the second harmonic blocking threshold. Disabled
CT Saturation This setting enables or disables CT saturation detection. Disabled
No Gap This setting enables or disables CT Gap detection. Disabled
IH5 Diff Set This setting defines the fifth harmonic blocking threshold. Disabled
A series of internal and external faults were simulated to determine the CT requirements for the differential
function. We performed these tests with different X/R ratios, CT burdens, fault currents, fault types and points on
the current waveform.
The system conditions, CT dimensioning factor and CT kneepoint voltage are as follows:

16
30
21
30
where:
● RL = Resistance of a single lead from device to current transformer
142 P64x-TM-EN-4.1
CHAPTER 7
TRANSFORMER CONDITION MONITORING

Chapter 7 - Transformer Condition Monitoring P64x
144 P64x-TM-EN-4.1
P64x Chapter 7 - Transformer Condition Monitoring
1 CHAPTER OVERVIEW

Chapter Overview 145
Thermal Overload Protection 146
Loss of Life Statistics 152
Through Fault Monitoring 156
RTD Protection 160
CLIO Protection 162
P64x-TM-EN-4.1 145
2 THERMAL OVERLOAD PROTECTION

Transformer overheating can be caused due to failures of the cooling system, external faults that are not cleared
promptly, or overload and abnormal system conditions. These abnormal conditions include low frequency, high
voltage, non-sinusoidal load current, or phase-voltage imbalance.
Overheating shortens the life of the transformer insulation in proportion to the duration and magnitude of the high
temperature. If excessive, this may even result in an immediate insulation failure. Overheating can also generate
gases that could result in electrical failure, or cause the transformer coolant to be heated above its flashpoint
temperature, introducing the risk of fire.
Studies suggest that the life of insulation is approximately halved for each 10°C rise in temperature above the
rated value. However, the life of insulation is not wholly dependent on the rise in temperature but on the time the
insulation is subjected to this elevated temperature. Due to the relatively large heat storage capacity of a
transformer, infrequent overloads of short duration may not damage it. However, sustained overloads of a few
percent may result in premature aging and consequent insulation failure.
Transformer thermal overload protection is designed to protect equipment from sustained overload. Thermal
overload protection allows modest but transient overload conditions to occur, while tripping for sustained
overloads, which would not be detected by standard overcurrent protection.
Transformer Losses
The losses in a transformer are shown in the following diagram:
Transformer Losses
Load Losses No Load Losses
Core Losses
Copper Losses Stray Losses Apparent Losses
(Iron Losses)
Eddy-current Losses Hysteresis Losses

V03200
Figure 62: Transformer losses
The flow of the magnetising current through the resistance of the winding creates a real but generally relatively
small I2R loss and voltage drop. The loss that is due to this magnetizing current in the primary winding is called the
apparent loss.
Time-varying fluxes in iron-based materials, cause losses called core losses, or iron losses. These iron losses are
divided into two categories; hysteresis losses and eddy-current losses.
The sum of copper losses and the stray losses is called the load loss. Copper losses are due to the flow of load
currents through the primary and secondary windings. They are equal to I2R, and they heat up the wires and
cause voltage drops. Stray losses are due to the stray capacitance and leakage inductance. Stray capacitance
exists between turns, between one winding and another, and between windings and the core.
146 P64x-TM-EN-4.1
2.1 THERMAL OVERLOAD IMPLEMENTATION

The thermal overload protection in this device is based on the IEEE Standard C57.91-1995. It provides thermal
overload protection for either an individual winding or the transformer as a whole. The thermal overload
protection settings are in the THERMAL OVERLOAD column.
For individual windings, you set the MonitoredWinding setting to to HV, LV, TV accordingly. If you wish to
protect the transformer as a whole set the MonitoredWinding setting to Biased Current, which provides an
overall loading picture of the transformer.
The device provides two 3-stage Definite Time delayed trip elements; one element for Hotspot temperature and
one for Top Oil temperature. Top Oil temperature can be calculated, or measured directly using CLIO or RTD
methods, but Hotspot temperature is always calculated.
A pre-trip alarm can be configured in the tPre-trip Set setting. This alarm indicates that thermal overload will trip
after the set time if the load level remains unchanged.
Four cooling modes are available. You can set the oil exponent constant and winding exponent constant
independently for each mode. You can set the cooling mode automatically in the PSL or manually in the setting file.
For the latter, you will need to configure two opto-inputs as CM Select 1X and CM Select X1, and you must wire the
contacts to energise or de-energise these inputs. The selected cooling mode would then be as follows:
CM Select 1X CM Select X1 Selected Cooling Mode
0 0 1
0 1 2
1 0 3
1 1 4
To calculate the Top Oil and hotspot winding temperature, the device takes into consideration the ratio of the
actual load to the rated load. If the monitored winding is set to HV, LV, or TV, the rated load is determined by the
HV rating, LV rating, or TV rating settings respectively and the Irated setting. If the monitored winding is set as
the the biased current, the rated load is calculated using the Sref power rating setting in the SYSTEM CONFIG
column and the Irated setting in the THERMAL PROTECTION column.
The thermal overload model is executed once every power cycle. The thermal overload trip can be based on either
hot spot temperature or top oil temperature, or both.
The device has up to three hot spot stages and up to three top oil stages. The tripping signal, Top Oil T>x Trip, is
asserted when the top oil (measured or calculated) temperature is above the setting, Top Oil>x Set, and the time
delay, tTop Oil>x Set has elapsed. Also, the tripping signal, Hotspot>x Trip, is asserted when the hottest-spot
(calculated only) temperature is above the setting, Hotspot>x Set, and the time delay, tHotspot>x Set has elapsed.
2.1.1 THERMAL OVERLOAD BIAS CURRENT

The biased current used by the thermal protection is not the same as the biased current used by the differential
protection. No vector correction or zero sequence filtering is performed. To calculate the bias current, the thermal
element considers the maximum RMS current on a per winding basis. Note that the bias current calculation
performed by the thermal element is not on a per-phase basis. The thermal bias current calculation is as follows:
Max [ I HVArms , I HVBrms , I HVCrms ] Max [ I LVArms , I LVBrms , I LVCrms ] Max [ ITVArms , ITVBrms , ITVCrms ]
+ +
HV _ FLCSref LV _ FLCSref TV _ FLCSref
I bias =
2
P64x-TM-EN-4.1 147
where:
● HV_FLCSref = HV full load current at the reference power
● LV_FLCSref = LV full load current at the reference power
● TV_FLCSref = TV full load current at the reference power
2.2 THE THERMAL MODEL

The simplest implementation of overload protection employs an I2t characteristic. You set time constants such as
the winding time constant at Hotspot location and top oil rise time constant, so that the thermal model can follow
the correct exponential heating and cooling profile. Transformer loads are becoming increasingly non-linear;
therefore the device uses true RMS current values to replicate the winding Hotspot temperature.
Note:
"True RMS" refers to the RMS value of a non-sinusoidal waveform including the fundamental and all other components.
2.2.1 TOP OIL TEMPERATURE CACULATIONS

If the Top Oil temperature is not available as a measured input quantity, it is calculated every cycle by the following
equation:
QTO = QA + DQTO
where:
● QTO = Top Oil temperature
● QA = Ambient temperature
● DQTO = Top Oil rise over ambient temperature due to a step load change
You can either measure the ambient temperature directly, or set it in the Ambient T setting. The ultimate top oil rise
is given by the following equation:
n
 K u2 R + 1 
∆ΘTO ,U = ∆ΘTO , R ⋅  
 R +1 
where:
Ku = the ratio of actual load to rated load
R = the ratio of the load loss at rated load to no load loss (Rated NoLoadLoss setting)
n = Oil exponent (Oil exp n setting)
QTO,R = Top Oil rise over ambient temperature at rated load (Top Oil Overamb setting)
The load current used in the calculations is the RMS value.
2.2.2 HOTSPOT CACULATIONS

The Hotspot temperature can only be obtained by calculation. The following equation is used to calculate the hot
spot temperature every cycle:
QH = QTO + DQH
148 P64x-TM-EN-4.1
where:
● QH = Hotspot (winding) temperature
● QTO = Top Oil temperature
● DQH = Hotspot rise above top oil temperature
The ultimate Hotspot rise over top oil is given by:
DQH,U = DQH,R . KU2m

where:
● DQH,R = winding hottest spot rise over top oil temperature at rated load. This parameter is set by the user
● KU = the ratio of actual load to rated load
● m = winding exponent (Winding exp m setting)
2.2.3 THERMAL STATE MEASUREMENT

DHot spot temperature, Top oil temperature and ambient temperature are stored in non-volatile memory. These
measurements are updated every power cycle. The thermal state can be reset to zero by any of the following:
● The Reset Thermal cell under the MEASUREMENT 3 column on the front panel
● A remote communications interface command
● A status input state change.
The top oil temperature, hot spot temperature, ambient temperature and pre-trip time left are available as a
measured value in the MEASUREMENT 3 column.
If you need a more accurate representation of the transformer thermal state, you can use temperature monitoring
devices (RTDs or CLIO), which target specific areas. For short period overloads, RTD, CLIO and overcurrent
protection techniques provide better protection.
The PSL provides a signal indicating that the transformer is de-energised (TFR De-energised). This signal is
asserted when all the circuit breakers are open. In this case, the transformer no-load losses are not considered. As
a result, the top oil and hottest spot temperatures are equal to the ambient temperature when the monitored
current is zero. If this signal is removed, the top oil and hottest spot temperatures are not equal to the ambient
temperature even when the monitored current is zero. In this case the top oil and hottest spot temperatures will
increase according to the described equations.
2.3 APPLICATION NOTES
2.3.1 RECOMMENDATIONS
Monitored Winding
You can set the monitored winding to HV, LV, TV or Biased Current. We recommend setting it to Biased
Current to provide an overall thermal condition for the transformer.
Ambient Temperature
Ambient temperature is an important factor when determining the load capability of a transformer, because you
add it to the temperature rise due to loading to determine the operating temperature. IEEE C57.91-1995 states
that transformer ratings are based on an average ambient temperature of 30°C.
The Ambient T Source setting defines whether the ambient temperature should be set to an average level or
measured directly using a CLI or RTD input. When measuring the ambient temperature, it should be averaged over
a 24-hour period.
P64x-TM-EN-4.1 149
Top Oil Temperature

The Top Oil T source setting defines whether the Top Oil temperature is calculated or measured.
We recommend setting the rated load (Rated Current) to 1.0 pu.
2.3.2 IEEE RECOMMENDATIONS
Winding Exponent
IEEE C57.91-1995 suggests the following winding and oil exponents.
Type of cooling m (winding exponent) n ( oil exponent)
OA 0.8 0.8
FA 0.8 0.9
Non-directed FOA or FOW 0.8 0.9
Directed FOA or FOW 1.0 1.0
The cooling mechanisms are:

● OA (Oil/Air): The cooling system transfers heat using oil or air without using pumps or fans.
● FA (Forced Air): The cooling is aided by fans, without any pumps to circulate the oil.
● FOA (Forced Oil and Air): The cooling system uses both pumps and fans to cool the winding.
● FOW (Forced Oil and Water): The heat exchanger is water-cooled and does not have the typical radiator
configuration. The cooler is normally a chamber with many tubes inside where the oil and water exchange
heat energy. In non-directed flow transformers, the pumped oil flows freely through the tank. In directed
flow transformers, the pumped oil is forced to flow through the windings.
The exponents are empirically derived and are required to calculate the variation of DQH and DQTO with load
changes. The value of m has been selected for each mode of cooling to approximately account for effects of
changes in resistance and viscosity with changes in load. The value of n has been selected for each mode of
cooling to approximately account for effects of change in resistance with change in load.
Oil Time Constant

When setting the Hotspot and Top Oil stages take into consideration the suggested temperature limits (IEEE Std.
C57.91-1995):
Suggested limits of temperature for loading above nameplate distribution transformers with 65° C rise
Top Oil temperature 120°C
Hotspot conductor temperature 200°C
Suggested limits of temperature for loading above nameplate power transformers with 65° C rise
Top Oil temperature 110°C
Hotspot conductor temperature 180°C
2.3.3 DATA PROVIDED BY TRANSFORMER MANUFACTURERS

The transformer manufacturer should provide information pertaining to the following parameters:
Rated NoLoadLoss: The ratio of load loss at rated load to no load loss.
Hot Spot Overtop: Winding hottest-spot rise over Top Oil at rated load
Top Oil overamb: Top Oil rise over ambient temperature at rated load
Winding exp m: Winding exponent
150 P64x-TM-EN-4.1
Oil exp n: Oil exponent

HotSpotRiseConst: Winding time constant at Hotspot location (this may also be estimated from the resistance
cooling curve during thermal tests)
TopOilRiseConst (Oil time constant)
The following tables are examples of the thermal data provided by the transformer manufacturer:
Thermal characteristics for a 735 MVA 300 kV +7% to -18% / 23 kV ODWF cooled generator transformer
Specification Value
No load losses (core losses) 340 kW
Load losses at nominal tap 1580 kW
Load losses at maximum current tap 1963 kW
Oil time constant 2.15 hr
Oil exponent 1.0
Top Oil rise over ambient temperature at rated load 33.4 K
Winding time constant at Hotspot location 14 mins
Winding hottest spot rise over Top Oil temperature at rated load 30.2 K
Winding exponent 2.0
Note:
OD (oil directed) indicates that oil from heat exchangers (radiators) is forced through the windings. WF (Water Forced) states
that the oil is externally cooled by pumped water.
Thermal characteristics for a 600 MVA 432/23.5 kV ODWF cooled generator transformer
Specification Value
No load losses (core losses) 237 kW
Load losses at nominal tap 1423 kW
Load losses at maximum current tap 1676 kW
Oil exponent 1.0
Top Oil rise over ambient temperature at rated load 46.6 K
Winding time constant at Hotspot location 9 mins
Winding hottest spot rise over Top Oil temperature at rated load 33.1K
Thermal characteristics for a IEC 60354 figures based on medium-large power transformers OD cooled
Specification Value
Oil exponent 1.0
Top Oil rise over ambient temperature at rated load 49 K
Winding time constant at Hotspot location 5-10 mins
Winding hottest spot rise over Top Oil temperature at rated load 29 K
P64x-TM-EN-4.1 151
3 LOSS OF LIFE STATISTICS

Deterioration of transformer insulation is a time dependent function of temperature, moisture and oxygen content.
The effects of moisture and oxygen can be minimized through designing in preservation systems for most modern
transformers, therefore it is temperature that is the main reason for transformer aging. Frequent overloading will
shorten the life expectancy of a transformer due to the elevated winding temperatures.
Insulation deterioration is not uniform and will be more pronounced at Hotspots within the transformer tank.
Therefore any asset management system intending to model the rate of deterioration is based on simulated real-
time Hotspot temperature algorithms. These models may take ambient temperature, Top Oil temperature, load
current, oil pump status (pumping or not), and radiator fan status (blowing or not).
Alstom transformer protection devices provide such a loss of life monitoring facility in accordance with the thermal
model defined in IEEE C57.91. The protection algorithm determines the current rate of life-loss, and uses that
information to indicate the likely remaining service time. The asset owner can be alerted in advance, so that he
can plan an outage in which to carry out the required maintenance such as reconditioning or rewinding.
3.1 LOSS OF LIFE IMPLEMENTATION

Loss of life settings are found in the THERMAL OVERLOAD column of the required setting group.
The device provides two single-stage definite time delay alarms based on aging acceleration factor (FAA) or loss of
life (LOL).
A reset command is provided to allow you to reset the calculated parameters displayed in the MEASUREMENTS 3
column: Loss of Life status (LOL status), Loss of Life aging factor (LOL Aging Factor), mean aging factor (FAA,m),
rate of loss of life (Rate of LOL), residual life at mean aging factor (Lres at FAA,m), and residual life at designed
(Lres at designed).
The loss of life model is executed once every power cycle.
3.1.1 LOSS OF LIFE CALCULATIONS

IEEE C57.91-1995 defines the aging acceleration factor as the rate at which transformer insulation aging for a
given maximum Hotspot temperature is accelerated compared with the aging rate at a reference maximum
Hotspot temperature. For transformers with average winding temperature rise of 65°C, the reference maximum
Hotspot temperature is 110°C. For transformers with average winding temperature rise of 55°C, the reference
maximum Hotspot temperature is 95°C. For maximum Hotspot temperatures in excess of the reference maximum
Hotspot temperature, the aging acceleration factor is greater than 1. For maximum Hotspot temperatures lower
than the reference maximum Hotspot temperature, the aging acceleration factor is less than 1.
The model used for loss of life statistics is given by the equations for LOL and FAA. LOL is calculated every hour
according to the following formula:
LOL = L(QH,r) - Lres(QH,r)
where:
● L(QH,r) = life hours at reference winding hottest-spot temperature (Life Hours at HS setting)
● Lres(QH,r) = residual life hours at reference winding hottest-spot temperature
The aging acceleration factor FAA is calculated once every cycle as follows:
 B 
 A+   B B 
L ( Θ H ,r )  Θ H ,r + 273  −
e  
 Θ H ,r + 273 Θ H + 273 
FAA = = B
=e
L ( ΘH ) 
 A+


 Θ H + 273 
e
152 P64x-TM-EN-4.1
If a 65°C average winding rise transformer is considered, the equation for FAA is as follows:
 B B 
 − 
 383 Θ H + 273 
FAA = e
If a 55°C average winding rise transformer is considered, the equation for FAA is as follows:
 B B 
 − 
 368 Θ H + 273 
FAA = e
where:
● L(QH) = life hours at winding hottest-spot temperature
● QH,r = hottest-spot temperature at rated load
● B = constant B from life expectancy curve. This parameter is set by the user. IEEE Std. C57.91-1995
recommends a B value of 15000.
The residual life hours at reference hottest-spot temperature is updated every hour as follows:
3600
∑F i =1
AA,i (Θ H )
Lres (Θ H , r ) = Lres , p (Θ H , r ) −
3600
where:
● Lres,p(QH,r) = residual life hours at reference temperature one hour ago
● FAA,i(QH) = mean aging acceleration factor, as calculated above (calculated every second)
The accumulated loss of life is updated in non-volatile memory once per hour. It is possible to reset this to a new
value if required; for example if the device is applied in a new location with a pre-aged resident transformer.
The rate of loss of life (ROLOL) in percentage per day is as follows. It is updated every day:
24
ROLOL = ⋅ FAA, m (Θ H ) ⋅100%
L (Θ H , r )
The mean aging acceleration factor, FAA,m, is as follows. It is updated every day:
N N
∑ FAAn ⋅ ∆tn ∑ FAAn
n =1 n =1
FAA, m = N
=
∑ ∆tn N
n =1
where:
● FAA,n is calculated every power cycle
● Dtn = 1 cycle
● FAA,m states the latest one-day statistics of FAA. When the device is energized for the first time, FAA,m default
value is 1.
The residual life in hours at FAA,m is as follows. It is updated every day:
Lres (Θ H , r )
Lres ( FAA,m ) =
FAA, m
P64x-TM-EN-4.1 153
3.2.1 LOL SETTING GUIDELINES

Set the life hours at the reference maximum Hotspot temperature. According to IEEE Std. C57.91-1995, the normal
insulation life at the reference temperature in hours or years must be user-defined. The following table extracted
from IEEE Std. C57.91-1995 gives values of normal insulation life for a well-dried, oxygen-free 65°C average
winding temperature rise insulation system at the reference temperature of 110°C.
Basis Normal Insulation life Hours Normal Insulation Life Years
50% retained tensile strength of insulation (former IEEE Std
65000 7.42
C57.92-1981 criterion)
25% retained tensile strength of insulation 135000 15.41
200 retained degree of polymerization in insulation 150000 17.12
Interpretation of distribution transformer functional life test
180000 20.55
data (former IEEE Std. C57.91-1981)
Note:
Tensile strength or degree of polymerization (D.P.) retention values were determined by sealed tube aging on well-dried
insulation samples in oxygen-free oil.
Note:
Refer to I.2 in annex I of the IEEE Std. C57.91-1995 for discussion of the effect of higher values of water and oxygen and also
for the discussion on the basis given above.
You should set the designed Hotspot temperature setting (Designed HS temp) to 110°C if the transformer is rated
65°C average winding rise. If the transformer is rated 55°C average winding rise, set it to 95°C.
As recommended by IEEE C57.91-1995, set the Constant B Set setting to 5000.
If the calculated aging acceleration factor is greater than the setting FAA> Set and the time delay tFAA> Set has
elapsed, the FAA alarm DDB signal is activated.
If the calculated loss of life is greater than the setting LOL>1 Set and the time delay tLOL> Set has elapsed, the
LOL alarm DDB signal is activated.
3.2.2 EXAMPLE
Consider a new 65°C average winding rise rated transformer whose life hours figure at designed maximum
Hotspot temperature is 180,000 hrs. As a result, you set the Life Hours at HS setting to 180,000, and the
Designed HS temp setting to 110.0°C. Set Constant B Set to 15,000 as recommended by IEEE. The aging
acceleration factor takes into consideration the constant B and the hottest spot temperature calculated by the
thermal function. For a distribution transformer, IEEE suggests 200°C as the limit for the maximum hot spot
temperature. The aging acceleration factor alarm will be asserted when 70% of the 200°C has been reached. The
aging acceleration factor is calculated as follows:
 B B   B B 
 −   383 − 0.7×200 + 273 
 383 hottest − spot −tempt + 273 
FAA = e =e  
= 17.2
Therefore:
FAA>set should be set to 17.2. tFAA> Set may be set to 10.00 min. LOL>1 Set may be set to 115,000 hrs, if
it is considered that the transformer has 65,000 hrs left (Life Hours at HS – hours left = 180,000 – 65,000 = 115,000
hrs). tLOL> Set may be set to 10.00 min. Finally, the Reset Life Hours setting determines the value of the LOL
154 P64x-TM-EN-4.1
measurement once the Reset LOL command is executed. The default value is zero because considering a new
transformer, after testing the thermal function the LOL measurement should be reset to zero.
You should perform certain tests to determine the age of an old transformer. Please obtain advice from the
transformer manufacturer.
P64x-TM-EN-4.1 155
4 THROUGH FAULT MONITORING

Through faults are a major cause of transformer damage and failure, as they can stress the insulation and
mechanical integrity of the transformer. Through-fault monitoring is usually used to tackle this problem. This
mechanism monitors fault currents passing through the transformer, which may significantly exceed its rated
current. The through-fault monitoring mechanism is based on an I2t calculation.
According to IEEE C57.109-1993(R2008), mechanical effects are more significant than thermal effects for fault-
current magnitudes near the design capability of the transformer. However, at fault-current magnitudes close to
the overload range, mechanical effects are less important unless the frequency of fault occurrence is high. Note
that mechanical effects are more important in large kVA transformers. The standard states that the maximum
duration limit for the worst case of mechanical duty is 2 s.
The standard defines the following transformer categories:
Category Single phase (kVA) Three-phase (kVA)
I 5 to 500 15 to 500
II 501 to 1667 501 to 5000
III 1668 to 10000 5001 to 30000
IV Above 10000 Above 30000
Categories I and II consider only the transformer short-circuit impedance, whereas categories III and IV consider
the system short-circuit impedance at the transformer location as well as transformer short-circuit impedance.
The short-circuit impedance is expressed as a percentage of the transformer rated voltage and the rated power of
the transformer.
4.1 THROUGH FAULT MONITORING IMPLEMENTATION

Through-fault monitoring can be enabled with the Through Fault setting in the TF MONITORING column.
The through-fault current monitoring function monitors the fault current level, the duration of the faulty condition
and the date and time for each through-fault. An I2t calculation based on the recorded time duration and
maximum current is performed for each phase.
This calculation is only performed when the current exceeds the TF I> Trigger setting and if the DDB signal Any
Diff Start is NOT asserted. Cumulative stored calculations for each phase are monitored so you can schedule the
transformer maintenance based on this data.
A single-stage alarm is available for through-fault monitoring. The alarm is issued if the maximum cumulative I2t in
the three phases exceeds the TF I2t> Alarm setting. A through fault event is recorded if any of the phase currents
is larger than the TF I> Trigger setting. You should always set TF I> Trigger greater than the overload capability of
the transformer.
156 P64x-TM-EN-4.1
4.2 THROUGH FAULT MONITORING LOGIC

IA magnitude
TF I > Trigger
&
IA2t 1
& Throu fa ult Alm
TF I 2t> Alarm
TF Recorder trig
IB magnitude
TF I > Trigger
&
IB2t
TF I 2t> Ala rm
IC magnitude
TF I > Trigger
&
IC2t
TF I 2t> Alarm
Any Diff Start
V03201
Figure 63: Through-fault alarm logic
4.3.1 TFM SETTING GUIDELINES

According to IEEE Std. C57.109-1993, values of 3.5 x normal base current may result from overloads rather than
faults. According to IEEE C57.91-1995, the suggested load limits depend on the type of transformer and are as
follows:
● For distribution transformers: Loads above the nameplate specification with 65°C rise is 300% of rated load
during short-time loading (0.5 hours or less).
For power transformers: Loads above the nameplate specification with 55°C rise is 200% of rated load.
To set TF I2t> Alarm you should consider the recommendations given in IEEE Std. C57.109-1993 for transformers
built from the early 1970s onwards. For transformers built before this time, always consult the transformer
manufacturer concerning the short circuit withstand capabilities.
Example
The through fault monitoring element can monitor either the HV, the LV or the TV winding. In three winding
applications, you should monitor the winding through which the highest current would flow during an external
fault. Fault studies are required to determine the maximum through fault current and which winding carries the
most current. For example, consider the following autotransformer:
P64x-TM-EN-4.1 157
175/175/30 MVA
230/115/13.8 kV
YNynd1
+5% / -15% TV
800:5 19 taps 2000:5
HV
a
A
b
B
c
C
Earthing
Protected zone transformer
c
LV
1200:5
B B

Correction Correction
B B
+ +
B B
Phase & amplitude

Correction
B
+
B
D D D
P645
V03116
Figure 64: P645 used to protect an autotransformer with loaded delta winding
Consider the case where an equivalent source and load are connected to the 230 kV terminal and an equivalent
source and load are connected to the 115 kV terminal, but only the load is connected to the 13.8 kV terminal. An
external fault on the 230 kV side would be fed by the source on the 115 kV side. Therefore, the current would
mainly flow from the 115 kV side to the 230 kV side. If the external fault occurs on the 115 kV side, the through-
fault current would flow from the 230 kV side to the 115 kV side. If an external fault occurs on the 13.8 kV side, the
through fault current would flow from the 230 kV and 115 kV sides to the 13.8 kV side. The source and transformer
impedances determine the fault current level.
Set the TF I> Trigger setting above the maximum overload. According to IEEE Std. C57.109-1993, values of 3.5 or
less times normal base current may result from overloads instead of faults. TF I> Trigger may be set to 3.85 pu. If
the monitored current is above this level and no differential element has started, then the I2t is calculated.
To set the TF I2t> Alarm consider the maximum through fault current and the maximum time duration. The
maximum through-fault current may be determined as 1/X, where X is the transformer impedance. This
approximation is valid when the source is strong, so that its impedance is small compared with the transformer
impedance. If the transformer has an impedance of 10%, the maximum through fault current is calculated as:
158 P64x-TM-EN-4.1
1/X = 1/0.1 = 10 pu
P64x-TM-EN-4.1 159
5 RTD PROTECTION
Prolonged overloading of transformers may cause their windings to overheat, resulting in premature aging of the
insulation, or in extreme cases, insulation failure. To protect against this, resistive temperature sensing devices
(RTDs) can be used to measure temperatures at various locations within a transformer. RTDs work by using the
resistance versus temperature characteristic of metals. When metal heats up, its resistance changes. This can be
used to feed back temperature information, which can be used by protection devices for temperature monitoring,
alarming, or making protection decisions.
Probes are usually placed in areas of the equipment that are susceptible to overheating or heat damage. This
could protect against winding Hotspot overheating or overtemperature in the insulating oil.
Direct temperature measurement can provide more reliable thermal protection than thermal model calculations.
Note:
Do Not select RTD options if RTD board is not fitted.
5.1 RTD PROTECTION IMPLEMENTATION

The P64x uses PT100 RTD probes to protect against any general or localized overheating. These can measure
temperatures between –40° and +300°C. At 0°C they have a resistance of 100 Ohms.
The device accepts inputs from up to ten 2-wire or 3-wire PT100 resistive temperature sensing devices (RTD). These
are connected as shown:
RTD 1 RTD 1
3-wire PT100 RTDs 2-wire PT100 RTDs
RTD 10 RTD 10
IED IED
V03202
Figure 65: Connection for RTD thermal probes
You can enable or disable each RTD using the Select RTD setting in the RTD PROTECTION column of the relevant
settings group. The setting contains a binary string of ten digits to represent the 10 RTDs in sequence from right to
left. For example if you set Select RTD to 0000000111, RTD1, RTD2 and RTD3 would be enabled and the associated
settings would be visible in the menu.
You set the temperature setting for the alarm stage for each RTD in the RTD Alarm Set cells and the alarm stage
time delay in the RTD Alarm Dly cells.
Likewise, you set the trip stage for each RTD in the RTD Trip Set cells and the trip stage time delay in the RTD Trip
Dly cells.
Should the measured resistance of an RTD be outside of the permitted range, an RTD failure alarm is raised,
indicating an open or short circuit RTD input. These conditions are signalled by the DDB signals RTD Open Cct, RTD
Short Cct and RTD Data Error. These DDB statuses are also shown in the MEASUREMENTS 3 column.
DDB signals are also available to indicate the alarm and trip of the each and any RTD. You can set the monitor bit
cells in the COMMISSION TESTS column to view the statuses of these signals.
160 P64x-TM-EN-4.1
5.2 RTD LOGIC

RTD Value
RTD Alarm Set & RTD 1 Alarm
RTD 1 Alarm
RTD Open Cct
RTD Short Cct

& Any RTD Alarm
RTD Data Error
RTD Board Fail RTD 10 A larm
RTD Value
RTD Trip Set & RTD 1 Trip
RTD 1 Trip
RTD Open Cct
RTD Short Cct

& Any RTD Trip
RTD Da ta Error
RTD Board Fail RTD 10 Trip
Note: This diagram does not show all stages. Other stages follow similar principles.
V03203
Figure 66: RTD logic
5.3.1 SETTING GUIDELINES FOR RTD PROTECTION

The following table shows typical operating temperatures for protected plant. These are for guidance only. You
must obtain the actual figures from the equipment manufacturers:
Parameter Typical service temperature Short term overloading at full load
60° - 80°C, depending on the type of
Bearing temperature generators 60 - 80°C+
bearing.
A temperature gradient from winding
Top oil temperature of
80°C (50 - 60°C above ambient). temperature is usually assumed, so that top oil
transformers
RTDs can provide winding protection
Winding hot spot temperature 98°C for normal aging of insulation. 140°C+ during emergencies
P64x-TM-EN-4.1 161
6 CLIO PROTECTION
To help with monitoring the condition of a power systems, various transducers such as vibration monitors,
tachometers, voltage, current and pressure transducers can be used to extract useful metrics from the system.
Such transducers work by converting the measured data into currents, which can then be fed into instrumentation
device such as meters or IEDs. This mechanism is called CLIO protection. CLIO stands for Current Loop Input
Output.
Transducers have current ranges associated with the full scale of what they are measuring. Typically these ranges
are 0-1 mA, 0-10 mA, 0-20 mA, or 4-20 mA.
Note:
Do Not select CLIO options if CLIO board is not fitted.
6.1 CURRENT LOOP INPUT IMPLEMENTATION

Four analog current loop inputs are provided for transducers with ranges of 0 – 1 mA, 0 – 10 mA, 0 – 20 mA, or 4 –
20 mA. Each input can be configured to accept any one of these ranges. Associated with each input are two
protection stages; one for alarming and the other for tripping. Each stage can be individually enabled or disabled
and each stage has a definite time delay setting.
Each current loop input may beset to alarm for an 'over' condition or an 'under' condition. You do this with the
setting CLI Alarm Fn and selecting under or over as appropriate. Likewise, each CL input may be also set to
trip for an 'over' condition or an 'under' condition. You do this with the setting CLI Trip Fn and selecting under or
over as appropriate. The sample interval is nominally 50 ms per input.
The relationship between the transducer measuring range and the current input range is linear. The maximum and
minimum settings correspond to the limits of the current input range. This relationship is shown below. The
diagram also shows the relationship between the measured current and the analog to digital conversion (ADC)
count. The hardware design allows for over-ranging, with the maximum ADC count corresponding to 1.0836 mA
for the 0 - 1 mA range, and 22.7556 mA for the 0 - 10 mA, 0 - 20 mA and 4 - 20 mA ranges. The device will
therefore continue to measure and display values beyond the Maximum setting, within its numbering capability.
162 P64x-TM-EN-4.1
Transducer Value Transducer Value

Maximum
Maximum
ADC ADC
Minimum Count Minimum Count
4095 4095
0 0
0 mA 1 mA Current I/P 0 mA 10 mA Current I/P
0 - 1 mA 0 - 10 mA
1.0836 mA 22.7556 mA
Transducer Value Transducer Value

Maximum Maximum
Minimum
ADC ADC
Minimum Count Count
4095 4095
0 0
0 mA 20 mA Current I/P 0 mA 4 mA 20 mA Current I/P
0 - 20 mA 4 - 20 mA 22.7556 mA
22.7556 mA
E03204
Figure 67: Current loop input ranges
Note:
If the Maximum is set less than the Minimum, the slopes of the graphs will be negative.
Power-on diagnostics and continuous self-checking of the current loop inputs are integrated into the hardware.
When a failure is detected, the protection associated with all the current loop inputs is disabled and a single alarm
DDB signal (CL Card I/P Fail) is set and an alarm is raised. A maintenance record with an error code is also
recorded with additional details about the type of failure.
For the 4 – 20 mA input range, a current level below 4 mA indicates that there is a fault with the transducer or the
wiring. An instantaneous undercurrent alarm element is available, with a setting range from 0 to 4 mA. This
element controls a DDB output signal for each CL input (CL(n)I< Fail Alm), where (n) is the number of the CL input.
You can then map this to a user defined alarm if required.
Hysteresis is implemented for each protection element. For ‘Over’ protection, the drop-off/pick-up ratio is 95%, for
‘Under’ protection, the ratio is 105%.
A timer block input is available for each current loop input stage. This will reset the CL input timers of the relevant
stage if energized. If a current loop input is blocked, the protection and alarm timer stages and the 4 – 20 mA
undercurrent alarm associated with that input are blocked. The blocking signals may be useful for blocking the
current loop inputs when the CB is open for example.
DDB signals are available for each current loop input to indicate the start of alarm and trip stages. These are CLI(n)
Alarm Start, and CLI(n) Trip Start, CLI(n) Alarm and CLI(n) Trip, where (n) is the number of the current loop input.
The Monitor Bit cells of the COMMISSIONTESTS column can be configured to show the state of the DDB signals.
P64x-TM-EN-4.1 163
The current loop input starts are mapped internally to the Any Start DDB signal.
6.2 CURRENT LOOP INPUT LOGIC

RTD Value
CLI1 Alarm S tart
RTD Alarm Set & CLI1 Alarm
CLI1 I< Fail A lm

4-20 mA input only
CLI Alarm Delay
CL Card I/P Fail
RTD Value
CLI1 Trip Start
RTD Trip Set & CLI1 Trip
CLI1 I< Fail A lm

4-20 mA input only
CLI Alarm Delay
CL Card I/P Fail
V3205 Note: This diagram does not show all stages. Other stages follow similar principles.
Figure 68: Current Loop Input logic
6.3 CLO IMPLEMENTATION

Four analog current outputs are provided with ranges of 0 - 1 mA, 0 - 10 mA, 0 - 20 mA or 4 - 20 mA, which can
alleviate the need for separate transducers. These may be used to feed moving coil ammeters for measuring
analog quantities, or to feed into a SCADA using an existing analog remote terminal unit (RTU).
The current loop output conversion task runs every 50 ms and the refresh interval for the output measurements is
nominally 50 ms.
You can set the measuring range for each analog output. The range limits are defined by the CLO Minimum and
CLO Maximum settings in the CLIO PROTECTION column for each CL output. This allows you to zoom in and
monitor a restricted range of the measurements with the desired resolution. You can set the voltage and current
quantities to either primary or secondary quantities with the CLO Set Values setting.
The output current of each analog output is linearly scaled to its range limits by the Maximum and Minimum
settings, as shown below:
164 P64x-TM-EN-4.1
Current Output Current Output
1 mA 10 mA
Relay Relay
Measurement Measurement
0 mA 0 mA
Minimum Maximum Minimum Maximum
0 - 1 mA 0 - 10 mA
Minimum
Current Output Current Output
20 mA 20 mA
4 mA
Relay Relay
Measurement 0 mA Measurement
0 mA
Minimum Maximum Minimum Maximum
0 - 20 mA 4 - 20 mA
E03206
Figure 69: Current Loop Output ranges
Note:
If the Maximum is set less than the Minimum, the slopes of the graphs will be negative.
The transducers inside the device are of the current output type. This means that the correct value of output is
always maintained over the load range specified. The range of load resistance varies a great deal, depending on
the design and the value of output current. Transducers with a full-scale output of 10 mA will normally feed any
load up to a value of 1000 ohms (compliance voltage 10V). This equates to an approximate cable length of 15 km.
We recommend using a screened cable, earthed at one end. This helps reduce interference on the output current
signal. The table below shows typical cable impedances per kilometer for common cables. The compliance voltage
dictates the maximum load that a transducer output can feed. Therefore, the 20 mA output will be restricted to a
maximum load of 500 ohms.
Cable 1/0.6 mm 1/0.85 mm 1/1.38 mm
CSA (mm2) 0.28 0.57 1.50
R (ohms/km) 65.52 32.65 12.38
You can connect the receiving equipment at any point in the output loop and install additional equipment later.
You do not need to adjust the transducer output, providing the compliance voltage is not exceeded.
Where you use the output current range for control purposes, you may wish to fit appropriately rated diodes, or
Zener diodes, across the terminals of each of the units in the series loop. This will guard against the possibility of
their internal circuitry becoming open circuit. In this way, a faulty unit in the loop does not cause all the indications
P64x-TM-EN-4.1 165
to disappear, because the constant current nature of the transducer output simply raises the voltage and
continues to force the correct output signal around the loop.
The device provides power-on diagnostics and continuous self-checking of the current loop hardware. If a failure is
detected, all the current loop output functions are disabled and an alarm signal (CL Card O/P Fail) is raised. A
maintenance record (with an error code) is also produced, which provides additional details about the type of
failure.
6.4.1 CLI SETTING GUIDELINES

For each analog input, you can define the following:
● The current input range: 0 – 1 mA, 0 – 10 mA, 0 – 20 mA, 4 – 20 mA
● The analog input function (in the form of a 16-character input label)
● Analog input minimum value
● Analog input maximum value
● Alarm threshold, range within the maximum and minimum set values
● Alarm function (under or over)
● Alarm delay
● Trip threshold, range within maximum and minimum set values
● Trip function (under or over)
● Trip delay
The Maximum and Minimum settings allow you to enter the range of physical or electrical quantities measured by
the transducer. These are without units, however, you can enter the transducer function and the unit of the
measurement using the 16-character user-defined CL Input Label. For example, if using an input to monitor a
power measuring transducer, the text could be “Active Power (MW)”.
You need to set the alarm and trip thresholds within the range of physical or electrical quantities. The device will
convert the current input value into its corresponding transducer measuring value for the protection calculation.
For example if the CL input minimum is -1000 and the CL input maximum is 1000 for a 0 to 10 mA input, an input
current of 10 mA is equivalent to a measurement value of 1000, 5 mA is 0, and 0 mA is -1000.
These values are available for display in the CLIO Input (n) cells in the MEASUREMENTS 3 menu. The top line shows
the CL Input Label and the bottom line shows the measurement value.
6.4.2 CLO SETTING GUIDELINES

The outputs can be assigned to any of the following relay measurements:
● Magnitudes of IA, IB, IC of every CT input
● Magnitudes of IA, IB, IC at HV, LV and TV sides of the transformer
● Magnitudes of IN Measured and IN Derived of every winding
● Magnitudes of I1, I2, I0 at HV, LV and TV sides of the transformer
● Magnitudes of VAB, VBC, VCA, VAN, VBN, VCN, VN Measured, VN Derived
● Magnitude of Vx
● VAN RMS, VBN RMS, VCN RMS
● Frequency
● CL Inputs 1-4
● RTD 1-10
166 P64x-TM-EN-4.1
The relationship of the output current to the value of the measured values is of vital importance and needs careful
consideration. Any receiving equipment must be used within its rating but, if possible, you should apply some kind
of standard.
One of the objectives is to monitor the voltage over a range of values, so you need an upper limit, for example
120%. However, this may lead to difficulties when it comes to scaling an instrument.
The same considerations apply to current transducer outputs and with added complexity to power transducers
outputs, where both the voltage and current transformer ratios must be taken into account.
Some of these difficulties do not need to be considered if the transducer is only feeding, for example, a SCADA
outstation. Any equipment, which can be programmed to apply a scaling factor to individual inputs can
accommodate most signals. The main consideration is to ensure that the transducer is capable of providing a
signal right up to the full-scale value of the input.
P64x-TM-EN-4.1 167
168 P64x-TM-EN-4.1
CHAPTER 8
RESTRICTED EARTH FAULT PROTECTION

Chapter 8 - Restricted Earth Fault Protection P64x
170 P64x-TM-EN-4.1
P64x Chapter 8 - Restricted Earth Fault Protection
1 CHAPTER OVERVIEW
The device provides extensive Restricted Earth Fault functionality. This chapter describes the operation of this
function including the principles of operation, logic diagrams and applications.
REF Protection Principles 172
Restricted Earth Fault Protection Implementation 178
Second Harmonic Blocking 183
P64x-TM-EN-4.1 171
2 REF PROTECTION PRINCIPLES

Winding-to-core faults in a transformer can be caused by insulation breakdown. Such faults can have very low
fault currents, but they still need to be picked up. If such faults are not identified, this could result in extreme
damage to very expensive equipment.
Often the associated fault currents are lower than the nominal load current. Neither overcurrent nor percentage
differential protection is sufficiently sensitive in this case. We therefore require a different type of protection
arrangement. Not only should the protection arrangement be sensitive, but it must create a protection zone, which
is limited to each transformer winding. Restricted Earth Fault protection (REF) is the protection mechanism used to
protect individual transformer winding sets.
The following figure shows a REF protection arrangement for protecting the delta side of a delta-star transformer.
Load
REF
IED protection zone
V00620
Figure 70: REF protection for delta side
The current transformers measuring the currents in each phase are connected in parallel. The currents from all
three phases are summed to form a differential current, sometimes known as a spill current. Under normal
operating conditions the currents of the three phases add up to zero resulting in zero spill current. A fault on the
star side will also not result in a spill current, as the fault current would simply circulate in the delta windings.
However, if any of the three delta windings were to develop a fault, the impedance of the faulty winding would
change and that would result in a mismatch between the phase currents, resulting in a spill current. If the spill
current is large enough, it will trigger a trip command.
The following figure shows a REF protection arrangement for the star side of a delta-star transformer.
REF
protection zone
Load
IED
V00621
Figure 71: REF protection for star side
Here we have a similar arrangement of current transformers connected in parallel. The difference is that we need
to measure the zero sequence current in the neutral line as well. An external unbalanced fault causes zero
sequence current to flow through the neutral line, resulting in uneven currents in the phases, which could cause
172 P64x-TM-EN-4.1
the protection to maloperate. By measuring this zero sequence current and placing it in parallel with the other
three, the currents are balanced, resulting in stable operation. Now only a fault inside the star winding can create
an imbalance sufficient to cause a trip.
2.1 RESISTANCE-EARTHED STAR WINDINGS

Most distribution systems use resistance-earthed systems to limit the fault current. Consider the diagram below,
which depicts an earth fault on the star winding of a resistance-earthed Dyn transformer (Dyn = Delta-Star with
star-point neutral connection).
87
1.0
IF IF
Source
IS Current p.u.
(x full load)
Pickup
IS
0.2
IF
64
20% 100%
Winding not protected
Fault position from neutral

V00669 (Impedance earthing)
Figure 72: REF Protection for resistance-earthed systems
The value of fault current (IF) depends on two factors:

● The value of earthing resistance (which makes the fault path impedance negligible)
● The fault point voltage (which is governed by the fault location).
Because the fault current (IF) is governed by the resistance, its value is directly proportional to the location of the
fault.
A restricted earth fault element is connected to measure IF directly. This provides very sensitive earth fault
protection. The overall differential protection is less sensitive, since it only measures the HV current IS. The value of
IS is limited by the number of faulty secondary turns in relation to the HV turns.
2.2 SOLIDLY-EARTHED STAR WINDINGS

Most transmission systems use solidly-earthed systems. Consider the diagram below, which depicts an earth fault
on the star winding of a solidly-earthed Dyn transformer.
87
10
IF 8 IF
Source Current p.u.
IS (x full load) 6
2 IS
IF
64 20% 40% 60% 80% 100%
Fault position from neutral

V00670 (Solid earthing)
Figure 73: REF Protection for solidly earthed system
P64x-TM-EN-4.1 173
In this case, the fault current IF is dependent on:

● The leakage reactance of the winding
● The impedance in the fault path
● The fault point voltage (which is governed by the fault location)
In this case, the value of fault current (IF) varies with the fault location in a complex manner.
A restricted earth fault element is connected to measure IF directly. This provides very sensitive earth fault
protection.
For solidly earthed systems, the operating current for the transformer differential protection is still significant for
faults over most of the winding. For this reason, independent REF protection may not have been previously
considered, especially where an additional device would have been needed. But with this product, it can be
applied without extra cost.
2.3 THROUGH FAULT STABILITY

In an ideal world, the CTs either side of a differentially protected system would be identical with identical
characteristics to avoid creating a differential current. However, in reality CTs can never be identical, therefore a
certain amount of differential current is inevitable. As the through-fault current in the primary increases, the
discrepancies introduced by imperfectly matched CTs is magnified, causing the differential current to build up.
Eventually, the value of the differential current reaches the pickup current threshold, causing the protection
element to trip. In such cases, the differential scheme is said to have lost stability. To specify a differential scheme’s
ability to restrain from tripping on external faults, we define a parameter called ‘through-fault stability limit’, which
is the maximum through-fault current a system can handle without losing stability.
2.4 RESTRICTED EARTH FAULT TYPES

There are two different types of Restricted Earth Fault; Low Impedance REF (also known as Biased REF) and High
Impedance REF. Each method compensates for the effect of through-fault errors in a different manner.
With Low Impedance REF, the through-fault current is measured and this is used to alter the sensitivity of the REF
element accordingly by applying a bias characteristic. So the higher the through fault current, the higher the
differential current must be for the device to issue a trip signal, Often a transient bias component is added to
improve stability during external faults.
Low impedance protection used to be considered less secure than high impedance protection. This is no longer
true as numerical IEDs apply sophisticated algorithms to match the performance of high-impedance schemes.
Some advantages of using Low Impedance REF are listed below:
● There is no need for dedicated CTs. As a result CT cost is substantially reduced.
● The wiring is simpler as it does not require an external resistor or Metrosil.
● Common phase current inputs can be used.
● It provides internal CT ratio mismatch compensation. It can match CT ratios up to 1:40 resulting flexibility in
substation design and reduced cost.
● Advanced algorithms make the protection secure.
With High Impedance REF, there is no bias characteristic, and the trip threshold is set to a constant level. However,
the High Impedance differential technique ensures that the impedance of the circuit is sufficiently high such that
the differential voltage under external fault conditions is lower than the voltage needed to drive differential current
through the device. This ensures stability against external fault conditions so the device will operate only for faults
occurring inside the protected zone.
High Impedance REF protection responds to a voltage across the differential junction points. During external faults,
even with severe saturation of some of the CTs, the voltage does not rise above certain level, because the other
174 P64x-TM-EN-4.1
CTs will provide a lower-impedance path compared with the device input impedance. The principle has been used
for more than half a century. Some advantages of using High Impedance REF are listed below:
● It provides a simple proven algorithm, which is fast, robust and secure.
● It is less sensitive to CT saturation.
2.4.1 LOW IMPEDANCE REF PRINCIPLE

Low Impedance REF can be used for either delta windings or star windings in both solidly grounded and resistance
grounded systems. The connection to a modern IED is as follows:
Phase A
Phase A
Phase B
Phase B
Phase C
Phase C
I Phase A
I Phase A
I Phase B
I Phase B
I Phase C
I Phase C
I Neutral
IED IED
Connecting IED to star winding for Low Connecting IED to delta winding for Low
Impedance REF Impedance REF
V00679
Figure 74: Low Impedance REF Connection
2.4.1.1 LOW IMPEDANCE BIAS CHARACTERISTIC

Usually, a triple slope biased characteristic is used as follows:
Differential current
Higher
slope
Operate region
Lower slope
Restraint region
Minimum operating current
Bias current
First knee point Second knee point
V00677
Figure 75: Three-slope REF bias characteristic
The flat area of the characteristic is the minimum differential current required to cause a trip (operate current) at
low bias currents. From the first kneepoint onwards, the operate current increases linearly with bias current, as
shown by the lower slope on the characteristic. This lower slope provides sensitivity for internal faults. From the
P64x-TM-EN-4.1 175
second knee point onwards, the operate current further increases linearly with bias current, but at a higher rate.
The second slope provides stability under through fault conditions.
Note:
In Restricted Earth Fault applications, Bias Current Compensation is also known as Low Impedance REF.
2.4.2 HIGH IMPEDANCE REF PRINCIPLE

This scheme is very sensitive and can protect against low levels of fault current, typical of winding faults.
High Impedance REF protection is based on the differential principle. It works on the circulating current principle as
shown in the following diagram.
Healthy CT Saturated CT
Protected
circuit
A-G
Zm1 Zm2
I = Is + IF
RCT1 RCT2
I IF
RL1 IS RL3
Vs RST
R
RL2 RL4
V00671
Figure 76: High Impedance REF principle
When subjected to heavy through faults the line current transformer may enter saturation unevenly, resulting in
imbalance. To ensure stability under these conditions a series connected external resistor is required, so that most
of the unbalanced current will flow through the saturated CT. As a result, the current flowing through the device
will be less than the setting, therefore maintaining stability during external faults.
Voltage across REF element Vs = IF (RCT2 + RL3 + RL4)
Stabilising resistor RST = Vs/Is –RR
where:
● IF = maximum secondary through fault current
● RR = device burden
● RCT = CT secondary winding resistance
● RL2 and RL3 = Resistances of leads from the device to the current transformer
● RST = Stabilising resistor
High Impedance REF can be used for either delta windings or star windings in both solidly grounded and
resistance grounded systems. The connection to a modern IED are as follows:
176 P64x-TM-EN-4.1
Phase A
Phase A
Phase B
Phase B
Phase C
Phase C
I Phase A
I Phase B
I Phase C
RSTAB I Neutral
I Neutral RSTAB
IED IED
Connecting IED to star winding for High Connecting IED to delta winding for High
Impedance REF Impedance REF
V00680
Figure 77: High Impedance REF Connection
P64x-TM-EN-4.1 177
3 RESTRICTED EARTH FAULT PROTECTION IMPLEMENTATION
3.1 ENABLING REF PROTECTION

A REF element is available for each of the windings (HV, LV, and if applicable, TV) as well as one for
Autotransformers. For each of these windings you can disable REF protection or set it to Low Impedance or
High Impedance using the settings REF HV Status, REF LV Status, REF TV Status and REF Auto Status in the
REF PROTECTION column.
Low impedance REF is blocked if:
● Current Transformer Supervision operates
● Stub Bus protection is activated (on a per-winding basis)
High impedance REF is not blocked by Current Transformer Supervision or Stub Bus Protection.

00001
00011
001
011
01011
01111
10000
11000
100
110
11010
11110
00100
01100
TV CT Terminals 010
00110
01110
178 P64x-TM-EN-4.1
Winding associations for the P643

You can select the REF element Phase side CT Input for each of the elements:
● For HV CT terminals, select from either HV Winding (Vector sum of multiple CT Input) or T2 input
● For LV CT Terminals, select from either LV Winding (Vector sum of multiple CT Input) or T2 input

You can select the REF element Phase side CT Input for each of the elements:
● For HV CT terminals, select from either HV Winding (Vector sum of multiple CT Input), T2, T3 and T4 inputs
● For LV CT Terminals, select from either LV Winding (Vector sum of multiple CT Input) T2, T3 and T4 inputs
● For TV CT Terminals, select from either TV Winding (Vector sum of multiple CT Input), T2 and T4 Inputs
3.3 LOW IMPEDANCE REF
3.3.1 SETTING THE BIAS CHARACTERISTIC

Low impedance REF uses a bias charactersitic for increasing sensitivity and stabilising for through faults. The
current required to trip the differential IED is called the Operate current. This Operate current is a function of the
differential current and the bias current according to the bias characteristic.
The differential current is defined as follows:
I diff = I A + I B + I C + K I N
( )
The bias current is as follows:
1
I bias =
2
{
max  I A , I B , I C  + K I N }
where:
● K = Neutral CT ratio / Line CT ratio
● IN = current measured by the neutral CT
The allowable range for K is:

0.05 < K < 15 for standard CTs
0.05 < K < 20 for sensitive CTs
The operate current is calculated according to the following characteristic:
P64x-TM-EN-4.1 179
I DIFF
Operate K2
Restrain
I S1 K1
I S2 I BIAS
E04021
Figure 78: REF bias characteristic
The following settings are provided to define this bias characteristic:

● IREF> Is1: sets the minimum trip threshold
● IREF> Is2: sets the bias current kneepoint whereby the required trip current starts increasing
● IREF> k1: defines the first slope (often set to 0%)
● IREF> k2: defines the second slope
Note:
Is1 and Is2 are relative to the line CT, which is always the reference CT.
3.3.2 DELAYED BIAS

To provide further stability when external faults are being cleared, the protection checks for the highest value of
bias current calculated during the previous cycle. If that value is higher than the present value, it is used to restrain
the tripping decision. This is referred to as the Residual Bias. The Residual Bias technique maintains through fault
stability for clearance of external faults.
3.3.3 TRANSIENT BIAS

If there is a sudden increase in the mean-bias measurement, an additional bias quantity is introduced in the bias
calculation. Transient Bias provides stability for external faults where CT saturation might occur.
The transient bias function enhances the stability of the differential element during external faults and allows for
the time delay in CT saturation caused by small external fault currents and high X/R ratios.
180 P64x-TM-EN-4.1
No transient bias is produced under load switching conditions, or when the CT comes out of saturation.
3.3.4 RESTRICTED EARTH FAULT LOGIC
REF HV Start
Id iff HV I diff
DT
Is1
& REF Trip HV
Ibias HV Is2 I bias
Blk REF HV
CTS HV 1
HV-LZREF sf OOR
REF IH2 Start HV

IH2 REF Block HV & Note: Same principle applies for LV and TV windings
Enabled
V00708
Figure 79: Low impedance restricted Earth Fault logic
3.4 HIGH IMPEDANCE REF

A high impedance restricted earth fault protection function is available for up to three windings. An external
resistor is required to provide stability in the presence of saturated line current transformers.
TN1 CT is associated with the HV winding high impedance REF, or with the autotransformer high impedance REF.
TN2 CT is associated with the LV winding high impedance REF and TN3 CT is associated with the TV winding high
impedance REF.
Current transformer supervision, HV StubBus Act, LV StubBus Act or TV StubBus Act signals do not block the high
impedance REF protection. You must configure logic in the PSL to block the high impedance REF when any of the
above signals are asserted.
3.4.1 HIGH IMPEDANCE REF CALCULATION PRINCIPLES

The primary operating current (Iop) is a function of the current transformer ratio, the device operate current
(IREF>Is), the number of current transformers in parallel with a REF element (n) and the magnetizing current of
each current transformer (Ie) at the stability voltage (Vs). This relationship can be expressed in three ways:
1. The maximum current transformer magnetizing current to achieve a specific primary operating current with
a particular operating current:
1  I op 
Ie <  − [ IREF > Is ] 
n  CT ratio 
2. The maximum current setting to achieve a specific primary operating current with a given current
transformer magnetizing current:
 I op 
[ IREF > Is ] <  − nI e 
 CT ratio 
3. The protection primary operating current for a particular operating current with a particular level of
magnetizing current:
I op = ( CT ratio ) ([ IREF > Is ] + nI e )
P64x-TM-EN-4.1 181
To achieve the required primary operating current with the current transformers that are used, you must select a
current setting for the high impedance element, as shown in item 2 above. You can calculate the value of the
stabilising resistor (RST) in the following manner.
Vs I ( R + 2 RL )
Rst = = F CT
[ IREF > Is ] [ IREF > Is ]
where:
● RCT = the resistance of the CT winding
● RL = the resistance of the lead from the CT to the IED.
Note:
The above formula assumes negligible relay burden.
We recommend a stabilizing resistor, which is continuously adjustable up to its maximum declared resistance.
182 P64x-TM-EN-4.1
4 SECOND HARMONIC BLOCKING
4.1 REF 2ND HARMONIC BLOCKING LOGIC
Idiff f undamental HV
Is-HS1 &
& REF I H2 S tart HV
Idiff 2nd harm / Idiff

fund
Idiff 2nd harmonic HV
IH2 REF S et HV Note: S ame principle ap plies for LV and TV wind ings
V00705
Figure 80: REF 2nd harmonic blocking logic
P64x-TM-EN-4.1 183
5 APPLICATION NOTES
5.1 STAR WINDING RESISTANCE EARTHED

Consider the following resistance earthed star winding below.
Primary Secondary
A a
V2 V1
B b
c
C
V00681
Figure 81: Star winding, resistance earthed
An earth fault on such a winding causes a current which is dependent on the value of earthing impedance. This
earth fault current is proportional to the distance of the fault from the neutral point since the fault voltage is
directly proportional to this distance.
The ratio of transformation between the primary winding and the short circuited turns also varies with the position
of the fault. Therefore the current that flows through the transformer terminals is proportional to the square of the
fraction of the winding which is short circuited.
The earthing resistor is rated to pass the full load current IFLC = V1/Ö3R
Assuming that V1 = V2 then T2 = Ö3T1
For a fault at x PU distance from the neutral, the fault current If = xV1/Ö3R
Therefore the secondary fault current referred to the primary is Iprimary = x2.IFLC/Ö3
If the fault is a single end fed fault, the primary current should be greater than 0.2 pu (Is1 default setting) for the
differential protection to operate. Therefore x2/Ö3 > 20%
The following diagram shows that 41% of the winding is protected by the differential element.
184 P64x-TM-EN-4.1
X in % Idiff in %
10 0.58
20 2.31
30 5.20
59% of unprotected winding
40 9.24
50 14.43
60 20.00
70 28.29
80 36.95 41% of protected winding
90 46.77
100 57.74
V00682
Figure 82: Percentage of winding protected
5.2 LOW IMPEDANCE REF PROTECTION APPLICATION
5.2.1 SETTING GUIDELINES FOR BIASED OPERATION

Two bias settings are provided in the REF characteristic. The K1 level of bias is applied up to through currents of
Is2, which is normally set to the rated current of the transformer. K1 is normally be set to 0% to give optimum
sensitivity for internal faults. However, if any CT mismatch is present under normal conditions, then K1 may be
increased accordingly, to compensate. We recommend a setting of 20% in this case.
K2 bias is applied for through currents above Is2 and would typically be set to 150%.
According to ESI 48-3 1977, typical settings for the Is1 thresholds are 10-60% of the winding rated current when
solidly earthed and 10-25% of the minimum earth fault current for a fault at the transformer terminals when
resistance earthed.
5.2.2 LOW IMPEDANCE REF SCALING FACTOR

The three line CTs are connected to the three-phase CTs, and the neutral CT is connected to the neutral CT input.
These currents are then used internally to derive both a bias and a differential current quantity for use by the low
impedance REF protection. The advantage of this mode of connection is that the line and neutral CTs are not
differentially connected, so the neutral CT can also be used to provide the measurement for the Standby Earth
Fault Protection. Also, no external components such as stabilizing resistors or Metrosils are required.
Line CTs 1000:1
Phase A
Phase B
Phase C
I Phase A
I Phase B
I Phase C
Neutral CT 200:1
I Neutral
IN IED
V00683
Figure 83: Low Impedance REF Scaling Factor
P64x-TM-EN-4.1 185
Another advantage of Low Impedance REF protection is that you can use a neutral CT with a lower ratio than the
line CTs in order to provide better earth fault sensitivity. In the bias calculation, the device applies a scaling factor
to the neutral current. This scaling factor is as follows:
Scaling factor = K = Neutral CT ratio / Line CT ratio
This results in the following differential and bias current equations:
I diff = I A + I B + I C + K I N
( )
1
I bias =
2
{
max  I A , I B , I C  + K I N }
5.2.3 PARAMETER CALCULATIONS
Consider a solidly earthed 90 MVA 132 kV transformer with a REF-protected star winding. Assume line CTS with a
ratio of 400:1.
Is1 is set to 10% of the winding nominal current:
= (0.1 x 90 x 106) / (Ö3 x 132 x 103)

= 39 Amps primary
= 39/400 = 0.0975 Amps secondary (approx 0.1 A)
Is2 is set to the rated current of the transformer:
= 90 x 106 / (Ö3 x 132 x 103)

= 390 Amps primary
= 390/400 = 0.975 Amps secondary (approx 1 A)
Set K1 to 0% and K2 to 150%
5.2.4 DUAL CB APPLICATION WITH DIFFERENT PHASE CT RATIOS

The following diagram shows the situation where low impedance REF is being used in a dual breaker (breaker-and-
a-half) application where the phase CT ratios (CTx and CTy) are different. In this example, one phase of a
conventional transformer is shown, but the explanation is also applicable to autotransformers.
CTy
CTx
Neutral CT N
V00754
Figure 84: Low-Z REF for dual CB application with different phase CT ratios
The low impedance REF function can be used in dual breaker (breaker-and-a-half) applications. The line CT ratios
can be different. In this case the low impedance REF differential and bias current formulae are calculated as
follows:
186 P64x-TM-EN-4.1
( )
I diff ( REF ) =  IACTx + IB CTx + IC CTx + K1 IACTy + K1 IB CTy + K1 IC CTy + K 2 IN 
 
1
I bias ( REF ) =
2 { ( )( )(
max  IACTx + K1 IACTy , IB CTx + K1 IB CTy , IC CTx + K1 IC CTy  + K 2 IN
  ) }
where:
● CTx and CTy (T1, T2, T3, T4 or T5) are the current inputs associated with a particular winding (given in the
settings HV CT Terminals, LV CT Terminals and TV CT Terminals respectively)
● K1 = CTy Ratio/CTx Ratio (Scaling Factor K1)
● K2 = Neutral CT Ratio/CTx Ratio (Scaling Factor K2)
● Reference: CTx, which is the same as T1-CT
Note:
The above formulae are valid for autotransformers and conventional transformers when the Phase CT Ratios are different
(CTx ≠ CTy) and the reference is CTx
5.2.5 DUAL CB APPLICATION WITH SAME PHASE CT RATIOS

The following diagram shows the situation where low impedance REF is being used in a dual breaker (breaker-and-
a-half) application where the phase CT ratios are identical. In this example, one phase of an autotransformer is
shown, but the explanation is also applicable to conventional transformers.
T1 CT T2 CT
Low
Impedance
REF
TN1 CT
T3 CT T4 CT T5 CT
V00707
Figure 85: Low-Z REF for dual CB application with same phase CT ratios
The low impedance REF function can be used in dual breaker (breaker-and-a-half) applications. The line CT ratios
may be identical. In this case the Restricted Earth Fault (REF) Low Impedance (Z) Differential and Bias current
formulae are calculated as follows:
P64x-TM-EN-4.1 187
n
I diff ( REF ) = ∑ ( IA
n =1
TxCT
 )
+ IBTxCT + IC TxCT  + K n I TN1 CT
  n  
  ∑ IATxCT  
  n =1  
1  n  
I bias ( REF ) = max  ∑ IB TxCT  + K n I TN1 CT 
2  n =1  
  n  
  ∑ IC TxCT  
  n =1  
where:
● Tx CT = T1, T2, T3, T4 or T5.
● Kn = TN1 CT Ratio/ Tx CT Ratio
● TN1 CT Ratio = Neutral CT Ratio.
● Reference: Tx CT.
5.2.6 CT REQUIREMENTS - LOW IMPEDANCE REF

We strongly recommend Class X or Class 5P current transformers for this application.
The CT requirements for low impedance REF protection are generally lower than those for differential protection.
As the line CTs for low impedance REF protection are the same as those used for differential protection the
differential CT requirements cover both differential and low impedance REF applications.
The current transformer knee-point voltage requirements are based on the following default settings for
transformer REF protection; IS1 = 27 A (primary value at 300/1 CT Ratio), IS2 = 270 A (primary value at 300/1 CT
ratio), K1 = 0%, K2 = 150%.
The K dimensioning factor for the REF function is smaller than that for the transformer differential protection. Since
the highest K factor must be considered, the CT requirements for transformer differential must be considered.
5.2.6.1 CT REQUIREMENTS - ONE BREAKER APPLICATION

To achieve through-fault stability, the K dimensioning factor must comply with the following:
2In < IF £ 64In
12 VK ³ 12In(RCT + 2RL + Rr)
5 £ X/R £ 120
where:
188 P64x-TM-EN-4.1
5.2.6.2 CT REQUIREMENTS - ONE-AND-A-HALF BREAKER APPLICATION

According to the test results, to achieve through-fault stability, the K dimensioning factor must comply with the
following:
2In < IF £ 64In
27 VK ³ 27In(RCT + 2RL + Rr)
5 £ X/R £ 20
where:
5.3 HIGH IMPEDANCE REF PROTECTION APPLICATION
5.3.1 HIGH IMPEDANCE REF OPERATING MODES

In the examples below, the respective Line CTS and measurement CTs must have the same CT ratios and similar
magnetising characteristics.
CT1
A a
B b
c
C
TN1 CT
TN2 CT
TN3 CT
CTN Rst
Varistor
V00684
Figure 86: Hi-Z REF protection for a grounded star winding
P64x-TM-EN-4.1 189
CT1
A
a
B
b
C c
TN 1 CT
TN 2 CT
Varistor TN 3 CT
Rst
V00685
Figure 87: Hi-Z REF protection for a delta winding
CT2
a
CT1
A
b
CTN
B
c
TN1 CT
Varistor
Rst
V00686
Figure 88: Hi-Z REF Protection for autotransformer configuration
5.3.2 SETTING GUIDELINES FOR HIGH IMPEDANCE OPERATION

This scheme is very sensitive and can protect against low levels of fault current in resistance grounded systems. In
this application, the IREF>Is settings should be chosen to provide a primary operating current less than 10-25% of
the minimum earth fault level.
This scheme can also be used in a solidly grounded system. In this application, the IREF>Is settings should be
chosen to provide a primary operating current between 10% and 60 % of the winding rated current.
The following diagram shows the application of a high impedance REF element to protect the LV winding of a
power transformer.
190 P64x-TM-EN-4.1
A 400:1
a
RCT
B b
RL
c
C
RL
RL
Transformer: High Z
RCT
90 MVA REF
33/132 kV
Dyn11, X = 5% RL
Buderns:
RCT = 0.5 W
RL = 0.98 W
V00687
Figure 89: High Impedance REF for the LV winding
5.3.2.1 STABILITY VOLTAGE CALCULATION

The transformer full load current, IFLC, is:
IFLC = (90 x 106) / (132 x 103 x Ö3) = 394 A

To calculate the stability voltage the maximum through fault level should be considered. The maximum through
fault level, ignoring the source impedance, IF, is:
IF = IFLC / XTX = 394 / 0.05 = 7873 A

The required stability voltage, VS, and assuming one CT saturated is:
Vs = KIF(RCT + 2RL)
The following figure can be used to determine the K factor and the operating time. The K factor is valid when:
● 5 ≤ X/R ≤ 120
and
● 0.5In ≤ I f ≤ 40In
We recommend a value of VK/VS = 4.
With the transformer at full load current and percentage impedance voltage of 394A and 5% respectively, the
prospective fault current is 7873 A and the required stability voltage Vs (assuming that one CT is saturated) is:
Vs = 0.9 x 7873 x (0.5 + 2 x 0.98) / 400 = 45.5 V
The CTs knee point voltage should be at least 4 times Vs so that an average operating time of 40 ms is achieved.
5.3.2.2 PRIMARY CURRENT CALCULATION

The primary operating current should be between 10 and 60 % of the winding rated current. Assuming that the
relay effective setting or primary operating current is approximately 30% of the full load current, the calculation
below shows that a setting of less than 0.3 A is required.
Effective setting = 0.3IFLC / CT Ratio = 30.3 x 394 / 400 = approximately 0.3 A
P64x-TM-EN-4.1 191
5.3.2.3 STABILISING RESISTOR CALCULATION

Assuming that a setting of 0.1A is selected the value of the stabilizing resistor, RST, required is
RST = Vs / (IREF> Is1 (HV)) = 45.5 / 0.1 = 455 ohms

To achieve an average operating time of 40 ms, Vk/Vs should be 3.5.
The Kneepoint voltage is:
VK = 4Vs = 4 x 45.5 = 182 V.
If the actual VK is greater than 4 times Vs, then the K factor increases. In this case, Vs should be recalculated.
Note:
K can reach a maximum value of approximately 1.
5.3.2.4 CURRENT TRANSFORMER CALCULATION

The effective primary operating current setting is:
IP = N(Is + nIe)
By re-arranging this equation, you can calculate the excitation current for each of the current transformers at the
stability voltage. This turns out to be:
Ie = (0.3 - 0.1) / 4 = 0.05 A
In summary, the current transformers used for this application must have a kneepoint voltage of 182 V or higher
(note that maximum Vk/Vs that may be considered is 16 and the maximum K factor is 1), with a secondary winding
resistance of 0.5 ohms or lower and a magnetizing current at 45.5 V of less than 0.05 A.
Assuming a CT kneepoint voltage of 200 V, the peak voltage can be estimated as:
VP = 2Ö2VK(VF-VK) = 2Ö2(200)(9004-200) = 3753 V
This value is above the peak voltage of 3000 V and therefore a non-linear resistor is required.
Note:
The kneepoint voltage value used in the above formula should be the actual voltage obtained from the CT magnetizing
characteristic and not a calculated value.
Note:
One stabilizing resistor, Alstom part No. ZB9016 756, and one varistor, Alstom part No. 600A/S1/S256 might be used.
5.3.3 USE OF METROSIL NON-LINEAR RESISTORS

Current transformers can develop high peak voltages under internal fault conditions. Metrosils are used to limit
these peak voltages to a value below the maximum withstand voltage (usually 3 kV).
You can use the following formulae to estimate the peak transient voltage that could be produced for an internal
fault. The peak voltage produced during an internal fault is a function of the current transformer kneepoint voltage
and the prospective voltage that would be produced for an internal fault if current transformer saturation did not
occur.
Vp = 2Ö(2VK(VF-VK))
Vf = I'f(RCT+2RL+RST)
192 P64x-TM-EN-4.1
where:
● Vp = Peak voltage developed by the CT under internal fault conditions
● Vk = Current transformer kneepoint voltage
● Vf = Maximum voltage that would be produced if CT saturation did not occur
● I'f = Maximum internal secondary fault current
● RCT = Current transformer secondary winding resistance
● RL = Maximum lead burden from current transformer to relay
● RST = Relay stabilising resistor
You should always use Metrosils when the calculated values are greater than 3000 V. Metrosils are connected
across the circuit to shunt the secondary current output of the current transformer from the device to prevent very
high secondary voltages.
Metrosils are externally mounted and take the form of annular discs. Their operating characteristics follow the
expression:
V = CI0.25
where:
● V = Instantaneous voltage applied to the Metrosil
● C = Constant of the Metrosil
● I = Instantaneous current through the Metrosil
With a sinusoidal voltage applied across the Metrosil, the RMS current would be approximately 0.52 x the peak
current. This current value can be calculated as follows:
4
 2VS ( RMS ) 
I RMS = 0.52  
 C 
 
where:
● VS(RMS) = RMS value of the sinusoidal voltage applied across the metrosil.
This is due to the fact that the current waveform through the Metrosil is not sinusoidal but appreciably distorted.
The Metrosil characteristic should be such that it complies with the following requirements:
● The Metrosil current should be as low as possible, and no greater than 30 mA RMS for 1 A current
transformers or 100 mA RMS for 5 A current transformers.
● At the maximum secondary current, the Metrosil should limit the voltage to 1500 V RMS or 2120 V peak for
0.25 second. At higher device voltages it is not always possible to limit the fault voltage to 1500 V rms, so
higher fault voltages may have to be tolerated.
The following tables show the typical Metrosil types that will be required, depending on relay current rating, REF
voltage setting etc.
Metrosils for devices with a 1 Amp CT

The Metrosil units with 1 Amp CTs have been designed to comply with the following restrictions:
● The Metrosil current should be less than 30 mA rms.
● At the maximum secondary internal fault current the Metrosil should limit the voltage to 1500 V rms if
possible.
The Metrosil units normally recommended for use with 1Amp CTs are as shown in the following table:
P64x-TM-EN-4.1 193
Nominal Characteristic Recommended Metrosil Type

Device Voltage Setting C b Single Pole Relay Triple Pole Relay
Up to 125 V RMS 450 0.25 600A/S1/S256 600A/S3/1/S802
125 to 300 V RMS 900 0.25 600A/S1/S1088 600A/S3/1/S1195
Note:
Single pole Metrosil units are normally supplied without mounting brackets unless otherwise specified by the customer.
Metrosils for devices with a 5 Amp CT

These Metrosil units have been designed to comply with the following requirements:
● The Metrosil current should be less than 100 mA rms (the actual maximum currents passed by the devices
shown below their type description.
● At the maximum secondary internal fault current the Metrosil should limit the voltage to 1500 V rms for
0.25secs. At the higher relay settings, it is not possible to limit the fault voltage to 1500 V rms so higher fault
voltages have to be tolerated.
The Metrosil units normally recommended for use with 5 Amp CTs and single pole relays are as shown in the
following table:
Secondary Internal Fault Current Recommended Metrosil types for various voltage settings
Amps RMS Up to 200 V RMS 250 V RMS 275 V RMS 300 V RMS
600A/S1/S1213 600A/S1/S1214 600A/S1/S1214 600A/S1/S1223
50A C = 540/640 C = 670/800 C =670/800 C = 740/870
35 mA RMS 40 mA RMS 50 mA RMS 50 mA RMS
600A/S2/P/
600A/S2/P/S1215 600A/S2/P/S1215 600A/S2/P/S1196
S1217
100A C = 570/670 C =570/670 C =620/740
C = 470/540
75 mA RMS 100 mA RMS 100 mA RMS
70 mA RMS
600A/S3/P/
600A/S3/P/S1220 600A/S3/P/S1221 600A/S3/P/S1222
S1219
150A C = 520/620 C = 570/670 C =620/740
C = 430/500
100 mA RMS 100 mA RMS 100 mA RMS
100 mA RMS
In some situations single disc assemblies may be acceptable, contact General Electric for detailed applications.
Note:
The Metrosils recommended for use with 5 Amp CTs can also be used with triple pole devices and consist of three single pole
units mounted on the same central stud but electrically insulated from each other. To order these units please specify "Triple
pole Metrosil type", followed by the single pole type reference. Metrosil for higher voltage settings and fault currents are
available if required.
5.3.4 CT REQUIREMENTS - HIGH IMPEDANCE REF

In a high impedance REF scheme, the required stability voltage requirement is described in terms of an external
fault (IF), burden (2RL + RCT) and a stability factor (K), as follows:
Vs => KIF(2RL + RCT)
194 P64x-TM-EN-4.1
where:
● RL = resistance of a single lead from device to current transformer
The assumption that one CT is completely saturated for an external fault does not describe what actually happens
when asymmetric CT saturation occurs. The CT that saturates will only saturate during parts of each current
waveform cycle. This means that the spill current waveform seen by the differential element will be highly non-
sinusoidal. The sensitivity to non-sinusoidal spill waveforms for through-faults will be a function of the REF
frequency response, the REF operating time, the REF current setting and the wave shapes.
The frequency response and the operating speed are factors that are inherent to the design. Spill current wave
shapes will be related to the ratio of the CT kneepoint voltage (VK) to the circuit impedance. The stability voltage is
determined by the current setting and the stabilising resistor. The stability of the High Impedance REF function
during through faults is determined by the ratio VK/VS. Where VK is the CT knee point voltage and VS is the stability
voltage.
The relationship between the VK/VS ratio and the required stability factor K has been found to be of a general form
for various designs that have undergone conjunctive testing. It is the absolute values of VK/VS and K that vary in
the relationship for different device designs.
Once stability has been considered, the next performance factor to take into account is the operating time for
internal faults. The CT kneepoint voltage as a multiple of the protection stability voltage setting (VK/VS) will govern
the operating time of a differential relay element for heavy internal faults with transiently offset fault current
waveforms. With the aid of the operating time curves derived for the device, it is possible to identify the ratio VK/VS
that is required to achieve a desired average operating speed for internal faults.
The approach with older electromechanical high impedance relays was to use an universally safe K factor of 1.0,
but the older relays operated quickly with a lower VK/Vs ratio. With more modern IEDs, it is desirable to identify the
optimum K factor for stability, so that the required VK/Vs ratio for stability and operating speed will not make CT
kneepoint voltage requirements worse than traditional requirements.
The high impedance REF CT requirements are shown in the following figure. They are valid for:
5 £ X/R £ 120 and 0.5In £ 40In
0.4 0.06
0.5
0.05
Average operating time
0.6
0.7 0.04
0.8 Average operating time (red curve) 0.03
K
Unstable
0.9 0.02
K (blue curve)
1.0
Stable 0.01
1.1
1.2 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VK /VS
V00752
Figure 90: High Impedance REF CT requirement
Using the above graphical tool:

1. Locate the required average operation time on the right-hand side of the vertical axis.
2. Draw a horizontal line across until it intersects the red curve
3. Draw a vertical line from the above intersection point
4. Read off the the Vk/Vs value from the horizontal axis
5. Where this vertical line intersects the blue curve, read off the K value on the left hand side of the vertical
axis
P64x-TM-EN-4.1 195
If we take the example where the average operating time is 38 ms, the above graphical operations reveal that
Vk/Vs = 4 and K = 0.95.
For best accuracy we recommend class X or class 5P current transformers (CTs). The CT requirements for high
impedance REF protection are generally lower than those for differential protection. If the line CTs for high
impedance REF protection are the same as those used for differential protection, the differential CT requirements
cover both differential and high impedance REF applications. However if the line CTs for high impedance REF are
not the same as those used for differential protection, the high impedance REF CT requirements can be obtained
by using the graph shown above.
196 P64x-TM-EN-4.1
CHAPTER 9
CURRENT PROTECTION FUNCTIONS

Chapter 9 - Current Protection Functions P64x
198 P64x-TM-EN-4.1
P64x Chapter 9 - Current Protection Functions
1 CHAPTER OVERVIEW
The P642, P643, P645 provides a wide range of current protection functions. This chapter describes the operation
of these functions including the principles, logic diagrams and applications.
Overcurrent Protection Principles 200
Phase Overcurrent Protection 211
Voltage Dependent Overcurrent Element 219
Negative Sequence Overcurrent Protection 222
Earth Fault Protection 226
Second Harmonic Blocking 232
P64x-TM-EN-4.1 199
2 OVERCURRENT PROTECTION PRINCIPLES

Most electrical power system faults result in an overcurrent of one kind or another. It is the job of protection
devices, formerly known as 'relays' but now known as Intelligent Electronic Devices (IEDs) to protect the power
system from faults. The general principle is to isolate the faults as quickly as possible to limit the danger and
prevent fault currents flowing through systems, which can cause severe damage to equipment and systems. At
the same time, we wish to switch off only the parts of the power grid that are absolutely necessary, to prevent
unnecessary blackouts. The protection devices that control the tripping of the power grid's circuit breakers are
highly sophisticated electronic units, providing an array of functionality to cover the different fault scenarios for a
multitude of applications.
The described products offer a range of overcurrent protection functions including:
● Phase Overcurrent protection
● Earth Fault Overcurrent protection
● Negative Sequence Overcurrent protection
● Sensitive Earth Fault protection
To ensure that only the necessary circuit breakers are tripped and that these are tripped with the smallest possible
delay, the IEDs in the protection scheme need to co-ordinate with each other. Various methods are available to
achieve correct co-ordination between IEDs in a system. These are:
● By means of time alone
● By means of current alone
● By means of a combination of both time and current.
Grading by means of current alone is only possible where there is an appreciable difference in fault level between
the two locations where the devices are situated. Grading by time is used by some utilities but can often lead to
excessive fault clearance times at or near source substations where the fault level is highest.
For these reasons the most commonly applied characteristic in co-ordinating overcurrent devices is the IDMT
(Inverse Definite Minimum Time) type.
2.1 IDMT CHARACTERISTICS

There are two basic requirements to consider when designing protection schemes:
● All faults should be cleared as quickly as possible to minimise damage to equipment
● Fault clearance should result in minimum disruption to the electrical power grid.
The second requirement means that the protection scheme should be designed such that only the circuit
breaker(s) in the protection zone where the fault occurs, should trip.
These two criteria are actually in conflict with one another, because to satisfy (1), we increase the risk of shutting
off healthy parts of the grid, and to satisfy (2) we purposely introduce time delays, which increase the amount of
time a fault current will flow. With IDMT protection applied to radial feeders, this problem is exacerbated by the
nature of faults in that the protection devices nearest the source, where the fault currents are largest, actually
need the longest time delay.
IDMT characteristics are described by operating curves. Traditionally, these were defined by the performance of
electromechanical relays. In numerical protection, equations are used to replicate these characteristics so that
they can be used to grade with older equipment.
The old electromechanical relays countered this problem somewhat due to their natural operate time v. fault
current characteristic, whereby the higher the fault current, the quicker the operate time. The characteristic typical
of these electromechanical relays is called Inverse Definite Minimum Time or IDMT for short.
200 P64x-TM-EN-4.1
2.1.1 IEC 60255 IDMT CURVES

There are four well-known variants of this characteristic:
● Standard Inverse
● Very inverse
● Extremely inverse
● UK Long Time inverse
These equations and corresponding curves governing these characteristics are very well known in the power
industry.
Standard Inverse
This characteristic is commonly known as the 3/10 characteristic, i.e. at ten times setting current and TMS of 1 the
relay will operate in 3 seconds.
The characteristic curve can be defined by the mathematical expression:
0.14
top = T 0.02
 I 
  −1
 Is 
The standard inverse time characteristic is widely applied at all system voltages – as back up protection on EHV
systems and as the main protection on HV and MV distribution systems.
In general, the standard inverse characteristics are used when:
● There are no co-ordination requirements with other types of protective equipment further out on the
system, e.g. Fuses, thermal characteristics of transformers, motors etc.
● The fault levels at the near and far ends of the system do not vary significantly.
● There is minimal inrush on cold load pick up. Cold load inrush is that current which occurs when a feeder is
energised after a prolonged outage. In general the relay cannot be set above this value but the current
should decrease below the relay setting before the relay operates.
Very Inverse
This type of characteristic is normally used to obtain greater time selectivity when the limiting overall time factor is
very low, and the fault current at any point does not vary too widely with system conditions. It is particularly
suitable, if there is a substantial reduction of fault current as the distance from the power source increases. The
steeper inverse curve gives longer time grading intervals. Its operating time is approximately doubled for a
reduction in setting from 7 to 4 times the relay current setting. This permits the same time multiplier setting for
several relays in series.
The characteristic curve can be defined by the mathematical expression:
13.5
top = T
I 
  −1
 Is 
Extremely Inverse
With this characteristic the operating time is approximately inversely proportional to the square of the current. The
long operating time of the relay at peak values of load current make the relay particularly suitable for grading with
fuses and also for protection of feeders which are subject to peak currents on switching in, such as feeders
supplying refrigerators, pumps, water heaters etc., which remain connected even after a prolonged interruption of
supply.
P64x-TM-EN-4.1 201
For cases where the generation is practically constant and discrimination with low tripping times is difficult to
obtain, because of the low impedance per line section, an extremely inverse relay can be very useful since only a
small difference of current is necessary to obtain an adequate time difference.
Another application for this relay is with auto reclosers in low voltage distribution circuits. As the majority of faults
are of a transient nature, the relay is set to operate before the normal operating time of the fuse, thus preventing
perhaps unnecessary blowing of the fuse.
Upon reclosure, if the fault persists, the recloser locks itself in the closed position and allows the fuse to blow to
clear the fault.
This characteristic is also widely used for protecting plant against overheating since overheating is usually an I2t
function.
This characteristic curve can be defined by the mathematical expression:
80
top = T 2
I 
  −1
 Is 
UK Long Time Inverse

This type of characteristic has a long time characteristic and may be used for protection of neutral earthing
resistors (which normally have a 30 second rating). The relay operating time at 5 times current setting is 30
seconds at a TMS of 1.
This can be defined by:
120
top = T
 I 
  −1
 Is 
In the above equations:
● top is the operating time
● T is the time multiplier setting
● I is the measured current
● Is is the current threshold setting.
The ratio I/Is is sometimes defined as ‘M’ or ‘PSM’ (Plug Setting Multiplier).
These curves are plotted as follows:
202 P64x-TM-EN-4.1
1000.00
100.00
Operating time (seconds) Long Time Inverse (LTI)
10.00
Standard Inverse (SI)
1.00
Very Inverse (VI)
Extremely Inverse (EI)
0.10
1 10 100
E00600 Current (multiples of IS)
Figure 91: IEC 60255 IDMT curves
2.1.2 EUROPEAN STANDARDS

The IEC 60255 IDMT Operate equation is:
 β 
top = T  α + L+C
 M −1 
and the IEC 60255 IDMT Reset equation is:
 β 
tr = T  α 
 1− M 
where:
● tr is the reset time
● T is the Time Multiplier setting
● M is the ratio of the measured current divided by the threshold current (I/Is)
● β is a constant, which can be chosen to satisfy the required curve characteristic
● α is a constant, which can be chosen to satisfy the required curve characteristic
● C is a constant for adding Definite Time (Definite Time adder)
● L is a constant (usually only used for ANSI/IEEE curves)
The constant values for the IEC IDMT curves are as follows:
Curve Description b constant a constant L constant
IEC Standard Inverse Operate 0.14 0.02 0
IEC Standard Inverse Reset 8.2 6.45 0
P64x-TM-EN-4.1 203

IEC Very Inverse Operate 13.5 1 0
IEC Very Inverse Reset 50.92 2.4 0
IEC Extremely Inverse Operate 80 2 0
IEC Extremely Inverse Reset 44.1 3.03 0
UK Long Time Inverse Operate* 120 1 0
UK Rectifier Operate* 45900 5.6 0
Rapid Inverse (RI) characteristic

The RI operate curve is represented by the following equation:
 
 1 
top = K 
0.236 
 0.339 − 
 M 
where:
● K is the Time Multiplier setting
Note:
* When using UK Long Time Inverse, UK Rectifier or RI for the Operate characteristic, DT (Definite Time) is always used for the
Reset characteristic.
2.1.3 NORTH AMERICAN STANDARDS

The IEEE IDMT Operate equation is:
 β 
top = TD  α + L+C
 M −1 
and the IEEE IDMT Reset equation is:
 β 
tr = TD  α 
 1− M 
where:
● tr is the reset time
● TD is the Time Dial setting
● b is a constant, which can be chosen to satisfy the required curve characteristic
● a is a constant, which can be chosen to satisfy the required curve characteristic
● C is a constant for adding Definite Time (Definite Time adder)
● L is a constant (usually only used for ANSI/IEEE curves)
The constant values for the IEEE curves are as follows:
204 P64x-TM-EN-4.1

IEEE Moderately Inverse Operate 0.0515 0.02 0.114
IEEE Moderately Inverse Reset 4.85 2 0
IEEE Very Inverse Operate 19.61 2 0.491
IEEE Very Inverse Reset 21.6 2 0
IEEE Extremely Inverse Operate 28.2 2 0.1217
IEEE Extremely Inverse Reset 29.1 2 0
CO8 US Inverse Operate 5.95 2 0.18
CO8 US Inverse Reset 5.95 2 0
CO2 US Short Time Inverse Operate 0.16758 0.02 0.11858
CO2 US Short Time Inverse Reset 2.261 2 0
The constant values for the ANSI curves are as follows:

ANSI Normally Inverse Operate 8.9341 2.0938 0.17966
ANSI Normally Inverse Reset 9 2 0
ANSI Short Time Inverse Operate 0.03393 1.2969 0.2663
ANSI Short Time Inverse Reset 0.5 2 0
ANSI Long Time Inverse Operate 2.18592 1 5.6143
ANSI Long Time Inverse Reset 15.75 2 0
Note:
* When using UK Long Time Inverse or UK Rectifier for the Operate characteristic, DT is always used for the Reset
characteristic.
P64x-TM-EN-4.1 205
2.1.4 IEC AND IEEE INVERSE CURVES
IEC Standard Inverse Curve IEC Very Inverse Curve
1000 1000
100 TMS 100 TMS
0.025 0.025
0.075 0.075
10 10
Time in seconds
Time in seconds
0.100 0.100
0.300 0.300
1 1
0.500 0.500
0.700 0.700
0.900 0.900
0.1 0.1
1.000 1.000
1.200 1.200
0.01 0.01
0.5 5 50 0.5 5 50
Current in Multiples of Setting Current in Multiples of Setting
E00757
Figure 92: IEC standard and very inverse curves
IEC Extremely Inverse Curve

IEEE Moderate Inverse Curve
1000
1000
100 TMS
0.05
100
0.025
0.5
0.075
10
1
Time in seconds
Time in seconds
0.100 10
5
0.300
1 10
0.500 1
0.700 30
0.900 50
0.1 0.1
1.000
70
1.200
0.01 100
0.01
0.5 5 50 0.5 5 50
E00758
Figure 93: IEC Extremely inverse and IEEE moderate inverse curves
206 P64x-TM-EN-4.1
IEEE Very Inverse Curve IEEE Extremely Inverse Curve
10000 10000
TD TD
1000 0.05 1000 0.05
0.5 0.5
100 100
1 1
Time in seconds
Time in seconds
5 5
10 10
10 10
1 30 1 30
50 50
0.1 0.1
70 70
0.01 100 0.01 100

0.5 5 50 0.5 5 50
E00759
Figure 94: IEEE very and extremely inverse curves
2.1.5 DIFFERENCES BETWEEN THE NORTH AMERICAN AND EUROPEAN STANDARDS

The IEEE and US curves are set differently to the IEC/UK curves, with regard to the time setting. A time multiplier
setting (TMS) is used to adjust the operating time of the IEC curves, whereas a time dial setting is used for the
IEEE/US curves. The menu is arranged such that if an IEC/UK curve is selected, the I> Time Dial cell is not visible
and vice versa for the TMS setting. For both IEC and IEEE/US type curves, a definite time adder setting is available,
which will increase the operating time of the curves by the set value.
2.2 PRINCIPLES OF IMPLEMENTATION

The range of protection products provides a very wide range of protection functionality. Despite the diverse range
of functionality provided, there is some commonality between the way many of the protection functions are
implemented. It is important to describe some of these basic principles before going deeper into the individual
protection functions.
A simple representation of protection functionality is shown in the following diagram:
P64x-TM-EN-4.1 207
Energising quantity Start signal
IDMT/DT
Threshold
& & & Trip Sign al
Function inhibit
Stage Blocking signals

1 Timer Settings
Stage Blocking sett ings
Voltage
Directional Check
Current
Timer Blocking signals

1
Timer Blocking settings
V00654
Figure 95: Principle of protection function implementation
An energising quantity is either a voltage input from a system voltage transformer, a current input from a system
current transformer or another quantity derived from one or both of these. The energising quantities are extracted
from the power system. The signals are converted to digital quantities where they can be processed by the IEDs
internal processor.
In general, an energising quantity, be it a current, voltage, power, frequency, or phase quantity, is compared with a
threshold value, which may be settable, or hard-coded depending on the function. If the quantity exceeds (for
overvalues) or falls short of (for undervalues) the threshold, a signal is produced, which when gated with the
various inhibit and blocking functions becomes the Start signal for that protection function. This Start signal is
generally made available to Fixed Scheme Logic (FSL) and Programmable Scheme Logic (PSL) for further
processing. It is also passed through a timer function to produce the Trip signal. The timer function may be an
IDMT curve, or a Definite Time delay, depending on the function. This timer may also be blocked with timer
blocking signals and settings. The timer can be configured by a range of settings to define such parameters as the
type of curve, The Time Multiplier Setting, the IDMT constants, the Definite Time delay etc.
In General Electric products, there are usually several independent stages for each of the functions, and for three-
phase functions, there are usually independent stages for each of the three phases.
Typically some stages use an Inverse Definite Minumum time (IDMT) timer function, and others use a Definite Time
timer (DT) function. If the DT time delay is set to '0', then the function is known to be "instantaneous". In many
instances, the term 'instantaneous protection" is used loosely to describe Definite Time protection stages, even
when the stage may not theoretically be instantaneous.
Many protection functions require a direction-dependent decision. Such functions can only be implemented where
both current and voltage inputs are available. For such functions, a directional check is required, whose output can
block the Start signal should the direction of the fault be wrong.
Note:
In the logic diagrams and descriptive text, it is usually sufficient to show only the first stage, as the design principles for
subsequent stages are usually the same (or at least very similar). Where there are differences between the functionality of
different stages, this is clearly indicated.
2.2.1 TIMER HOLD FACILITY

The Timer Hold facility is available for stages with IDMT functionality , and is controlled by the timer reset settings
for the relevant stages (e.g. I>1 tReset, I>2 tReset ). These cells are not visible for the IEEE/US curves if an inverse
time reset characteristic has been selected, because in this case the reset time is determined by the time dial
setting (TDS).
208 P64x-TM-EN-4.1
This feature may be useful in certain applications, such as when grading with upstream electromechanical
overcurrent relays, which have inherent reset time delays. If you set the hold timer to a value other than zero, the
resetting of the protection element timers will be delayed for this period. This allows the element to behave in a
similar way to an electromechanical relay. If you set the hold timer to zero, the overcurrent timer for that stage will
reset instantaneously as soon as the current falls below a specified percentage of the current setting (typically
95%).
Another situation where the timer hold facility may be used to reduce fault clearance times is for intermittent
faults. An example of this may occur in a plastic insulated cable. In this application it is possible that the fault
energy melts and reseals the cable insulation, thereby extinguishing the fault. This process repeats to give a
succession of fault current pulses, each of increasing duration with reducing intervals between the pulses, until the
fault becomes permanent.
When the reset time is instantaneous, the device will repeatedly reset and not be able to trip until the fault
becomes permanent. By using the Timer Hold facility the device will integrate the fault current pulses, thereby
reducing fault clearance time.
2.3 MAGNETISING INRUSH RESTRAINT

Whenever there is an abrupt change of magnetising voltage (e.g. when a transformer is initially connected to a
source of AC voltage), there may be a substantial surge of current through the primary winding called inrush
current.
In an ideal transformer, the magnetizing current would rise to approximately twice its normal peak value as well,
generating the necessary MMF to create this higher-than-normal flux. However, most transformers are not
designed with enough of a margin between normal flux peaks and the saturation limits to avoid saturating in a
condition like this, and so the core will almost certainly saturate during this first half-cycle of voltage. During
saturation, disproportionate amounts of MMF are needed to generate magnetic flux. This means that winding
current, which creates the MMF to cause flux in the core, could rise to a value way in excess of its steady state
peak value. Furthermore, if the transformer happens to have some residual magnetism in its core at the moment
of connection to the source, the problem could be further exacerbated.
The following figure shows the magnetizing inrush phenomenon:
P64x-TM-EN-4.1 209
+Fm
Steady state
-Fm
2Fm
Switch on at voltage
zero – No residual flux
V = Voltage, F = Flux, Im = magnetising current, Fm = maximum flux
V03123
Figure 96: Magnetising inrush phenomenon
The main characteristics of magnetising inrush currents are:

● Higher magnitude than the transformer rated current magnitude
● Containing harmonics and DC offset
● Much longer time constant than that of the DC offset component of fault current
We can see that inrush current is a regularly occurring phenomenon and should not be considered a fault, as we
do not wish the protection device to issue a trip command whenever a transformer is switched on at an
inconvenient point during the input voltage cycle. This presents a problem to the protection device, because it
should always trip on an internal fault. The problem is that typical internal transformer faults may produce
overcurrents which are not necessarily greater than the inrush current. Furthermore, faults tend to manifest
themselves on switch on, due to the high inrush currents. For this reason, we need to find a mechanism that can
distinguish between fault current and inrush current. Fortunately, this is possible due to the different natures of the
respective currents. An inrush current waveform is rich in harmonics, especially 2nd harmonics, whereas an
internal fault current consists only of the fundamental. We can therefore develop a restraining method based on
the 2nd harmonic content of the inrush current. The mechanism by which this is achieved, is called second
harmonic blocking.
210 P64x-TM-EN-4.1
3 PHASE OVERCURRENT PROTECTION

Phase current faults are faults where fault current flows between two or more phases of a power system. The fault
current may be between the phase conductors only or, between two or more phase conductors and earth.
Although not as common as earth faults (single phase to earth), phase faults are typically more severe.
3.1 PHASE OVERCURRENT PROTECTION FOR POWER TRANSFORMERS

A fault external to a power transformer can result in damage to the transformer. If the fault is not cleared
promptly, the resulting overload on the transformer can cause severe overheating and failure. Overcurrent
elements may be used to clear the transformer from a faulted bus or line before the transformer is damaged.
For faults internal to the transformer, the overcurrent protection is less effective because sensitive settings and
fast operation times are usually not possible.
Sensitive settings are not possible because the pickup should allow overloading of the transformer when required.
Fast operating times are not possible because of the grading required with respect to downstream overcurrent
relays.
3.2 PHASE OVERCURRENT PROTECTION IMPLEMENTATION

The product provides three overcurrent elements for backup phase overcurrent protection. Each element provides
four-stages of non-directional or directional three-phase overcurrent protection with independent time delay
characteristics. You can select the overcurrent element operating quantity for each of the elements with the
setting cells Overcurrent 1, Overcurrent 2 and Overcurrent 3 in the OVERCURRENT column of the relevant settings
group. You can set each element as T1, T2, T3, T4, T5, HV winding, LV winding or TV winding. The HV, LV
and TV windings comprise the vector sums of the CT inputs assigned to that particular winding.
All overcurrent and directional settings apply to all three phases but are independent for each of the four stages.
You may set the overcurrent element as directional only if the three phase VT input is available in the P643/5 and if
the two single phase VT inputs are available in the P642. You may assign the VT to either of the HV, LV or TV
windings. Therefore, overcurrent directional elements are available for the current inputs associated with the
winding that has the VT input assigned.
The first two stages of overcurrent protection have time-delayed characteristics which you can set as IDMT or DT.
The third and fourth stages have definite time characteristics only.
Stages 1, 2 provide a choice of operate and reset characteristics, where you can select between:
● A range of standard IDMT (Inverse Definite Minimum Time) curves
● DT (Definite Time)
This is achieved using the cells
● I>(n) Function for the overcurrent operate characteristic
● I>(n) Reset Char for the overcurrent reset characteristic (IEEE curves only)
where (n) is the number of the stage.
The IDMT-capable stages (1 and 2) also provide a Timer Hold facility. This is configured using the cells I>(n) tReset,
where (n) is the number of the stage. This is not applicable for curves based on the IEEE standard.
Note:
Stages 3 and 4 can have definite time characteristics only.
P64x-TM-EN-4.1 211

00001
00011
001
011
01011
01111
10000
11000
100
110
11010
11110
00100
01100
TV CT Terminals 010
00110
01110

If an overcurrent element is assigned to the HV winding then the associated setting I>(n) Current Set is relative to
the T1 CT. Therefore if if the T1 CT setting is changed, then I>(n) Current Set will be affected accordingly.
The same is true for the LV winding and its associated T3 CT as well as for the TV winding and its associated T2 CT.

If an overcurrent element is assigned to the HV winding then the associated setting I>(n) Current Set is relative to
the T1 CT. Therefore if the T1 CT setting is changed, then I>(n) Current Set will be affected accordingly.
The same is true for the LV winding and its associated T5 CT as well as for the TV winding and its associated T3 CT.
212 P64x-TM-EN-4.1
3.4 NON-DIRECTIONAL OVERCURRENT LOGIC
IA POC1 I>1 Start A
IDMT/DT
I> Threshold*1
& & POC 1 I>1 Trip A
POC1 IA2H Start
I> Blocking
&
2H Blocks I>1
Timer Setting s
POC1 I>1 Start B

IB
IDMT/DT
I> Threshold*1
& & POC 1 I>1 Trip B
POC1 IB2H Start
I> Blocking
&
2H Blocks I>1
Timer Setting s
POC1 I>1 Start C

IC
IDMT/DT
I> Threshold*1
& & POC 1 I>1 Trip C
POC1 IC2H Start
I> Blocking
&
2H Blocks I>1 1 POC1 I>1 Start
Timer Setting s
POC1 IH2 Any St 1 POC1 I>1 Trip

IH2 Cross Block
&
Enabled
POC 1 I>1 TBlk
*1 The threshold set tin gs are influence d by Vo ltage Control Overcurrent functionality
V00672
Figure 97: Non-directional overcurrent logic diagram
Phase Overcurrent Modules are level detectors that detect when the current magnitude exceeds a set threshold.
When this happens, the Phase Overcurrent Module in question issues a signal, which is gated with some blocking
signals to produce the Start signal. This Start signal is gated with other blocking signals and applied to the
IDMT/DT timer module. It is also made available directly to the user for use in the PSL. For each stage, there are
three Phase Overcurrent Modules, one for each phase. The three Start signals from each of these phases are OR'd
together to create a 3-phase Start signal.
The outputs of the IDMT/DT timer modules are the trip signals which are used to drive the tripping output relay.
These tripping signals are also OR'd together to create a 3-phase Trip signal.
The IDMT/DT timer modules can be blocked by:
● A Phase Overcurrent Timer Block (I>(n) Timer Block)
If any one of the above signals is high, or goes high before the timer has counted out, the IDMT/DT timer module is
inhibited (effectively reset) until the blocking signal goes low again. There are separate phase overcurrent timer
block signals, which are independent for each overcurrent stage.
P64x-TM-EN-4.1 213
The start signal can be blocked by:

● The Second Harmonic blocking function on a per phase basis or for all three phases. The relevant bits are
set in the I> Blocking cell and this is combined with the relevant second harmonic blocking DDBs.
The G14 Data type is used for the I>Blocking setting:
Bit number I> Blocking function
Bit 0 VTS Blocks I>1
Bit 4 2H Blocks I>1
Bit 5 2H Blocks I>2
Bit 9 2H Blocks I>3
Bit 10 2H Blocks I>4
These can be set via the Front panel HMI or with the settings application software.
The Phase Overcurrent threshold setting can be influenced by theVoltage Controlled Overcurrent functions, if this
functionality is available and used.
3.5 DIRECTIONAL ELEMENT

If fault current can flow in both directions through a protected location, you will need to use a directional
overcurrent element to determine the direction of the fault. Once the direction has been determined the device
can decide whether to allow tripping or to block tripping. To determine the direction of a phase overcurrent fault,
the device must compare the phase angle of the fault current with that of a known reference quantity. The phase
angle of this known reference quantity must be independent of the faulted phase. Typically this will be the line
voltage between the other two phases.
The phase fault elements of the IEDs are internally polarized by the quadrature phase-phase voltages, as shown in
the table below:
Phase of protection Operate current Polarizing voltage
A Phase IA VBC
B Phase IB VCA
C Phase IC VAB
Under system fault conditions, the fault current vector lags its nominal phase voltage by an angle depending on
the system X/R ratio. The IED must therefore operate with maximum sensitivity for currents lying in this region. This
is achieved by using the IED characteristic angle (RCA). This is the is the angle by which the current applied to the
IED must be displaced from the voltage applied to the IED to obtain maximum sensitivity.
The device provides a setting I> Char Angle, which is set globally for all overcurrent stages. It is possible to set
characteristic angles anywhere in the range –95° to +95°.
A directional check is performed based on the following criteria:
Directional forward
-90° < (angle(I) - angle(V) - RCA) < 90°
Directional reverse
-90° > (angle(I) - angle(V) - RCA) > 90°
214 P64x-TM-EN-4.1
3.5.1 IMPLEMENTING DIRECTIONALISATION

A directional element is available for all of the phase overcurrent stages in this device. These are found in the
direction setting cells for the relevant stage (e.g. I>1 Direction, I>2 Direction). They can be set to non-directional,
directional forward, or directional reverse.
Under system fault conditions, the fault current vector will lag its nominal phase voltage by an angle dependent
upon the system X/R ratio. Therefore the device must operate with maximum sensitivity for currents lying in this
region. This is achieved by means of the characteristic angle (RCA) setting, which defines the angle by which the
applied current must be displaced from the applied voltage in order to obtain maximum sensitivity. This is set in
cell I>Char Angle. You can set characteristic angles anywhere in the range from –95° to +95°.
In the P642, the standard single-phase VT input cam be complemented by an optional single-phase VT that can be
used to directionalise some of the overcurrent protection elements. This connection is shown on the wiring
diagrams and labelled as 'Vbc OPTIONAL'. The settings for the optional VT input that can be used to directionalise
overcurrent elements are the same as those for the overfluxing input and are described by the Aux’ VT Location,
Aux' VT Primary and Aux' VT Sec'y settings in the CT AND VT RATIOS column.
In the P643 and P645, the standard single-phase VT input can be complemented by an optional three-phase VT
input that can be used to directionalise some of the overcurrent protection elements. This connection is shown on
the wiring diagrams and labelled as ‘OPTIONAL”. The settings for the optional VT input that can be used to
directionalise overcurrent elements are those described by the ’Main VT Location, Main VT Primary and Main VT
Sec'y settings settings in the CT AND VT RATIOS column.
The overcurrent elements that can be directionalised are those associated with the windings to which the optional
VTs are assigned. You can only directionalise overcurrent elements associated with the winding to which the
optional input is assigned.
So, to provide directional overcurrent you need:
● To have the appropriate VT option
● Connect the VT input to the winding that you want directional protection for AND assign the optional VT
input to that winding in the CT AND VT RATIOS column
● Set the overcurrent to directional (either forward or reverse).
As well as directionalising a particular winding current, for models with more than two winding inputs, you can
directionalise individual inputs if they are associated with that winding.
For close up three-phase faults, all three voltages will collapse to zero and no healthy phase voltages will be
present. For this reason, the device includes a synchronous polarisation feature that stores the pre-fault voltage
information and continues to apply this to the directional overcurrent elements for a time period of 3.2 seconds.
This ensures that either instantaneous or time-delayed directional overcurrent elements will be allowed to operate,
even with a three-phase voltage collapse.
P64x-TM-EN-4.1 215
3.5.2 DIRECTIONAL OVERCURRENT LOGIC
IA POC1 I>1 Start A
IDMT/DT
I> Threshold
& & POC1 I>1 Trip
POC1 IA2H Start

I> Blocking
&
2H Blocks I>1
Timer Settings
POC1 IH2 Any St

I> Blocking
&
2H Blocks I>1
2H 1PH Block
IA
VAB
I>1 Direction
Non-Directional
Directional FWD Directional
Directional REV check
VTS Slow Block

I> Blocking &
VTS Blocks I>1
POC1 I>1 TBlk
Notes: Shown for phase A only. Same principle applies f or phases B and C.
This diagram does not show all st ages. Ot her stages f ollow similar p rinciples.
V00689
Figure 98: Directional overcurrent logic diagram
The directional overcurrent logic works the same way as non-directional logic except that there is a Directional
Check function, based on the following criteria:
● Directional forward: -90° < (angle(I) - angle(V) - RCA) < 90°
● Directional reverse: -90° > (angle(I) - angle(V) - RCA) > 90°
The polarising voltages for each phase are as follows:

Phase of Protection Operate Current Polarising Voltage
A Phase IA VBC
B Phase IB VCA
C Phase IC VAB
When the element is selected as directional, blocking of the Voltage Transformer Supervision (VTS Block) is
available (I>Blocking cell). When the relevant bit is set to 1, operation of the VTS will block the stage if
directionalised. When set to 0, the stage will revert to non-directional on operation of the VTS.
3.6.1 SETTING GUIDELINES

The overcurrent inverse time characteristic on the HV side of the transformer must grade with the overcurrent
inverse time characteristic on the LV side which in turn must grade with the LV outgoing circuits. The overcurrent
function provides limited protection for internal transformer faults because sensitive settings and fast operation
216 P64x-TM-EN-4.1
times are usually not possible. Sensitive settings are not possible because the pickup should allow overloading of
the transformer when required. Fast operating times are not possible because of the grading required with respect
to downstream overcurrent relays. To allow fast operating times, phase instantaneous overcurrent functions with
low transient overreach are required.
The pickup of the time delayed overcurrent element can be set to 125-150% of the maximum MVA rating to allow
overloading of the transformer according to IEEE Std. C37.91-2000.
As recommended by IEEE Std. C37.91-2000, you should set the instantaneous overcurrent element to pick up at a
value higher than the maximum asymmetrical through fault current. This is usually the fault current through the
transformer for a low-side three-phase fault. For instantaneous elements, variations in settings of 125–200% are
common. For elements subject to transient overreach, a pickup of 175% of the calculated maximum low-side
three-phase symmetrical fault current generally provides sufficient margin to avoid false tripping for a low-side
bus fault, while still providing protection for severe internal faults. Due to low transient overreach of the third and
fourth overcurrent stages, you may set the instantaneous overcurrent element to 120-130% of the through-fault
level, thus ensuring stability for through faults. The instantaneous pickup setting should also consider the effects of
transformer magnetising inrush current.
In summary, there are a few application considerations to make when applying overcurrent devices to protect a
transformer:
● When applying overcurrent protection to the HV side of a power transformer it is usual to apply a high set
instantaneous overcurrent element in addition to the time delayed low-set, to reduce fault clearance times
for HV fault conditions. Typically, this will be set to approximately 1.3 times the LV fault level, so that it will
only operate for HV faults. A 30% safety margin is sufficient due to the low transient overreach of the third
and fourth overcurrent stages. Transient overreach defines the response of a relay to DC components of
fault current and is quoted as a percentage. A device with a low transient overreach will be largely
insensitive to a DC offset and may therefore be set more closely to the steady state AC waveform.
● The second requirement for this element is that it should remain inoperative during transformer
energisation, when a large primary current flows for a transient period. In most applications, the
requirement to set the device above the LV fault level will automatically result in settings that will be above
the level of magnetising inrush current.
With the third and fourth overcurrent stages, it is possible to apply settings corresponding to 40% of the peak
inrush current while maintaining stability for the condition.
Where an instantaneous element is required to accompany the time delayed protection, as described above, you
should use the third or fourth overcurrent stages as these have wider setting ranges.
P64x-TM-EN-4.1 217
3.6.2 PARALLEL FEEDERS
33 kV
R1 R2
OC/EF OC/EF
SBEF
R3 R4
DOC/DEF DOC/DEF
OC/EF OC/EF
11 kV
R5
OC/EF
Loads
E00603
Figure 99: Typical distribution system using parallel transformers
In the application shown in the diagram, a fault at ‘F’ could result in the operation of both R3 and R4 resulting in
the loss of supply to the 11 kV busbar. Hence, with this system configuration, it is necessary to apply directional
protection devices at these locations set to 'look into' their respective transformers. These devices should co-
ordinate with the non-directional devices, R1 and R2, to ensure discriminative operation during such fault
conditions.
In such an application, R3 and R4 may commonly require non-directional overcurrent protection elements to
provide protection to the 11 kV busbar, in addition to providing a back-up function to the overcurrent devices on
the outgoing feeders (R5).
For this application, stage 1 of the R3 and R4 overcurrent protection would be set to non-directional and time
graded with R5, using an appropriate time delay characteristic. Stage 2 could then be set to directional (looking
back into the transformer) and also have a characteristic which provides correct co-ordination with R1 and R2.
Directionality for each of the applicable overcurrent stages can be set in the directionality cells (I>1 Direction).
Note:
The principles outlined for the parallel transformer application are equally applicable for plain feeders that are operating in
parallel.
218 P64x-TM-EN-4.1
4 VOLTAGE DEPENDENT OVERCURRENT ELEMENT

Where long feeders are protected by overcurrent devices, the detection of remote phase-to-phase faults may
prove difficult due to the fact that the current pick-up of phase overcurrent elements must be set above the
maximum load current, thereby limiting the element's minimum sensitivity.
If the current seen by a local device for a remote fault condition is below its overcurrent setting, a voltage
dependent element may be used to increase the sensitivity to such faults. As a reduction in system voltage will
occur during overcurrent conditions, this may be used to enhance the sensitivity of the overcurrent protection by
reducing the pick up level.
The voltage dependant overcurrent element (either voltage controlled or voltage restrained) remains blocked
unless the associated breaker is closed. However, even when this element is blocked due to the breaker being
opened, the undervoltage element settings, V<1 Poledead Inh or V<2 Poledead Inh, can be used to block the
undervoltage element.
The voltage dependant overcurrent element is also provided with a timer hold setting, which, if set to a value other
than zero, delays the resetting of the protection element timers for this period.
4.1 CURRENT SETTING THRESHOLD SELECTION

The threshold setting used in the level detector depends on whether there is a Voltage Dependent condition. The
Overcurrent function selects the threshold setting according to the following diagram:
Start
Yes Use the threshold setting

Does a Voltage Dependent
calculated by the Voltage
condition exist?
Dependent function
No
Use the current threshold setting

defined in the OVERCURRENT
column
End
V00673
Figure 100: Selecting the current threshold setting
4.2 VCO IMPLEMENTATION

Voltage Controlled Overcurrent Protection is implemented in the OVERCURRENT column of the relevant settings
group, under the sub-heading VCONTROLLED O/C.
The function is available for in two stages, 1 and 2. When VCO is enabled, the under voltage detector is used to
produce a step change in the current setting, when the voltage falls below the voltage setting VCO>1 V<Setting
for stage 1 and VCO>2 V<Setting for stage 2. To achieve this, the current setting is multiplied by a constant, which
is less than 1, set by VCO>1 k Setting for stage 1 and VCO>2 k Setting for stage 2.
P64x-TM-EN-4.1 219
Each of the stages can be set to HV Winding, LV Winding, TV Winding, T1, T2, T3, T4, or T5. If the current signal
chosen for a VCO stage does not belong to the winding where the VT is located, then the VCO element is blocked
and a configuration error alarm is asserted.
The operating characteristic of the current setting when voltage controlled mode is selected is as follows:
Current
setting
Current pickup setting
K x Current pickup setting
Measured voltage
Voltage threshold setting
E00642
Figure 101: Modification of current pickup level for voltage controlled overcurrent protection
In the P643 and P6455, VCO requires an optional three-phase VT to be fitted, and in the P642 it requires that two
single-phase VTs are fitted. In P643/5, the phase-to-phase voltages are derived from the measured phase-to-
neutral voltages. In the P642, two phase-to-phase voltages are measured and the third one is calculated. In the
P642 Vab and Vbc are measured, then Vca is calculated.
4.3 VRO IMPLEMENTATION

Voltage Restrained Overcurrent protection is implemented in the OVERCURRENT column of the relevant settings
group, under the sub-heading V RESTRAINED O/C. The function is available in two stages 1 and 2. In voltage
restrained mode the effective operating current of the protection element is continuously variable as the applied
voltage varies between two voltage thresholds, VRO> V<1 Set and VRO> V<2 Set, as shown in the figure below.
Each of the stages can be set to HV Winding, LV Winding, TV Winding, T1, T2, T3, T4, or T5. If the current signal
chosen for a VRO stage does not belong to the winding where the VT is located, then the VRO element is blocked
and a configuration error alarm is asserted. The operating characteristic of the current setting when voltage
restrained mode is selected is as follows:
For V > Vs1: Current setting (IS) = I>
For Vs2< V < Vs1: Current setting (IS) = K I> + (I> - K I>) {(V- Vs2) / (Vs1- Vs2)}
For V < Vs2: Current setting (IS) = K I>
Where:
I> = VRO> Curr’ Set
IS = Current setting at voltage V
V = Voltage applied to relay element
Vs1 = V<1 Set
Vs2 = V<2 Set
220 P64x-TM-EN-4.1
I> Set
KI> Set
V<2 Set V<1 Set Measured voltage
E00760
Figure 102: Modification of current pickup level for voltage restrained overcurrent protection
In P643 and P645 models, VRO requires an optional three-phase VT to be fitted, whereas, the P642 model requires
that two single-phase VTs are fitted. Also, in P643 and P645 models, the phase-to-phase voltages are derived from
the measured phase-to-neutral voltages. In the P642, two phase-to-phase voltages are measured and the third
one is calculated. In the P642 Vab and Vbc are measured, then Vca is calculated.
This protection mode is considered to be better suited to Generator-Transformer applications.
P64x-TM-EN-4.1 221
5 NEGATIVE SEQUENCE OVERCURRENT PROTECTION

When applying standard phase overcurrent protection, the overcurrent elements must be set significantly higher
than the maximum load current. This limits the element’s sensitivity. Most protection schemes also use an earth
fault element operating from residual current, which improves sensitivity for earth faults. However, certain faults
may arise which can remain undetected by such schemes. Negative Phase Sequence Overcurrent elements can
help in such cases.
Any unbalanced fault condition will produce a negative sequence current component. Therefore, a negative phase
sequence overcurrent element can be used for both phase-to-phase and phase-to-earth faults. Negative Phase
Sequence Overcurrent protection offers the following advantages:
● Negative phase sequence overcurrent elements are more sensitive to resistive phase-to-phase faults,
where phase overcurrent elements may not operate.
● In certain applications, residual current may not be detected by an earth fault element due to the system
configuration. For example, an earth fault element applied on the delta side of a delta-star transformer is
unable to detect earth faults on the star side. However, negative sequence current will be present on both
sides of the transformer for any fault condition, irrespective of the transformer configuration. Therefore, a
negative phase sequence overcurrent element may be used to provide time-delayed back-up protection for
any uncleared asymmetrical faults downstream.
5.1 NPSOC PROTECTION IMPLEMENTATION

The product provides three overcurrent elements for backup negative phase sequence overcurrent protection.
Each element provides four-stages of negative sequence overcurrent protection with independent time delay
characteristics. You can select the overcurrent element operating quantity for each of the elements with the
setting cells NPS O/C 1, NPS O/C 2 and NPS O/C 3 in the NEG SEQ O/C column of the relevant settings group. You
can set each element as T1, T2, T3, T4, T5, HV winding, LV winding or TV winding. The HV, LV and TV
windings comprise the vector sums of the CT inputs associated with a particular winding.
Stages 1, 2 provide a choice of operate and reset characteristics, where you can select between:
This is achieved using the cells

● I2>(n) Function for the overcurrent operate characteristic
● I2>(n) Reset Char for the overcurrent reset characteristic (IEEE only)
The IDMT-capable stages, (1 and 2) also provide a Timer Hold facility. This is configured using the cells
I2>(n) tReset, where (n) is the number of the stage. This is not applicable for curves based on the IEEE standard.
222 P64x-TM-EN-4.1
5.2 NON-DIRECTIONAL NPSOC LOGIC
NPOC1 I 2>1 Start

I2
IDMT/DT
I2>1 Current Set
& & NPOC1 I 2>1 Trip
CTS B lock
NPOC1 I nhibit
NPOC1 I 2>1 TB lk
V00674
Figure 103: Negative Sequence Overcurrent logic - non-directional operation
For Negative Phase Sequence Overcurrent Protection, the energising quanitity I2> is compared with the threshold
voltage I2>1 Current Set. If the value exceeds this setting a start signal is generated, provided there are no blocks.
5% hysteresis is built into the comparator such that the drop-off value is 0.95 x of the current set threshold.
The function can be blocked by an Inhibit signal or by a CTS blocking signal.
The start signal is fed into a timer to produce the trip signal. The timer can be blocked by the timer block signal
This diagram and description applies to each stage of each element, where x is the number of the element and n
is the number of the stage.

Where negative phase sequence current may flow in either direction through an IED location, such as parallel lines
or ring main systems, directional control should be used.
Directionality is achieved by comparing the angle between the negative phase sequence voltage and the negative
phase sequence current. A directional element is available for all of the negative sequence overcurrent stages.
This is found in the I2>(n) Direction cell for the relevant stage for the relevant element. It can be set to non-
directional, directional forward, or directional reverse.
A suitable characteristic angle setting (I2> Char Angle) is chosen to provide optimum performance. This setting
should be set equal to the phase angle of the negative sequence current with respect to the inverted negative
sequence voltage (–V2), in order to be at the centre of the directional characteristic.
P64x-TM-EN-4.1 223
5.3.1 DIRECTIONAL NPSOC LOGIC
NPOC1 I 2>1 Start

I2
IDMT/DT
I2>1 Current Set
& & & NPOC1 I 2>1 Trip
CTS B lock
NPOC1 I nhibit
I2>1 Direction
V2
Directional
I2> V2pol Set
check
VTS Slow Block

&
I2> VTS Blocking
NPOC1 I 2>1 TB lk
Note: This diagram does not sho w all stages. Other stages follow similar principles.
V00675
Figure 104: Negative Phase Sequence Overcurrent logic - directional operation
phase sequence current. The element may be selected to operate in either the forward or reverse direction. A
suitable characteristic angle setting (I2>Char Angle) is chosen to provide optimum performance. This setting
For the negative phase sequence directional elements to operate, the device must detect a polarising voltage
above a minimum threshold, I2>V2pol Set. This must be set in excess of any steady state negative phase
sequence voltage. This may be determined during the commissioning stage by viewing the negative phase
sequence measurements in the device.
When the element is selected as directional (directional devices only), a VTS blocking option is available. When the
relevant bit is set to 1, operation of the Voltage Transformer Supervision (VTS) will block the stage. When set to 0,
the stage will revert to non-directional.
5.4.1 SETTING GUIDELINES (GENERAL)

Since the negative phase sequence overcurrent protection does not respond to balanced-load or three-phase
faults, negative sequence overcurrent elements may provide the desired overcurrent protection. This is particularly
applicable to Δ−Y grounded transformers where only 58% of the secondary per unit phase-to-ground fault current
appears in any one primary phase conductor. Backup protection can be particularly difficult when the Y is
impedance-grounded.
5.4.2 SETTING GUIDELINES (CURRENT THRESHOLD)

A negative phase sequence element can be connected in the primary supply to the transformer and set as
sensitively as required to protect for secondary phase-to-earth or phase-to-phase faults. This function will also
provide better protection than the phase overcurrent function for internal transformer faults. The NPS overcurrent
224 P64x-TM-EN-4.1
protection should be set to coordinate with the low-side phase and earth elements for phase-to-earth and phase-
to-phase faults.
The current pick-up threshold must be set higher than the negative phase sequence current due to the maximum
normal load imbalance. This can be set practically at the commissioning stage, making use of the measurement
function to display the standing negative phase sequence current. The setting should be at least 20% above this
figure.
Where the negative phase sequence element needs to operate for specific uncleared asymmetric faults, a precise
threshold setting would have to be based on an individual fault analysis for that particular system due to the
complexities involved. However, to ensure operation of the protection, the current pick-up setting must be set
approximately 20% below the lowest calculated negative phase sequence fault current contribution to a specific
remote fault condition.
5.4.3 SETTING GUIDELINES (TIME DELAY)

Correct setting of the time delay for this function is vital. You should also be very aware that this element is applied
primarily to provide back-up protection to other protection devices or to provide an alarm. It would therefore
normally have a long time delay.
The time delay set must be greater than the operating time of any other protection device (at minimum fault level)
that may respond to unbalanced faults such as phase overcurrent elements and earth fault elements.
5.4.4 SETTING GUIDELINES (DIRECTIONAL ELEMENT)

Where negative phase sequence current may flow in either direction through an IED location, such as parallel lines
or ring main systems, directional control of the element should be employed (VT models only).
phase sequence current and the element may be selected to operate in either the forward or reverse direction. A
suitable relay characteristic angle setting (I2> Char Angle) is chosen to provide optimum performance. This setting
The angle that occurs between V2 and I2 under fault conditions is directly dependent on the negative sequence
source impedance of the system. However, typical settings for the element are as follows:
● For a transmission system the relay characteristic angle (RCA) should be set equal to –60°
● For a distribution system the relay characteristic angle (RCA) should be set equal to –45°
For the negative phase sequence directional elements to operate, the device must detect a polarising voltage
above a minimum threshold, I2> V2pol Set. This must be set in excess of any steady state negative phase
sequence voltage. This may be determined during the commissioning stage by viewing the negative phase
sequence measurements in the device.
P64x-TM-EN-4.1 225
6 EARTH FAULT PROTECTION

Earth faults are overcurrent faults where the fault current flows to earth. Earth faults are the most common type of
fault.
Earth faults can be measured directly from the system by means of:
● A separate current Transformer (CT) located in a power system earth connection
● A residual connection of the three line CTs, where the Earth faults can be derived mathematically by
summing the three measured phase currents.
Depending on the device model, it will provide one or more of the above means for Earth fault protection.
6.1 EARTH FAULT PROTECTION ELEMENTS

The product provides two (P642) or four (P643/P645) earth fault elements for earth fault protection backup. Each
element provides four-stages of non-directional or directional three-phase overcurrent protection with
independent time delay characteristics. You can select the overcurrent element operating quantity for each of the
elements with the setting cells Earth Fault 1, Earth Fault 2 , Earth Fault 3 and Earth Fault 4 in the EARTH FAULT
column of the relevant settings group. You can set each element as T1, T2, T3, T4, T5, HV winding, LV
winding or TV winding.
Earth Fault 1, Earth Fault 2 and Earth Fault 3 can either measure the earth fault directly or derive it by summing
the phase currents, Earth Fault 4 (P643/P645 only) may only derive the earth fault. This depends on the settings:
EF 1 Input, EF 2 Input, EF 3 Input, which you can set to Measured or Derived and, EF 4 Input (P643/P645 only),
which may only be Derived. For the derived element, the HV, LV and TV windings comprise the vector sums of
the CT inputs associated with a particular winding. For the measured elements TN1, TN2 and TN3 are used.
Each earth fault element provides four stages of Earth Fault protection with independent time delay
characteristics.
Stages 1 and 2 provide a choice of operate and reset characteristics, where you can select between:
This is achieved using the cells:

● IN>(n) Function for the overcurrent operate characteristics
● IN>(n) Reset Char for the overcurrent reset characteristic (IEEE only)

Stages 1 and 2 provide a Timer Hold facility. This is configured using the cells IN>(n) tReset.
226 P64x-TM-EN-4.1
6.2 NON-DIRECTIONAL EARTH FAULT LOGIC
EF1 IN>1 Start

IN
IDMT/ DT
IN>1 Current
& & EF1 IN>1 Trip
CTS Block
EF1 IH2 Start

IN> Blocking &
2 H Blocks IN>1
EF 1 IN>1 TBlk
V00690
Figure 105: Non-directional EF logic (single stage)
The Earth Fault current is compared with a set threshold for each stage of each element. If it exceeds this
threshold, a Start signal is triggered, providing it is not blocked. This can be blocked by the second harmonic
blocking function, or an Inhibit Earth Fault DDB signal.
The timer can be blocked by the relevant timer block signal.
Earth Fault protection can follow the same IDMT characteristics as described in the Overcurrent Protection
Principles section. Please refer to this section for details of IDMT characteristics.
The diagram and description applies to all stages of all earth fault elements.
6.3 IDG CURVE

The IDG curve is commonly used for time delayed earth fault protection in the Swedish market. This curve is
available in stage 1 of the Earth Fault protection.
The IDG curve is represented by the following equation:
 I 
top = 5.8 − 1.35 log e  
 IN > Setting 
where:
top is the operating time
I is the measured current
IN> Setting is an adjustable setting, which defines the start point of the characteristic
Note:
Although the start point of the characteristic is defined by the "ΙN>" setting, the actual current threshold is a different setting
called "IDG Ιs". The "IDG Ιs" setting is set as a multiple of "ΙN>".
Note:
When using an IDG Operate characteristic, DT is always used with a value of zero for the Rest characteristic.
An additional setting "IDG Time" is also used to set the minimum operating time at high levels of fault current.
P64x-TM-EN-4.1 227
10
8 IDGIsIsSetting
IDG SettingRange
Range
time (seconds)
(seconds)
7
6
Operating time
5
Operating
3
IDG Time
IDG Time Setting
Setting Range
Range
2
0
1 10 100
I/IN>
V00611
Figure 106: IDG Characteristic

If Earth fault current can flow in both directions through a protected location, you will need to use a directional
overcurrent element to determine the direction of the fault. Typical systems that require such protection are
parallel feeders (both plain and transformer) and ring main systems, each of which are relatively common in
distribution networks.
A directional element is available for all of the Earth Fault stages for both Earth fault columns. These are found in
the direction setting cells for the relevant stage. They can be set to non-directional, directional forward, or
directional reverse.
The P642 has two neutral current inputs (TN1 and TN2). The P643 and P645 have three terminal current inputs
(TN1, TN2 and TN3). The earth fault overcurrent elements can be directionalised if the TN input is associated with
the winding to which the optional VT input has been connected and assigned.
For standard earth fault protection, two options are available for polarisation; Residual Voltage or Negative
Sequence.
6.4.1 RESIDUAL VOLTAGE POLARISATION

With earth fault protection, the polarising signal needs to be representative of the earth fault condition. As residual
voltage is generated during earth fault conditions, this quantity is commonly used to polarise directional earth
fault elements. This is known as Zero Sequence Voltage polarisation, Residual Voltage polarisation or Neutral
Displacement Voltage (NVD) polarisation.
Small levels of residual voltage could be present under normal system conditions due to system imbalances, VT
inaccuracies, device tolerances etc. For this reason, the device includes a user settable threshold (IN> VNPol set),
which must be exceeded in order for the DEF function to become operational. The residual voltage measurement
provided in the MEASUREMENTS 1 column of the menu may assist in determining the required threshold setting
during the commissioning stage, as this will indicate the level of standing residual voltage present.
Note:
Residual voltage is nominally 180° out of phase with residual current. Consequently, the DEF elements are polarised from the
"-Vres" quantity. This 180° phase shift is automatically introduced within the device.
228 P64x-TM-EN-4.1
The directional criteria with residual voltage polarisation is given below:

● Directional forward: -90° < (angle(IN) - angle(VN + 180°) - RCA) < 90°
● Directional reverse : -90° > (angle(IN) - angle(VN + 180°) - RCA) > 90°
The device derives this voltage internally from the 3-phase voltage input tha must be supplied from either a 5-limb
VT or three single-phase VTs. A three-limb VT has no path for residual flux and is therefore unsuitable to supply the
device.
6.4.1.1 DIRECTIONAL EARTH FAULT LOGIC WITH RESIDUAL VOLTAGE POLARISATION
EF1 IN>1 Start

IN
IDMT/DT
IN>1 Current
& & & EF1 IN>1 Trip
CTS B lock
EF1 IH2 Start

IN> Blocking &
IN>1 2H B lock
IN> Direction
VN
IN> VNpol Set
IN Directional
check
Low Current
VTS Slow Block

IN> Blocking &
IN>1 VTS Block
EF 1 IN>1 TB lk
This diagram does no t show all st ages. Ot her stages f ollow similar p rinciples.
V00691
Figure 107: Directional EF logic with neutral voltage polarization (single stage)
Voltage Transformer Supervision (VTS) selectively blocks the directional protection or causes it to revert to non-
directional operation. When selected to block the directional protection, VTS blocking is applied to the directional
checking which effectively blocks the Start outputs as well.
6.4.2 NEGATIVE SEQUENCE POLARISATION

In some applications, the use of residual voltage polarisation may be not possible to achieve, or at the very least,
problematic. For example, a suitable type of VT may be unavailable, or an HV/EHV parallel line application may
present problems with zero sequence mutual coupling.
In such situations, the problem may be solved by using Negative Phase Sequence (NPS) quantities for polarisation.
This method determines the fault direction by comparing the NPS voltage with the NPS current. The operating
quantity, however, is still residual current.
This can be used for both the derived and measured standard earth fault elements. It requires a suitable voltage
and current threshold to be set in cells IN> V2pol set and IN> I2pol set respectively.
Negative phase sequence polarising is not recommended for impedance earthed systems regardless of the type
of VT feeding the relay. This is due to the reduced earth fault current limiting the voltage drop across the negative
P64x-TM-EN-4.1 229
sequence source impedance to negligible levels. If this voltage is less than 0.5 volts the device will stop providing
directionalisation.
The directional criteria with negative sequence polarisation is given below:
● Directional forward: -90° < (angle(I2) - angle(V2 + 180°) - RCA) < 90°
● Directional reverse : -90° > (angle(I2) - angle(V2 + 180°) - RCA) > 90°
6.4.2.1 DIRECTIONAL EARTH FAULT LOGIC WITH NPS POLARISATION
EF1 IN>1 Start

IN
IN
IDMT/DT
IN>1 Current
& & & EF1 IN>1 Trip
CTS B lock
EF1 IH2 Start

IN> Blocking &
IN>1 2H B lock
IN> Direction
V2
V2
IN> V2pol Set
I2
Directional
check
IN> I2pol Set
VTS Slow Block

IN> Blocking &
IN>1 2H B lock
EF 1 IN>1 TB lk
This diagram d oes no t show all st ages. Ot her stages f ollow similar principles.
V00692
Figure 108: Directional Earth Fault logic with negative phase sequence polarisation (single stage)
Voltage Transformer Supervision (VTS) selectively blocks the directional protection or causes it to revert to non-
directional operation. When selected to block the directional protection, VTS blocking is applied to the directional
checking which effectively blocks the Start outputs as well.
The directional criteria with negative sequence polarisation is given below:
● Directional forward: -90° < (angle(I2) - angle(V2 + 180°) - RCA) < 90°
● Directional reverse : -90° > (angle(I2) - angle(V2 + 180°) - RCA) > 90°
6.5.1 SETTING GUIDELINES (NON-DIRECTIONAL)

To provide backup protection for downstream equipment such as the power transformer and busbar, Standby
Earth Fault (SBEF) protection is commonly applied. This function is fulfilled by a separate earth fault current input,
fed from a single CT in the transformer earth connection. The earth fault elements may be used to provide the
SBEF function.
230 P64x-TM-EN-4.1
A Neutral Earthing Resistor (NER) is used to limit the earth fault level to a particular value. It is possible that under
an earth fault condition a flashover of the NER could occur, which could lead to a dramatic increase in the earth
fault current. For this reason, it may be appropriate to apply two-stage SBEF protection. The first stage should
have suitable current and time characteristics which coordinate with downstream earth fault protection. The
second stage may then be set with a higher current setting but with zero time delay, providing fast clearance of an
earth fault which gives rise to an NER flashover.
The remaining two stages are available for customer-specific applications.
6.5.2 SETTING GUIDELINES (DIRECTIONAL ELEMENT)

With directional earth faults, the residual current under fault conditions lies at an angle lagging the polarising
voltage. Hence, negative RCA settings are required for DEF applications. This is set in the cell I> Char Angle in the
relevant earth fault menu.
We recommend the following RCA settings:
● Resistance earthed systems: 0°
● Distribution systems (solidly earthed): -45°
● Transmission systems (solidly earthed): -60°
P64x-TM-EN-4.1 231
7 SECOND HARMONIC BLOCKING
7.1 SECOND HARMONIC BLOCKING IMPLEMENTATION

A separate second harmonic blocking function is applied to the following overcurrent protection types:
● Phase Overcurrent protection (Overcurrent 1, Overcurrent 2 and Overcurrent 3)
● Earth Fault protection elements (Earth Fault 1, Earth Fault 2 and Earth Fault 3)
● There is no second harmonic blocking for Negative Phase Sequence Overcurrent protection
Second harmonic blocking is applicable to all stages of each of the elements. For POC, 2nd harmonic blocking can
be applied to each phase individually (phase segregated), or to all three phases at once (cross-block).
The function works by identifying and measuring the inrush currents present at switch on. It does this by
comparing the value of the second harmonic current components to the value of the fundamental component. If
this ratio exceeds the set thresholds, then the blocking signal is generated. The threshold is defined by the settings
IH2 I> Set and IH2 IN> Set for Phase Overcurrent protection and Earth Fault protection respectively.
We only want the function to block the protection if the fundamental current component is within the normal
range. If this exceeds the normal range, then this is indicative of a fault, which must be protected. For this reason
there is another settable trigger IH2 IN> Unblock for Phase Overcurrent protection and IH2 I> Unblock for Earth
fault protection, which when exceeded, stops the 2nd harmonic blocking function.
Each overcurrent protection element has an I>Blocking setting with which the stages to be blocked can be
selected.
232 P64x-TM-EN-4.1
7.2 SECOND HARMONIC BLOCKING LOGIC
&
IA fundament al
& POC1 IH2 Any St
IH2 I> Unblock
1
&
& POC1 IA2H Start

POC1 IB2H Start
IA 2nd harm / IA f und

IA 2 nd harmonic
POC1 IC2H Start
IH2 I> Set
IA fu ndament al
IH2 I> Unblock

&
&
IB 2nd harm / IB f und

IB 2 nd harmonic
IH2 I> Set
IC 2nd harmonic
IH2 I> Unblock

&
&
IC 2nd harm / I C fund

IC 2nd harmonic
Note: This diagram does not show a ll stages. Other stages follow similar principles.
IH2 I> Set
V00703
Figure 109: Phase overcurrent 2nd harmonic blocking Logic
P64x-TM-EN-4.1 233
7.3 EF SECOND HARMONIC BLOCKING LOGIC
IN fundamental
IH2 IN> Unblock &

& EF1 IH2 Start
IA 2nd harm / IA f und

IN 2nd harmonic
IH2 IN> set
V00704
Figure 110: Earth fault 2nd harmonic blocking Logic

During the energization period, the second harmonic component of the inrush current may be as high as 70%. The
second harmonic level may be different for each phase, which is why phase segregated blocking is available.
If the setting is too low, the 2nd harmonic blocking may prevent tripping during some internal transformer faults. If
the setting is too high, the blocking may not operate for low levels of inrush current which could result in undesired
tripping of the overcurrent element during the energization period. In general, a setting of 15% to 20% is suitable.
234 P64x-TM-EN-4.1
CHAPTER 10
CB FAIL PROTECTION
Chapter 10 - CB Fail Protection P64x
236 P64x-TM-EN-4.1
P64x Chapter 10 - CB Fail Protection
1 CHAPTER OVERVIEW
The device provides a Circuit Breaker Fail Protection function. This chapter describes the operation of this function
including the principles, logic diagrams and applications.
Circuit Breaker Fail Protection 238
Circuit Breaker Fail Implementation 239
Circuit Breaker Fail Logic 241
P64x-TM-EN-4.1 237
2 CIRCUIT BREAKER FAIL PROTECTION

When a fault occurs, one or more protection devices will operate and issue a trip command to the relevant circuit
breakers. Operation of the circuit breaker is essential to isolate the fault and prevent, or at least limit, damage to
the power system. For transmission and sub-transmission systems, slow fault clearance can also threaten system
stability.
For these reasons, it is common practice to install Circuit Breaker Failure protection (CBF). CBF protection monitors
the circuit breaker and establishes whether it has opened within a reasonable time. If the fault current has not
been interrupted following a set time delay from circuit breaker trip initiation, the CBF protection will operate,
whereby the upstream circuit breakers are back-tripped to ensure that the fault is isolated.
CBF operation can also reset all start output contacts, ensuring that any blocks asserted on upstream protection
are removed.
238 P64x-TM-EN-4.1
3 CIRCUIT BREAKER FAIL IMPLEMENTATION

Depending on the P64x model (P642, P643, P645), up to five independent sets of circuit breaker failure settings are
available, supporting one phase current and one earth undercurrent function for each set. Each CB Failure set can
be enabled or disabled by the settings T1 CBF Status, T2 CBF Status, T3 CBF Status, T4 CBF Status and T5 CBF
Status respectively.
You can enable or disable each Earth undercurrent element with the IN< Status setting. If enabled, you can set
each earth undercurrent element as measured or derived using the IN< Input setting. When enabled, it can be set
as measured or derived. Depending on the model, you can use single phase CTs connected to the three nuetral CT
connections TN1, TN2 and TN3 for CB failure function (see wiring diagram). You define this with the IN< Terminal
setting.
3.1 CIRCUIT BREAKER FAIL TIMERS

The circuit breaker failure protection incorporates two timers, CB Fail 1 Timer and CB Fail 2 Timer, allowing
configuration for the following scenarios:
● Simple CBF, where only CB Fail 1 Timer is enabled. For any protection trip, the CB Fail 1 Timer is started, and
normally reset when the circuit breaker opens to isolate the fault. If breaker opening is not detected, the CB
Fail 1 Timer times out and closes an output contact assigned to breaker fail (using the programmable
scheme logic). This contact is used to back-trip upstream switchgear, generally tripping all infeeds
connected to the same busbar section.
● A retripping scheme, plus delayed back-tripping. Here, CB Fail 1 Timer is used to issue a trip command to a
second trip circuit of the same circuit breaker. This requires the circuit breaker to have duplicate circuit
breaker trip coils. This mechanism is known as retripping. If retripping fails to open the circuit breaker, a
back-trip may be issued following an additional time delay. The back-trip uses CB Fail 2 Timer, which was
also started at the instant of the initial protection element trip.
You can configure the CBF elements CB Fail 1 Timer and CBF Fail 2 Timer to operate for trips triggered by
protection elements within the device. Alternatively you can use an external protection trip by allocating one of the
opto-inputs to the External Trip DDB signal in the PSL.
You can reset the CBF from a breaker open indication (from the pole dead logic) or from a protection reset. In these
cases resetting is only allowed if the undercurrent elements have also been reset. The resetting mechanism is
determined by the settings Volt Prot Reset and Ext Prot Reset.
The resetting options are summarised in the following table:
Initiation (Menu Selectable) CB Fail Timer Reset Mechanism
The resetting mechanism is fixed (e.g. 50/51/46/21/87)
Current based protection
IA< operates AND IB< operates AND IC< operates AND IN< operates
The resetting mechanism is fixed.
Sensitive Earth Fault element
ISEF< Operates
Three options are available:
● All I< and IN< elements operate
Non-current based protection (e.g. 27/59/81/32L)
● Protection element reset AND all I< and IN< elements operate
● CB open (all 3 poles) AND all I< and IN< elements operate
Three options are available.
● All I< and IN< elements operate
External protection
● External trip reset AND all I< and IN< elements operate
● CB open (all 3 poles) AND all I< and IN< elements operate
P64x-TM-EN-4.1 239
3.2 ZERO CROSSING DETECTION

When there is a fault and the circuit breaker interrupts the CT primary current, the flux in the CT core decays to a
residual level. This decaying flux introduces a decaying DC current in the CT secondary circuit known as
subsidence current. The closer the CT is to its saturation point, the higher the subsidence current.
The time constant of this subsidence current depends on the CT secondary circuit time constant and it is generally
long. If the protection clears the fault, the CB Fail function should reset fast to avoid maloperation due to the
subsidence current. To compensate for this the device includes a zero-crossing detection algorithm, which ensures
that the CB Fail re-trip and back-trip signals are not asserted while subsidence current is flowing. If all the samples
within half a cycle are greater than or smaller than 0 A (10 mS for a 50 Hz system), then zero crossing detection is
asserted, thereby blocking the operation of the CB Fail function. The zero-crossing detection algorithm is used
after the circuit breaker in the primary system has opened ensuring that the only current flowing in the AC
secondary circuit is the subsidence current.
This zero-crossing detection algorithm considers the current inputs T1, T2, T3, T4 and T5 on a per phase basis. If
IN< Input is set as measured, the zero crossing detection algorithm considers the current inputs TN1, TN2 and
TN3. If IN< Input is set as derived, the zero crossing detection algorithm considers the current inputs T1, T2, T3,
T4 and T5. If more than 12 consecutive samples are greater than 0A or more than 12 consecutive samples are
smaller than 0A, then a zero crossing detection condition is asserted, which blocks the operation of the circuit
breaker failure function. The zero crossing detection is asserted after the breaker in the primary system has
opened to ensure that the current flowing in the AC secondary circuit is just the subsidence current.
240 P64x-TM-EN-4.1
4 CIRCUIT BREAKER FAIL LOGIC
Any Trip
1 S
Extern CB1 Trip Q
R 1 Trip St ate
T1 IA< Start
T1 IB< Start
&
T1 IC< St art
T1 IN< St art
V<1 Trip & S

Q
V>1 Trip R
VN>1 Trip
F>1 Trip
F<1 Trip 1 1 Reset State
CLI1 Trip
RTD 1 Trip &
Top Oil >1 Trip 1
Hot Spot >1 Trip &

Volt Prot Reset
Prot Reset & I<
I< Only &
CB Open & I<
CB1 Closed
1
&
Note on SR Latches
S All latches are reset dominant and are triggered on the
positive edge. If the edge occurs while the reset is active,
Q
the detect ion of t he edge is delayed until the reset
Ext Prot Reset & R becomes non-active.
Prot Reset & I<
I< Only 1
CB Open & I<
&
Extern CB1 Trip
&
1
&
V00694
Figure 111: Circuit Breaker Fail Logic - part 1
P64x-TM-EN-4.1 241
CT Select ion Alm

1
CT1 Excluded &
& CB1 ReTrip 3ph
CB Fail 1 Status
Enabled
Disabled 1
Trip St ate
CB Fail 2 Status
Enabled &
& CB1 BkTrip 3ph
Disabled
Reset State
1
T1 IA< Start
1
CT1A ZCD
T1 IB< Start
1
CT1B ZCD
&
T1 IC< St art
1
CT1C ZCD
T1 IN< St art
1
CT1 In ZCD
V00695
Figure 112: Circuit Breaker Fail Logic - part 2
242 P64x-TM-EN-4.1
5 APPLICATION NOTES
5.1 RESET MECHANISMS FOR CB FAIL TIMERS

It is common practise to use low set undercurrent elements to indicate that circuit breaker poles have interrupted
the fault or load current. This covers the following situations:
● Where circuit breaker auxiliary contacts are defective, or cannot be relied on to definitely indicate that the
breaker has tripped.
● Where a circuit breaker has started to open but has become jammed. This may result in continued arcing at
the primary contacts, with an additional arcing resistance in the fault current path. Should this resistance
severely limit fault current, the initiating protection element may reset. Therefore, reset of the element may
not give a reliable indication that the circuit breaker has opened fully.
For any protection function requiring current to operate, the device uses operation of undercurrent elements to
detect that the necessary circuit breaker poles have tripped and reset the CB fail timers. However, the
undercurrent elements may not be reliable methods of resetting CBF in all applications. For example:
● Where non-current operated protection, such as under/overvoltage or under/overfrequency, derives
measurements from a line connected voltage transformer. Here, I< only gives a reliable reset method if the
protected circuit would always have load current flowing. In this case, detecting drop-off of the initiating
protection element might be a more reliable method.
● Where non-current operated protection, such as under/overvoltage or under/overfrequency, derives
measurements from a busbar connected voltage transformer. Again using I< would rely on the feeder
normally being loaded. Also, tripping the circuit breaker may not remove the initiating condition from the
busbar, and so drop-off of the protection element may not occur. In such cases, the position of the circuit
breaker auxiliary contacts may give the best reset method.
5.2 SETTING GUIDELINES (CB FAIL TIMER)

The following timing chart shows the CB Fail timing during normal and CB Fail operation. The maximum clearing
time should be less than the critical clearing time which is determined by a stability study. The CB Fail back-up trip
time delay considers the maximum CB clearing time, the CB Fail reset time plus a safety margin. Typical CB
clearing times are 1.5 or 3 cycles. The CB Fail reset time should be short enough to avoid CB Fail back-trip during
normal operation. Phase and ground undercurrent elements must be asserted for the CB Fail to reset. The
assertion of the undercurrent elements might be delayed due to the subsidence current that might be flowing
through the secondary AC circuit.
P64x-TM-EN-4.1 243
CBF resets:
1. Undercurrent element asserts
2. Undercurrent element asserts and the
breaker status indicates an open position
3. Protection resets and the undercurrent
Fault occurs element asserts
CBF Safety
Protection Maximum breaker reset margin
Normal operating time clearing time time time
operation
t
Protection Local Bks clearing

Breaker failure operating time CBF back-up trip time delay time
operation
Local 86 Remote CB
operating clearing time
time
Maximum fault clearing time
V00693 Fault occurs
Figure 113: CB Fail timing
The following examples consider direct tripping of a 2-cycle circuit breaker. Typical timer settings to use are as
follows:
Typical Delay For 2 Cycle Circuit
CB Fail Reset Mechanism tBF Time Delay
Breaker
CB interrupting time + element reset time (max.) + error in tBF
Initiating element reset 50 + 50 + 10 + 50 = 160 ms
timer + safety margin
CB auxiliary contacts opening/ closing time (max.) + error in tBF
CB open 50 + 10 + 50 = 110 ms
timer + safety margin
CB interrupting time + undercurrent element (max.) + safety
Undercurrent elements 50 + 25 + 50 = 125 ms
margin operating time
Note:
All CB Fail resetting involves the operation of the undercurrent elements. Where element resetting or CB open resetting is
used, the undercurrent time setting should still be used if this proves to be the worst case.
Where auxiliary tripping relays are used, an additional 10-15 ms must be added to allow for trip relay operation.
5.3 SETTING GUIDELINES (UNDERCURRENT)

The phase undercurrent settings (I<) must be set less than load current to ensure that I< operation correctly
indicates that the circuit breaker pole is open. A typical setting for overhead line or cable circuits is 20%In. Settings
of 5% of In are common for generator CB Fail.
The earth fault undercurrent elements must be set less than the respective trip. For example:
IN< = (IN> trip)/2
244 P64x-TM-EN-4.1
CHAPTER 11
VOLTAGE PROTECTION FUNCTIONS

Chapter 11 - Voltage Protection Functions P64x
246 P64x-TM-EN-4.1
P64x Chapter 11 - Voltage Protection Functions
1 CHAPTER OVERVIEW
The device provides a wide range of voltage protection functions. This chapter describes the operation of these
functions including the principles, logic diagrams and applications.
Undervoltage Protection 248
Overvoltage Protection 251
Residual Overvoltage Protection 254
Negative Sequence Overvoltage Protection 258
P64x-TM-EN-4.1 247
2 UNDERVOLTAGE PROTECTION
Undervoltage conditions may occur on a power system for a variety of reasons, some of which are outlined below:
● Undervoltage conditions can be related to increased loads, whereby the supply voltage will decrease in
magnitude. This situation would normally be rectified by voltage regulating equipment such as AVRs (Auto
Voltage Regulators) or On Load Tap Changers. However, failure of this equipment to bring the system
voltage back within permitted limits leaves the system with an undervoltage condition, which must be
cleared.
● If the regulating equipment is unsuccessful in restoring healthy system voltage, then tripping by means of
an undervoltage element is required.
● Faults occurring on the power system result in a reduction in voltage of the faulty phases. The proportion by
which the voltage decreases is dependent on the type of fault, method of system earthing and its location.
Consequently, co-ordination with other voltage and current-based protection devices is essential in order to
achieve correct discrimination.
● Complete loss of busbar voltage. This may occur due to fault conditions present on the incomer or busbar
itself, resulting in total isolation of the incoming power supply. For this condition, it may be necessary to
isolate each of the outgoing circuits, such that when supply voltage is restored, the load is not connected.
Therefore, the automatic tripping of a feeder on detection of complete loss of voltage may be required. This
can be achieved by a three-phase undervoltage element.
● Where outgoing feeders from a busbar are supplying induction motor loads, excessive dips in the supply
may cause the connected motors to stall, and should be tripped for voltage reductions that last longer than
a pre-determined time.
2.1 UNDERVOLTAGE PROTECTION IMPLEMENTATION

Undervoltage Protection is implemented in the VOLT PROTECTION column of the relevant settings group. The
Undervoltage parameters are contained within the sub-heading UNDERVOLTAGE.
The product provides two stages of Undervoltage protection with independent time delay characteristics.
Stage 1 provides a choice of operate characteristics, where you can select between:
● An IDMT characteristic
You set this using the V<1 Function setting.

The IDMT characteristic is defined by the following formula:
t = K/( M-1)
where:
● K = Time multiplier setting
● t = Operating time in seconds
● M = Measured voltage / IED setting voltage (V<(n) Voltage Set)
The undervoltage stages can be configured either as phase-to-neutral or phase-to-phase voltages in the V<
Measur't Mode cell.
There is no Timer Hold facility for Undervoltage.
Stage 2 can have definite time characteristics only. This is set in the V<2 Status cell.
Outputs are available for single or three-phase conditions via the V< Operate Mode cell for each stage.
248 P64x-TM-EN-4.1
2.2 UNDERVOLTAGE PROTECTION LOGIC

V< Mea sur't Mo de
V<1 Start A/A B
V<1 Voltag e Set & t

& V<1 Trip A/ AB
0
V<1 Time Delay
V< Mea su r't Mo de
V<1 Start B/B C
V<1 Voltage Set & t

& V<1 Trip B/ BC
0
V<1 Time Delay
V< Mea su r't Mode
V<1 Start C/CA
V<1 Voltage Set & t

& V<1 Trip C/CA
0
V<1 Time Delay
1
&
All Poles De ad
1 V<1 Start
V<1 Poled ead I nh &
& &
Ena bled
VTS Fast Block 1

&
V<1 Timer Blo ck 1 V<1 Trip
&
V< Operate Mode &
Any Ph ase
Thre e Pha se
Note: This diagram doe s not show a ll stag es. Other stag es follow similar principles.
VTS Fast Block only ap plies f or d irectiona l models.
V00803
Figure 114: Undervoltage - single and three phase tripping mode (single stage)
The Undervoltage protection function detects when the voltage magnitude for a certain stage falls short of a set
threshold. If this happens a Start signal, signifying the "Start of protection", is produced. This Start signal can be
blocked by the VTS Fast Block signal and an All Poles Dead signal. This Start signal is applied to the timer module
to produce the Trip signal, which can be blocked by the undervoltage timer block signal (V<(n) Timer Block). For
each stage, there are three Phase undervoltage detection modules, one for each phase. The three Start signals
from each of these phases are OR'd together to create a 3-phase Start signal (V<(n) Start), which can be be
activated when any of the three phases start (Any Phase), or when all three phases start (Three Phase), depending
on the chosen V< Operate Mode setting.
The outputs of the timer modules are the trip signals which are used to drive the tripping output relay. These
tripping signals are also OR'd together to create a 3-phase Trip signal, which are also controlled by the V< Operate
Mode setting.
If any one of the above signals is low, or goes low before the timer has counted out, the timer module is inhibited
(effectively reset) until the blocking signal goes high.
In some cases, we do not want the undervoltage element to trip; for example, when the protected feeder is de-
energised, or the circuit breaker is opened, an undervoltage condition would obviously be detected, but we would
not want to start protection. To cater for this, an All Poles Dead signal blocks the Start signal for each phase. This
is controlled by the V<Poledead Inh cell, which is included for each of the stages. If the cell is enabled, the relevant
stage will be blocked by the integrated pole dead logic. This logic produces an output when it detects either an
open circuit breaker via auxiliary contacts feeding the opto-inputs or it detects a combination of both
undercurrent and undervoltage on any one phase.
P64x-TM-EN-4.1 249
2.3.1 UNDERVOLTAGE SETTING GUIDELINES

In most applications, undervoltage protection is not required to operate during system earth fault conditions. If this
is the case you should select phase-to-phase voltage measurement, as this quantity is less affected by single-
phase voltage dips due to earth faults.
The voltage threshold setting for the undervoltage protection should be set at some value below the voltage
excursions that may be expected under normal system operating conditions. This threshold is dependent on the
system in question but typical healthy system voltage excursions may be in the order of 10% of nominal value.
The same applies to the time setting. The required time delay is dependent on the time for which the system is able
to withstand a reduced voltage.
If motor loads are connected, then a typical time setting may be in the order of 0.5 seconds.
Stage 1 is used for tripping and can be disabled, or selected as IDMT or DT. You can set stage 2 as an alarm stage
to warn the user of unusual voltage conditions.
If only a single-phase VT signal is available and you require an undervoltage alarm, you must set the VTS status
signal in the SUPERVISION column to Indication or disabled.
250 P64x-TM-EN-4.1
3 OVERVOLTAGE PROTECTION
Overvoltage conditions are generally related to loss of load conditions, whereby the supply voltage increases in
magnitude. This situation would normally be rectified by voltage regulating equipment such as AVRs (Auto Voltage
Regulators) or On Load Tap Changers. However, failure of this equipment to bring the system voltage back within
permitted limits leaves the system with an overvoltage condition which must be cleared.
Note:
During earth fault conditions on a power system there may be an increase in the healthy phase voltages. Ideally, the system
should be designed to withstand such overvoltages for a defined period of time.
3.1 OVERVOLTAGE PROTECTION IMPLEMENTATION

Overvoltage Protection is implemented in the VOLT PROTECTION column of the relevant settings group. The
Overvoltage parameters are contained within the sub-heading OVERVOLTAGE.
The product provides two stages of overvoltage protection with independent time delay characteristics.
You set this using the V>1 Function setting.

t = K/( M - 1)
where:
● K = Time multiplier setting
● M = Measured voltage setting voltage (V>(n) Voltage Set)
The overvoltage stages can be configured either as phase-to-neutral or phase-to-phase voltages in the V>
Measur't Mode cell.
There is no Timer Hold facility for Overvoltage.
Stage 2 can have definite time characteristics only. This is set in the V>2 Status cell.
Outputs are available for single or three-phase conditions via the V> Operate Mode cell for each stage.
P64x-TM-EN-4.1 251
3.2 OVERVOLTAGE PROTECTION LOGIC

V> Mea su r't Mode
V>1 Start A/A B
t
V>1 Voltage Set & V>1 Trip A/ AB
0
V>1 Time Delay
V> Measu r't Mo de

V>1 Start B/B C
t
V>1 Voltage Set & V>1 Trip B/ BC
0
V>1 Time Delay
V> Mea sur't Mo de

V>1 Start C/CA
t
V>1 Voltag e Set & V>1 Trip C/CA
0
V>1 Time Delay 1

&
1 V>1 Start
&
&
1
&
V>1 Timer Block 1 V>1 Trip
&
V> Operate mode &
Any Ph ase
Thre e Pha se
Notes: This diagram does n ot show all stage s. Other stage s follo w similar principles.
VTS Fast Block only ap plies f or directiona l mode ls.
V00 804
Figure 115: Overvoltage - single and three phase tripping mode (single stage)
The Overvoltage protection function detects when the voltage magnitude for a certain stage exceeds a set
threshold. If this happens a Start signal, signifying the "Start of protection", is produced. This Start signal can be
blocked by the VTS Fast Block signal. This start signal is applied to the timer module to produce the Trip signal,
which can be blocked by the overvoltage timer block signal (V>(n) Timer Block). For each stage, there are three
Phase overvoltage detection modules, one for each phase. The three Start signals from each of these phases are
OR'd together to create a 3-phase Start signal (V>(n) Start), which can then be activated when any of the three
phases start (Any Phase), or when all three phases start (Three Phase), depending on the chosen V> Operate Mode
setting.
The outputs of the timer modules are the trip signals which are used to drive the tripping output relay. These
tripping signals are also OR'd together to create a 3-phase Trip signal, which are also controlled by the V> Operate
Mode setting.
If any one of the above signals is low, or goes low before the timer has counted out, the timer module is inhibited
(effectively reset) until the blocking signal goes high.
252 P64x-TM-EN-4.1
3.3.1 OVERVOLTAGE SETTING GUIDELINES

The provision of multiple stages and their respective operating characteristics allows for a number of possible
applications:
● Definite Time can be used for both stages to provide the required alarm and trip stages.
● Use of the IDMT characteristic allows grading of the time delay according to the severity of the overvoltage.
As the voltage settings for both of the stages are independent, the second stage could then be set lower
than the first to provide a time-delayed alarm stage.
● If only one stage of overvoltage protection is required, or if the element is required to provide an alarm only,
the remaining stage may be disabled.
This type of protection must be co-ordinated with any other overvoltage devices at other locations on the system.
Transformers can typically withstand a 110% overvoltage condition continuously. The withstand times for higher
overvoltages should be declared by the transformer manufacturer.
To prevent operation during earth faults, the element should operate from the phase-phase voltages. To achieve
this, you set V>1 Measur’t Mode to Phase-Phase and V>1 Operating Mode set to Three-phase. You should
typically set the overvoltage threshold V>1 Voltage Set to 100% - 120% of the nominal phase‑phase voltage. You
should also set the time delay to prevent unwanted tripping of the delayed overvoltage protection function due to
transient over voltages, which do not pose a risk to the transformer. A typical delay setting would be 1 s - 3 s, with
a longer delay being applied for lower voltage threshold settings.
The second stage can be used to provide instantaneous high-set over voltage protection. The typical threshold
setting to be applied, V>2 Voltage Set, would typically be 130 - 150% of the nominal phase‑phase voltage. For
instantaneous operation, you should set the time delay to 0 s.
If you select phase-to-neutral operation, take care to ensure that the element will grade with other protections
during earth faults, where the phase-neutral voltage can rise significantly.
This type of protection must be coordinated with any other overvoltage devices at other locations on the system.
P64x-TM-EN-4.1 253
4 RESIDUAL OVERVOLTAGE PROTECTION

On a healthy three-phase power system, the sum of the three-phase to earth voltages is nominally zero, as it is the
vector sum of three balanced vectors displaced from each other by 120°. However, when an earth fault occurs on
the primary system, this balance is upset and a residual voltage is produced. This condition causes a rise in the
neutral voltage with respect to earth. Consequently this type of protection is also commonly referred to as 'Neutral
Voltage Displacement' or NVD for short.
This residual voltage is derived (from the phase voltages). Derived values are used where the model does not
support measured functionality.
This offers an alternative means of earth fault detection, which does not require any measurement of current. This
may be particularly advantageous in high impedance earthed or insulated systems, where the provision of core
balanced current transformers on each feeder may be either impractical, or uneconomic, or for providing earth
fault protection for devices with no current transformers.
4.1 RESIDUAL OVERVOLTAGE PROTECTION IMPLEMENTATION

Residual Overvoltage Protection is implemented in the RESIDUAL O/V NVD column of the relevant settings group.
Some applications require more than one stage. For example an insulated system may require an alarm stage and
a trip stage. It is common in such a case for the system to be designed to withstand the associated healthy phase
overvoltages for a number of hours following an earth fault. In such applications, an alarm is generated soon after
the condition is detected, which serves to indicate the presence of an earth fault on the system. This gives time for
system operators to locate and isolate the fault. The second stage of the protection can issue a trip signal if the
fault condition persists.
The product provides two stages of Residual Overvoltage protection with independent time delay characteristics.

t = K/( M - 1)
where:
● K= Time multiplier setting
● M = Derived residual voltage setting voltage (VN> Voltage Set)
You set this using the VN>1 Function setting.

Stage 1 also provides a Timer Hold facility.
Stage 2 can have definite time characteristics only. This is set in the VN>2 status cell
The device derives the residual voltage internally from the three-phase voltage inputs supplied from either a 5-limb
VT or three single-phase VTs. These types of VT design provide a path for the residual flux and consequently permit
the device to derive the required residual voltage. In addition, the primary star point of the VT must be earthed.
Three-limb VTs have no path for residual flux and are therefore unsuitable for this type of protection.
254 P64x-TM-EN-4.1
4.2 RESIDUAL OVERVOLTAGE LOGIC
804
VN>1 Start
VN
VN>1 Voltage Set & 700
& IDMT/DT VN>1 Trip
832
VTS Fast Block
418
VN>1 Timer Blk
V00802
Figure 116: Residual Overvoltage logic
The Residual Overvoltage module (VN>) is a level detector that detects when the voltage magnitude exceeds a set
threshold, for each stage. When this happens, the comparator output produces a Start signal (VN>(n) Start), which
signifies the "Start of protection". This can be blocked by a VTS Fast block signal. This Start signal is applied to the
timer module. The output of the timer module is the VN> (n) Trip signal which is used to drive the tripping output
relay.
4.3.1 CALCULATION FOR SOLIDLY EARTHED SYSTEMS

Consider a Phase-A to Earth fault on a simple radial system.
P64x-TM-EN-4.1 255
E S IED F
ZS ZL
VA
VA
VC VB VC VB VC VB
VA VRES
VRES
VA
VB VB VB
VC VC VC
VRES = ZS0
X3E
2ZS1 + ZS0 + 2ZL1 + ZL0
E00800
Figure 117: Residual voltage for a solidly earthed system
As can be seen from the above diagram, the residual voltage measured on a solidly earthed system is solely
dependent on the ratio of source impedance behind the protection to the line impedance in front of the protection,
up to the point of fault. For a remote fault far away, the ZS/ZL: ratio will be small, resulting in a correspondingly
small residual voltage. Therefore, the protection only operates for faults up to a certain distance along the system.
The maximum distance depends on the device setting.
4.3.2 CALCULATION FOR IMPEDANCE EARTHED SYSTEMS

Consider a Phase-A to Earth fault on a simple radial system.
256 P64x-TM-EN-4.1
E S IED F
ZS ZL
N
ZE
VA - G
S R VA - G
G,F G,F
G,F
VC - G VC - G VC - G
VB - G VB - G VB - G
VRES VRES VRES
VB - G VB - G VB - G
VA - G VA - G
VC - G VC - G VC - G
ZS0 + 3ZE
VRES = X3E
2ZS1 + ZS0 + 2ZL1 + ZL0 + 3Z
E
E00801
Figure 118: Residual voltage for an impedance earthed system
An impedance earthed system will always generate a relatively large degree of residual voltage, as the zero
sequence source impedance now includes the earthing impedance. It follows then that the residual voltage
generated by an earth fault on an insulated system will be the highest possible value (3 x phase-neutral voltage),
as the zero sequence source impedance is infinite.

The voltage setting applied to the elements is dependent on the magnitude of residual voltage that is expected to
occur during the earth fault condition. This in turn is dependent on the method of system earthing employed.
Also, you must ensure that the protection setting is set above any standing level of residual voltage that is present
on the system.
P64x-TM-EN-4.1 257
5 NEGATIVE SEQUENCE OVERVOLTAGE PROTECTION

Where an incoming feeder is supplying rotating plant equipment such as an induction motor, correct phasing and
balance of the supply is essential. Incorrect phase rotation will result in connected motors rotating in the wrong
direction. For directionally sensitive applications, such as elevators and conveyor belts, it is unacceptable to allow
this to happen.
Imbalances on the incoming supply cause negative phase sequence voltage components. In the event of incorrect
phase rotation, the supply voltage would effectively consist of 100% negative phase sequence voltage only.
5.1 NEGATIVE SEQUENCE OVERVOLTAGE IMPLEMENTATION

Negative Sequence Overvoltage Protection is implemented in the NEG SEQUENCE O/V column of the relevant
settings group.
The device includes one Negative Phase Sequence Overvoltage element with a single stage. Only Definite time is
possible.
This element monitors the input voltage rotation and magnitude (normally from a bus connected voltage
transformer) and may be interlocked with the motor contactor or circuit breaker to prevent the motor from being
energised whilst incorrect phase rotation exists.
The element is enabled using the V2> status cell.
5.2 NEGATIVE SEQUENCE OVERVOLTAGE LOGIC
V2> Start
V2
Start
V2> Voltage Set & & DT V2> Trip
Counter
VTS Fast Block
V2> Accelerate
V00805
Figure 119: Negative Sequence Overvoltage logic
The Negative Voltage Sequence Overvoltage module (V2>) is a level detector that detects when the voltage
magnitude exceeds a set threshold. When this happens, the comparator output Overvoltage Module produces a
Start signal (V2> Start), which signifies the "Start of protection". This can be blocked by a VTS Fast block signal.
This Start signal is applied to the DT timer module. The output of the DT timer module is the V2> Trip signal which
is used to drive the tripping output relay.
The V2> Accelerate signal accelerates the operating time of the function, by reducing the number of confirmation
cycles needed to start the function. At 50 Hz, this means the protection Start is reduced by 20 ms.

The primary concern is usually the detection of incorrect phase rotation (rather than small imbalances), therefore a
sensitive setting is not required. The setting must be higher than any standing NPS voltage, which may be present
due to imbalances in the measuring VT, device tolerances etc.
A setting of approximately 15% of rated voltage may be typical.
258 P64x-TM-EN-4.1
Note:
Standing levels of NPS voltage (V2) are displayed in the V2 Magnitude cell of the MEASUREMENTS 1 column.
The operation time of the element depends on the application, but a typical setting would be in the region of 5
seconds.
P64x-TM-EN-4.1 259
260 P64x-TM-EN-4.1
CHAPTER 12
FREQUENCY PROTECTION FUNCTIONS

Chapter 12 - Frequency Protection Functions P64x
262 P64x-TM-EN-4.1
P64x Chapter 12 - Frequency Protection Functions
1 CHAPTER OVERVIEW
The device provides a range of frequency protection functions. This chapter describes the operation of these
functions including the principles, logic diagrams and applications.
Overfluxing Protection 264
Frequency Protection 270
P64x-TM-EN-4.1 263
2 OVERFLUXING PROTECTION
If a power transformer is connected to an active load such as a generator, it is possible that the ratio of voltage to
frequency exceeds certain limits. This will result in Overfluxing, sometimes known as overexcitation. An excessively
high voltage or excessively low frequency causes the V/f ratio to rise, producing high flux densities in the magnetic
core of the transformer. Overfluxing causes the transformer core to saturate resulting in stray flux in non-
laminated components not designed to carry flux. This in turn causes eddy currents in solid components (e.g. core
bolts and clamps) and end-of-core laminations causing rapid overheating and damage. Transformer
manufacturers provide information about the V/f capability as a function of time. The limit is either in the form of a
curve or a set-point with a time delay.
Transformer overfluxing might arise for the following reasons:
● High system voltage
● Generator full load rejection
● Increased voltage due to light loading of transmission lines (Ferranti effect)
● Low system frequency
● Generator excitation at low speed with Automatic Voltage Regulator (AVR) in service
● Geomagnetic disturbance (effects of solar radiation)
● Low frequency earth current circulation through a transmission system
The initial effect of overfluxing is to increase the magnetising current for a transformer. This current will be seen as
a differential current, which could cause the device to maloperate, therefore some sort of restraint is needed. The
fifth harmonic component of the current is used to block the differential element during mild or short term
overfluxing conditions.
Persistent overfluxing however, may result in thermal damage or degradation of a transformer as a result of
overheating.
The following protection strategy is therefore advisable to address potential overfluxing conditions:
● Maintain protection stability during transient overfluxing by blocking the differential protection
● Ensure tripping for persistent overfluxing by applying the overfluxing protection. It is common practice to
use the overfluxing element to protect the transformer during system disturbance, especially on large
network transformers.
2.1 OVERFLUXING PROTECTION IMPLEMENTATION

The Overfluxing settings are in the OVERFLUXING column of the relevant settings group. Depending on your device
model, it provides one or two overfluxing elements with four stages of overfluxing protection plus an additional
alarm stage). The P642 has a single-phase VT only, therefore only one overfluxing element is provided. The P643
and P645 can have a single-phase VT and a 3-phase VT, and therefore provides a single-phase overfluxing
element and a three-phase overfluxing element. Both elements are similar in functionality and follow the same
logical principles.
You enable or disable each stage of the overfluxing protection for each element by the relevant Status cells V/
Hz>(n) Status and V/HZ Alm Status.
The first stage can be set to operate with a definite time or inverse time delay (IDMT). This stage can be used to
provide the protection trip output. The other three stages are all definite time stages. These can be combined with
the first stage inverse time characteristic to create a combined multi-stage overfluxing trip operating
characteristic using PSL.
An inhibit signal is provided for the first stage 1 only. This allows a definite time stage to override a section of the
inverse time characteristic if required. The inhibit signal has the effect of resetting the timer, the start signal and
the trip signal.
264 P64x-TM-EN-4.1
In addition to tripping stages 1 to 4, an Alarm stage is also provided (V/Hz> Alm) for each of the elements. This can
be used to indicate an unhealthy condition.
2.1.1 TIME-DELAYED OVERFLUXING PROTECTION

Protection against damage due to prolonged overfluxing is achieved by using the first overfluxing protection stage
with the IDMT characteristic. The setting flexibility of this element, by adjustment of the time delay at various V/Hz
values, makes it suitable for various country-specific requirements. The manufacturer of the transformer should be
able to supply information about the short-time over-excitation capabilities, which you can use to determine
appropriate settings for the V/Hz tripping element. This variable time overfluxing protection should be used to trip
the transformer directly.
The IDMT characteristic is T = TMS/(M – 1)2

where:
M = (V/f p.u.) / (V/f trip setting)
V and F are measured entities
10000
t=TMS/(M-1) 2
1000
operating time (s)
100
TMS = 12
TMS = 8
10 TMS= 4
TMS = 2
TMS = 1
1
1.05 1.15 1.25 1.35 1.45 1.55
V00864 M = (V/f)/Setting
Figure 120: Variable time overfluxing protection characteristic
The IDMT characteristic is implemented as a thermal function. The internal IDMT timer is treated as a thermal
replica with a cooling characteristic. After a V/Hz excursion, the timer should reset according to the reset cooling
characteristic. Otherwise, if the unit is subjected to another V/Hz excursion before it has cooled to normal
condition, damage could occur before the V/Hz trip point is reached.
A linear reset curve with a Reset Time (V/Hz>x tReset) setting is used for this purpose. The actual reset time left is:
Reset time = tReset * IDMTtimer/tTarget
Where tTarget = TMS/(M-1)2.

The actual trip time delay is:
Trip delay = tTarget * (1-RESETtimer/tReset)
P64x-TM-EN-4.1 265
To make use of the time delayed overfluxing protection, the device must be supplied with a voltage signal which is
representative of the primary system voltage on the source side of the transformer. This is defined by the Ref
Voltage setting in the OVERFLUXING column.
The following diagram explains the reset characteristic. It will take tReset time for the thermal replica to reset
completely to zero after it has reached 100% of V/f>1 trip at stage 1. If the thermal replica has not reached 100%
of V/f>1 Trip, the reset time will be reduced proportionally. For example, if the reset time is set to 100 seconds, and
the thermal replica has only reached 50% of V/f> Trip when V/Hz resets, the reset time will be 50 seconds as
shown in stage 2. If another V/Hz excursion appears before the first reset reaches V/f Reset, the V/Hz time delay
takes the reset time left into consideration, as shown in stage 3.
Stage1 Stage2 Stage3

V/f>1 Trip
V/f>1 Reset
tReset
V/f in p.u.
V00868
Figure 121: Overfluxing reset characteristic
2.1.2 5TH HARMONIC BLOCKING

A differential current 5th harmonic blocking feature can be used to prevent possible maloperation under transient
overfluxing conditions. The 5th harmonic signal is derived from the differential current waveform on each phase.
Blocking is on a per phase basis.
To ensure tripping for persistent overfluxing, caused by high system voltage or low system frequency, the device
provides time delayed overfluxing protection. Where there is any risk of persistent geomagnetic overfluxing, with
normal system voltage and frequency, the 5th harmonic differential current facility can be used to initiate tripping
after a long time delay. This time delay would need to be programmed in the PSL as shown:
Other trip signals

1 Any Trip
IA5H Diff Start
1000 Fault REC TRIG
IB5H Diff Start 1 Pick-up
0
IC5H Diff Start
100
Trip Initial Dwell Relay 3 Output
0
V00863
Figure 122: 5th harmonic blocking time delay in PSL
266 P64x-TM-EN-4.1
2.1.3 OVERFLUXING PROTECTION LOGIC

The overfluxing protection logic is shown below. This diagram shows the case where the first stage timer is set to
IDMT. You can select a DT timer for the first stage if required with the setting V/Hz>1 Trip Func. The diagram shown
is for the 3-phase VT element. The single-phase element follows the same principles.
3ph V/Hz>1 Start

V/f
IDMT
V/Hz>1 Trip Set & 3ph V/Hz>1 Trip
Freq Not found
Blk 3ph V/Hz>1 V/Hz>1 Trip V/Hz>1

TMS Delay
3ph V/Hz>1 Start

V/f
DT
V/Hz>1 Trip Set & 3ph V/Hz>1 Trip
Freq Not found

V/Hz>1 Delay
V/f
DT
V/Hz Alarm Set & 3Ph V/Hz> Alarm
Freq Not found

V/Hz Alarm
Delay
Note: The diagram is for a 3 -phase VT. The logic for a 1 -phase VT is the same.
This diagram does not show all stages. Other stages follow similar principles.
V00867
Figure 123: Overfluxing protection logic
2.2.1 OVERFLUXING PROTECTION SETTING GUIDELINES

The pick up value for the overfluxing elements depends on the nominal core flux density levels. Unit transformers
generally run at higher flux densities than transmission and distribution transformers, so they require a higher pick
up setting and shorter tripping times which reflect this. Transmission transformers can also be at risk from
overfluxing conditions, and you should take withstand levels into consideration when deciding on the required
settings.
The IEEE C37.91-2000 standard states that overexcitation of a transformer can occur whenever the ratio of the per
unit voltage to per unit frequency (V/Hz) at the secondary terminals of a transformer exceeds its rating of 1.05 per
unit (PU) on transformer base at full load, 0.8 power factor, or 1.1 PU at no load.
Please refer to clause 4.1.6 in IEEE C57.12.00-2006 for further clarification on the capability of a transformer to
operate above rated voltage and below rated frequency.
The element is set in terms of the actual ratio of voltage to frequency. You can therefore calculate the overfluxing
threshold setting V/Hz>(n) Trip Set, as follows:
A setting of 1.05 p.u. would equate to 110/50 x 1.05 = 2.31
P64x-TM-EN-4.1 267
where:
● The VT secondary voltage at rated primary volts is 110 V
● The rated frequency is 50 Hz
You should set the overfluxing alarm stage threshold V/Hz Alarm Set, lower than the trip stage setting, to provide
an indication that abnormal conditions are present and to alert an operator to adjust system parameters
accordingly.
You should choose the time delay settings to match the withstand characteristics of the protected transformer. For
an inverse time characteristic, set the time multiplier setting, V/Hz>1 Trip TMS such that the operating
characteristic closely matches the withstand characteristic of transformer. For definite time trip stages, set the
time delay V/Hz>(n) Trip Delay cells. The alarm stage time delay is set in the V/Hz Alarm Delay cell.
You can use PSL to combine the stages to create a multi-stage V/Hz trip operating characteristic, as shown below:
Note:
Consult the manufacturers’ withstand characteristics before formulating these settings.
V/Hz>1
V/Hz>4
V/Hz(%)
V/Hz>3
V/Hz>2
Multi-
Characteristic
V00865 V/Hz(%)
Figure 124: Multi-stage overfluxing characteristic
268 P64x-TM-EN-4.1
V/Hz>2 = 1.4 p.u.

t=1s
V/Hz>2 Trip
V/Hz>3 Trip
1 R14 V/Hz Trip
V/Hz>3 = 1.2 p.u. V/Hz>3 Start

t=4s
V/Hz>1 = 1.06
V/Hz>1 Inhibit TMS = 0.08 V/Hz>1 Trip
V/Hz>4 = 1.1 p.u.

t=0s V/Hz>4 Start
E00866
Figure 125: Scheme logic for multi-stage overfluxing characteristic
P64x-TM-EN-4.1 269
3 FREQUENCY PROTECTION
Power generation and utilisation needs to be well balanced in any industrial, distribution or transmission network.
These electrical networks are dynamic entities, with continually varying loads and supplies, which are continually
affecting the system frequency. Increased loading reduces the system frequency and generation needs to be
increased to maintain the frequency of the supply. Conversely decreased loading increases the system frequency
and generation needs to be reduced. Sudden fluctuations in load can cause rapid changes in frequency, which
need to be dealt with quickly.
Unless corrective measures are taken at the appropriate time, frequency decay can go beyond the point of no
return and cause widespread network collapse, which has dire consequences.
Normally, generators are rated for a particular band of frequency. Operation outside this band can cause
mechanical damage to the turbine blades. Protection against such contingencies is required when frequency does
not improve even after load shedding steps have been taken. This type of protection can be used for operator
alarms or turbine trips in case of severe frequency decay.
Clearly a range of methods is required to ensure system frequency stability. The frequency protection in this device
provides both underfrequency and overfrequency protection.
Frequency Protection is implemented in the FREQ PROTECTION column of the relevant settings group.
3.1 UNDERFREQUENCY PROTECTION

A reduced system frequency implies that the net load is in excess of the available generation. Such a condition can
arise, when an interconnected system splits, and the load left connected to one of the subsystems is in excess of
the capacity of the generators in that particular subsystem. Industrial plants that are dependent on utilities to
supply part of their loads will experience underfrequency conditions when the incoming lines are lost.
Many types of industrial loads have limited tolerances on the operating frequency and running speeds (e.g.
synchronous motors). Sustained underfrequency has implications on the stability of the system, whereby any
subsequent disturbance may damage equipment and even lead to blackouts. It is therefore essential to provide
protection for underfrequency conditions.
3.1.1 UNDERFREQUENCY PROTECTION IMPLEMENTATION

Simple underfrequency Protection is configured in the FREQ PROTECTION column of the relevant settings group.
The device provides 4 stages of underfrequency protection. The function uses the following settings (shown for
stage 1 only - other stages follow the same principles).
● F<1 Status: enables or disables underfrequency protection for the relevant stage
● F<1 Setting: defines the frequency pickup setting
● F<1 Time Delay: sets the time delay
270 P64x-TM-EN-4.1
3.1.2 UNDERFREQUENCY PROTECTION LOGIC
Freq 1155
Averaging F<1 Start
DT
1161
F<1 Setting & F<1 Trip
F<1 Status
Enabled
890
All Poles Dead
1
Freq Not Found 1370
1149
F<1 Timer Block
V00861
Figure 126: Underfrequency logic (single stage)
If the frequency is below the setting and not blocked the DT timer is started. If the frequency cannot be
determined, the function is blocked.
3.1.3 APPLICATION NOTES
3.1.3.1 SETTING GUIDELINES

In order to minimise the effects of underfrequency, a multi-stage load shedding scheme may be used with the
plant loads prioritised and grouped. During an underfrequency condition, the load groups are disconnected
sequentially, with the highest priority group being the last one to be disconnected.
The effectiveness of each load shedding stage depends on the proportion of power deficiency it represents. If the
load shedding stage is too small compared with the prevailing generation deficiency, then there may be no
improvement in the frequency. This should be taken into account when forming the load groups.
Time delays should be sufficient to override any transient dips in frequency, as well as to provide time for the
frequency controls in the system to respond. These should not be excessive as this could jeopardize system
stability. Time delay settings of 5 - 20 s are typical.
The protection function should be set so that declared frequency-time limits for the generating set are not
infringed. Typically, a 10% underfrequency condition should be continuously sustainable.
3.2 OVERFREQUENCY PROTECTION

An increased system frequency arises when the mechanical power input to a generator exceeds the electrical
power output. This could happen, for instance, when there is a sudden loss of load due to tripping of an outgoing
feeder from the plant to a load centre. Under such conditions, the governor would normally respond quickly to
obtain a balance between the mechanical input and electrical output, thereby restoring normal frequency.
Overfrequency protection is required as a backup to cater for cases where the reaction of the control equipment is
too slow.
3.2.1 OVERFREQUENCY PROTECTION IMPLEMENTATION

Simple overfrequency Protection is configured in the FREQ PROTECTION column of the relevant settings group.
The device provides 2 stages of overfrequency protection. The function uses the following settings (shown for
stage 1 only - other stages follow the same principles).
● F>1 Status: enables or disables underfrequency protection for the relevant stage
● F>1 Setting: defines the frequency pickup setting
● F>1 Time Delay: sets the time delay
P64x-TM-EN-4.1 271
3.2.2 OVERFREQUENCY PROTECTION LOGIC
1159
Freq Averaging F>1 Start
DT
1165
F>1 Setting & F>1 Trip
F>1 Status
Enabled
890
All Poles Dead
1
Freq Not Found 1370
1153
F>1 Timer Block
V00862
Figure 127: Overfrequency logic (single stage)
If the frequency is above the setting and not blocked, the DT timer is started and after this has timed out, the trip is
produced. If the frequency cannot be determined, the function is blocked.
3.2.3 APPLICATION NOTES
3.2.3.1 SETTING GUIDELINES

Following changes on the network caused by faults or other operational requirements, it is possible that various
subsystems will be formed within the power network. It is likely that these subsystems will suffer from a
generation/load imbalance. The "islands" where generation exceeds the existing load will be subject to
overfrequency conditions. Severe over frequency conditions may be unacceptable to many industrial loads, since
running speeds of motors will be affected. The overfrequency element can be suitably set to sense this
contingency.
272 P64x-TM-EN-4.1
CHAPTER 13
MONITORING AND CONTROL

Chapter 13 - Monitoring and Control P64x
274 P64x-TM-EN-4.1
P64x Chapter 13 - Monitoring and Control
1 CHAPTER OVERVIEW
As well as providing a range of protection functions, the product includes comprehensive monitoring and control
functionality.
Event Records 276
Disturbance Recorder 283
Measurements 284
Current Input Exclusion Function 286
Circuit Breaker Control 288
Pole Dead Function 293
P64x-TM-EN-4.1 275
2 EVENT RECORDS
General Electric devices record events in an event log. This allows you to establish the sequence of events that led
up to a particular situation. For example, a change in a digital input signal or protection element output signal
would cause an event record to be created and stored in the event log. This could be used to analyse how a
particular power system condition was caused. These events are stored in the IED's non-volatile memory. Each
event is time tagged.
The event records can be displayed on an IED's front panel but it is easier to view them through the settings
application software. This can extract the events log from the device and store it as a single .evt file for analysis on
a PC.
The event records are detailed in the VIEW RECORDS column. The first event (0) is always the latest event. After
selecting the required event, you can scroll through the menus to obtain further details.
If viewing the event with the settings application software, simply open the extracted event file. All the events are
displayed chronologically. Each event is summarised with a time stamp (obtained from the Time & Date cell) and a
short description relating to the event (obtained from the Event Text cell. You can expand the details of the event
by clicking on the + icon to the left of the time stamp.
The following table shows the correlation between the fields in the setting application software's event viewer and
the cells in the menu database.
Field in Event Viewer Equivalent cell in menu DB Cell reference User settable?
Left hand column header VIEW RECORDS ® Time & Date 01 03 No
Right hand column header VIEW RECORDS ® Event Text 01 04 No
Description SYSTEM DATA ® Description 00 04 Yes
Plant reference SYSTEM DATA ® Plant Reference 00 05 Yes
Model number SYSTEM DATA ® Model Number 00 06 No
Address Displays the Courier address relating to the event N/A No
Event type VIEW RECORDS ® Menu Cell Ref 01 02 No
Event Value VIEW RECORDS ® Event Value 01 05 No
Evt Unique Id VIEW RECORDS ® Evt Unique ID 01 FE No
The Select Event setting allows access to individual event records, with the latest event stored at position 0. This
setting also defines the maximum number of records available.
In addition to the event log, there are two logs which contain duplicates of the last 5 maintenance records and the
last 5 fault records. The purpose of this is to provide convenient access to the most recent fault and maintenance
events.
2.1 EVENT TYPES

There are several different types of event:
● Opto-input events (Change of state of opto-input)
● Contact events (Change of state of output relay contact)
● Alarm events
● Fault record events
● Standard events
● Security events
276 P64x-TM-EN-4.1
Standard events are further sub-categorised internally to include different pieces of information. These are:
● Protection events (starts and trips)
● Maintenance record events
● Platform events
Note:
The first event in the list (event 0) is the most recent event to have occurred.
2.1.1 OPTO-INPUT EVENTS

If one or more of the opto-inputs has changed state since the last time the protection algorithm ran (which runs at
several times per cycle), a new event is created, which logs the logic states of all opto-inputs. You can tell which
opto-input has changed state by comparing the new event with the previous one.
The description of this event type, as shown in the Event Text cell is always Logic Inputs # where # is the
batch number of the opto-inputs. This is '1', for the first batch of opto-inputs and '2' for the second batch of opto-
inputs (if applicable).
The event value shown in the Event Value cell for this type of event is a binary string. This shows the logical states
of the opto-inputs, where the Least Significant Bit (LSB), on the right corresponds to the first opto-input Input L1.
The same information is also shown in the Opto I/P Status cell in the SYSTEM DATA column. This information is
updated continuously, whereas the information in the event log is a snapshot at the time when the event was
created.
2.1.2 CONTACT EVENTS

If one or more of the output relays (also known as output contacts) has changed state since the last time the
protection algorithm ran (which runs at several times per cycle), a new event is created, which logs the logic states
of all output relays. You can tell which output relay has changed state by comparing the new event with the
previous one.
The description of this event type, as shown in the Event Text cell is always Output Contacts # where # is the
batch number of the output relay contacts. This is '1', for the first batch of output contacts and '2' for the second
batch of output contacts (if applicable).
The event value shown in the Event Value cell for this type of event is a binary string. This shows the logical states
of the output relays, where the LSB (on the right) corresponds to the first output contact Output R1.
The same information is also shown in the Relay O/P Status cell in the SYSTEM DATA column. This information is
created.
2.1.3 ALARM EVENTS

The IED monitors itself on power up and continually thereafter. If it notices any problems, it will register an alarm
event.
The description of this event type, as shown in the Event Text cell is cell dependent on the type of alarm and will be
one of those shown in the following tables, followed by OFF or ON.
The event value shown in the Event Value cell for this type of event is a 32 bit binary string. There are one or more
banks 32 bit registers, depending on the device model. These contain all the alarm types and their logic states (ON
or OFF).
The same information is also shown in the Alarm Status (n) cells in the SYSTEM DATA column. This information is
created.
P64x-TM-EN-4.1 277
Alarm Status 1
Bit no. Bit Mask (hex) Alarm Description
0 0x00000001 Not Used
1 0x00000002 Not Used
2 0x00000004 Setting Group selection by DDB inputs invalid
3 0x00000008 CB Status Alarm
4 0x00000010 RTD Thermal Alarm
5 0x00000020 RTD Open Circuit Failure
6 0x00000040 RTD Short Circuit Failure
7 0x00000080 RTD Data Inconsistency Error
8 0x00000100 RTD Board Failure
9 0x00000200 Current Loop Input 1 Alarm
13 0x00002000 Current Loop Input 1 Undercurrent Fail Alarm
17 0x00020000 Out of Service Alarm
18 0x00040000 Frequency Out of Range Alarm
19 0x00080000 UNUSED
20 0x00100000 UNUSED
21 0x00200000 UNUSED
22 0x00400000 Current Loop Input Failure
23 0x00800000 Current Loop Input Output Failure
24 0x01000000 VCO1 Configuration Alarm
25 0x02000000 VCO2 Configuration Alarm
26 0x04000000 UNUSED
27 0x08000000 CTS Fail Alarm
28 0x10000000 Circuitry FLT Alm
29 0x20000000 VTS VT Fail Alarm
30 0x40000000 Thermal Pre-trip Alarm
31 0x80000000 Aging Acceleration Factor (FAA) alarm
Alarm Status 2
0 0x00000001 LOL alarm
1 0x00000002 Breaker Fail Any Trip
2 0x00000004 CB Fail Alarm T1
278 P64x-TM-EN-4.1

20 0x00100000 UNUSED
21 0x00200000 HV V/Hz>1 Alarm
22 0x00400000 HV V/Hz>2 PrTrp
23 0x00800000 LV V/Hz>1 Alarm
24 0x01000000 LV V/Hz>2 PrTrp
25 0x02000000 UNUSED
26 0x04000000 UNUSED
27 0x08000000 Frequency Protection Alarm
28 0x10000000 Through fault Alarm
29 0x20000000 Z1 Test Mode
30 0x40000000 Z2 Test Mode
31 0x80000000 UNUSED
Alarm Status 3
0 0x00000001 Battery Fail alarm indication
1 0x00000002 Failure
2 0x00000004 unused
3 0x00000008 Enrolled GOOSE IED absent alarm indication
4 0x00000010 Network Interface Card not fitted/failed alarm
5 0x00000020 Network Interface Card not responding alarm
6 0x00000040 Network Interface Card fatal error alarm indication
7 0x00000080 Network Interface Card software reload alarm
8 0x00000100 Bad TCP/IP Configuration Alarm
9 0x00000200 Bad OSI Configuration Alarm
10 0x00000400 Network Interface Card link fail alarm indication
11 0x00000800 Main card/NIC software mismatch alarm indication
12 0x00001000 IP address conflict alarm indication
13 0x00002000 unused
14 0x00004000 unused
P64x-TM-EN-4.1 279

15 0x00008000 unused
16 0x00010000 unused
17 0x00020000 unused
18 0x00040000 unused
19 0x00080000 unused
20 0x00100000 SNTP Failure Alarm
21 0x00200000 MMS libraries memory allocation fails.
22 0x00400000 unused
23 0x00800000 unused
24 0x01000000 unused
25 0x02000000 unused
26 0x04000000 unused
27 0x08000000 unused
28 0x10000000 unused
29 0x20000000 unused
30 0x40000000 unused
31 0x80000000 unused
Alarm Status 4
0 0x00000001 User Alarm 1 (0=Self-reset, 1=Manual reset)
280 P64x-TM-EN-4.1

2.1.4 FAULT RECORD EVENTS

An event record is created for every fault the IED detects. This is also known as a fault record.
The event type description shown in the Event Text cell for this type of event is always Fault Recorded.
The IED contains a separate register containing the latest fault records. This provides a convenient way of viewing
the latest fault records and saves searching through the event log. You access these fault records using the Select
Fault setting, where fault number 0 is the latest fault.
A fault record is triggered by the Fault REC TRIG signal DDB, which is assigned in the PSL. The fault recorder
records the values of all parameters associated with the fault for the duration of the fault. These parameters are
stored in separate Courier cells, which become visible depending on the type of fault.
The fault recorder stops recording only when:
The Start signal is reset AND the undercurrent is ON OR the Trip signal is reset, as shown below:
Start signal resets

& Fault recorder stops recording
Undercurrent is ON
1
Trip signal resets
Fault recorder trigger
V01234
Figure 128: Fault recorder stop conditions
The event is logged as soon as the fault recorder stops. The time stamp assigned to the fault corresponds to the
start of the fault. The timestamp assigned to the fault record event corresponds to the time when the fault
recorder stops.
Note:
We recommend that you do not set the triggering contact to latching. This is because if you use a latching contact, the fault
record would not be generated until the contact has been fully reset.
2.1.5 MAINTENANCE EVENTS

Internal failures detected by the self-test procedures are logged as maintenance records. Maintenance records are
special types of standard events.
The event type description shown in the Event Text cell for this type of event is always Maint Recorded.
The Event Value cell also provides a unique binary code.
P64x-TM-EN-4.1 281
The IED contains a separate register containing the latest maintenance records. This provides a convenient way of
viewing the latest maintenance records and saves searching through the event log. You access these fault records
using the Select Maint setting.
The maintenance record has a number of extra menu cells relating to the maintenance event. These parameters
are Maint Text, Maint Type and Maint Data. They contain details about the maintenance event selected with the
Select Maint cell.
2.1.6 PROTECTION EVENTS

The IED logs protection starts and trips as individual events. Protection events are special types of standard events.
The event type description shown in the Event Text cell for this type of event is dependent on the protection event
that occurred. Each time a protection event occurs, a DDB signal changes state. It is the name of this DDB signal
followed by 'ON' or 'OFF' that appears in the Event Text cell.
The Event Value cell for this type of event is a 32 bit binary string representing the state of the relevant DDB
signals. These binary strings can also be viewed in the COMMISSION TESTS column in the relevant DDB batch cells.
Not all DDB signals can generate an event. Those that can are listed in the RECORD CONTROL column. In this
column, you can set which DDBs generate events.
2.1.7 SECURITY EVENTS

An event record is generated each time a setting that requires an access level is executed.
The event type description shown in the Event Text cell displays the type of change.
2.1.8 PLATFORM EVENTS

Platform events are special types of standard events.
The event type description shown in the Event Text cell displays the type of change.
282 P64x-TM-EN-4.1
3 DISTURBANCE RECORDER
The disturbance recorder feature allows you to record selected current and voltage inputs to the protection
elements, together with selected digital signals. The digital signals may be inputs, outputs, or internal DDB signals.
The disturbance records can be extracted using the disturbance record viewer in the settings application software.
The disturbance record file can also be stored in the COMTRADE format. This allows the use of other packages to
view the recorded data.
The integral disturbance recorder has an area of memory specifically set aside for storing disturbance records. The
number of records that can be stored is dependent on the recording duration. The minimum duration is 0.1 s and
the maximum duration is 10.5 s.
When the available memory is exhausted, the oldest records are overwritten by the newest ones.
Each disturbance record consists of a number of analogue data channels and digital data channels. The relevant
CT and VT ratios for the analogue channels are also extracted to enable scaling to primary quantities.
The fault recording times are set by a combination of the Duration and Trigger Position cells. The Duration cell
sets the overall recording time and the Trigger Position cell sets the trigger point as a percentage of the duration.
For example, the default settings show that the overall recording time is set to 1.5 s with the trigger point being at
33.3% of this, giving 0.5 s pre-fault and 1 s post fault recording times.
With the Trigger Mode set to Single, if further triggers occurs whilst a recording is taking place, the recorder will
ignore the trigger. However, with the Trigger Mode set to Extended, the post trigger timer will be reset to zero,
extending the recording time.
You can select any of the IED's analogue inputs as analogue channels to be recorded. You can also map any of the
opto-inputs output contacts to the digital channels. In addition, you may also map a number of DDB signals such
as Starts and LEDs to digital channels.
You may choose any of the digital channels to trigger the disturbance recorder on either a low to high or a high to
low transition, via the Input Trigger cell. The default settings are such that any dedicated trip output contacts will
trigger the recorder.
It is not possible to view the disturbance records locally via the front panel LCD. You must extract these using
suitable setting application software such as MiCOM S1 Agile.
P64x-TM-EN-4.1 283
4 MEASUREMENTS
4.1 MEASURED QUANTITIES

The device measures directly and calculates a number of system quantities, which are updated every second. You
can view these values in the relevant MEASUREMENT columns or with the Measurement Viewer in the settings
application software. Depending on the model, the device may measure and display some or more of the following
quantities:
● Measured and calculated analogue current and voltage values
● Power and energy quantities
● Peak, fixed and rolling demand values
● Frequency measurements
● Thermal measurements
4.1.1 MEASURED AND CALCULATED CURRENTS

The device measures phase-to-phase and phase-to-neutral current values. The values are produced by sampling
the analogue input quantities, converting them to digital quantities to present the magnitude and phase values.
Sequence quantities are produced by processing the measured values. These are also displayed as magnitude and
phase angle values.
These measurements are contained in the MEASUREMENTS 1 column.
4.1.2 MEASURED AND CALCULATED VOLTAGES

The device measures phase-to-phase and phase-to-neutral voltage values. The values are produced by sampling
the analogue input quantities, converting them to digital quantities to present the magnitude and phase values.
Sequence quantities are produced by processing the measured values. These are also displayed as magnitude and
phase angle values.
4.1.3 POWER AND ENERGY QUANTITIES

Using the measured voltages and currents the device calculates the apparent, real and reactive power quantities.
These are produced on a phase by phase basis together with three-phase values based on the sum of the three
individual phase values. The signing of the real and reactive power measurements can be controlled using the
measurement mode setting. The four options are defined in the following table:
Measurement Mode Parameter Signing
Export Power +
0 Import Power –
(Default) Lagging Vars +
Leading VArs –
Export Power –
Import Power +
1
Lagging Vars +
Leading VArs –
Export Power +
Import Power –
2
Lagging Vars –
Leading VArs +
284 P64x-TM-EN-4.1
Measurement Mode Parameter Signing

Export Power –
Import Power +
3
Lagging Vars –
Leading VArs +
The device also calculates the per-phase and three-phase power factors.
These power values increment the total real and total reactive energy measurements. Separate energy
measurements are maintained for the total exported and imported energy. The energy measurements are
incremented up to maximum values of 1000 GWhr or 1000 GVARhr at which point they reset to zero. It is possible
to reset these values using the menu or remote interfaces using the Reset demand cell.
4.1.4 DEMAND VALUES

The device produces fixed, rolling, and peak demand values. You reset these quantities using the Reset demand
cell.
The fixed demand value is the average value of a quantity over the specified interval. Values are produced for
three phase real and reactive power. The fixed demand values displayed are those for the previous interval. The
values are updated at the end of the fixed demand period according to the Fix Dem Period setting in the
MEASURE'T SETUP column.
The rolling demand values are similar to the fixed demand values, but a sliding window is used. The rolling demand
window consists of a number of smaller sub-periods. The resolution of the sliding window is the sub-period length,
with the displayed values being updated at the end of each of the sub-periods according to the Roll Sub Period
setting in the MEASURE'T SETUP column.
Peak demand values are produced for each phase current and the real and reactive power quantities. These
display the maximum value of the measured quantity since the last reset of the demand values.
4.1.5 OTHER MEASUREMENTS

Depending on the model, the device produces a range of other measurements such as thermal measurements.
4.2 MEASUREMENT SETUP

You can define the way measurements are set up and displayed using the MEASURE'T SETUP column and the
measurements are shown in the relevant MEASUREMENTS tables.
4.3 OPTO-INPUT TIME STAMPING

Each opto-input sample is time stamped within a tolerance of +/- 1 ms with respect to the Real Time Clock. These
time stamps are used for the opto event logs and for the disturbance recording. The device needs to be
synchronised accurately to an external clock source such as an IRIG-B signal or a master clock signal provided in
the relevant data protocol.
For both the filtered and unfiltered opto-inputs, the time stamp of an opto-input change event is the sampling time
at which the change of state occurred. If multiple opto-inputs change state at the same sampling interval, these
state changes are reported as a single event.
P64x-TM-EN-4.1 285
5 CURRENT INPUT EXCLUSION FUNCTION

In the P643 and P645, it is possible to exclude current inputs from the protection functions. This may be useful for
example in a phase shifting transformer, or during the commissioning or maintenance process.
When a current input is excluded, the device sets the current from that input to zero for calculation purposes, even
if the current measured is not zero. The device compares the actual current flowing with the under current element
threshold to ensure that the CT input is excluded if the current is below the undercurrent threshold when the
master CT exclusion DDB signal is not asserted. The under current threshold is fixed to 0.05 In.
5.1 CURRENT INPUT EXCLUSION LOGIC

CT Exclu Ena
&
CT1 Exclu E na 1 S
Q CT1 Excluded
R
CT1 PhA UnderCur
&
CT1 PhB UnderCur &
CT1 PhC UnderCur

&
1
Note: This diagram doe s not show all stages. Other stag es follow similar principles.
V01231
P643
CT1 Excluded
CT2 Excluded insuff No. o f CT
CT3 Excluded
P645
CT1 Excluded
CT2 Excluded
CT3 Excluded insuff No. o f CT
CT4 Excluded
CT5 Excluded
V01232
Figure 129: CT Exclusion logic
Only one current input can be excluded from the P643 and a maximum of three current inputs can be excluded
from the P645. An alarm DDB (Insuff No. of CT) is issued when more than the maximum number of current inputs
are excluded. The status of the exclusion DDB signals (CTx Excluded) is stored in the device's internal non-volatile
memory. An alarm (Disc CT Invalid) is raised if the stored statuses do not match the statuses after the power
supply is re-established. When the Disc CT Invalid DDB signal is asserted, all protection functions using the
relevant CT inputs are blocked.
Note:
For the differential element to operate correctly, the number of CTs used cannot be less than 2. Also CTs should be excluded
one at a time.
286 P64x-TM-EN-4.1
5.2.1 CURRENT INPUT EXCLUSION EXAMPLE

In the following figure, the adjacent isolators to CB1 are open and locked because of maintenance work on CB1.
1 CB1 2 CB2
Autotransformer
230/115/13.8 kV
Auxiliary
services
CB4 CB5
V01236
Figure 130: CT input exclusion - 1.5 CB application
The current transformer associated with CB1 is connected to the T1 CT input. Auxiliary contacts from CB1 isolators
1 and 2 must be connected to an opto-input as follows.
+V DC
98b - 1
Opto input 14 1 CT1 Exclu E na
98b - 2
Opto input 14
-V DC
V01233
Figure 131: CT input exclusion - auxiliary contact connection
When isolators 1 and 2 are open, the opto-input L14 is energized and CT1 Exclu Ena is asserted. To set CT1
Excluded, T1 CT Phase A, B and C undercurrent elements must also be asserted.
P64x-TM-EN-4.1 287
6 CIRCUIT BREAKER CONTROL

Although some circuit breakers do not provide auxiliary contacts, most provide auxiliary contacts to reflect the
state of the circuit breaker. These are:
● CBs with 52A contacts (where the auxiliary contact follows the state of the CB)
● CBs with 52B contacts (where the auxiliary contact is in the opposite state from the state of the CB)
● CBs with both 52A and 52B contacts
Circuit Breaker control is only possible if the circuit breaker in question provides auxiliary contacts. The CB Status
Input cell in the CB CONTROL column must be set to the type of circuit breaker. If no CB auxiliary contacts are
available then this cell should be set to None, and no CB control will be possible.
For local control, the CB control by cell should be set accordingly.
The output contact can be set to operate following a time delay defined by the setting Man Close Delay. One
reason for this delay is to give personnel time to safely move away from the circuit breaker following a CB close
command.
The control close cycle can be cancelled at any time before the output contact operates by any appropriate trip
signal, or by activating the Reset Close Dly DDB signal.
The length of the trip and close control pulses can be set via the Trip Pulse Time and Close Pulse Time settings
respectively. These should be set long enough to ensure the breaker has completed its open or close cycle before
the pulse has elapsed.
If an attempt to close the breaker is being made, and a protection trip signal is generated, the protection trip
command overrides the close command.
If the CB fails to respond to the control command (indicated by no change in the state of CB Status inputs) an
alarm is generated after the relevant trip or close pulses have expired. This alarm can be viewed on the LCD
display, remotely, or can be assigned to an output contact using the programmable scheme logic (PSL).
Note:
The CB Healthy Time set under this menu section is applicable to manual circuit breaker operations only.
The device includes the following options for control of a single circuit breaker:
● The IED menu (local control)
● The Hotkeys (local control)
● The function keys (local control)
● The opto-inputs (local control)
● SCADA communication (remote control)
6.1 CB CONTROL USING THE IED MENU

You can control manual trips and closes with the CB Trip/Close command in the SYSTEM DATA column. This can be
set to No Operation, Trip, or Close accordingly.
For this to work you have to set the CB control by cell to option 1 Local, option 3 Local + Remote, option 5
Opto+Local, or option 7 Opto+Local+Remote in the CB CONTROL column.
6.2 CB CONTROL USING THE HOTKEYS

The hotkeys allow you to manually trip and close the CB without the need to enter the SYSTEM DATA column. For
this to work you have to set the CB control by cell to option 1 Local, option 3 Local+Remote, option 5 Opto
+Local, or option 7 Opto+Local+Remote in the CB CONTROL column.
288 P64x-TM-EN-4.1
CB control using the hotkey is achieved by pressing the right-hand button directly below LCD screen. This button is
only enabled if:
● The CB Control by setting is set to one of the options where local control is possible (option 1,3,5, or 7)
● The CB Status Input is set to '52A', '52B', or 'Both 52A and 52B'
If the CB is currently closed, the command text on the bottom right of the LCD screen will read Trip. Conversely, if
the CB is currently open, the command text will read Close.
If you execute a Trip, a screen with the CB status will be displayed once the command has been completed. If
you execute a Close, a screen with a timing bar will appear while the command is being executed. This screen
also gives you the option to cancel or restart the close procedure. The time delay is determined by the Man Close
Delay setting in the CB CONTROL menu. When the command has been executed, a screen confirming the present
status of the circuit breaker is displayed. You are then prompted to select the next appropriate command or exit.
If no keys are pressed for a period of 5 seconds while waiting for the command confirmation, the device will revert
to showing the CB Status. If no key presses are made for a period of 25 seconds while displaying the CB status
screen, the device will revert to the default screen.
To avoid accidental operation of the trip and close functionality, the hotkey CB control commands are disabled for
10 seconds after exiting the hotkey menu.
The hotkey functionality is summarised graphically below:
Default Display
HOTKEY CB CTRL
Hotkey Menu
CB closed CB open
<CB STATUS> EXECUTE <CB STATUS> EXECUTE EXECUTE CLOSE

CLOSED CB TRIP OPEN CB CLOSE 30 secs
TRIP EXIT CONFIRM CANCEL EXIT CLOSE CANCEL CONFIRM CANCEL RESTART
E01209
Figure 132: Hotkey menu navigation
6.3 CB CONTROL USING THE FUNCTION KEYS

For most models, you can also use the function keys to allow direct control of the circuit breaker. This has the
advantage over hotkeys, that the LEDs associated with the function keys can indicate the status of the CB. The
default PSL is set up such that Function key 2 initiates a trip and Function key 3 initiates a close. For this to work
you have to set the CB control by cell to option 5 Opto+Local, or option 7 Opto+Local+Remote in the CB
CONTROL column.
As shown below, function keys 2 and 3 have already been assigned to CB control in the default PSL.
P64x-TM-EN-4.1 289
Function Key 2 Init Trip CB
Non- FnKey LED2 Red

Latching FnKey LED2 Grn
Function Key 3 Init Close CB
1 Non- FnKey LED3 Red

Close in Prog
Latching FnKey LED3 Grn
V01245
Figure 133: Default function key PSL
The programmable function key LEDs have been mapped such that they will indicate yellow whilst the keys are
activated.
Note:
Not all models provide function keys.
6.4 CB CONTROL USING THE OPTO-INPUTS

Certain applications may require the use of push buttons or other external signals to control the various CB control
operations. It is possible to connect such push buttons and signals to opto-inputs and map these to the relevant
DDB signals.
For this to work, you have to set the CB control by cell to option 4 opto, option 5 Opto+Local, option 6 Opto
+Remote, or option 7 Opto+Local+Remote in the CB CONTROL column.
6.5 REMOTE CB CONTROL

Remote CB control can be achieved by setting the CB Trip/Close cell in the SYSTEM DATA column to trip or close by
using a command over a communication link.
For this to work, you have to set the CB control by cell to option 2 Remote, option 3 Local+Remote, option 6
Opto+remote, or option 7 Opto+Local+Remote in the CB CONTROL column.
We recommend that you allocate separate relay output contacts for remote CB control and protection tripping.
This allows you to select the control outputs using a simple local/remote selector switch as shown below. Where
this feature is not required the same output contact(s) can be used for both protection and remote tripping.
290 P64x-TM-EN-4.1
Protection Trip
Trip
Remote
Control
Trip Close
Remote
Control
Close
Local
Remote
Trip Close
E01207
Figure 134: Remote Control of Circuit Breaker
6.6 CB HEALTHY CHECK

A CB Healthy check is available if required. This facility accepts an input to one of the opto-inputs to indicate that
the breaker is capable of closing (e.g. that it is fully charged). A time delay can be set with the setting CB Healthy
Time. If the CB does not indicate a healthy condition within the time period following a Close command, the device
will lockout and alarm.
P64x-TM-EN-4.1 291
6.7 CB CONTROL LOGIC

CB Control
Disabled Opto
Local Opto+Local
1 Enable opt o-initiated CB trip and close
Remot e Opto+Remot e
Local+Remote Opto+Rem+Local
HMI Trip Control Trip

1
& & S
Init Trip CB Q
R & Man CB Trip Fail
&
Init close CB 1 Close in Pro g
HMI Close Dela yed con trol close time

& S
Control Close
Q
Close pulse
R &
S
Q
Pulsed outpu t latched in HMI
R
& CB Cls Fail
Reset Close Dly 1
Trip Command In 1
1
Ext. Trip 3ph
Control Trip
CB Open 3 ph
CB hea lthy window
CB Closed 3 ph
& Man CB Unhealthy
CB He alt hy
V01290
Figure 135: CB Control logic
292 P64x-TM-EN-4.1
7 POLE DEAD FUNCTION

The Pole Dead Logic is used to determine and indicate that one or more phases of the line are not energised. A
Pole Dead condition is determined either by measuring:
● the line currents and/or voltages, or
● by monitoring the status of the circuit breaker auxiliary contacts, as shown by dedicated DDB signals.
It can also be used to block operation of underfrequency and undervoltage elements where applicable.
7.1 POLE DEAD FUNCTION IMPLEMENTATION

Pole Dead logic can be implemented in all of the P64x models. If implemented in the P642, it requires a model with
two single phase VT inputs. If implemented in the P643 or P645, it requires a three phase VT input.
In the P642, the phase -to-phase voltages VAB and VBC are considered, whilst in the P643 and P645, the phase -to-
neutral votlages VAN, VBN and VCN are considered.
The pole dead function is used to determine when the circuit breaker poles are open. This indication may be
forced, using status indication from CB auxiliary contacts (52a or 52b) mapped to opto-inputs, or internally
determined by the device. If internally determined, the 52b contacts are used and inverted in the PSL because only
the CBx closed DDB signal is available for each breaker. The device will also initiate a pole dead condition for the
following conditions:
● VTS Slow Block DDB signal is low,
● The line current and voltage fall below a preset threshold.
This is necessary so that a pole dead indication is still given even when an upstream breaker is opened. The
undervoltage and undercurrent thresholds have the following, fixed, pick-up and drop-off levels:
● VA<, VB<, VC<, these level detectors operate on phase voltages and have a fixed setting, Pick-up level = 10 V
(Vn = 100/120 V), 40 V (Vn = 380/480 V), Drop Off level = 30 V (Vn = 100/120 V), 120V (Vn = 380/480 V).
● VAB<, VBC<, these level detectors operate on phase-phase voltages and have a fixed setting, Pick-up level =
70 V (Vn = 100/120 V), Drop Off level = 95 V (Vn = 100/120 V).
● IA<, IB<, IC<, these level operate on phase currents and have a fixed setting, Pick-up level = 0.05 In, Drop Off
level = 0.055 In.
Note:
f the VT is connected at the busbar side, auxiliary contacts (52a or 52b) must be connected to the device for a correct pole
dead indication.
P64x-TM-EN-4.1 293
7.2 POLE DEAD LOGIC

IA
Hardcoded threshold & 1 Pole Dead A
VAB
Hardcoded threshold &
VCA
Hardcoded threshold
IB
Hardcoded threshold & 1 Pole Dead B
VAB
VCA
Hardcoded threshold
IC
Hardcoded threshold & 1 Pole Dead C
VBC
1 Any Po le Dead
VCA
& All Poles Dead
Hardcoded threshold
VTS Slow Block
CB1 Closed
3Ph CB Open
Terminal HV
Selection
P642: 01 CB1 Close d & 3Ph CB Open
Terminal LV
Selection
P642: 10 CB2 Closed & 3Ph CB Open
V01228
Figure 136: Pole Dead logic - P642
294 P64x-TM-EN-4.1
IA
Hardcoded threshold & 1 Pole Dead A
VA
Hardcoded threshold
IB
Hardcoded threshold & 1 Pole Dead B
VB
Hardcoded threshold
IC
Hardcoded threshold & 1 Pole Dead C
VC
1 Any Po le Dead
Hardcoded threshold
VTS Slow Block

& All Poles Dead
3Ph _CB _Open
Terminal HV Terminal TV
Selection Selection
P643: 001 CB1 Closed & 3Ph CB_Open P643: 010 CB2 Closed & 3Ph CB Open
P645: 00001
CB1 Closed CB3 Closed

P643: 011 & 3Ph CB Open P645: 00110 & 3Ph CB Open
P645: 00011 CB2 Closed CB2 Closed
LV P645: 00100 CB3 Closed & 3Ph CB Open

Terminal
Selection
CB3 Closed & 3Ph CB Open CB4 Closed

P643: 100 P645: 01100 & 3Ph CB Open
CB3 Closed
CB3 Close d
& 3Ph CB Open
P643: 110 CB2 Close d
CB5 Closed & 3Ph CB Open

P645: 10000
CB5 Closed
& 3Ph CB Open
P645: 11000 CB4 Closed
V01229
Figure 137: Pole Dead logic - P643 and P645
If both the line current and voltage fall below a certain threshold the device will initiate a Pole Dead condition. The
undervoltage (V<) and undercurrent (I<) thresholds are hardcoded internally.
If one or more poles are dead, the device will indicate which phase is dead and will also assert the Any Pole Dead
DDB signal. If all phases are dead the Any Pole Dead signal would be accompanied by the All Poles Dead signal.
If the VT fails, a VTS Slow Block signal is taken from the VTS logic to block the Pole Dead indications that would be
generated by the undervoltage and undercurrent thresholds. However, the VTS logic will not block the Pole Dead
indications if they are initiated by a CBx Closed signal. A CBx closed signal is inverted and automatically initiates a
Pole Dead condition regardless of the current and voltage measurement.
P64x-TM-EN-4.1 295
7.3 CB STATUS INDICATION

The Pole Dead logic needs a way of initiating the Pole Dead indications for a 3-phase CB Open condition, which
bypasses the VTS blocking. This is normally achieved with a CB State Monitoring function. However, the P64x does
not contain a dedicated CB state monitoring function, so it needs a mechanism by which to achieve this. To do
this, we produce an internal DDB signal (3 ph CB Open), by looking at the status of the CB auxiliary contacts of the
windings to which the voltage transformers are connected. Each terminal (T1 to T5) has an external CBx Closed
DDB signal associated with it, which are connected to the CB auxiliary contacts if available. The internal 3ph CB
Open indication is produced by ANDing together the statuses of the relevant CBs. This is dependent on the model
and the terminal status configuration, and is shown in the logic diagram.
For cases where there are no auxiliary contacts available, the CB Open 3 ph signal must be forced low to avoid a
false Pole Dead indication. You can do this by forcing all five CBx Closed DDB signals high using opto-inputs as
shown below.
High
Opto Input 7 1 CB1 Closed
V01230
Figure 138: Forcing CB Closed signals
296 P64x-TM-EN-4.1
CHAPTER 14
SUPERVISION
Chapter 14 - Supervision P64x
298 P64x-TM-EN-4.1
P64x Chapter 14 - Supervision
1 CHAPTER OVERVIEW
This chapter describes the supervison functions.
Voltage Transformer Supervision 300
Current Transformer Supervision 305
Trip Circuit Supervision 308
P64x-TM-EN-4.1 299
2 VOLTAGE TRANSFORMER SUPERVISION

The Voltage Transformer Supervision (VTS) function is used to detect failure of the AC voltage inputs to the
protection. This may be caused by voltage transformer faults, overloading, or faults on the wiring, which usually
results in one or more of the voltage transformer fuses blowing.
If there is a failure of the AC voltage input, the IED could misinterpret this as a failure of the actual phase voltages
on the power system, which could result in unnecessary tripping of a circuit breaker.
The VTS logic is designed to prevent such a situation by detecting voltage input failures, which are NOT caused by
power system phase voltage failure, and automatically blocking associated voltage dependent protection
elements. A time-delayed alarm output is available to warn of a VTS condition.
The following scenarios are possible with respect to the failure of the VT inputs.
● Loss of one or two-phase voltages
● Loss of all three-phase voltages under load conditions
● Absence of three-phase voltages upon line energisation
2.1 LOSS OF ONE OR TWO PHASE VOLTAGES

If the power system voltages are healthy, no Negative Phase Sequence (NPS) current will be present. If however,
one or two of the AC voltage inputs are missing, there will be Negative Phase Sequence voltage present, even if the
actual power system phase voltages are healthy. VTS works by detecting Negative Phase Sequence (NPS) voltage
without the presence of Negative Phase Sequence current. So if there is NPS voltage present, but no NPS current,
it is certain that there is a problem with the voltage transformers and a VTS block should be applied to voltage
dependent protection functions to prevent maloperation. The use of negative sequence quantities ensures correct
operation even where three-limb or V-connected VTs are used.
2.2 LOSS OF ALL THREE PHASE VOLTAGES

If all three voltage inputs are lost, there will be no Negative Phase Sequence quantities present, but the device will
see that there is no voltage input. If this is caused by a power system failure, there will be a step change in the
phase currents. However, if this is not caused by a power system failure, there will be no change in any of the
phase currents. So if there is no measured voltage on any of the three phases and there is no change in any of the
phase currents, this indicates that there is a problem with the voltage transformers and a VTS block should be
applied to voltage dependent protection functions to prevent maloperation.
2.3 ABSENCE OF ALL THREE PHASE VOLTAGES ON LINE ENERGISATION

On line energization there should be a change in the phase currents as a result of loading or line charging current.
Under this condition we need an alternative method of detecting three-phase VT failure.
If there is no measured voltage on all three phases during line energization, two conditions might apply:
● A three-phase VT failure
● A close-up three-phase fault.
The first condition would require VTS to block the voltage-dependent functions.
In the second condition, voltage dependent functions should not be blocked, as tripping is required.
To differentiate between these two conditions overcurrent level detectors are used (VTS I> Inhibit and VTS I2>
Inhibit). These prevent a VTS block from being issued in case of a genuine fault. These elements should be set in
excess of any non-fault based currents on line energisation (load, line charging current, transformer inrush current
if applicable), but below the level of current produced by a close-up three-phase fault.
300 P64x-TM-EN-4.1
If the line is closed where a three-phase VT failure is present, the overcurrent detector will not operate and a VTS
block will be applied. Closing onto a three-phase fault will result in operation of the overcurrent detector and
prevent a VTS block being applied.
2.4 VTS IMPLEMENTATION

Voltage Transformer Supervision is usually used with devices with a 3-phase voltage input, such as the P643 and
P645 with the optional 3phase VT input. it can however be implemented in a P642, but only if you have ordered a
model with 2-VT inputs, and if the VTs are configured as shown in the wiring diagrams.
VTS is implemented in the SUPERVISION column of the relevant settings group, under the sub-heading VT
SUPERVISION.
The following settings are relevant for VT Supervision:
● VTS Status: determines whether the VTS Operate output will be a blocking output or an alarm indication
only
● VTS Reset Mode: determines whether the Reset is to be manual or automatic
● VTS Time delay: determines the operating time delay
● VTS I> Inhibit: inhibits VTS operation in the case of a phase overcurrent fault
● VTS I2> Inhibit: inhibits VTS operation in the case of a negative sequence overcurrent fault
VTS is only enabled during a live line condition (as indicated by the pole dead logic) to prevent operation under
dead system conditions.
P64x-TM-EN-4.1 301
2.5 VTS LOGIC

All Poles Dead
IA
VTS I> Inhibit
IB
1
VTS I> Inhibit
IC
VTS I> Inhibit
VA
Hardcoded threshold
VB
&
Hardcoded threshold 1 & S
Q
VC R 1
& VTS Slow Block
Hardcoded threshold
Delt a IA
1 & VTS Fast Block

Hardcoded threshold
Delt a IB
1 & S
Q
Hardcoded threshold
R
Delt a IC
Hardcoded threshold
V2
I2
I2>1 Current Set &
VTS Reset Mode

Ma nual &
1
Auto
MCB/VTS
VTS Status
Indicat ion
Blocking
1 S 1 VT Fail Alarm
Any Pole Dead & Q
R
&
VTS Acc Ind
Figure 139: VTS logic (P642 with 2 single-phase VTs)
302 P64x-TM-EN-4.1
All Poles Dead
IA
VTS I> Inhibit
IB
1
VTS I> Inhibit
IC
VTS I> Inhibit
VAB
Hardcoded threshold
&
VBC 1 & S
Q
R 1
Hardcoded threshold & VTS Slow Block
Delt a IA
1 & VTS Fast Block

Hardcoded threshold
Delt a IB
1 & S
Q
Hardcoded threshold
R
Delt a IC
Hardcoded threshold
V2
I2
I2>1 Current Set &
VTS Reset Mode

Ma nual &
1
Auto
MCB/VTS
VTS Status
Indicat ion
Blocking
1 S 1 VT Fail Alarm
Any Pole Dead & Q
R
&
VTS Acc Ind
Figure 140: VTS logic (P643 and P645 with 3-phase VTs)
For the P643 and P645, a 3-phase VT is used and each of the input voltages VA, VB and VC are with respect to
earth. For the P642, two single-phase VTs are used and the two input voltages VA and VB are phase-to-phase
voltages
P64x-TM-EN-4.1 303
As can be seen from the diagram, the VTS function is inhibited if:
● An All Poles Dead DDB signal is present
● A phase overcurrent condition exists
● A Negative Phase Sequence current exists
● If the phase current changes over the period of 1 cycle
The VTS will operate if:

● All three of the input voltages are lower than the VTS Pickup threshold AND the function is not inhibited by
any of the above criteria
● Negative Sequence Voltage is present AND the function is not inhibited by any of the above criteria
The NPS voltage and current detection criteria (used for the case when one or two voltage inputs are lost) is
inhibited if an Any Pole Dead signal is present.
304 P64x-TM-EN-4.1
3 CURRENT TRANSFORMER SUPERVISION

The Current Transformer Supervision function (CTS) is used to detect failure of the AC current inputs to the
protection. This may be caused by internal current transformer faults, overloading, or faults on the wiring. If there
is a failure of the AC current input, the protection could misinterpret this as a failure of the actual phase currents
on the power system, which could result in maloperation. Also, interruption in the AC current circuits can cause
dangerous CT secondary voltages to be generated.
3.1 CTS IMPLEMENTATION

Differential current transformer supervision is based on the measurement of the ratio of negative sequence
current to positive sequence current (I2/I1) for each CT. When this ratio is not zero, one of the following two
conditions may be present:
● There is an unbalanced fault
● There is a 1 or 2 phase CT problem
If the I2/I1 ratio is greater than the high set value, CTS I2/I1>2 at all ends, it is almost certainly a genuine fault
condition, thus the CTS will not operate. If this ratio is detected at one end only, one of the following conditions
may be present:
● A CT problem
● A single end fed fault condition
The positive sequence current I1 is used to confirm whether it is a CT problem or not. If I1 is greater than the
setting CTS I1 at all terminals, it must be a CT problem and CTS is allowed to operate. If this condition is detected at
only one end, the device assumes it is caused by either an inrush condition or a single-end fed internal fault. In this
case, CTS operation is blocked.
The CTS status setting under the CT SUPERVISION sub-heading can be set to either indication or
restraint. In indication mode, the CTS alarm time delay is automatically set to zero. If a CT failure is present, an
alarm would be issued without delay, but the differential protection would remain unrestricted. In restraint mode,
the differential protection is blocked for 20 ms after CT failure has been detected, after which the restraint region
of the bias characteristic increases according to the setting Is-CTS , which has been defined in the DIFF
PROTECTION column.
Idiff/In
Operating region K2
Is-CTS
K1
Is1
Restraint region
Is1/K1 Is2 Ibias/In

V01226
Figure 141: CTS restraint region increase
The low impedance REF, earth fault and NPS overcurrent protection functions are internally blocked by CTS when a
CT failure is detected in the relevant CT. However, earth fault protection is immune to CTS blocking if IN> input is
set to measured.
P64x-TM-EN-4.1 305
The CTS monitors the positive and negative sequence currents of all CTs (2 to 5, depending on the model). A faulty
CT is determined if the following conditions are present at the same time:
● The positive sequence current in at least two current inputs exceeds the set release threshold I1 (CTS I1
setting under the SUPERVISON column). This also means that CTS can only operate if minimum load current
of the protected object is present.
● A high set ratio of negative to positive sequence current, CTS I2/I1>2, is exceeded at one end.
● At all other ends the ratio of negative to positive sequence current is less than a low set value, CTS I2/I1> 1,
or no significant current is present (positive sequence current is below the release threshold I1).
Only a single or double phase CT failure can be detected by this logic. The probability of symmetrical three-phase
CT failures is very low, therefore in practice this is not a significant problem.
3.2 CTS LOGIC

CT1 I1 > CTS I1
CT2 I1 > CTS I1
CT3 I1 > CTS I1 ≥2 1 CT Fail alarm
CT4 I1 > CTS I1
CT5 I1 > CTS I1
Inhibit CTS 1
1
Inrush detector & CTS Blk
CT Exclusion Alarm
CT1 I2/I1 > CTS I2/I1>2

CT2 I2/I1 > CTS I2/I1>1 & CT1 Fail
&
CT3 I2/I1 > CTS I2/I1>1 &
CT4 I2/I1 > CTS I2/I1>1
& CTS CT1
CT5 I2/I1 > CTS I2/I1>1
CT1 I2/I1 > CTS I2/I1>1

&
CT3 I2/I1 > CTS I2/I1>1 &
CT4 I2/I1 > CTS I2/I1>1
& CTS CT2
CT5 I2/I1 > CTS I2/I1>1
CT1 I2/I1 > CTS I2/I1>1

&
CT3 I2/I1 > CTS I2/I1>2 &
CT4 I2/I1 > CTS I2/I1>1
& CTS CT3
CT5 I2/I1 > CTS I2/I1>1
CT1 I2/I1 > CTS I2/I1>1

&
CT3 I2/I1 > CTS I2/I1>1 &
CT4 I2/I1 > CTS I2/I1>2
& CTS CT4
CT5 I2/I1 > CTS I2/I1>1
CT1 I2/I1 > CTS I2/I1>1

&
CT3 I2/I1 > CTS I2/I1>1 &
CT4 I2/I1 > CTS I2/I1>1
& CTS CT5
CT5 I2/I1 > CTS I2/I1>2
1
CTS Status
Indication
Restrain
V01227
Figure 142: CTS logic diagram
306 P64x-TM-EN-4.1

The positive sequence current in at least two current inputs exceeds the CTS I1 setting. The CTS I1 setting should
be below the minimum load current of the protected object. Therefore, 10% of the rated current might be used.
The high set ratio of negative to positive sequence current, CTS I2/I1>2, should be set below the ratio of negative
sequence to positive sequence current for the minimum unbalanced fault current. When the balanced full load
current is flowing and the secondary of Phase A CT1 is disconnected, the currents measured by the device are:
IA = 0
IB = 1 Ð -120°
IC = 1 Ð -240°
The positive and negative sequence currents are calculated as:
1 2
I1 = ( I A + aI B + a 2 I C ) =
3 3
1 1
I1 = ( I A + a 2 I B + aI C ) =
3 3
The ratio of negative to positive sequence current is 50%, therefore a typical setting of 40% might be used.
The low set ratio of negative to positive sequence current, CTS I2/I1>1, should be set above the maximum load
unbalance. In practise, the levels of standing negative phase sequence current present on the system govern this
minimum setting. This can be determined from a system study, or by making use of the device's measurement
facilities at the commissioning stage. If the latter method is adopted, it is important to take the measurements
during maximum system load conditions, to ensure that all single-phase loads are accounted for. A 20% setting
might be used.
If the following information is recorded by the relay during commissioning:
I full load = 500 A
I2 = 50 A
Therefore I2/I1 ratio is given by I2/I1 = 50/500 = 0.1
To allow for tolerances and load variations a setting of 20% of this value may be typical. Therefore set CTS I2/I1>1
= 20%.
Due to the sensitive settings suggested above, a long time delay is necessary to ensure a true CT failure. We
recommend using the default setting for this time time delay. After the CTS Time Delay expires (CTS Time Delay),
the CTS Fail Alarm is asserted.
P64x-TM-EN-4.1 307
4 TRIP CIRCUIT SUPERVISION

In most protection schemes, the trip circuit extends beyond the IED enclosure and passes through components
such as links, relay contacts, auxiliary switches and other terminal boards. Such complex arrangements may
require dedicated schemes for their supervision.
There are two distinctly separate parts to the trip circuit; the trip path, and the trip coil. The trip path is the path
between the IED enclosure and the CB cubicle. This path contains ancillary components such as cables, fuses and
connectors. A break in this path is possible, so it is desirable to supervise this trip path and to raise an alarm if a
break should appear in this path.
The trip coil itself is also part of the overall trip circuit, and it is also possible for the trip coil to develop an open-
circuit fault.
This product supports a number of trip circuit supervision (TCS) schemes.
4.1 TRIP CIRCUIT SUPERVISION SCHEME 1

This scheme provides supervision of the trip coil with the CB open or closed, however, it does not provide
supervision of the trip path whilst the breaker is open. The CB status can be monitored when a self-reset trip
contact is used. However, this scheme is incompatible with latched trip contacts, as a latched contact will short out
the opto-input for a time exceeding the recommended Delayed Drop-off (DDO) timer setting of 400 ms, and
therefore does not support CB status monitoring. If you require CB status monitoring, further opto-inputs must be
used.
Note:
A 52a CB auxiliary contact follows the CB position. A 52b auxiliary contact is the opposite.
+ve
Trip Output Relay 52A Trip coil

Trip path
Blocking diode
52B
R1 Opto-input Circuit Breaker

V01214 -ve
Figure 143: TCS Scheme 1
When the CB is closed, supervision current passes through the opto-input, blocking diode and trip coil. When the
CB is open, supervision current flows through the opto-input and into the trip coil via the 52b auxiliary contact.
This means that Trip Coil supervision is provided when the CB is either closed or open, however Trip Path
supervision is only provided when the CB is closed. No supervision of the trip path is provided whilst the CB is open
(pre-closing supervision). Any fault in the trip path will only be detected on CB closing, after a 400 ms delay.
4.1.1 RESISTOR VALUES

The supervision current is a lot less than the current required by the trip coil to trip a CB. The opto-input limits this
supervision current to less than 10 mA. If the opto-input were to be short-circuited however, it could be possible for
the supervision current to reach a level that could trip the CB. For this reason, a resistor R1 is often used to limit the
current in the event of a short-circuited opto-input. This limits the current to less than 60mA. The table below
shows the appropriate resistor value and voltage setting for this scheme.
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 (ohms)
48/54 24/27 1.2k
308 P64x-TM-EN-4.1
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 (ohms)
110/125 48/54 2.7k
220/250 110/125 5.2k
Warning:
This Scheme is not compatible with Trip Circuit voltages of less than 48 V.
4.1.2 PSL FOR TCS SCHEME 1
0 0
Opto Input dropoff Straight *Output Relay
400 0
50
& pickup Latching LED
0
User Alarm
*NC stands for Normally Closed. V01217
Figure 144: PSL for TCS Scheme 1
The opto-input can be used to drive a Normally Closed Output Relay, which in turn can be used to drive alarm
equipment. The signal can also be inverted to drive a latching programmable LED and a user alarm DDB signal.
The DDO timer operates as soon as the opto-input is energised, but will take 400 ms to drop off/reset in the event
of a trip circuit failure. The 400 ms delay prevents a false alarm due to voltage dips caused by faults in other
circuits or during normal tripping operation when the opto-input is shorted by a self-reset trip contact. When the
timer is operated the NC (normally closed) output relay opens and the LED and user alarms are reset.
The 50 ms delay on pick-up timer prevents false LED and user alarm indications during the power up time,
following a voltage supply interruption.

This scheme provides supervision of the trip coil with the breaker open or closed but does not provide pre-closing
supervision of the trip path. However, using two opto-inputs allows the IED to correctly monitor the circuit breaker
status since they are connected in series with the CB auxiliary contacts. This is achieved by assigning one opto-
input to the 52a contact and another opto-input to the 52b contact. Provided the CB Status setting in the CB
CONTROL column is set to Both 52A and 52B, the IED will correctly monitor the status of the breaker. This
scheme is also fully compatible with latched contacts as the supervision current will be maintained through the
52b contact when the trip contact is closed.
+ve
Trip Output Relay Trip coil

Trip path 52A
52B
R1 Opto-input 1
Circuit Breaker
-ve
R2 Opto-input 2
V01215
P64x-TM-EN-4.1 309
When the breaker is closed, supervision current passes through opto input 1 and the trip coil. When the breaker is
open current flows through opto input 2 and the trip coil. No supervision of the trip path is provided whilst the
breaker is open. Any fault in the trip path will only be detected on CB closing, after a 400 ms delay.

Optional resistors R1 and R2 can be added to prevent tripping of the CB if either opto-input is shorted. The table
below shows the appropriate resistor value and voltage setting for this scheme.
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 and R2 (ohms)
48/54 24/27 1.2k
110/125 48/54 2.7k
220/250 110/125 5.2k
Warning:
Opto Input 1 CB Aux 3ph(52 -A)
0 0
1 dropoff straight *Output Relay
400 0
Opto Input 2 CB Aux 3ph(52 -B)
50
0
User Alarm
In TCS scheme 2, both opto-inputs must be low before a trip circuit fail alarm is given.

TCS Scheme 3 is designed to provide supervision of the trip coil with the breaker open or closed. It provides pre-
closing supervision of the trip path. Since only one opto-input is used, this scheme is not compatible with latched
trip contacts. If you require CB status monitoring, further opto-inputs must be used.
+ve
R3
Output Relay Trip coil
Trip path 52A
R2
52B
Opto-input R1 Circuit Breaker

-ve
V01216
When the CB is closed, supervision current passes through the opto-input, resistor R2 and the trip coil. When the
CB is open, current flows through the opto-input, resistors R1 and R2 (in parallel), resistor R3 and the trip coil. The
310 P64x-TM-EN-4.1
supervision current is maintained through the trip path with the breaker in either state, therefore providing pre-
closing supervision.

Resistors R1 and R2 are used to prevent false tripping, if the opto-input is accidentally shorted. However, unlike the
other two schemes. This scheme is dependent upon the position and value of these resistors. Removing them
would result in incomplete trip circuit monitoring. The table below shows the resistor values and voltage settings
required for satisfactory operation.
Opto Voltage Setting with R1
Trip Circuit Voltage Resistor R1 & R2 (ohms) Resistor R3 (ohms)
Fitted
48/54 24/27 1.2k 600
110/250 48/54 2.7k 1.2k
220/250 110/125 5.0k 2.5k
Warning:
0 0
Opto Input dropoff Straight *Output Relay
400 0
50
0
User Alarm
P64x-TM-EN-4.1 311
312 P64x-TM-EN-4.1
CHAPTER 15
DIGITAL I/O AND PSL CONFIGURATION

Chapter 15 - Digital I/O and PSL Configuration P64x
314 P64x-TM-EN-4.1
P64x Chapter 15 - Digital I/O and PSL Configuration
1 CHAPTER OVERVIEW
This chapter introduces the PSL (Programmable Scheme Logic) Editor, and describes the configuration of the digital
inputs and outputs. It provides an outline of scheme logic concepts and the PSL Editor. This is followed by details
about allocation of the digital inputs and outputs, which require the use of the PSL Editor. A separate "Settings
Application Software" document is available that gives a comprehensive description of the PSL, but enough
information is provided in this chapter to allow you to allocate the principal digital inputs and outputs.
Configuring Digital Inputs and Outputs 316
Scheme Logic 317
Configuring the Opto-Inputs 319
Assigning the Output Relays 320
Fixed Function LEDs 321
Configuring Programmable LEDs 322
Function Keys 324
Control Inputs 325
P64x-TM-EN-4.1 315
2 CONFIGURING DIGITAL INPUTS AND OUTPUTS

Configuration of the digital inputs and outputs in this product is very flexible. You can use a combination of
settings and programmable logic to customise them to your application. You can access some of the settings
using the keypad on the front panel, but you will need a computer running the settings application software to fully
interrogate and configure the properties of the digital inputs and outputs.
The settings application software includes an application called the PSL Editor (Programmable Scheme Logic
Editor). The PSL Editor lets you allocate inputs and outputs according to your specific application. It also allows you
to apply attributes to some of the signals such as a drop-off delay for an output contact.
In this product, digital inputs and outputs that are configurable are:
● Optically isolated digital inputs (opto-inputs). These can be used to monitor the status of associated plant.
● Output relays. These can be used for purposes such as initiating the tripping of circuit breakers, providing
alarm signals, etc..
● Programmable LEDs. The number and colour of the programmable LEDs varies according to the particular
product being applied.
● Function keys and associated LED indications. These are not provided on all products, but where they are,
each function key has an associated tri-colour LED.
● IEC 61850 GOOSE inputs and outputs. These are only provided on products that have been specified for
connection to an IEC61850 system, and the details of the GOOSE are presented in the documentation on
IEC61850.
316 P64x-TM-EN-4.1
3 SCHEME LOGIC
The product is supplied with pre-loaded Fixed Scheme Logic (FSL) and Programmable Scheme Logic (PSL).
The Scheme Logic is a functional module within the IED, through which all mapping of inputs to outputs is handled.
The scheme logic can be split into two parts; the Fixed Scheme Logic (FSL) and the Programmable Scheme Logic
(PSL). It is built around a concept called the digital data bus (DDB). The DDB encompasses all of the digital signals
(DDBs) which are used in the FSL and PSL. The DDBs included digital inputs, outputs, and internal signals.
The FSL is logic that has been hard-coded in the product. It is fundamental to correct interaction between various
protection and/or control elements. It is fixed and cannot be changed.
The PSL gives you a facility to develop custom schemes to suit your application if the factory-programmed default
PSL schemes do not meet your needs. Default PSL schemes are programmed before the product leaves the
factory. These default PSL schemes have been designed to suit typical applications and if these schemes suit your
requirements, you do not need to take any action. However, if you want to change the input-output mappings, or
to implement custom scheme logic, you can change these, or create new PSL schemes using the PSL editor.
The PSL consists of components such as logic gates and timers, which combine and condition DDB signals.
The logic gates can be programmed to perform a range of different logic functions. The number of inputs to a logic
gate are not limited. The timers can be used either to create a programmable delay or to condition the logic
outputs. Output contacts and programmable LEDs have dedicated conditioners.
The PSL logic is event driven. Only the part of the PSL logic that is affected by the particular input change that has
occurred is processed. This minimises the amount of processing time used by the PSL ensuring industry leading
performance.
The following diagram shows how the scheme logic interacts with the rest of the IED.
Energising quantities Protection functions Fixed LEDs

SL outputs
SL inputs
Opto-inputs Programmable LEDs

PSL and FSL
Function keys Output relays

Goose outputs
Control inputs
Goose inputs
Control input Ethernet

module processing module
V02011
Figure 149: Scheme Logic Interfaces
P64x-TM-EN-4.1 317
3.1 PSL EDITOR

The Programmable Scheme Logic (PSL) is a module of programmable logic gates and timers in the IED, which can
be used to create customised logic to qualify how the product manages its response to system conditions. The
IED's digital inputs are combined with internally generated digital signals using logic gates, timers, and
conditioners. The resultant signals are then mapped to digital outputs signals including output relays and LEDs.
The PSL Editor is a tool in the settings application software that allows you to create and edit scheme logic
diagrams. You can use the default scheme logic which has been designed to suit most applications, but if it does
not suit your application you can change it. If you create a different scheme logic with the software, you need to
upload it to the device to apply it.
3.2 PSL SCHEMES

Your product is shipped with default scheme files. These can be used without modification for most applications, or
you can choose to use them as a starting point to design your own scheme. You can also create a new scheme
from scratch. To create a new scheme, or to modify an existing scheme, you will need to launch the settings
application software. You then need to open an existing PSL file, or create a new one, for the particular product
that you are using, and then open a PSL file. If you want to create a new PSL file, you should select File then New
then Blank scheme... This action opens a default file appropriate for the device in question, but deletes the
diagram components from the default file to leave an empty diagram with configuration information loaded. To
open an existing file, or a default file, simply double-click on it.
3.3 PSL SCHEME VERSION CONTROL

To help you keep track of the PSL loaded into products, a version control feature is included. The user interface
contains a PSL DATA column, which can be used to track PSL modifications. A total of 12 cells are contained in the
PSL DATA column; 3 for each setting group.
Grp(n) PSL Ref: When downloading a PSL scheme to an IED, you will be prompted to enter the relevant group
number and a reference identifier. The first 32 characters of the reference identifier are displayed in this cell. The
horizontal cursor keys can scroll through the 32 characters as the LCD display only displays 16 characters.
Example:
Grp(n) PSL Ref
Date/time: This cell displays the date and time when the PSL scheme was downloaded to the IED.
Example:
18 Nov 2002
08:59:32.047
Grp(n) PSL ID: This cell displays a unique ID number for the downloaded PSL scheme.
Example:
Grp(n) PSL ID
ID - 2062813232
318 P64x-TM-EN-4.1
4 CONFIGURING THE OPTO-INPUTS

The number of optically isolated status inputs (opto-inputs) depends on the specific model supplied. The use of the
inputs will depend on the application, and their allocation is defined in the programmable scheme logic (PSL). In
addition to the PSL assignment, you also need to specify the expected input voltage. Generally, all opto-inputs will
share the same input voltage range, but if different voltage ranges are being used, this device can accommodate
them.
In the OPTO CONFIG column there is a global nominal voltage setting. If all opto-inputs are going to be energised
from the same voltage range, you select the appropriate value in the setting. If you select Custom in the setting,
then the cells Opto Input 1, Opto Input 2, etc. become visible. You use these cells to set the voltage ranges for
each individual opto-input.
Within the OPTO CONFIG column there are also settings to control the filtering applied to the inputs, as well as the
pick-up/drop-off characteristic.
The filter control setting provides a bit string with a bit associated with all opto-inputs. Setting the bit to ‘1’ means
that a half-cycle filter is applied to the inputs. This helps to prevent incorrect operation in the event of power
system frequency interference on the wiring. Setting the field to ‘0’ removes the filter and provides for faster
operation.
The Characteristic setting is a single setting that applies to all the opto-inputs. It is used to set the pick-up/drop-
off ratios of the input signals. As standard it is set to 80% pick-up and 60% drop-off, but you can change it to other
available thresholds if that suits your operational requirements.
P64x-TM-EN-4.1 319
5 ASSIGNING THE OUTPUT RELAYS

Relay contact action is controlled using the PSL. DDB signals are mapped in the PSL and drive the output relays.
The driving of an output relay is controlled by means of a relay output conditioner. Several choices are available for
how output relay contacts are conditioned. For example, you can choose whether operation of an output relay
contact is latched, has delay on pick-up, or has a delay on drop-off. You make this choice in the Contact
Properties window associated with the output relay conditioner.
To map an output relay in the PSL you should use the Contact Conditioner button in the toolbar to import it. You
then condition it according to your needs. The output of the conditioner respects the attributes you have assigned.
The toolbar button for a Contact Conditioner looks like this:
The PSL contribution that it delivers looks like this:
Note:
Contact Conditioners are only available if they have not all been used. In some default PSL schemes, all Contact Conditioners
might have been used. If that is the case, and you want to use them for something else, you will need to re-assign them.
On the toolbar there is another button associated with the relay outputs. The button looks like this:
This is the "Contact Signal" button. It allows you to put replica instances of a conditioned output relay into the PSL,
preventing you having to make cross-page connections which might detract from the clarity of the scheme.
320 P64x-TM-EN-4.1
6 FIXED FUNCTION LEDS

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.
● Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is
cleared from the front display. Also the trip LED can be configured as self-resetting.
● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or
maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.
● Out of service (Yellow) is ON when the IED's functions are unavailable.
● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if
the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.
6.1 TRIP LED LOGIC

When a trip occurs, the trip LED is illuminated. It is possible to reset this with a number of ways:
● Directly with a reset command (by pressing the Clear Key)
● With a reset logic input
● With self-resetting logic
You enable the automatic self-resetting with the Sys Fn Links cell in the SYSTEM DATA column. A '0' disables self
resetting and a '1' enables self resetting.
The reset occurs when the circuit is reclosed and the Any Pole Dead signal has been reset for three seconds
providing the Any Start signal is inactive. The reset is prevented if the Any Start signal is active after the breaker
closes.
The Trip LED logic is as follows:
Any Trip S
Q Trip LED Trigger
Reset R
1
Reset Relays/LED
Sys Fn Links
Trip LED S/Reset
3s
&
Any Pole Dead
Any Start
V01211
Figure 150: Trip LED logic
P64x-TM-EN-4.1 321
7 CONFIGURING PROGRAMMABLE LEDS

There are three types of programmable LED signals which vary according to the model being used. These are:
● Single-colour programmable LED. These are red when illuminated.
● Tri-colour programmable LED. These can be illuminated red, green, or amber.
● Tri-colour programmable LED associated with a Function Key. These can be illuminated red, green, or
amber.
DDB signals are mapped in the PSL and used to illuminate the LEDs. For single-coloured programmable LEDs there
is one DDB signal per LED. For tri-coloured LEDs there are two DDB signals associated with the LED. Asserting LED
# Grn will illuminate the LED green. Asserting LED # Red will illuminate the LED red. Asserting both DDB signals will
illuminate the LED amber.
The illumination of an LED is controlled by means of a conditioner. Using the conditioner, you can decide whether
the LEDs reflect the real-time state of the DDB signals, or whether illumination is latched pending user intervention.
To map an LED in the PSL you should use the LED Conditioner button in the toolbar to import it. You then condition
it according to your needs. The output(s) of the conditioner respect the attribute you have assigned.
The toolbar button for a tri-colour LED looks like this:
The PSL contribution that it delivers looks like this:
The toolbar button for a single-colour LED looks like this:
The PSL contribution that it delivers looks like this.
Note:
LED Conditioners are only available if they have not all been used up, and in some default PSL schemes they might be. If that
is the case and you want to use them for something else, you will need to re-assign them.
On the toolbar there is another button associated with the LEDs. For a tri-coloured LED the button looks like this:
For a single-colour LED it looks like this:
It is the "LED Signal" button. It allows you to put replica instances of a conditioned LED into the PSL, preventing you
having to make cross-page connections which might detract from the clarity of the scheme.
322 P64x-TM-EN-4.1
Note:
All LED DDB signals are always shown in the PSL Editor. However, the actual number of LEDs depends on the device
hardware. For example, if a small 20TE device has only 4 programmable LEDs, LEDs 5-8 will not take effect even if they are
mapped in the PSL.
P64x-TM-EN-4.1 323
8 FUNCTION KEYS
For most models, a number of programmable function keys are available. This allows you to assign function keys
to control functionality via the programmable scheme logic (PSL). Each function key is associated with a
programmable tri-colour LED, which you can program to give the desired indication on activation of the function
key.
These function keys can be used to trigger any function that they are connected to as part of the PSL. The function
key commands are found in the FUNCTION KEYS column.
Each function key is associated with a DDB signal as shown in the DDB table. You can map these DDB signals to
any function available in the PSL.
The Fn Key Status cell displays the status (energised or de-energised) of the function keys by means of a binary
string, where each bit represents a function key starting with bit 0 for function key 1.
Each function key has three settings associated with it, as shown:
● Fn Key (n), which enables or disables the function key
● Fn Key (n) Mode, which allows you to configure the key as toggled or normal
● Fn Key (n) label, which allows you to define the function key text that is displayed
The Fn Key (n) cell is used to enable (unlock) or disable (unlock) the function key signals in PSL. The Lock setting has
been provided to prevent further activation on subsequent key presses. This allows function keys that are set to
Toggled mode and their DDB signal active ‘high’, to be locked in their active state therefore preventing any
further key presses from deactivating the associated function. Locking a function key that is set to the “Normal”
mode causes the associated DDB signals to be permanently off. This safety feature prevents any inadvertent
function key presses from activating or deactivating critical functions.
When the Fn Key (n) Mode cell is set to Toggle, the function key DDB signal output will remain in the set state
until a reset command is given. In the Normal mode, the function key DDB signal will remain energised for as long
as the function key is pressed and will then reset automatically. In this mode, a minimum pulse duration can be
programmed by adding a minimum pulse timer to the function key DDB output signal.
The Fn Key Label cell makes it possible to change the text associated with each individual function key. This text
will be displayed when a function key is accessed in the function key menu, or it can be displayed in the PSL.
The status of all function keys are recorded in non-volatile memory. In case of auxiliary supply interruption their
status will be maintained.
Note:
All function key DDB signals are always shown in the PSL Editor. However, the actual number of function keys depends on the
device hardware. For example, if a small 20TE device has no function keys, the function key DDBs mapped in the PSL will not
take effect.
324 P64x-TM-EN-4.1
9 CONTROL INPUTS
The control inputs are software switches, which can be set or reset locally or remotely. These inputs can be used to
trigger any PSL function to which they are connected. There are three setting columns associated with the control
inputs: CONTROL INPUTS, CTRL I/P CONFIG and CTRL I/P LABELS. These are listed in the Settings and Records
appendix at the end of this manual.
P64x-TM-EN-4.1 325
326 P64x-TM-EN-4.1
CHAPTER 16
COMMUNICATIONS
Chapter 16 - Communications P64x
328 P64x-TM-EN-4.1
P64x Chapter 16 - Communications
1 CHAPTER OVERVIEW
This product supports Substation Automation System (SAS), and Supervisory Control and Data Acquisition (SCADA)
communication. The support embraces the evolution of communications technologies that have taken place since
microprocessor technologies were introduced into protection, control, and monitoring devices which are now
ubiquitously known as Intelligent Electronic Devices for the substation (IEDs).
As standard, all products support rugged serial communications for SCADA and SAS applications. By option, any
product can support Ethernet communications for more advanced SCADA and SAS applications.

Communication Interfaces 330
Serial Communication 331
Standard Ethernet Communication 334
Redundant Ethernet Communication 335
Data Protocols 352
Read Only Mode 396
Time Synchronisation 398
P64x-TM-EN-4.1 329
2 COMMUNICATION INTERFACES
The products have a number of standard and optional communication interfaces. The standard and optional
hardware and protocols are summarised below:
Port Availability Physical layer Use Data Protocols
Front Standard RS232 Local settings Courier
Rear Port 1 RS232 / RS485 / K- SCADA Courier, MODBUS, IEC60870-5-103, DNP3.0
Standard
(RP1 copper) Bus Remote settings (order option)
Rear Port 1 SCADA Courier, MODBUS, IEC60870-5-103, DNP3.0
Optional Fibre
(RP1 fibre) Remote settings (order option)
Rear Port 2 RS232 / RS485 / K- SCADA SK4: Courier only
Optional
(RP2) Bus Remote settings SK5: InterMicom only
IEC 61850 or DNP3 IEC 61850, Courier (tunnelled) or DNP3.0
Ethernet Optional Ethernet
Remote settings (order option)
Note:
Optional communications boards are always fitted into slot A.
Note:
It is only possible to fit one optional communications board, therefore RP2 and Ethernet communications are mutually
exclusive.
330 P64x-TM-EN-4.1
3 SERIAL COMMUNICATION
The physical layer standards that are used for serial communications for SCADA purposes are:
● EIA(RS)485 (often abbreviated to RS485)
● K-Bus (a proprietary customization of RS485)
EIA(RS)232 is used for local communication with the IED (for transferring settings and downloading firmware
updates).
RS485 is similar to RS232 but for longer distances and it allows daisy-chaining and multi-dropping of IEDs.
K-Bus is a proprietary protocol quite similar to RS485, but it cannot be mixed on the same link as RS485. Unlike
RS485, K-Bus signals applied across two terminals are not polarised.
It is important to note that these are not data protocols. They only describe the physical characteristics required
for two devices to communicate with each other.
For a description of the K-Bus standard see K-Bus (on page332) and General Electric's K-Bus interface guide
reference R6509.
A full description of the RS485 is available in the published standard.
3.1 EIA(RS)232 BUS

The EIA(RS)232 interface uses the IEC 60870-5 FT1.2 frame format.
The device supports an IEC 60870-5 FT1.2 connection on the front-port. This is intended for temporary local
connection and is not suitable for permanent connection. This interface uses a fixed baud rate of 19200 bps, 11-bit
frame (8 data bits, 1 start bit, 1 stop bit, even parity bit), and a fixed device address of '1'.
EIA(RS)232 interfaces are polarised.
3.2 EIA(RS)485 BUS

The RS485 two-wire connection provides a half-duplex, fully isolated serial connection to the IED. The connection is
polarized but there is no agreed definition of which terminal is which. If the master is unable to communicate with
the product, and the communication parameters match, then it is possible that the two-wire connection is
reversed.
The RS485 bus must be terminated at each end with 120 Ω 0.5 W terminating resistors between the signal wires.
The RS485 standard requires that each device be directly connected to the actual bus. Stubs and tees are
forbidden. Loop bus and Star topologies are not part of the RS485 standard and are also forbidden.
Two-core screened twisted pair cable should be used. The final cable specification is dependent on the application,
although a multi-strand 0.5 mm2 per core is normally adequate. The total cable length must not exceed 1000 m. It
is important to avoid circulating currents, which can cause noise and interference, especially when the cable runs
between buildings. For this reason, the screen should be continuous and connected to ground at one end only,
normally at the master connection point.
The RS485 signal is a differential signal and there is no signal ground connection. If a signal ground connection is
present in the bus cable then it must be ignored. At no stage should this be connected to the cable's screen or to
the product’s chassis. This is for both safety and noise reasons.
It may be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal level has an
indeterminate state because the bus is not being actively driven. This can occur when all the slaves are in receive
mode and the master is slow to turn from receive mode to transmit mode. This may be because the master is
waiting in receive mode, in a high impedance state, until it has something to transmit. Jabber causes the receiving
device(s) to miss the first bits of the first character in the packet, which results in the slave rejecting the message
and consequently not responding. Symptoms of this are; poor response times (due to retries), increasing message
error counts, erratic communications, and in the worst case, complete failure to communicate.
P64x-TM-EN-4.1 331
3.2.1 EIA(RS)485 BIASING REQUIREMENTS

Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1 V. There should only be
one bias point on the bus, which is best situated at the master connection point. The DC source used for the bias
must be clean to prevent noise being injected.
Note:
Some devices may be able to provide the bus bias, in which case external components would not be required.
6 – 9 V DC
180 Ω bias
Master 120 Ω
180 Ω bias
0V 120 Ω
Slave Slave Slave
V01000
Figure 151: RS485 biasing circuit
Warning:
It is extremely important that the 120 Ω termination resistors are fitted. Otherwise
the bias voltage may be excessive and may damage the devices connected to the
bus.
3.3 K-BUS
K-Bus is a robust signalling method based on RS485 voltage levels. K-Bus incorporates message framing, based on
a 64 kbps synchronous HDLC protocol with FM0 modulation to increase speed and security.
The rear interface is used to provide a permanent connection for K-Bus, which allows multi-drop connection.
A K-Bus spur consists of up to 32 IEDs connected together in a multi-drop arrangement using twisted pair wiring.
The K-Bus twisted pair connection is non-polarised.
It is not possible to use a standard EIA(RS)232 to EIA(RS)485 converter to convert IEC 60870-5 FT1.2 frames to K-
Bus. A protocol converter, namely the KITZ101, KITZ102 or KITZ201, must be used for this purpose. Please consult
General Electric for information regarding the specification and supply of KITZ devices. The following figure
demonstrates a typical K-Bus connection.
332 P64x-TM-EN-4.1
C C C
IED IED IED
RS232 K-Bus
Computer RS232-USB converter KITZ protocol converter

V01001
Figure 152: Remote communication using K-Bus
Note:
An RS232-USB converter is only needed if the local computer does not provide an RS232 port.
Further information about K-Bus is available in the publication R6509: K-Bus Interface Guide, which is available on
request.
P64x-TM-EN-4.1 333
4 STANDARD ETHERNET COMMUNICATION

The type of Ethernet board depends on the chosen model. The available boards and their features are described in
the Hardware Design chapter of this manual.
The Ethernet interface is required for either IEC 61850 or DNP3 over Ethernet (protocol must be selected at time of
order). With either of these protocols, the Ethernet interface also offers communication with the settings
application software for remote configuration and record extraction.
Fibre optic connection is recommended for use in permanent connections in a substation environment, as it offers
advantages in terms of noise rejection. The fibre optic port provides 100 Mbps communication and uses type
BFOC 2.5 (ST) connectors. Fibres should be suitable for 1300 nm transmission and be multimode 50/125 µm or
62.5/125 µm.
Connection can also be made to a 10Base-T or a 100Base-TX Ethernet switch using the RJ45 port.
334 P64x-TM-EN-4.1
5 REDUNDANT ETHERNET COMMUNICATION

Redundancy is required where a single point of failure cannot be tolerated. It is required in critical applications
such as substation automation. Redundancy acts as an insurance policy, providing an alternative route if one
route fails.
Ethernet communication redundancy is available for most General Electric products, using a Redundant Ethernet
Board (REB). The REB is a Network Interface Card (NIC), which incorporates an integrated Ethernet switch. The
board provides two Ethernet transmitter/receiver pairs.
In addition to the two Ethernet transmitter/receiver pairs, the REB provides link activity indication in the form of
LEDs, link fail indication in the form of watchdog contacts, and a dedicated time synchronisation input.
The dedicated time synchronisation input is designed to connect to an IRIG-B signal. Both modulated and un-
modulated IRIG-B formats are supported according to the selected option. Simple Network Time Protocol (SNTP) is
supported over the Ethernet communications.
5.1 SUPPORTED PROTOCOLS

A range of Redundant Ethernet Boards are available to support different protocols for different requirements. One
of the key requirements of substation redundant communications is "bumpless" redundancy. This means the
ability to transfer from one communication path to another without noticeable consequences. Standard protocols
of the time could not meet the demanding requirements of network availability for substation automation
solutions. Switch-over times were unacceptably long. For this reason, companies developed proprietary protocols.
More recently, however, standard protocols, which support bumpless redundancy (namely PRP and HSR) have
been developed and ratified.
As well as supporting standard non-bumpless protocols such as RSTP, the REB was originally designed to support
bumpless redundancy, using proprietary protocols (SHP, DHP) before the standard protocols became available.
Since then, variants have been produced for the newer standard protocols.
REB variants for each of the following protocols are available:
● PRP (Parallel Redundancy Protocol)
● HSR (High-availability Seamless Redundancy)
● RSTP (Rapid Spanning Tree Protocol)
● Failover
Note:
The protocol you require must be selected at the time of ordering.
5.2 PARALLEL REDUNDANCY PROTOCOL

PRP (Parallel Reundancy Protocol) is defined in IEC 62439-3. PRP provides bumpless redundancy and meets the
most demanding needs of substation automation. The PRP implementation of the REB is compatible with any
standard PRP device.
PRP uses two independent Ethernet networks operating in parallel. PRP systems are designed so that there should
be no common point of failure between the two networks, so the networks have independent power sources and
are not connected together directly.
Devices designed for PRP applications have two ports attached to two separate networks and are called Doubly
Attached Nodes (DAN). A DAN has two ports, one MAC address and one IP address.
The sending node replicates each frame and transmits them over both networks. The receiving node processes the
frame that arrives first and discards the duplicate. Therefore there is no distinction between the working and
backup path. The receiving node checks that all frames arrive in sequence and that frames are correctly received
on both ports.
P64x-TM-EN-4.1 335
Devices such as printers that have a single Ethernet port can be connected to either of the networks but will not
directly benefit from the PRP principles. Such devices are called Singly Attached Nodes (SAN). For devices with a
single Ethernet port that need to connect to both LANs, this can be achieved by employing Ethernet Redundancy
Boxes (sometimes abbreviated to RedBox). Devices with a single Ethernet port that connect to both LANs by
means of a RedBox are known as Virtual DAN (VDAN).
The figure below summarises DAN, SAN, VDAN, LAN, and RedBox connectivity.
DAN DAN
SAN DAN
LAN B
LAN A
REDUNDANCY
BOX
VDAN
VDAN SAN SAN
VDAN
E01028
Figure 153: IED attached to separate LANs
In a DAN, both ports share the same MAC address so it does not affect the way devices talk to each other in an
Ethernet network (Address Resolution Protocol at layer 2). Every data frame is seen by both ports.
When a DAN sends a frame of data, the frame is duplicated on both ports and therefore on both LAN segments.
This provides a redundant path for the data frame if one of the segments fails. Under normal conditions, both LAN
segments are working and each port receives identical frames.
336 P64x-TM-EN-4.1
5.2.1 PRP APPLICATION IN THE SUBSTATION
MiCOM H382
SCADA or DS Agile
DS Agile gateways
H600 switch H600 switch
Ethernet
Up to
C C
6 links C264
L/R L/R C
C264 H368 Px4x

Ethernet
Up to
4 links
C
L/R C
RS485
Bay level C Bay level Bay level

Type 1 Type 2 Type 3
TX copper link
FX optical fibre Ethernet
E01070 RS485, RS422
Figure 154: PRP application in the substation
5.3 HIGH-AVAILABILITY SEAMLESS REDUNDANCY (HSR)

HSR is standardized in IEC 62439-3 (clause 5) for use in ring topology networks. Similar to PRP, HSR provides
bumpless redundancy and meets the most demanding needs of substation automation. HSR has become the
reference standard for ring-topology networks in the substation environment. The HSR implementation of the
redundancy Ethernet board (REB) is compatible with any standard HSR device.
HSR works on the premise that each device connected in the ring is a doubly attached node running HSR (referred
to as DANH). Similar to PRP, singly attached nodes such as printers are connected via Ethernet Redundancy Boxes
(RedBox).
5.3.1 HSR MULTICAST TOPOLOGY

When a DANH is sending a multicast frame, the frame (C frame) is duplicated (A frame and B frame), and each
duplicate frame A/B is tagged with the destination MAC address and the sequence number. The frames A and B
differ only in their sequence number, which is used to identify one frame from the other. Each frame is sent to the
network via a separate port. The destination DANH receives two identical frames, removes the HSR tag of the first
frame received and passes this (frame D) on for processing. The other duplicate frame is discarded. The nodes
forward frames from one port to the other unless it was the node that injected it into the ring.
P64x-TM-EN-4.1 337
Source
DANH DANH Redbox Switch
D frame C frame D frame

A frame B frame
Singly Attached
Nodes
D frame D frame D frame
DANH DANH DANH

V01030
Figure 155: HSR multicast topology
Only about half of the network bandwidth is available in HSR for multicast or broadcast frames because both
duplicate frames A & B circulate the full ring.
5.3.2 HSR UNICAST TOPOLOGY

With unicast frames, there is just one destination and the frames are sent to that destination alone. All non-
recipient devices simply pass the frames on. They do not process them in any way. In other words, D frames are
produced only for the receiving DANH. This is illustrated below.
338 P64x-TM-EN-4.1
Source
DANH DANH Redbox Switch
C frame
A frame B frame
Singly Attached
Nodes
D frame
DANH DANH DANH
Destination V01031
Figure 156: HSR unicast topology
For unicast frames, the whole bandwidth is available as both frames A & B stop at the destination node.
5.3.3 HSR APPLICATION IN THE SUBSTATION
P64x-TM-EN-4.1 339
T1000 switch
LINK
RX
PC SCADA
TX
reset LINK
RX
TX
DS Agile gateways
Px4x H49 H49 H49 Px4x
C C
C C C C C C
Px4x Px4x Px4x Px4x Px4x Px4x
Bay 1 Bay 2 Bay 3

E01066
Figure 157: HSR application in the substation
5.4 RAPID SPANNING TREE PROTOCOL

RSTP is a standard used to quickly reconnect a network fault by finding an alternative path. It stops network loops
whilst enabling redundancy. It can be used in star or ring connections as shown in the following figure.
Switch 1 Switch 2 Switch 1 Switch 2
IED 1 IED 2 IED 1 IED 2
Star connection with redundant ports Ring connection managed by RST P

managed by RSTP blocking function . blocking function on upper switches
and IEDs interconnected directly .
V01010
Figure 158: IED attached to redundant Ethernet star or ring circuit
The RSTP implementation in this product is compatible with any devices that use RSTP.
RSTP can recover network faults quickly, but the fault recovery time depends on the number of devices on the
network and the network topology. A typical figure for the fault recovery time is 300ms. Therefore, RSTP cannot
achieve the “bumpless” redundancy that some other protocols can.
Refer to IEEE 802.1D 2004 standard for detailed information about the opration of the protocol.
340 P64x-TM-EN-4.1
5.5 CONFIGURING IP ADDRESSES

An IP address is a logical address assigned to devices in a computer network that uses the Internet Protocol (IP) for
communication between nodes. IP addresses are stored as binary numbers but they are represented using
Decimal Dot Notation, where four sets of decimal numbers are separated by dots as follows:
XXX.XXX.XXX.XXX
For example:
10.86.254.85
An IP address in a network is usually associated with a subnet mask. The subnet mask defines which network the
device belongs to. A subnet mask has the same form as an IP address.
For example:
255.255.255.0
Both the IED and the REB each have their own IP address. The following diagram shows the IED as IP1 and the REB
as IP2.
Note:
IP1 and IP2 are different but use the same subnet mask.
The switch IP address must be configured through the Ethernet network.
Set by IED Configurator
IED (IP1) AAA.BBB.CCC.DDD
REB (IP2) WWW.XXX.YYY.ZZZ

Set by Hardware Dip Switch SW2 for SHP, DHP
Set by Redundant Ethernet Configurator for PRP, HSR or
Set by Switch Manager for SHP and DHP RSTP
Set by Redundant Ethernet Configurator for
PRP, HSR or RSTP Fixed at 254 for SHP or DHP
Set by Redundant Ethernet Configurator for PRP, HSR or RSTP
V01069
Figure 159: IED and REB IP address configuration
5.5.1 CONFIGURING THE IED IP ADDRESS

If you are using IEC 61850, set the IED IP address using the IEC 61850 Configurator software. In the IEC 61850
Configurator, set Media to Single Copper or Redundant Fibre.
If you are using DNP3 over Ethernet, set the IED IP address by editing the DNP3 file, using the DNP3 Configurator
software. In the DNP3 Configurator, set Ethernet Media to Copper, even though the redundant Ethernet network
uses fibre optic cables.
5.5.2 CONFIGURING THE REB IP ADDRESS

The board IP address must be configured before connecting the IED to the network to avoid an IP address conflict.
The way you configure the IP address depends on the redundancy protocol you have chosen.
PRP/HSR
If using PRP or HSR, you configure the REB IP address using the PRP/HSR Configurator software.
P64x-TM-EN-4.1 341
RSTP
If using RSTP, you configure the REB IP address using the PRP/HSR Configurator software.
5.6 REDUNDANT ETHERNET CONFIGURATOR

The Redundant Ethernet Configurator tool is intended for MiCOM Px4x IEDs with redundant Ethernet using PRP
(Parallel Redundancy Protocol), or HSR (High-availability Seamless Redundancy). This tool is used to identify IEDs,
switch between PRP and HSR or configure their parameters, configure the redundancy IP address, or configure the
SNTP IP address.
5.6.1 CONNECTING THE IED TO A PC

Connect the IED to the PC on which the Configurator tool is used. This connection is done through an Ethernet
switch or through a media converter.
RJ45
Ethernet switch
Media
Converter
TXA RXA TXB RXB
TX RX
RXA TXA RXB TXB RXA TXA RXB TXB
IED IED
(a) (b)
V01806
Figure 160: Connection using (a) an Ethernet switch and (b) a media converter
5.6.2 INSTALLING THE CONFIGURATOR

To install the configurator:
1. Double click the WinPcap installer.
2. Double click the Configurator installer.
3. Click Next and follow the on-screen instructions.
342 P64x-TM-EN-4.1
5.6.3 STARTING THE CONFIGURATOR

To start the configurator:
1. Select the Configurator from the Windows Programs menu.
2. The Login screen appears. For user mode login, enter the Login name as User and click OK with no
password.
3. If the login screen does not appear, check all network connections.
4. The main window appears. In the bottom right-hand corner of the main window, click the Language button
to select the language.
5. The Network Board drop-down list shows the Network Board, IP Address and MAC Address of the PC in
which the Configurator is running.
5.6.4 PRP/HSR DEVICE IDENTIFICATION

To configure the redundant Ethernet board, go to the main window and click the Identify Device button. A list of
devices are shown with the following details:
● Device address
● MAC address
● Version number of the firmware
● SNTP IP address
● Date & time of the real-time clock, from the board.
Select the device you wish to configure. The MAC address of the selected device is highlighted.
5.6.5 SELECTING THE DEVICE MODE

You must now select the device mode that you wish to use. This will be either PRP or HSR. To do this, select the
appropriate radio button then click the Update button. You will be asked to confirm a device reboot. Click OK to
confirm.
5.6.6 PRP/HSR IP ADDRESS CONFIGURATION

To change the network address component of the IP address:
1. From the main window click the IP Config button. The Device setup screen appears.
2. Enter the required board IP address and click OK. This is the redundancy network address, not the IEC 61850
IP address.
3. The board network address is updated and displayed in the main window.
5.6.7 SNTP IP ADDRESS CONFIGURATION

To Configure the SNTP server IP address:
1. From the main window click the SNTP Config button. The Device setup screen appears.
2. Enter the required MAC SNTP address and server IP SNTP Address. Click OK.
3. The updated MAC and IP SNTP addresses appear in the main screen.
P64x-TM-EN-4.1 343
5.6.8 CHECK FOR CONNECTED EQUIPMENT

To check what devices are connected to the device being monitored:
1. From the main window, select the device.
2. Click the Equipment button.
3. At the bottom of the main window, a box shows the ports where devices are connected and their MAC
addresses.
5.6.9 PRP CONFIGURATION

To view or configure the PRP Parameters:
1. Ensure that you have set the device mode to PRP.
2. Click the PRP/HSR Config button. The PRP Config screen appears.
3. To view the available parameters, click the Get PRP Parameters button.
4. To change the parameters, click the Set Parameters button and modify their values.
If you need to restore the default values of the parameters, click the Restore Defaults button.
The configurable parameters are as follows:
● Multicast Address: Use this field to configure the multicast destination address. All DANPs in the network
must be configured to operate with the same multicast address for the purpose of network supervision.
● Node Forget Time: This is the time after which a node entry is cleared in the nodes table.
● Life Check Interval: This defines how often a node sends a PRP_Supervision frame. All DANPs shall be
configured with the same Life Check Interval.
5.6.10 HSR CONFIGURATION

To view or configure the HSR Parameters:
1. Click the PRP/HSR Config button. The HSR Config screen appears.
2. To view the available parameters in the board that is connected, click the Retrieve HSR Parameters from
IED button.
3. To change the parameters, click the Set Parameters button and modify their values.
If you need to restore the default values of the parameters, click the Restore Defaults button.
The configurable parameters are as follows:
● Multicast Address: Use this field to configure the multicast destination address. All DANPs in the network
must be configured to operate with the same multicast address for the purpose of network supervision.
● Node Forget Time: This is the time after which a node entry is cleared in the nodes table.
● Life Check Interval: This defines how often a node sends a PRP_Supervision frame. All DANPs must be
configured with the same Life Check Interval.
● Proxy Node Table Forget Time: This is the time after which a node entry is cleared in the ProxyTable
● Proxy Node Table Max Entries: This is the maximum number of entries in the ProxyTable
● Entry Forget Time: This is the time after which an entry is removed from the duplicates
● Node Reboot Interval: This is the minimum time during which a node that reboots remains silent
5.6.11 FILTERING DATABASE

The Filtering Database is used to determine how frames are forwarded or filtered across the on-board Ethernet
switch. Filtering information specifies the set of ports to which frames received from a specific port are forwarded.
The Ethernet switch examines each received frame to see if the frame's destination address matches a source
address listed in the Filtering Database. If there is a match, the device uses the filtering/forwarding information for
344 P64x-TM-EN-4.1
that source address to determine how to forward or filter the frame. Otherwise the frame is forwarded to all the
ports in the Ethernet switch (broadcast).
General tab
The Filtering Database contains two types of entry; static and dynamic. The Static Entries are the source addresses
entered by an administrator. The Dynamic Entries are the source addresses learnt by the switch process. The
Dynamic Entries are removed from the Filtering Database after the Ageing Time. The Database holds a maximum
of 1024 entries.
1. To access the forwarding database functions, if required, click the Filtering Database button in the main
window.
2. To view the Forwarding Database Size, Number of Static Entries and Number of Dynamic Entries, click Read
Database Info.
3. To set the Aging Time, enter the number of seconds in the text box and click the Set button.
Filtering Entries tab

The Filtering Database configuration pages are used to view, add or delete entries from the Filtering Database. This
feature is available only for the administrator. This Filtering Database is mainly used during the testing to verify the
PRP/HSR functionality. To add an entry in the forwarding database, click the Filtering Entries tab. Configure as
follows:
1. Select the Port Number and MAC Address
2. Set the Entry type (Dynamic or Static)
3. Set the cast type (Unicast or Multicast)
4. Set theMGMT and Rate Limit
5. Click the Create button. The new entry appears in the forwarding database.
To delete an entry from the forwarding database, select the entry and click the Delete Entry button.
Goose Filtering tab

This page configures the source MACs from which GOOSE messages will be allowed or blocked. The filtering can be
configured by either the MAC address range boxes or by selecting or unselecting the individual MAC addresses in
the MAC table. After you have defined the addresses to be allowed or blocked you need to update the table and
apply the filter:
● Update Table: This updates the MAC table according to the filtering range entered in the MAC address
range boxes.
● Apply Filter: This applies the filtering configuration in the MAC table to the HSR/PRP board.
5.6.12 END OF SESSION

To finish the session:
1. In the main window, click the Quit button, a new screen appears.
2. If a database backup is required, click Yes, a new screen appears.
3. Click the ... button to browse the path. Enter the name in the text box.
5.7 RSTP CONFIGURATOR

The RSTP Configurator tool is intended for MiCOM Px4x IEDs with redundant Ethernet using RSTP (Rapid Spanning
Tree Protocol). This tool is used to identify IEDs, configure the redundancy IP address, configure the SNTP IP
address and configure the RSTP parameters.
P64x-TM-EN-4.1 345
5.7.1 CONNECTING THE IED TO A PC

Connect the IED to the PC on which the Configurator tool is used. This connection is done through an Ethernet
switch or through a media converter.
RJ45
Ethernet switch
Media
Converter
TX1 RX1 TX2 RX2
TX RX
RX1 TX1 RX2 TX2 RX1 TX1 RX2 TX2
IED IED
(a) (b)
V01803
Figure 161: Connection using (a) an Ethernet switch and (b) a media converter
5.7.2 INSTALLING THE CONFIGURATOR

To install the configurator:
1. Double click the WinPcap installer.
2. Double click the Configurator installer.
3. Click Next and follow the on-screen instructions.
5.7.3 STARTING THE CONFIGURATOR

To start the configurator:
1. Select the Configurator from the Windows Programs menu.
2. The Login screen appears. For user mode login, enter the Login name as User and click OK with no
password.
3. If the login screen does not appear, check all network connections.
4. The main window appears. In the bottom right-hand corner of the main window, click the Language button
to select the language.
5. The Network Board drop-down list shows the Network Board, IP Address and MAC Address of the PC in
which the Configurator is running.
346 P64x-TM-EN-4.1
5.7.4 RSTP DEVICE IDENTIFICATION

To configure the redundant Ethernet board, go to the main window and click Identify Device.
Note:
Due to the time needed to establish the RSTP protocol, wait 25 seconds between connecting the PC to the IED and clicking the
Identify Device button.
The redundant Ethernet board connected to the PC is identified and its details are listed.
● Device address
● MAC address
● Version number of the firmware
● SNTP IP address
● Date & time of the real-time clock, from the board.
5.7.5 RSTP IP ADDRESS CONFIGURATION

To change the network address component of the IP address,
1. From the main window click the IP Config button.
2. The Device Setup screen appears showing the IP Base Address. This is the board redundancy network
address, not the IEC 61850 IP address.
3. Enter the required board IP address.
4. Click OK. The board network address is updated and displayed in the main window.
5.7.6 SNTP IP ADDRESS CONFIGURATION

To Configure the SNTP server IP address:
2. Enter the required MAC SNTP address and server IP SNTP Address. Click OK.

addresses.
5.7.8 RSTP CONFIGURATION

1. To view or configure the RSTP Bridge Parameters, from the main window, click the device address to select
the device. The selected device MAC address appears highlighted.
2. Click the RSTP Config button. The RSTP Config screen appears.
3. To view the available parameters in the board that is connected, click the Get RSTP Parameters button.
4. To set the configurable parameters such as Bridge Max Age, Bridge Hello Time, Bridge Forward Delay, and
Bridge Priority, modify the parameter values according to the following table and click Set RSTP
Parameters.
P64x-TM-EN-4.1 347
Maximum value
S.No Parameter Default value (second) Minimum value (second)
(second)
1 Bridge Max Age 20 6 40
2 Bridge Hello Time 2 1 10
3 Bridge Forward Delay 15 4 30
4 Bridge Priority 32768 0 61440
5.7.8.1 BRIDGE PARAMETERS

To read the RSTP bridge parameters from the board,
1. From the main window click the device address to select the device. The RSTP Config window appears and
the default tab is Bridge Parameters.
2. Click the Get RSTP Parameters button. This displays all the RSTP bridge parameters from the Ethernet
board.
3. To modify the RSTP parameters, enter the values and click Set RSTP Parameters.
4. To restore the default values, click Restore Default and click Set RSTP Parameters.
The grayed parameters are read-only and cannot be modified.
Note:
When assigning the bridge priority, make sure the root of the network is the Ethernet switch, not the IEDs. This reduces the
number of hops to reach all devices in the network. Also make sure the priority values for all IEDs are higher than that of the
switch.
5.7.8.2 PORT PARAMETERS

This function is useful if you need to view the parameters of each port.
1. From the main window, click the device address to select the device. The RSTP Config window appears.
2. Select the Port Parameters tab, then click Get Parameters to read the port parameters. Alternatively, select
the port numbers to read the parameters.
5.7.8.3 PORT STATES

This is used to see which ports of the board are enabled or disabled.
1. From the main window, click the device address to select the device. The RSTP Config window appears.
2. Select the Port States tab then click the Get Port States button. This lists the ports of the Ethernet board. A
tick shows they are enabled.
5.7.8.4 END OF SESSION

5.8 SWITCH MANAGER

Switch Manager is used to manage Ethernet ring networks and MiCOM H35x-V2 and H36x-V2 SNMP facilities. It is
a set of tools used to manage, optimize, diagnose and supervise your network. It also handles the version software
of the switch.
The Switch Manager tool is also intended for MiCOM Px4x IEDs with redundant Ethernet using Self Healing Protocol
(SHP) and Dual Homing Protocol (DHP). This tool is used to identify IEDs and General Electric Switches, and to
348 P64x-TM-EN-4.1
configure the redundancy IP address for the General Electric proprietary Self Healing Protocol and Dual Homing
Protocol.
Switch hardware
General Electric switches are stand-alone devices (H3xx, H6x families) or embedded in a computer device rack, for
example MiCOM C264 (SWDxxx, SWRxxx, SWUxxx Ethernet boards) or PC board (MiCOM H14x, MiCOM H15x,
MiCOM H16x).
Switch range
There are 3 types of General Electric switches:
● Standard switches: SWU (in C264), H14x (PCI), H34x, H6x
● Redundant Ring switches: SWR (in C264), H15x (PCI), H35x,
● Redundant Dual Homing switches: SWD (in C264), H16x (PCI), H36x
Switch Manager allows you to allocate an IP addresses for General Electric switches. Switches can then be
synchronized using the Simple Network Time Protocol (SNTP) or they can be administrated using the Simple
Network Management Protocol (SNMP).
All switches have a single 6-byte MAC address.
Redundancy Management
Standard Ethernet does not support a loop at the OSI link layer (layer 2 of the 7 layer model). A mesh topology
cannot be created using a standard Hub and switch. Redundancy needs separate networks using hardware in
routers or software in dedicated switches using STP (Spanning Tree Protocol). However, this redundancy
mechanism is too slow for one link failure in electrical automation networks.
General Electric has developed its own Redundancy ring and star mechanisms using two specific Ethernet ports of
the redundant switches. This redundancy works between General Electric switches of the same type. The two
redundant Ethernet connections between General Electric switches create one private redundant Ethernet LAN.
The Ethernet ports dedicated to the redundancy are optical Ethernet ports. The General Electric redundancy
mechanism uses a single specific address for each Ethernet switch of the private LAN. This address is set using DIP
switches or jumpers.
Switch Manager monitors the redundant address of the switches and the link topology between switches.
5.8.1 INSTALLATION
Switch Manager requirements

● PC with Windows XP or later
● Ethernet port
● 200 MB hard disk space
● PC IP address configured in Windows in same IP range as switch
Network IP address
IP addressing is needed for time synchronization of GE switches and for SNMP management.
Switch Manager is used to define IP addresses of GE switches. These addresses must be in the range of the system
IP, depending on the IP mask of the engineering PC for substation maintenance.
GE switches have a default multicast so the 3rd word of the IP address is always 254.
Installation procedure
Run Setup.exe and follow the on-screen instructions.
P64x-TM-EN-4.1 349
5.8.2 SETUP
1. Make sure the PC has one Ethernet port connected to the GE switch.
2. Configure the PC's Ethernet port on the same subnet as the GE switch.
3. Select User or Admin mode. In User mode enter the user name as User, leave the password blank and click
OK. In Admin mode you can not upload the firmware on the Ethernet repeaters.
4. In Admin mode enter the user name as Admin, enter the password and click OK. All functions are available
including Expert Maintenance facilities.
5. Click the Language button in the bottom right of the screen and select your language.
6. If several Ethernet interfaces are used, in the Network board drop-down box, select the PC Network board
connected to the GE switch. The IP and MAC addresses are displayed below the drop-down box.
7. Periodically click the Ring Topology button (top left) to display or refresh the list of GE switches that are
connected.
5.8.3 NETWORK SETUP

To configure the network options:
1. From the main window click the Settings button. The Network Setup screen appears.
2. Enter the required board IP address. The first two octets can be configured. The third octet is always 254.
The last octet is set using the DIP switches (SW2) on the redundant Ethernet board, next to the ribbon
connector.
3. Click OK. The board network address is updated and displayed in the main window.
5. Enter the required MAC SNTP Address and server IP SNTP Address. Click OK.
7. Click the Saturation button. A new screen appears.
8. Set the saturation level and click OK. The default value is 300.
5.8.4 BANDWIDTH USED

To show how much bandwidth is used in the ring,
Click the Ring% button, at the bottom of the main window. The percentage of bandwidth used in the ring is
displayed.
5.8.5 RESET COUNTERS

To reset the switch counters,
1. Click Switch Counter Reset.
2. Click OK.

addresses.
350 P64x-TM-EN-4.1
5.8.7 MIRRORING FUNCTION

Port mirroring is a method of monitoring network traffic that forwards a copy of each incoming and outgoing
packet from one port of the repeater to another port where the data can be studied. Port mirroring is managed
locally and a network administrator uses it as a diagnostic tool.
To set up port mirroring:
1. Select the address of the device in the main window.
2. Click the Mirroring button, a new screen appears.
3. Click the checkbox to assign a a mirror port. A mirror port copies the incoming and outgoing traffic of the
port.
5.8.8 PORTS ON/OFF

To enable or disable ports:
2. Click Ports On/Off, a new screen appears.
3. Click the checkbox to enable or disable a port. A disabled port has an empty checkbox.
5.8.9 VLAN
The Virtual Local Area Network (VLAN) is a technique used to split an interconnected physical network into several
networks. This technique can be used at all ISO/OSI levels. The VLAN switch is mainly at OSI level 1 (physical VLAN)
which allows communication only between some Ethernet physical ports.
Ports on the switch can be grouped into Physical VLANs to limit traffic flooding. This is because it is limited to ports
belonging to that VLAN and not to other ports.
Port-based VLANs are VLANs where the packet forwarding decision is based on the destination MAC address and
its associated port. You must define outgoing ports allowed for each port when using port-based VLANs. The VLAN
only governs the outgoing traffic so is unidirectional. Therefore, if you wish to allow two subscriber ports to talk to
each other, you must define the egress port for both ports. An egress port is an outgoing port, through which a
data packet leaves.
To assign a physical VLAN to a set of ports:
2. Click the VLAN button, a new screen appears.
3. Use the checkboxes to select which ports will be in the same VLAN. By default all the ports share the same
VLAN.
5.8.10 END OF SESSION

P64x-TM-EN-4.1 351
6 DATA PROTOCOLS
The products supports a wide range of protocols to make them applicable to many industries and applications.
The exact data protocols supported by a particular product depend on its chosen application, but the following
table gives a list of the data protocols that are typically available.
SCADA data protocols

Data Protocol Layer 1 protocol Description
Courier K-Bus, RS232, RS485, Ethernet Standard for SCADA communications developed by General Electric.
MODBUS RS485 Standard for SCADA communications developed by Modicon.
IEC 60870-5-103 RS485 IEC standard for SCADA communications
Standard for SCADA communications developed by Harris. Used mainly in
DNP 3.0 RS485, Ethernet
North America.
IEC 61850 Ethernet IEC standard for substation automation. Facilitates interoperability.
The relationship of these protocols to the lower level physical layer protocols are as follows:
IEC 60870-5-103
MODBUS IEC 61850
Data Protocols
DNP3.0 DNP3.0
Courier Courier Courier Courier
Data Link Layer EIA(RS)485 Ethernet EIA(RS)232 K-Bus
Physical Layer Copper or Optical Fibre
6.1 COURIER
This section should provide sufficient detail to enable understanding of the Courier protocol at a level required by
most users. For situations where the level of information contained in this manual is insufficient, further
publications (R6511 and R6512) containing in-depth details about the protocol and its use, are available on
request.
Courier is an General Electric proprietary communication protocol. Courier uses a standard set of commands to
access a database of settings and data in the IED. This allows a master to communicate with a number of slave
devices. The application-specific elements are contained in the database rather than in the commands used to
interrogate it, meaning that the master station does not need to be preconfigured. Courier also provides a
sequence of event (SOE) and disturbance record extraction mechanism.
6.1.1 PHYSICAL CONNECTION AND LINK LAYER

Courier can be used with three physical layer protocols: K-Bus, EIA(RS)232 or EIA(RS)485.
Several connection options are available for Courier
● The front serial RS232 port (for connection to Settings application software on, for example, a laptop
● Rear Port 1 (RP1) - for permanent SCADA connection via RS485 or K-Bus
● Optional fibre port (RP1 in slot A) - for permanent SCADA connection via optical fibre
● Optional Rear Port 2 (RP2) - for permanent SCADA connection via RS485, K-Bus, or RS232
For either of the rear ports, both the IED address and baud rate can be selected using the front panel menu or by
the settings application software.
352 P64x-TM-EN-4.1
6.1.2 COURIER DATABASE

The Courier database is two-dimensional and resembles a table. Each cell in the database is referenced by a row
and column address. Both the column and the row can take a range from 0 to 255 (0000 to FFFF Hexadecimal.
Addresses in the database are specified as hexadecimal values, for example, 0A02 is column 0A row 02.
Associated settings or data are part of the same column. Row zero of the column has a text string to identify the
contents of the column and to act as a column heading.
The product-specific menu databases contain the complete database definition.
6.1.3 SETTINGS CATEGORIES

There are two main categories of settings in protection IEDs:
● Control and support settings
● Protection settings
With the exception of the Disturbance Recorder settings, changes made to the control and support settings are
implemented immediately and stored in non-volatile memory. Changes made to the Protection settings and the
Disturbance Recorder settings are stored in ‘scratchpad’ memory and are not immediately implemented. These
need to be committed by writing to the Save Changes cell in the CONFIGURATION column.
6.1.4 SETTING CHANGES

Courier provides two mechanisms for making setting changes. Either method can be used for editing any of the
settings in the database.
Method 1
This uses a combination of three commands to perform a settings change:
First, enter Setting mode: This checks that the cell is settable and returns the limits.
1. Preload Setting: This places a new value into the cell. This value is echoed to ensure that setting corruption
has not taken place. The validity of the setting is not checked by this action.
2. Execute Setting: This confirms the setting change. If the change is valid, a positive response is returned. If
the setting change fails, an error response is returned.
3. Abort Setting: This command can be used to abandon the setting change.
This is the most secure method. It is ideally suited to on-line editors because the setting limits are extracted before
the setting change is made. However, this method can be slow if many settings are being changed because three
commands are required for each change.
Method 2
The Set Value command can be used to change a setting directly. The response to this command is either a
positive confirm or an error code to indicate the nature of a failure. This command can be used to implement a
setting more rapidly than the previous method, however the limits are not extracted. This method is therefore most
suitable for off-line setting editors such as MiCOM S1 Agile, or for issuing preconfigured control commands.
6.1.5 EVENT EXTRACTION

You can extract events either automatically (rear serial port only) or manually (either serial port). For automatic
extraction, all events are extracted in sequential order using the Courier event mechanism. This includes fault and
maintenance data if appropriate. The manual approach allows you to select events, faults, or maintenance data
as desired.
P64x-TM-EN-4.1 353
6.1.5.1 AUTOMATIC EVENT RECORD EXTRACTION

This method is intended for continuous extraction of event and fault information as it is produced. It is only
supported through the rear Courier port.
When new event information is created, the Event bit is set in the Status byte. This indicates to the Master device
that event information is available. The oldest, non-extracted event can be extracted from the IED using the Send
Event command. The IED responds with the event data.
Once an event has been extracted, the Accept Event command can be used to confirm that the event has been
successfully extracted. When all events have been extracted, the Event bit is reset. If there are more events still to
be extracted, the next event can be accessed using the Send Event command as before.
6.1.5.2 MANUAL EVENT RECORD EXTRACTION

The VIEW RECORDS column (location 01) is used for manual viewing of event, fault, and maintenance records. The
contents of this column depend on the nature of the record selected. You can select events by event number and
directly select a fault or maintenance record by number.
Event Record Selection ('Select Event' cell: 0101)

This cell can be set the number of stored events. For simple event records (Type 0), cells 0102 to 0105 contain the
event details. A single cell is used to represent each of the event fields. If the event selected is a fault or
maintenance record (Type 3), the remainder of the column contains the additional information.
Fault Record Selection ('Select Fault' cell: 0105)

This cell can be used to select a fault record directly, using a value between 0 and 4 to select one of up to five
stored fault records. (0 is the most recent fault and 4 is the oldest). The column then contains the details of the fault
record selected.
Maintenance Record Selection ('Select Maint' cell: 01F0)

This cell can be used to select a maintenance record using a value between 0 and 4. This cell operates in a similar
way to the fault record selection.
If this column is used to extract event information, the number associated with a particular record changes when
a new event or fault occurs.
Event Types
The IED generates events under certain circumstances such as:
● Change of state of output contact
● Change of state of opto-input
● Protection element operation
● Alarm condition
● Setting change
● Password entered/timed-out
Event Record Format

The IED returns the following fields when the Send Event command is invoked:
● Cell reference
● Time stamp
● Cell text
● Cell value
354 P64x-TM-EN-4.1
The Menu Database contains tables of possible events, and shows how the contents of the above fields are
interpreted. Fault and Maintenance records return a Courier Type 3 event, which contains the above fields plus two
additional fields:
● Event extraction column
● Event number
These events contain additional information, which is extracted from the IED using column B4. Row 01 contains a
Select Record setting that allows the fault or maintenance record to be selected. This setting should be set to the
event number value returned in the record. The extended data can be extracted from the IED by uploading the text
and data from the column.
6.1.6 DISTURBANCE RECORD EXTRACTION

The stored disturbance records are accessible through the Courier interface. The records are extracted using
column (B4).
The Select Record cell can be used to select the record to be extracted. Record 0 is the oldest non-extracted
record. Older records which have been already been extracted are assigned positive values, while younger records
are assigned negative values. To help automatic extraction through the rear port, the IED sets the Disturbance bit
of the Status byte, whenever there are non-extracted disturbance records.
Once a record has been selected, using the above cell, the time and date of the record can be read from the
Trigger Time cell (B402). The disturbance record can be extracted using the block transfer mechanism from cell
B40B and saved in the COMTRADE format. The settings application software software automatically does this.
6.1.7 PROGRAMMABLE SCHEME LOGIC SETTINGS

The programmable scheme logic (PSL) settings can be uploaded from and downloaded to the IED using the block
transfer mechanism.
The following cells are used to perform the extraction:
● Domain cell (B204): Used to select either PSL settings (upload or download) or PSL configuration data
(upload only)
● Sub-Domain cell (B208): Used to select the Protection Setting Group to be uploaded or downloaded.
● Version cell (B20C): Used on a download to check the compatibility of the file to be downloaded.
● Transfer Mode cell (B21C): Used to set up the transfer process.
● Data Transfer cell (B120): Used to perform upload or download.
The PSL settings can be uploaded and downloaded to and from the IED using this mechanism. The settings
application software must be used to edit the settings. It also performs checks on the validity of the settings before
they are transferred to the IED.
6.1.8 TIME SYNCHRONISATION

The time and date can be set using the time synchronization feature of the Courier protocol. The device will correct
for the transmission delay. The time synchronization message may be sent as either a global command or to any
individual IED address. If the time synchronization message is sent to an individual address, then the device will
respond with a confirm message. If sent as a global command, the (same) command must be sent twice. A time
synchronization Courier event will be generated/produced whether the time-synchronization message is sent as a
global command or to any individual IED address.
If the clock is being synchronized using the IRIG-B input then it will not be possible to set the device time using the
Courier interface. An attempt to set the time using the interface will cause the device to create an event with the
current date and time taken from the IRIG-B synchronized internal clock.
P64x-TM-EN-4.1 355
6.1.9 COURIER CONFIGURATION

communication protocol – in this case Courier.
COMMUNICATIONS
RP1 Protocol
Courier
4. Move down to the next cell (RP1 Address). This cell controls the address of the RP1 port on thje device. Up to
32 IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so
that messages from the master control station are accepted by one IED only. Courier uses an integer
number between 1 and 254 for the Relay Address. It is set to 255 by default, which has to be changed. It is
important that no two IEDs share the same address.
COMMUNICATIONS
RP1 Address
100
controls how long the IED waits without receiving any messages on the rear port before revoking any
password access that was enabled and discarding any changes. For the rear port this can be set between 1
and 30 minutes.
COMMUNICATIONS
RP1 Inactivtimer
10.00 mins.
COMMUNICATIONS
RP1 PhysicalLink
Copper
7. Move down to the next cell (RP1 Card Status). This cell is not settable. It displays the status of the chosen
physical layer protocol for RP1.
COMMUNICATIONS
RP1 Card Status
K-Bus OK
356 P64x-TM-EN-4.1
8. Move down to the next cell (RP1 Port Config). This cell controls the type of serial connection. Select between
K-Bus or RS485.
COMMUNICATIONS
RP1 Port Config
K-Bus
9. If using EIA(RS)485, the next cell (RP1 Comms Mode) selects the communication mode. The choice is either
IEC 60870 FT1.2 for normal operation with 11-bit modems, or 10-bit no parity. If using K-Bus this cell will not
appear.
COMMUNICATIONS
RP1 Comms Mode
IEC 60870 FT1.2
10. If using EIA(RS)485, the next cell down controls the baud rate. Three baud rates are supported; 9600, 19200
and 38400. If using K-Bus this cell will not appear as the baud rate is fixed at 64 kbps.
COMMUNICATIONS
RP1 Baud rate
19200
6.2 IEC 60870-5-103

The specification IEC 60870-5-103 (Telecontrol Equipment and Systems Part 5 Section 103: Transmission
Protocols), defines the use of standards IEC 60870-5-1 to IEC 60870-5-5, which were designed for communication
with protection equipment
This section describes how the IEC 60870-5-103 standard is applied to the Px40 platform. It is not a description of
the standard itself. The level at which this section is written assumes that the reader is already familiar with the
IEC 60870-5-103 standard.
This section should provide sufficient detail to enable understanding of the standard at a level required by most
users.
The IEC 60870-5-103 interface is a master/slave interface with the device as the slave device. The device conforms
to compatibility level 2, as defined in the IEC 60870-5-103.standard.
The following IEC 60870-5-103 facilities are supported by this interface:
● Initialization (reset)
● Time synchronization
● Event record extraction
● General interrogation
● Cyclic measurements
● General commands
● Disturbance record extraction
● Private codes

Two connection options are available for IEC 60870-5-103:
● Rear Port 1 (RP1) - for permanent SCADA connection via RS485
If the optional fibre optic port is fitted, a menu item appears in which the active port can be selected. However the
selection is only effective following the next power up.
P64x-TM-EN-4.1 357
The IED address and baud rate can be selected using the front panel menu or by the settings application software.
6.2.2 INITIALISATION
Whenever the device has been powered up, or if the communication parameters have been changed a reset
command is required to initialize the communications. The device will respond to either of the two reset
commands; Reset CU or Reset FCB (Communication Unit or Frame Count Bit). The difference between the two
commands is that the Reset CU command will clear any unsent messages in the transmit buffer, whereas the
Reset FCB command does not delete any messages.
The device will respond to the reset command with an identification message ASDU 5. The Cause of Transmission
(COT) of this response will be either Reset CU or Reset FCB depending on the nature of the reset command. The
content of ASDU 5 is described in the IEC 60870-5-103 section of the Menu Database, available from General
Electric separately if required.
In addition to the above identification message, it will also produce a power up event.

The time and date can be set using the time synchronization feature of the IEC 60870-5-103 protocol. The device
will correct for the transmission delay as specified in IEC 60870-5-103. If the time synchronization message is sent
as a send/confirm message then the device will respond with a confirm message. A time synchronization Class 1
event will be generated/produced whether the time-synchronization message is sent as a send confirm or a
broadcast (send/no reply) message.
IEC 60870-5-103 interface. An attempt to set the time via the interface will cause the device to create an event
with the current date and time taken from the IRIG-B synchronized internal clock.
6.2.4 CONFIGURABLE IEC 60870-5-103 SIGNAL LIST

From Software Version 91 onwards, there is a new setting cell which allows the IEC 60870-5-103 private range
signals to be selected and de-selected from IEC 60870-5-103 communication.
The IEC 60870-5-103 standard (compatible range) signals, that are provided according to the relay type and
implementation, are always enabled. These signals cannot be disabled.
This new setting cell is Config Mode in the PROTOCOL CFG column.
There are two settings associated with this cell. These are:
In this mode, the IED behaviour for IEC 60870-5-103 protocol is identical to pre-Software Version 91 IEDs.
All the implemented signals (IEC 60870-5-103 compatible range and private range signals) are enabled for
Fixed
IEC 60870-5-103 communication. The COT behaviour will be according to the device IEC 60870-5-103 profile.
This mode is provided for backward compatibility. This is the default setting.
In this mode, the user can select which IEC 60870-5-103 private range signals are enabled for IEC
60870-5-103 communication.
The selection is done using new DDB mask setting cells in the PROTOCOL CFG column. The DDB mask value
Std+UserConfig controls only the signal selection (enabled or disabled) for IEC 60870-5-103 communication. It does not
modify the COT behaviour of the signals. The COT behaviour of the private range signals will be according to
the device IEC 60870-5-103 profile.
By default, only IEC 60870-5-103 standard signals are enabled. All private range signals are disabled.
When the Config Mode cell is set to Std+UserConfig, the DDB masks become visible in the PROTOCOL CFG
column. These masks function in a similar way to the DDB masks in the RECORD CONTROL column. Editing these
masks controls the DDB signals that are enabled for communication of the equivalent IEC 60870-5-103 private
range signal, as listed in the IEC 60870-5-103 profile in the Menu Database.
358 P64x-TM-EN-4.1
Within these masks, only individual DDBs that are equivalent to IEC 60870-5-103 private range signals are
editable. By default, all of the individual DDBs that are equivalent to IEC 60870-5-103 private range signals are set
to 0 (zero), that is disabled for communication. Setting any individual DDB to 1 (one), enables the equivalent IEC
60870-5-103 private range signal for communication.
Within these masks, individual DDBs that are either equivalent to IEC 60870-5-103 standard range signals, or do
not have any equivalent IEC 60870-5-103 private range signal, are not editable.
6.2.5 SPONTANEOUS EVENTS

Events are categorized using the following information:
● Function type
● Information Number
The IEC 60870-5-103 profile in the Menu Database contains a complete listing of all events produced by the
device.
From Software Version 91 onwards, the IEC 60870-5-103 private range signals can be individually selected for GI
reporting. Set the Config Mode cell to Std+UserConfig, and configure the DDB masks as required.
6.2.6 GENERAL INTERROGATION (GI)

The GI request can be used to read the status of the device, the function numbers, and information numbers that
will be returned during the GI cycle. These are shown in the IEC 60870-5-103 profile in the Menu Database.
From Software Version 91 onwards, the IEC 60870-5-103 private range signals can be individually selected for GI
reporting. Set the Config Mode cell to Std+UserConfig, and configure the DDB masks as required.
6.2.7 CYCLIC MEASUREMENTS

The device will produce measured values using ASDU 9 on a cyclical basis, this can be read from the device using a
Class 2 poll (note ADSU 3 is not used). The rate at which the device produces new measured values can be
controlled using the measurement period setting. This setting can be edited from the front panel menu or using
MiCOM S1 Agile. It is active immediately following a change.
The device transmits its measurands at 2.4 times the rated value of the analogue value.
6.2.8 COMMANDS
A list of the supported commands is contained in the Menu Database. The device will respond to other commands
with an ASDU 1, with a cause of transmission (COT) indicating ‘negative acknowledgement’.
6.2.9 TEST MODE

It is possible to disable the device output contacts to allow secondary injection testing to be performed using
either the front panel menu or the front serial port. The IEC 60870-5-103 standard interprets this as ‘test mode’. An
event will be produced to indicate both entry to and exit from test mode. Spontaneous events and cyclic measured
data transmitted whilst the device is in test mode will have a COT of ‘test mode’.
6.2.10 DISTURBANCE RECORDS

The disturbance records are stored in uncompressed format and can be extracted using the standard
mechanisms described in IEC 60870-5-103.
Note:
IEC 60870-5-103 only supports up to 8 records.
P64x-TM-EN-4.1 359
6.2.11 COMMAND/MONITOR BLOCKING

The device supports a facility to block messages in the monitor direction (data from the device) and also in the
command direction (data to the device). Messages can be blocked in the monitor and command directions using
one of the two following methods
● The menu command RP1 CS103Blcking in the COMMUNICATIONS column
● The DDB signals Monitor Blocked and Command Blocked
6.2.12 IEC 60870-5-103 CONFIGURATION

communication protocol – in this case IEC 60870-5-103.
COMMUNICATIONS
RP1 Protocol
IEC 60870-5-103
4. Move down to the next cell (RP1 Address). This cell controls the IEC 60870-5-103 address of the IED. Up to 32
IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so that
messages from the master control station are accepted by one IED only. IEC 60870-5-103 uses an integer
number between 0 and 254 for the address. It is important that no two IEDs have the same IEC 60870 5 103
address. The IEC 60870-5-103 address is then used by the master station to communicate with the IED.
COMMUNICATIONS
RP1 address
162
5. Move down to the next cell (RP1 Baud Rate). This cell controls the baud rate to be used. Two baud rates are
supported by the IED, 9600 bits/s and 19200 bits/s. Make sure that the baud rate selected on the
IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
6. Move down to the next cell (RP1 Meas Period). The next cell down controls the period between
IEC 60870-5-103 measurements. The IEC 60870-5-103 protocol allows the IED to supply measurements at
regular intervals. The interval between measurements is controlled by this cell, and can be set between 1
and 60 seconds.
COMMUNICATIONS
RP1 Meas Period
30.00 s
360 P64x-TM-EN-4.1
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. The next cell down (RP1 CS103Blcking) can be used for monitor or command blocking.
COMMUNICATIONS
RP1 CS103Blcking
Disabled
9. There are three settings associated with this cell; these are:
Disabled No blocking selected.
When the monitor blocking DDB Signal is active high, either by energising an opto input or control input,
Monitor Blocking reading of the status information and disturbance records is not permitted. When in this mode the device
returns a "Termination of general interrogation" message to the master station.
When the command blocking DDB signal is active high, either by energising an opto input or control input,
Command Blocking all remote commands will be ignored (i.e. CB Trip/Close, change setting group etc.). When in this mode the
device returns a "negative acknowledgement of command" message to the master station.
6.3 DNP 3.0

This section describes how the DNP 3.0 standard is applied in the product. It is not a description of the standard
itself. The level at which this section is written assumes that the reader is already familiar with the DNP 3.0
standard.
The descriptions given here are intended to accompany the device profile document that is included in the Menu
Database document. The DNP 3.0 protocol is not described here, please refer to the documentation available from
the user group. The device profile document specifies the full details of the DNP 3.0 implementation. This is the
standard format DNP 3.0 document that specifies which objects; variations and qualifiers are supported. The
device profile document also specifies what data is available from the device using DNP 3.0. The IED operates as a
DNP 3.0 slave and supports subset level 2, as described in the DNP 3.0 standard, plus some of the features from
level 3.
The DNP 3.0 protocol is defined and administered by the DNP Users Group. For further information on DNP 3.0 and
the protocol specifications, please see the DNP website (www.dnp.org).

DNP 3.0 can be used with two physical layer protocols: EIA(RS)485, or Ethernet.
Several connection options are available for DNP 3.0
● An RJ45 connection on an optional Ethernet board - for permanent SCADA Ethernet connection
● A fibre connection on an optional Ethernet board - for permanent SCADA Ethernet connection
When using a serial interface, the data format is: 1 start bit, 8 data bits, 1 stop bit and optional configurable parity
bit.
P64x-TM-EN-4.1 361
6.3.2 OBJECT 1 BINARY INPUTS

Object 1, binary inputs, contains information describing the state of signals in the IED, which mostly form part of
the digital data bus (DDB). In general these include the state of the output contacts and opto-inputs, alarm signals,
and protection start and trip signals. The ‘DDB number’ column in the device profile document provides the DDB
numbers for the DNP 3.0 point data. These can be used to cross-reference to the DDB definition list. See the
relevant Menu Database document. The binary input points can also be read as change events using Object 2 and
Object 60 for class 1-3 event data.
6.3.3 OBJECT 10 BINARY OUTPUTS

Object 10, binary outputs, contains commands that can be operated using DNP 3.0. Therefore the points accept
commands of type pulse on (null, trip, close) and latch on/off as detailed in the device profile in the relevant Menu
Database document, and execute the command once for either command. The other fields are ignored (queue,
clear, trip/close, in time and off time).
There is an additional image of the Control Inputs. Described as Alias Control Inputs, they reflect the state of the
Control Input, but with a dynamic nature.
● If the Control Input DDB signal is already SET and a new DNP SET command is sent to the Control Input, the
Control Input DDB signal goes momentarily to RESET and then back to SET.
● If the Control Input DDB signal is already RESET and a new DNP RESET command is sent to the Control
Input, the Control Input DDB signal goes momentarily to SET and then back to RESET.
DNP Latch DNP Latch DNP Latch DNP Latch

ON ON OFF OFF
Control Input
(Latched)
Aliased Control
Input
(Latched)
Control Input
(Pulsed )
Aliased Control
Input
(Pulsed )
The pulse width is equal to the duration of one protection iteration
V01002
Figure 162: Control input behaviour
Many of the IED’s functions are configurable so some of the Object 10 commands described in the following
sections may not be available. A read from Object 10 reports the point as off-line and an operate command to
Object 12 generates an error response.
Examples of Object 10 points that maybe reported as off-line are:
● Activate setting groups: Ensure setting groups are enabled
● CB trip/close: Ensure remote CB control is enabled
362 P64x-TM-EN-4.1
● Reset NPS thermal: Ensure NPS thermal protection is enabled

● Reset thermal O/L: Ensure thermal overload protection is enabled
● Reset RTD flags: Ensure RTD Inputs is enabled
● Control inputs: Ensure control inputs are enabled
6.3.4 OBJECT 20 BINARY COUNTERS

Object 20, binary counters, contains cumulative counters and measurements. The binary counters can be read as
their present ‘running’ value from Object 20, or as a ‘frozen’ value from Object 21. The running counters of object
20 accept the read, freeze and clear functions. The freeze function takes the current value of the object 20 running
counter and stores it in the corresponding Object 21 frozen counter. The freeze and clear function resets the Object
20 running counter to zero after freezing its value.
Binary counter and frozen counter change event values are available for reporting from Object 22 and Object 23
respectively. Counter change events (Object 22) only report the most recent change, so the maximum number of
events supported is the same as the total number of counters. Frozen counter change events (Object 23) are
generated whenever a freeze operation is performed and a change has occurred since the previous freeze
command. The frozen counter event queues store the points for up to two freeze operations.
6.3.5 OBJECT 30 ANALOGUE INPUT

Object 30, analogue inputs, contains information from the IED’s measurements columns in the menu. All object 30
points can be reported as 16 or 32-bit integer values with flag, 16 or 32-bit integer values without flag, as well as
short floating point values.
Analogue values can be reported to the master station as primary, secondary or normalized values (which takes
into account the IED’s CT and VT ratios), and this is settable in the COMMUNICATIONS column in the IED.
Corresponding deadband settings can be displayed in terms of a primary, secondary or normalized value.
Deadband point values can be reported and written using Object 34 variations.
The deadband is the setting used to determine whether a change event should be generated for each point. The
change events can be read using Object 32 or Object 60. These events are generated for any point which has a
value changed by more than the deadband setting since the last time the data value was reported.
Any analogue measurement that is unavailable when it is read is reported as offline. For example, the frequency
would be offline if the current and voltage frequency is outside the tracking range of the IED. All Object 30 points
are reported as secondary values in DNP 3.0 (with respect to CT and VT ratios).
6.3.6 OBJECT 40 ANALOGUE OUTPUT

The conversion to fixed-point format requires the use of a scaling factor, which is configurable for the various
types of data within the IED such as current, voltage, and phase angle. All Object 40 points report the integer
scaling values and Object 41 is available to configure integer scaling quantities.
6.3.7 OBJECT 50 TIME SYNCHRONISATION

Function codes 1 (read) and 2 (write) are supported for Object 50 (time and date) variation 1. The DNP Need Time
function (the duration of time waited before requesting another time sync from the master) is supported, and is
configurable in the range 1 - 30 minutes.
Courier interface. An attempt to set the time using the interface will cause the device to create an event with the
current date and time taken from the IRIG-B synchronized internal clock.
6.3.8 DNP3 DEVICE PROFILE

This section describes the specific implementation of DNP version 3.0 within General Electric MiCOM P40 Agile IEDs
for both compact and modular ranges.
P64x-TM-EN-4.1 363
The devices use the DNP 3.0 Slave Source Code Library version 3 from Triangle MicroWorks Inc.
This document, in conjunction with the DNP 3.0 Basic 4 Document Set, and the DNP Subset Definitions Document,
provides complete information on how to communicate with the devices using the DNP 3.0 protocol.
This implementation of DNP 3.0 is fully compliant with DNP 3.0 Subset Definition Level 2. It also contains many
Subset Level 3 and above features.
6.3.8.1 DNP3 DEVICE PROFILE TABLE

The following table provides the device profile in a similar format to that defined in the DNP 3.0 Subset Definitions
Document. While it is referred to in the DNP 3.0 Subset Definitions as a “Document”, it is just one component of a
total interoperability guide. This table, in combination with the subsequent Implementation and Points List tables
should provide a complete interoperability/configuration guide for the device.
The following table provides the device profile in a similar format to that defined in the DNP 3.0 Subset Definitions
Document. While it is referred to in the DNP 3.0 Subset Definitions as a "Document", it is just one component of a
total interoperability guide. This table, in combination with the subsequent Implementation and Points List tables
should provide a complete interoperability/configuration guide for the device.
DNP 3.0
Device Profile Document
Vendor Name: General Electric
Device Name: MiCOM P40Agile Protection Relays – compact and modular range
Models Covered: All models
Highest DNP Level Supported*: For Requests: Level 2
*This is the highest DNP level FULLY supported. Parts of level 3 are For Responses: Level 2
also supported
Device Function: Slave
Notable objects, functions, and/or qualifiers supported in addition to the highest DNP levels supported (the complete list is described in the
DNP 3.0 Implementation Table):
For static (non-change event) object requests, request qualifier codes 00 and 01 (start-stop), 07 and 08 (limited quantity), and 17 and 28 (index)
are supported in addition to the request qualifier code 06 (no range (all points))
Static object requests sent with qualifiers 00, 01, 06, 07, or 08 will be responded with qualifiers 00 or 01
Static object requests sent with qualifiers 17 or 28 will be responded with qualifiers 17 or 28
For change-event object requests, qualifiers 17 or 28 are always responded
16-bit and 32-bit analogue change events with time may be requested
The read function code for Object 50 (time and date) variation 1 is supported
Analogue Input Deadbands, Object 34, variations 1 through 3, are supported
Floating Point Analogue Output Status and Output Block Objects 40 and 41 are supported
Sequential file transfer, Object 70, variations 2 through 7, are supported
Device Attribute Object 0 is supported
Maximum Data Link Frame Size (octets): Transmitted: 292
Received: 292
Maximum Application Fragment Size (octets) Transmitted: Configurable (100 to 2048). Default 2048
Received: 249
Maximum Data Link Retries: Fixed at 2
Maximum Application Layer Retries: None
Requires Data Link Layer Confirmation: Configurable to Never or Always
Requires Application Layer Confirmation: When reporting event data (Slave devices only)
When sending multi-fragment responses (Slave devices only)
Timeouts while waiting for:
Data Link Confirm: Configurable
364 P64x-TM-EN-4.1
DNP 3.0
Complete Application Fragment: None
Application Confirm: Configurable
Complete Application Response: None
Others:
Data Link Confirm Timeout: Configurable from 0 (Disabled) to 120s, default 10s.
Application Confirm Timeout: Configurable from 1 to 120s, default 2s.
Select/Operate Arm Timeout: Configurable from 1 to 10s, default 10s.
Need Time Interval (Set IIN1-4): Configurable from 1 to 30, default 10min.
Application File Timeout 60 s
Analog Change Event Scan Period: Fixed at 0.5s
Counter Change Event Scan Period Fixed at 0.5s
Frozen Counter Change Event Scan Period Fixed at 1s
Maximum Delay Measurement Error: 2.5 ms
Time Base Drift Over a 10-minute Interval: 7 ms
Sends/Executes Control Operations:
Write Binary Outputs: Never
Select/Operate: Always
Direct Operate: Always
Direct Operate - No Ack: Always
Count > 1 Never
Pulse On Always
Pulse Off Sometimes
Latch On Always
Latch Off Always
Queue Never
Clear Queue Never
Note: Paired Control points will accept Pulse On/Trip and Pulse On/Close, but only single point will accept the Pulse Off control command.
Reports Binary Input Change Events when no specific variation Configurable to send one or the other
requested:
Reports time-tagged Binary Input Change Events when no specific Binary input change with time
variation requested:
Sends Unsolicited Responses: Never
Sends Static Data in Unsolicited Responses: Never
No other options are permitted
Default Counter Object/Variation: Configurable, Point-by-point list attached
Default object: 20
Default variation: 1
Counters Roll Over at: 32 bits
Sends multi-fragment responses: Yes
Sequential File Transfer Support:
Append File Mode No
Custom Status Code Strings No
Permissions Field Yes
P64x-TM-EN-4.1 365
DNP 3.0
File Events Assigned to Class No
File Events Send Immediately Yes
Multiple Blocks in a Fragment No
Max Number of Files Open 1
6.3.8.2 DNP3 IMPLEMENTATION TABLE

The implementation table provides a list of objects, variations and control codes supported by the device:
Request Response
Object
(Library will parse) (Library will respond with)
Object Variation Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex)
Description (dec)
Number Number (hex)
1 0 Binary Input (Variation 0 is used to 1 (read) 00, 01 (start-stop)
request default variation) 22 (assign class) 06 (no range, or all)
07, 08 (limited qty)
17, 27, 28 (index)
1 1 Binary Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
(default - see 06 (no range, or all) 17, 28 (index - see note 2)
note 1) 07, 08 (limited qty)
17, 27, 28 (index)
1 2 Binary Input with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
06 (no range, or all) 17, 28 (index - see note 2)
17, 28 (index)
2 0 Binary Input Change - Any 1 (read) 06 (no range, or all)
Variation 07, 08 (limited qty)
2 1 Binary Input Change without Time 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
2 2 Binary Input Change with Time 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
10 0 Binary Output Status - Any 1 (read) 00, 01 (start-stop)
Variation 06 (no range, or all)
17, 27, 28 (index)
10 2 Binary Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 28 (index)
12 1 Control Relay Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate)
5 (direct op)
6 (dir. op, noack)
20 0 Binary Counter - Any Variation 1 (read) 00, 01 (start-stop)
22 (assign class) 06 (no range, or all)
17, 27, 28 (index)
7 (freeze) 00, 01 (start-stop)
8 (freeze noack) 06 (no range, or all)
9 (freeze clear) 07, 08 (limited qty)
10 (frz. cl. Noack)
20 1 32-Bit Binary Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
20 2 16-Bit Binary Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
20 5 32-Bit Binary Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
366 P64x-TM-EN-4.1
Request Response
Object
Description (dec)
Number Number (hex)
20 6 16-Bit Binary Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 0 Frozen Counter - Any Variation 1 (read) 00, 01 (start-stop)
06 (no range, or all)
17, 27, 28 (index)
21 1 32-Bit Frozen Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 2 16-Bit Frozen Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 5 32-Bit Frozen Counter with Time of 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Freeze 06 (no range, or all) 17, 28 (index - see note 1)
17, 27, 28 (index)
21 6 16-Bit Frozen Counter with Time of 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Freeze 06 (no range, or all) 17, 28 17, 28 (index - see note 1)
17, 27, 28 (index)
21 9 32-Bit Frozen Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 10 16-Bit Frozen Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
`22 0 Counter Change Event - Any 1 (read) 06 (no range, or all)
22 1 32-Bit Counter Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see without Time 07, 08 (limited qty)
note 1)
22 2 16-Bit Counter Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
without Time 07, 08 (limited qty)
22 5 32-Bit Counter Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Time 07, 08 (limited qty)
22 6 16-Bit Counter Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 0 Frozen Counter Event (Variation 0 1 (read) 06 (no range, or all)
is used to request default 07, 08 (limited qty)
variation)
23 1 32-Bit Frozen Counter Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see 07, 08 (limited qty)
note 1)
23 2 16-Bit Frozen Counter Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 5 32-Bit Frozen Counter Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 6 16-Bit Frozen Counter Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
30 0 Analog Input - Any Variation 1 (read) 00, 01 (start-stop)
17, 27, 28 (index)
30 1 32-Bit Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 2 16-Bit Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
P64x-TM-EN-4.1 367
Request Response
Object
Description (dec)
Number Number (hex)
30 3 32-Bit Analog Input without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 4 16-Bit Analog Input without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 5 Short floating point 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
32 0 Analog Change Event - Any 1 (read) 06 (no range, or all)
32 1 32-Bit Analog Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see without Time 07, 08 (limited qty)
note 1)
32 2 16-Bit Analog Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
without Time 07, 08 (limited qty)
32 3 32-Bit Analog Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
32 4 16-Bit Analog Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
32 5 Short floating point Analog 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Change Event without Time 07, 08 (limited qty)
32 7 Short floating point Analog 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Change Event with Time 07, 08 (limited qty)
34 0 Analog Input Deadband (Variation 1 (read) 00, 01 (start-stop)
0 is used to request default 06 (no range, or all)
variation) 07, 08 (limited qty)
17, 27, 28 (index)
34 1 16 Bit Analog Input Deadband 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
2 (write) 00, 01 (start-stop)
17, 27, 28 (index)
34 2 32 Bit Analog Input Deadband 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
17, 27, 28 (index)
34 3 Short Floating Point Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Deadband 06 (no range, or all) 17, 28 (index - see note 2)
17, 27, 28 (index)
17, 27, 28 (index)
40 0 Analog Output Status (Variation 0 1 (read) 00, 01 (start-stop)
is used to request default 06 (no range, or all)
variation) 07, 08 (limited qty)
17, 27, 28 (index)
40 1 32-Bit Analog Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
40 2 16-Bit Analog Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
368 P64x-TM-EN-4.1
Request Response
Object
Description (dec)
Number Number (hex)
40 3 Short Floating Point Analog 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Output Status 06 (no range, or all) 17, 28 (index - see note 2)
17, 27, 28 (index)
41 1 32-Bit Analog Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate) 27 (index)
5 (direct op)
6 (dir. op, noack)
41 2 16-Bit Analog Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate) 27 (index)
5 (direct op)
6 (dir. op, noack)
41 3 Short Floating Point Analog 3 (select) 17, 27, 28 (index) 129 response echo of request
Output Block 4 (operate)
5 (direct op)
6 (dir. op, noack)
1 1 (read) 07 (limited qty = 1) 129 response 07 (limited qty = 1)
50 (default - see Time and Date
note 1)
2 (write) 07 (limited qty = 1)
60 0 Not defined
60 1 Class 0 Data 1 (read) 06 (no range, or all)
70 0 File Event - Any Variation 1 (read) 06 (no range, or all)
70 2 File Authentication 29 (authenticate) 5b (free-format) 129 response 5B (free-format)
70 3 File Command 25 (open) 5b (free-format)
27 (delete)
70 4 File Command Status 26 (close) 5b (free-format) 129 response 5B (free-format)
30 (abort)
70 5 File Transfer 1 (read) 5b (free-format) 129 response 5B (free-format)
70 6 File Transfer Status 129 response 5B (free-format)
70 7 File Descriptor 28 (get file info) 5b (free-format) 129 response 5B (free-format)
80 1 Internal Indications 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
No Object (function code only) 13 (cold restart)
No Object (function code only) 14 (warm restart)
No Object (function code only) 23 (delay meas.)
Note:
A Default variation refers to the variation responded to when variation 0 is requested and/or in class 0, 1, 2, or 3 scans.
P64x-TM-EN-4.1 369
Note:
For static (non-change-event) objects, qualifiers 17 or 28 are only responded to when a request is sent with qualifiers 17 or
28, respectively. Otherwise, static object requests sent with qualifiers 00, 01, 06, 07, or 08, will be responded to with qualifiers
00 or 01. For change-event objects, qualifiers 17 or 28 are always responded to.
6.3.8.3 DNP3 INTERNAL INDICATIONS

The following table lists the DNP3.0 Internal Indications (IIN) and identifies those that are supported by the device.
The IIN form an information element used to convey the internal states and diagnostic results of a device. This
information can be used by a receiving station to perform error recovery or other suitable functions. The IIN is a
two-octet field that follows the function code in all responses from the device. When a request cannot be
processed due to formatting errors or the requested data is not available, the IIN is always returned with the
appropriate bits set.
Bit Indication Description Supported
Octet 1
Set when a request is received with the destination address of the all stations
address (6553510). It is cleared after the next response (even if a response to a
0 All stations message received global request is required). Yes
This IIN is used to let the master station know that a "broadcast" message was
received by the relay.
Set when data that has been configured as Class 1 data is ready to be sent to
the master.
1 Class 1 data available Yes
The master station should request this class data from the relay when this bit
is set in a response.
the master.
the master.
The relay requires time synchronization from the master station (using the
Time and Date object).
4 Time-synchronization required Yes
This IIN is cleared once the time has been synchronized. It can also be cleared
by explicitly writing a 0 into this bit of the Internal Indication object.
Set when some or all of the relays digital output points (Object 10/12) are in the
Local state. That is, the relays control outputs are NOT accessible through the
5 Local DNP protocol. No
This IIN is clear when the relay is in the Remote state. That is, the relays control
outputs are fully accessible through the DNP protocol.
Set when an abnormal condition exists in the relay. This IIN is only used when
6 Device in trouble the state cannot be described by a combination of one or more of the other IIN No
bits.
Set when the device software application restarts. This IIN is cleared when the
7 Device restart master station explicitly writes a 0 into this bit of the Internal Indications Yes
object.
Octet 2
0 Function code not implemented The received function code is not implemented within the relay. Yes
The relay does not have the specified objects or there are no objects assigned
to the requested class.
1 Requested object(s) unknown Yes
This IIN should be used for debugging purposes and usually indicates a
mismatch in device profiles or configuration problems.
370 P64x-TM-EN-4.1
Bit Indication Description Supported

Parameters in the qualifier, range or data fields are not valid or out of range.
This is a 'catch-all' for application request formatting errors. It should only be
2 Out of range Yes
used for debugging purposes. This IIN usually indicates configuration
problems.
Event buffer(s), or other application buffers, have overflowed. The master
station should attempt to recover as much data as possible and indicate to the
3 Buffer overflow Yes
user that there may be lost data. The appropriate error recovery procedures
should be initiated by the user.
The received request was understood but the requested operation is already
4 Already executing
executing.
Set to indicate that the current configuration in the relay is corrupt. The
5 Bad configuration Yes
master station may download another configuration to the relay.
6 Reserved Always returned as zero.
7 Reserved Always returned as zero.
6.3.8.4 DNP3 RESPONSE STATUS CODES

When the device processes Control Relay Output Block (Object 12) requests, it returns a set of status codes; one for
each point contained within the original request. The complete list of codes appears in the following table:
Code Number Identifier Name Description
0 Success The received request has been accepted, initiated, or queued.
The request has not been accepted because the ‘operate’ message was received after the
1 Timeout arm timer (Select Before Operate) timed out.
The arm timer was started when the select operation for the same point was received.
The request has not been accepted because no previous matching ‘select’ request exists. (An
2 No select ‘operate’ message was sent to activate an output that was not previously armed with a
matching ‘select’ message).
The request has not been accepted because there were formatting errors in the control
3 Format error
request (‘select’, ‘operate’, or ‘direct operate’).
The request has not been accepted because a control operation is not supported for this
4 Not supported
point.
The request has not been accepted because the control queue is full or the point is already
5 Already active
active.
6 Hardware error The request has not been accepted because of control hardware problems.
7 Local The request has not been accepted because local access is in progress.
8 Too many operations The request has not been accepted because too many operations have been requested.
9 Not authorized The request has not been accepted because of insufficient authorization.
127 Undefined The request not been accepted because of some other undefined reason.
Note:
Code numbers 10 through to 126 are reserved for future use.
6.3.9 DNP3 CONFIGURATION

P64x-TM-EN-4.1 371
communication protocol – in this case DNP3.0.
COMMUNICATIONS
RP1 Protocol
DNP3.0
4. Move down to the next cell (RP1 Address). This cell controls the DNP3.0 address of the IED. Up to 32 IEDs can
be connected to one spur, therefore it is necessary for each IED to have a unique address so that messages
from the master control station are accepted by only one IED. DNP3.0 uses a decimal number between 1
and 65519 for the Relay Address. It is important that no two IEDs have the same address.
COMMUNICATIONS
RP1 Address
1
supported by the IED 1200 bps, 2400 bps, 4800 bps, 9600 bps, 19200 bps and 38400 bps. Make sure that
the baud rate selected on the IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
COMMUNICATIONS
RP1 Parity
None
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. Move down to the next cell (RP1 Time Sync). This cell affects the time synchronisation request from the
master by the IED. It can be set to enabled or disabled. If enabled it allows the DNP3.0 master to
synchronise the time on the IED.
COMMUNICATIONS
RP1 Time Sync
Enabled
6.3.9.1 DNP3 CONFIGURATOR

A PC support package for DNP3.0 is available as part of the supplied settings application software (MiCOM S1 Agile)
to allow configuration of the device's DNP3.0 response. The configuration data is uploaded from the device to the
PC in a block of compressed format data and downloaded in a similar manner after modification. The new DNP3.0
configuration takes effect after the download is complete. To restore the default configuration at any time, from
the CONFIGURATION column, select the Restore Defaults cell then select All Settings.
In MiCOM S1 Agile, the DNP3.0 data is shown in three main folders, one folder each for the point configuration,
integer scaling and default variation (data format). The point configuration also includes screens for binary inputs,
binary outputs, counters and analogue input configuration.
372 P64x-TM-EN-4.1
If the device supports DNP Over Ethernet, the configuration related settings are done in the folder DNP Over
Ethernet.
6.4 MODBUS
This section describes how the MODBUS standard is applied to the Px40 platform. It is not a description of the
standard itself. The level at which this section is written assumes that the reader is already familiar with the
MODBUS standard.
The MODBUS protocol is a master/slave protocol, defined and administered by the MODBUS Organization For
further information on MODBUS and the protocol specifications, please see the Modbus web site
(www.modbus.org).

Two connection options are available for MODBUS
The MODBUS interface uses ‘RTU’ mode communication rather than ‘ASCII’ mode as this provides more efficient
use of the communication bandwidth. This mode of communication is defined by the MODBUS standard.
When using a serial interface, the data format is: 1 start bit, 8 data bits, 1 parity bit with 1 stop bit, or 2 stop bits (a
total of 11 bits per character).
6.4.2 MODBUS FUNCTIONS

The following MODBUS function codes are supported:
● 01: Read Coil Status
● 02: Read Input Status
● 03: Read Holding Registers
● 04: Read Input Registers
● 06: Preset Single Register
● 08: Diagnostics
● 11: Fetch Communication Event Counter
● 12: Fetch Communication Event Log
● 16: Preset Multiple Registers 127 max
These are interpreted by the MiCOM IED in the following way:

● 01: Read status of output contacts (0xxxx addresses)
● 02: Read status of opto inputs (1xxxx addresses)
● 03: Read setting values (4xxxx addresses)
● 04: Read measured values (3xxxx addresses
● 06: Write single setting value (4xxxx addresses)
● 16: Write multiple setting values (4xxxx addresses)
6.4.3 RESPONSE CODES
MCode MODBUS Description MiCOM Interpretation

01 Illegal Function Code The function code transmitted is not supported by the slave.
P64x-TM-EN-4.1 373
MCode MODBUS Description MiCOM Interpretation

The start data address in the request is not an allowable value. If any of the addresses in
the range cannot be accessed due to password protection then all changes within the
02 Illegal Data Address request are discarded and this error response will be returned.
Note: If the start address is correct but the range includes non–implemented addresses
this response is not produced.
A value referenced in the data field transmitted by the master is not within range. Other
03 Illegal Value
values transmitted within the same packet will be executed if inside range.
The write command cannot be implemented due to the database being locked by another
06 Slave Device Busy interface. This response is also produced if the software is busy executing a previous
request.
6.4.4 REGISTER MAPPING

The device supports the following memory page references:
● Memory Page: Interpretation
● 0xxxx: Read and write access of the output relays
● 1xxxx: Read only access of the opto inputs
● 3xxxx: Read only access of data
● 4xxxx: Read and write access of settings
where xxxx represents the addresses available in the page (0 to 9999).

A complete map of the MODBUS addresses supported by the device is contained in the relevant menu database,
which is available on request.
Note:
The "extended memory file" (6xxxx) is not supported.
Note:
MODBUS convention is to document register addresses as ordinal values whereas the actual protocol addresses are literal
values. The MiCOM relays begin their register addresses at zero. Therefore, the first register in a memory page is register
address zero. The second register is register address 1 and so on.
Note:
The page number notation is not part of the address.
6.4.5 EVENT EXTRACTION

The device supports two methods of event extraction providing either automatic or manual extraction of the
stored event, fault, and maintenance records.
6.4.5.1 AUTOMATIC EVENT RECORD EXTRACTION

The automatic extraction facilities allow all types of record to be extracted as they occur. Event records are
extracted in sequential order including any fault or maintenance data that may be associated with the event.
The MODBUS master can determine whether the device has any events stored that have not yet been extracted.
This is performed by reading the status register 30001 (G26 data type). If the event bit of this register is set then the
device has non-extracted events available. To select the next event for sequential extraction, the master station
writes a value of 1 to the record selection register 40400 (G18 data type). The event data together with any fault/
maintenance data can be read from the registers specified below. Once the data has been read, the event record
can be marked as having been read by writing a value of '2' to register 40400.
374 P64x-TM-EN-4.1
6.4.5.2 MANUAL EVENT RECORD EXTRACTION

There are three registers available to manually select stored records and three read-only registers allowing the
number of stored records to be determined.
● 40100: Select Event
● 40101: Select Fault
● 40102: Select Maintenance Record
For each of the above registers a value of 0 represents the most recent stored record. The following registers can
be read to indicate the numbers of the various types of record stored.
● 30100: Number of stored records
● 30101: Number of stored fault records
● 30102: Number of stored maintenance records
Each fault or maintenance record logged causes an event record to be created. If this event record is selected, the
additional registers allowing the fault or maintenance record details will also become populated.
6.4.5.3 RECORD DATA

The location and format of the registers used to access the record data is the same whether they have been
selected using either automatic or manual extraction.
MODBUS
Event Description Length Comments
Address
Time and Date 30103 4 See G12 data type description
Event Type 30107 1 See G13 data type description
Nature of value depends on event type. This will contain the status as a binary flag
Event Value 30108 2
for contact, opto-input, alarm, and protection events.
This indicates the MODBUS register address where the change occurred.
Alarm 30011
Relays 30723
Optos 30725
MODBUS Address 30110 1
Protection events – like the relay and opto addresses this will map onto the
MODBUS address of the appropriate DDB status register depending on which bit
of the DDB the change occurred. These will range from 30727 to 30785.
For platform events, fault events and maintenance events the default is 0.
This register will contain the DDB ordinal for protection events or the bit number
Event Index 30111 1 for alarm events. The direction of the change will be indicated by the most
significant bit; 1 for 0 – 1 change and 0 for 1 – 0 change.
0 means that there is no additional data.
1 means fault record data can be read from 30113 to 30199 (number of registers
Additional Data Present 30112 1
depends on the product).
2 means maintenance record data can be read from 30036 to 30039.
If a fault record or maintenance record is directly selected using the manual mechanism then the data can be read
from the register ranges specified above. The event record data in registers 30103 to 30111 will not be available.
It is possible using register 40401(G6 data type) to independently clear the stored relay event/fault and
maintenance records. This register also provides an option to reset the device indications, which has the same
effect on the relay as pressing the clear key within the alarm viewer using the HMI panel menu.
6.4.6 DISTURBANCE RECORD EXTRACTION

The IED provides facilities for both manual and automatic extraction of disturbance records.
P64x-TM-EN-4.1 375
Records extracted over MODBUS from Px40 devices are presented in COMTRADE format. This involves extracting
an ASCII text configuration file and then extracting a binary data file.
Each file is extracted by reading a series of data pages from the IED The data page is made up of 127 registers,
giving a maximum transfer of 254 bytes per page.
The following set of registers is presented to the master station to support the extraction of uncompressed
disturbance records:
MODBUS registers
MODBUS Register Name Description
Provides the status of the relay as bit flags:
b0: Out of service
b1: Minor self test failure
b2: Event
b3: Time synchronization
3x00001 Status register b4: Disturbance
b5: Fault
b6: Trip
b7: Alarm
b8 to b15: Unused
A ‘1’ on b4 indicates the presence of a disturbance
Indicates the total number of disturbance records currently stored in the
3x00800 No of stored disturbances
relay, both extracted and non-extracted.
Indicates the unique identifier value for the oldest disturbance record
Unique identifier of the oldest stored in the relay. This is an integer value used in conjunction with the
3x00801
disturbance record ‘Number of stored disturbances’ value to calculate a value for manually
selecting records.
This register is used to manually select disturbance records. The values
written to this cell are an offset of the unique identifier value for the
Manual disturbance record
4x00250 oldest record. The offset value, which ranges from 0 to the Number of
selection register
stored disturbances - 1, is added to the identifier of the oldest record to
generate the identifier of the required record.
This register is used during the extraction process and has a number of
commands. These are:
b0: Select next event
Record selection command b1: Accept event
4x00400
register b2: Select next disturbance record
b3: Accept disturbance record
b4: Select next page of disturbance data
b5: Select data file
3x00930 - 3x00933 Record time stamp These registers return the timestamp of the disturbance record.
This register informs the master station of the number of registers in the
3x00802 No of registers in data page
data page that are populated.
These 127 registers are used to transfer data from the relay to the master
3x00803 - 3x00929 Data page registers
station. They are 16-bit unsigned integers.
The disturbance record status register is used during the extraction
Disturbance record status
3x00934 process to indicate to the master station when data is ready for
register
extraction. See next table.
This is used to select the required data file format. This is reserved for
4x00251 Data file format selection
future use.
376 P64x-TM-EN-4.1
Note:
Register addresses are provided in reference code + address format. E.g. 4x00001 is reference code 4x, address 1 (which is
specified as function code 03, address 0x0000 in the MODBUS specification).
The disturbance record status register will report one of the following values:
Disturbance record states

State Description
This will be the state reported when no record is selected; such as after power on or after a record has been
Idle
marked as extracted.
Busy The relay is currently processing data.
Page ready The data page has been populated and the master station can now safely read the data.
Configuration complete All of the configuration data has been read without error.
Record complete All of the disturbance data has been extracted.
An error occurred during the extraction process where the disturbance being extracted was overwritten by a
Disturbance overwritten
new record.
An attempt was made by the master station to automatically select the next oldest non-extracted
No non-extracted disturbances
disturbance when all records have been extracted.
Not a valid disturbance An attempt was made by the master station to manually select a record that did not exist in the relay.
Command out of sequence The master station issued a command to the relay that was not expected during the extraction process.
6.4.6.1 MANUAL EXTRACTION PROCEDURE

The procedure used to extract a disturbance manually is shown below. The manual method of extraction does not
allow for the acceptance of disturbance records.
P64x-TM-EN-4.1 377
Start
Get number of
disturbances from
register 3x00800
No Are there Yes

disturbances?
Get oldest disturbance ID

from register 3x00801
Select required disturbance

by writing the ID value of
the required record to
register 4x00250
Get disturbance time stamp

Extract disturbance data from registers 3x00930 –
3x00933
End
V01003
Figure 163: Manual selection of a disturbance record
6.4.6.2 AUTOMATIC EXTRACTION PROCEDURE

There are two methods that can be used for automatically extracting disturbances:
Method 1
Method 1 is simpler and is better at extracting single disturbance records (when the disturbance recorder is polled
regularly).
378 P64x-TM-EN-4.1
Start
Read status word from

register 3x0001
Is disturbance bit No
(bit 4) set?
Yes
Error
Select next oldest non-

extracted record by writing
0x04 to register 4x00400
Send command to accept

Extract disturbance data record by writing 0x08 to
register 4x00400
V01004
Figure 164: Automatic selection of disturbance record - method 1
Method 2
Method 2 is more complex to implement but is more efficient at extracting large quantities of disturbance records.
This may be useful when the disturbance recorder is polled only occasionally and therefore may have many stored
records.
P64x-TM-EN-4.1 379
Start
FirstTime = True
Read status word from

register 3x0001
FirstTime = True
Is disturbance bit
(bit 4) set? No
Yes
Select next oldest non- Yes Is FirstTime =

extracted record by writing
True?
0x04 to register 4x00400
No
FirstTime = False
Send command to accept

Error and select next record by
FirstTime = True Extract disturbance record
writing 0x0C to register
4x00400
V01005
Figure 165: Automatic selection of disturbance record - method 2
6.4.6.3 EXTRACTING THE DISTURBANCE DATA

The extraction of the disturbance record is a two-stage process that involves extracting the configuration file first
and then the data file. first the configuration file must be extracted, followed by the data file:
380 P64x-TM-EN-4.1
Extracting the Comtrade configuration file
Start
(Record selected)
To parent
procedure
Read DR status value Busy
Check DR status
for error
conditions or Error
Busy status
Configuration complete What is the value Other

of DR status?
Page ready
Read number of
registers in data page
from address 3x00802
Read data page

registers starting at
3x00803
Store data to ASCII file Send ‘Get next page of

Configuration complete
in the order the data data’ to register
(begin extracting data were received 4x00400
file)
V01006
Figure 166: Configuration file extraction
P64x-TM-EN-4.1 381
Extracting the comtrade data file
Start
(Configuration
complete)
Send ‘Select Data File’

to register 4x00400
To parent
procedure
Read DR status value Busy
Check DR status
for error
conditions or Error
Busy status
Record complete What is the value Other

of DR status?
Page ready
Read number of
registers in data page
from address 3x00802
Read data page

registers starting at
3x00803
Record complete (mark Store data to binary file Send ‘Get next page of
record as extracted; in the order the data data’ to register
automatic extraction only) were received 4x00400
V01007
Figure 167: Data file extraction
During the extraction of the COMTRADE files, an error may occur, which will be reported on the DR Status register
3x00934. In this case, you must take action to re-start the record extraction or to abort according to the table
below.
Value State Description
This will be the state reported when no record is selected; such as after power on or after a record has
0 Idle
been marked as extracted.
1 Busy The relay is currently processing data.
2 Page ready The data page has been populated and the master station can now safely read the data.
Configuration
3 All of the configuration data has been read without error.
complete
4 Record complete All of the disturbance data has been extracted.
Disturbance An error occurred during the extraction process where the disturbance being extracted was overwritten
5
overwritten by a new record.
382 P64x-TM-EN-4.1
Value State Description

No unextracted An attempt was made by the master station to automatically select the next oldest unextracted
6
disturbances disturbance when all records have been extracted.
7 Not a valid disturbance An attempt was made by the master station to manually select a record that did not exist in the relay.
Command out of
8 The master station issued a command to the relay that was not expected during the extraction process.
sequence
6.4.7 SETTING CHANGES

All the IED settings are 4xxxx page addresses. The following points should be noted when changing settings:
● Settings implemented using multiple registers must be written to using a multi-register write operation.
● The first address for a multi-register write must be a valid address. If there are unmapped addresses within
the range being written to, the data associated with these addresses will be discarded.
● If a write operation is performed with values that are out of range, the illegal data response will be
produced. Valid setting values within the same write operation will be executed.
● If a write operation is performed, which attempts to change registers requiring a higher level of password
access than is currently enabled then all setting changes in the write operation will be discarded.
6.4.8 PASSWORD PROTECTION

The following registers are available to control password protection:
Function MODBUS Registers
Password entry 4x00001 to 4x00002 and 4x20000 to 4x20003
Setting to change password level 1 (4 character) 4x00023 to 4x00024
Setting to change password level 1 (8 character) 4x20008 to 4x20011
Setting to change password level 2 4x20016 to 4x20019
Setting to change password level 3 4x20024 to 4x20027
Can be read to indicate current access level 3x00010
6.4.9 PROTECTION AND DISTURBANCE RECORDER SETTINGS

Setting changes to either of these areas are stored in a scratchpad area and will not be used by the IED unless
confirmed. Register 40405 can be used either to confirm or abort the setting changes within the scratchpad area.
The IED supports four groups of protection settings. The MODBUS addresses for each of the four groups are
repeated within the following address ranges.
● Group 1: 4x1000 - 4x2999
● Group 2: 4x3000 - 4x4999
● Group 3: 4x5000 - 4x6999
● Group 4: 4x7000 - 4x8999
In addition to the basic editing of the protection setting groups, the following functions are provided:
● Default values can be restored to a setting group or to all of the relay settings by writing to register 4x0402.
● It is possible to copy the contents of one setting group to another by writing the source group to register
40406 and the target group to 4x0407.
The setting changes performed by either of the two operations defined above are made to the scratchpad area.
These changes must be confirmed by writing to register 4x0405.
The active protection setting groups can be selected by writing to register 40404. An illegal data response will be
returned if an attempt is made to set the active group to one that has been disabled.
P64x-TM-EN-4.1 383

The date-time data type G12 allows real date and time information to be conveyed to a resolution of 1 ms. The
structure of the data type is compliant with the IEC 60870-5-4 Binary Time 2a format.
The seven bytes of the date/time frame are packed into four 16-bit registers and are transmitted in sequence
starting from byte 1. This is followed by a null byte, making eight bytes in total.
Register data is usually transmitted starting with the highest-order byte. Therefore byte 1 will be in the high-order
byte position followed by byte 2 in the low-order position for the first register. The last register will contain just byte
7 in the high order position and the low order byte will have a value of zero.
G12 date & time data type structure

Bit Position
Byte 7 6 5 4 3 2 1 0
1 m7 m6 m5 m4 m3 m2 m1 m0
2 m15 m14 m13 m12 m11 m10 m9 m8
3 IV R I5 I4 I3 I2 I1 I0
4 SU R R H4 H3 H2 H1 H0
5 W2 W1 W0 D4 D3 D2 D1 D0
6 R R R R M3 M2 M1 M0
7 R Y6 Y5 Y4 Y3 Y2 Y1 Y0
Key to table:
● m = milliseconds: 0 to 59,999
● I = minutes: 0 to 59
● H = hours: 0 to 23
● W = day of the week: 1 to 7 starting from Monday
● D = day of the month: 1 to 31
● M = month of the year: 1 to 12 starting from January
● Y = year of the century: 0 to 99
● R = reserved: 0
● SU = summertime: 0 = GMT, 1 = summertime
● IV = invalid: 0 = invalid value, 1 = valid value
Since the range of the data type is only 100 years, the century must be deduced. The century is calculated as the
one that will produce the nearest time value to the current date. For example: 30-12-99 is 30-12-1999 when
received in 1999 & 2000, but is 30-12-2099 when received in 2050. This technique allows 2 digit years to be
accurately converted to 4 digits in a ±50 year window around the current date.
The invalid bit has two applications:
● It can indicate that the date-time information is considered inaccurate, but is the best information available.
● It can indicate that the date-time information is not available.
The summertime bit is used to indicate that summertime (day light saving) is being used and, more importantly, to
resolve the alias and time discontinuity which occurs when summertime starts and ends. This is important for the
correct time correlation of time stamped records.
The day of the week field is optional and if not calculated will be set to zero.
The concept of time zone is not catered for by this data type and hence by the relay. It is up to the end user to
determine the time zone. Normal practice is to use UTC (universal co-ordinated time).
384 P64x-TM-EN-4.1
6.4.11 POWER AND ENERGY MEASUREMENT DATA FORMATS

The power and energy measurements are available in two data formats:
Data Type G29: an integer format using 3 registers
Data Type G125: a 32 bit floating point format using 2 registers
The G29 registers are listed in the first part of the MEASUREMENTS 2 column of the Courier database. The G125
equivalents appear at the end of the MEASUREMENTS 2 column.
Data type G29

Data type G29 consists of three registers:
The first register is the per unit (or normalised) power or energy measurement. It is a signed 16 bit quantity. This
register is of Data Type G28.
The second and third registers contain a multiplier to convert the per unit value to a real value. These are unsigned
32-bit quantities. These two registers together are of Data Type G27.
Thee overall power or energy value conveyed by the G29 data type is therefore G29 = G28 x G27.
The IED calculates the G28 per unit power or energy value as:
G28 = (measured secondary quantity/CT secondary)(110V/(VT secondary).
Since data type G28 is a signed 16-bit integer, its dynamic range is constrained to +/- 32768. You should take this
limitation into consideration for the energy measurements, as the G29 value will saturate a long time before the
equivalent G125 does.
The associated G27 multiplier is calculated as:
G27 = (CT primary)(VT primary/110V) when primary value measurements are selected
and
G27 = (CT secondary)(VT secondary/110V) when secondary value measurements are selected.
Due to the required truncations from floating point values to integer values in the calculations of the G29
component parts and its limited dynamic range, we only recommend using G29 values when the MODBUS master
cannot deal with the G125 IEEE754 floating point equivalents.
Note:
The G29 values must be read in whole multiples of three registers. It is not possible to read the G28 and G27 parts with
separate read commands.
Example of Data Type G29

Assuming the CT/VT configurations are as follows:
● Main VT Primary 6.6 kV
● Main VT Secondary 110 V
● Phase CT Primary 3150 A
● Phase CT Secondary 1 A
The Three-phase Active Power displayed on the measurement panel on the front display of the IED would be 21.94
MW
The registers related to the Three-phase Active Power are: 3x00327, 3x00328, 3x00329
Register Address Data read from these registers Format of the data
3x00327 116 G28
3x00328 2 G27
P64x-TM-EN-4.1 385
Register Address Data read from these registers Format of the data
3x00329 57928 G27
The Equivalent G27 value = [216 * Value in the address 3x00328 + Value in the address 3x00329] = 216*2 + 57928 =
189000
The Equivalent value of power G29 = G28 * Equivalent G27 =116 * 189000 =21.92 MW
Note:
The above calculated value (21.92 MW) is same as the power value measured on the front panel display.
Data type G125

Data type G125 is a short float IEEE754 floating point format, which occupies 32 bits in two consecutive registers.
The high order byte of the format is in the first (low order) register and the low order byte in the second register.
The value of the G125 measurement is as accurate as the IED's ability to resolve the measurement after it has
applied the secondary or primary scaling factors. It does not suffer from the truncation errors or dynamic range
limitations associated with the G29 data format.
6.4.12 MODBUS CONFIGURATION

3. Move to the first cell down (RP1 protocol). This is a non settable cell, which shows the chosen
communication protocol – in this case Modbus.
COMMUNICATIONS
RP1 Protocol
Modbus
4. Move down to the next cell (RP1 Address). This cell controls the Modbus address of the IED. Up to 32 IEDs
can be connected to one spur, therefore it is necessary for each IED to have a unique address so that
messages from the master control station are accepted by only one IED. Modbus uses a decimal number
between 1 and 247 for the Relay Address. It is important that no two IEDs have the same address.
COMMUNICATIONS
RP1 Address
1
controls how long the IED waits without receiving any messages on the rear port before it reverts to its
default state, including revoking any password access that was enabled. For the rear port this can be set
between 1 and 30 minutes.
COMMUNICATIONS
RP1 Inactivtimer
10.00 mins
386 P64x-TM-EN-4.1
supported by the IED 1200 bits/s, 2400 bits/s, 4800 bits/s, 9600 bits/s, 19200 bits/s and 38400 bits/s. Make
sure that the baud rate selected on the IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
COMMUNICATIONS
RP1 Parity
None
8. Move down to the next cell (Modbus IEC Time). This cell controls the order in which the bytes of information
are transmitted. There is a choice of Standard or Reverse. When Standard is selected the time format
complies with IEC 60870-5-4 requirements such that byte 1 of the information is transmitted first, followed
by bytes 2 through to 7. If Reverse is selected the transmission of information is reversed.
COMMUNICATIONS
Modbus IEC Time
Standard
6.5 IEC 61850

This section describes how the IEC 61850 standard is applied to General Electric products. It is not a description of
the standard itself. The level at which this section is written assumes that the reader is already familiar with the
IEC 61850 standard.
IEC 61850 is the international standard for Ethernet-based communication in substations. It enables integration of
all protection, control, measurement and monitoring functions within a substation, and additionally provides the
means for interlocking and inter-tripping. It combines the convenience of Ethernet with the security that is so
essential in substations today.
There are two editions of most parts of the IEC 61850 standard; edition 1 and edition 2. The edition which this
product supports depends on the Software Version.
From Software Version 90 onwards, it is possible to select between edition 1 and edition 2. Switching between
edition 1 and edition 2 is described in the Selection of the IEC 61850 Edition section.
An additional section detailing the enhancements in edition 2 models is documented later in this chapter, if
applicable.
6.5.1 BENEFITS OF IEC 61850

The standard provides:
● Standardised models for IEDs and other equipment within the substation
● Standardised communication services (the methods used to access and exchange data)
● Standardised formats for configuration files
● Peer-to-peer communication
The standard adheres to the requirements laid out by the ISO OSI model and therefore provides complete vendor
interoperability and flexibility on the transmission types and protocols used. This includes mapping of data onto
P64x-TM-EN-4.1 387
Ethernet, which is becoming more and more widely used in substations, in favour of RS485. Using Ethernet in the
substation offers many advantages, most significantly including:
● Ethernet allows high-speed data rates (currently 100 Mbps, rather than tens of kbps or less used by most
serial protocols)
● Ethernet provides the possibility to have multiple clients
● Ethernet is an open standard in every-day use
● There is a wide range of Ethernet-compatible products that may be used to supplement the LAN installation
(hubs, bridges, switches)
6.5.2 IEC 61850 INTEROPERABILITY

A major benefit of IEC 61850 is interoperability. IEC 61850 standardizes the data model of substation IEDs, which
allows interoperability between products from multiple vendors.
An IEC 61850-compliant device may be interoperable, but this does not mean it is interchangeable. You cannot
simply replace a product from one vendor with that of another without reconfiguration. However the terminology
is pre-defined and anyone with prior knowledge of IEC 61850 should be able to integrate a new device very quickly
without having to map all of the new data. IEC 61850 brings improved substation communications and
interoperability to the end user, at a lower cost.
6.5.3 THE IEC 61850 DATA MODEL

The data model of any IEC 61850 IED can be viewed as a hierarchy of information, whose nomenclature and
categorization is defined and standardized in the IEC 61850 specification.
Data Attributes
stVal q t PhA PhB PhC
Data Objects
Pos A
Logical Nodes : 1 to n
LN1: XCBR LN2: MMXU
Logical Device : IEDs 1 to n
Physical Device (network address)
V01008
Figure 168: Data model layers in IEC 61850
The levels of this hierarchy can be described as follows:
Data Frame format

Layer Description
Identifies the actual IED within a system. Typically the device’s name or IP address can be used (for
Physical Device
example Feeder_1 or 10.0.0.2.
Identifies groups of related Logical Nodes within the Physical Device. For the MiCOM IEDs, 5 Logical
Logical Device
Devices exist: Control, Measurements, Protection, Records, System.
388 P64x-TM-EN-4.1
Layer Description
Identifies the major functional areas within the IEC 61850 data model. Either 3 or 6 characters are
used as a prefix to define the functional group (wrapper) while the actual functionality is identified by
Wrapper/Logical Node Instance a 4 character Logical Node name suffixed by an instance number.
For example, XCBR1 (circuit breaker), MMXU1 (measurements), FrqPTOF2 (overfrequency protection,
stage 2).
This next layer is used to identify the type of data you will be presented with. For example, Pos
Data Object
(position) of Logical Node type XCBR.
This is the actual data (measurement value, status, description, etc.). For example, stVal (status value)
Data Attribute
indicating actual position of circuit breaker for Data Object type Pos of Logical Node type XCBR.
6.5.4 IEC 61850 IN MICOM IEDS

IEC 61850 is implemented by use of a separate Ethernet card. This Ethernet card manages the majority of the
IEC 61850 implementation and data transfer to avoid any impact on the performance of the protection functions.
To communicate with an IEC 61850 IED on Ethernet, it is necessary only to know its IP address. This can then be
configured into either:
● An IEC 61850 client (or master), for example a bay computer (MiCOM C264)
● An HMI
● An MMS browser, with which the full data model can be retrieved from the IED, without any prior knowledge
of the IED
The IEC 61850 compatible interface standard provides capability for the following:
● Read access to measurements
● Refresh of all measurements at a standard rate.
● Generation of non-buffered and buffered reports on change of status or measurement
● SNTP time synchronization over an Ethernet link. (This is used to synchronize the IED's internal real time
clock.
● GOOSE peer-to-peer communication
● Disturbance record extraction by IEC 61850 MMS file transfer. The record is extracted as an ASCII format
COMTRADE file
● Controls (Direct and Select Before Operate)
Note:
Setting changes are not supported in the current IEC 61850 implementation. Currently these setting changes are carried out
using the settings application software.
6.5.5 IEC 61850 DATA MODEL IMPLEMENTATION

The data model naming adopted in the IEDs has been standardised for consistency. Therefore the Logical Nodes
are allocated to one of the five Logical Devices, as appropriate.
The data model is described in the Model Implementation Conformance Statement (MICS) document, which is
available as a separate document.
6.5.6 IEC 61850 COMMUNICATION SERVICES IMPLEMENTATION

The IEC 61850 communication services which are implemented in the IEDs are described in the Protocol
Implementation Conformance Statement (PICS) document, which is available as a separate document.
P64x-TM-EN-4.1 389
6.5.7 IEC 61850 PEER-TO-PEER (GOOSE) COMMUNICATIONS

The implementation of IEC 61850 Generic Object Oriented Substation Event (GOOSE) enables faster
communication between IEDs offering the possibility for a fast and reliable system-wide distribution of input and
output data values. The GOOSE model uses multicast services to deliver event information. Multicast messaging
means that messages are sent to selected devices on the network. The receiving devices can specifically accept
frames from certain devices and discard frames from the other devices. It is also known as a publisher-subscriber
system. When a device detects a change in one of its monitored status points it publishes a new message. Any
device that is interested in the information subscribes to the data it contains.
6.5.8 MAPPING GOOSE MESSAGES TO VIRTUAL INPUTS

Each GOOSE signal contained in a subscribed GOOSE message can be mapped to any of the virtual inputs within
the PSL. The virtual inputs allow the mapping to internal logic functions for protection control, directly to output
contacts or LEDs for monitoring.
An IED can subscribe to all GOOSE messages but only the following data types can be decoded and mapped to a
virtual input:
● BOOLEAN
● BSTR2
● INT16
● INT32
● INT8
● UINT16
● UINT32
● UINT8
6.5.8.1 IEC 61850 GOOSE CONFIGURATION

All GOOSE configuration is performed using the IEC 61850 Configurator tool available in the MiCOM S1 Agile
software application.
All GOOSE publishing configuration can be found under the GOOSE Publishing tab in the configuration editor
window. All GOOSE subscription configuration parameters are under the External Binding tab in the configuration
editor window.
Settings to enable GOOSE signalling and to apply Test Mode are available using the HMI.
6.5.9 ETHERNET FUNCTIONALITY

IEC 61850 Associations are unique and made between the client and server. If Ethernet connectivity is lost for any
reason, the associations are lost, and will need to be re-established by the client. The IED has a TCP_KEEPALIVE
function to monitor each association, and terminate any which are no longer active.
The IED allows the re-establishment of associations without disruption of its operation, even after its power has
been removed. As the IED acts as a server in this process, the client must request the association. Uncommitted
settings are cancelled when power is lost, and reports requested by connected clients are reset. The client must
re-enable these when it next creates the new association to the IED.
6.5.10 IEC 61850 CONFIGURATION

You cannot configure the device for IEC 61850 edition 1 using the HMI panel on the product. For this you must use
the IEC 61850 Configurator, which is part of the settings application software. If the device is compatible with
edition 2, however, you can configure it with the HMI. To configure IEC61850 edition 2 using the HMI, you must first
enable the IP From HMI setting, after which you can set the media (copper or fibre), IP address, subnet mask and
gateway address.
390 P64x-TM-EN-4.1
IEC 61850 allows IEDs to be directly configured from a configuration file. The IED’s system configuration
capabilities are determined from an IED Capability Description file (ICD), supplied with the product. By using ICD
files from the products to be installed, you can design, configure and test (using simulation tools), a substation’s
entire protection scheme before the products are installed into the substation.
To help with this process, the settings application software provides an IEC 61850 Configurator tool, which allows
the pre-configured IEC 61850 configuration file to be imported and transferred to the IED. As well as this, you can
manually create configuration files for all products, based on their original IED capability description (ICD file).
Other features include:
● The extraction of configuration data for viewing and editing.
● A sophisticated error checking sequence to validate the configuration data before sending to the IED.
Note:
Some configuration data is available in the IEC61850 CONFIG. column, allowing read-only access to basic configuration data.
6.5.10.1 IEC 61850 CONFIGURATION BANKS

There are two configuration banks:
● Active Configuration Bank
● Inactive Configuration Bank
Any new configuration sent to the IED is automatically stored in the inactive configuration bank, therefore not
immediately affecting the current configuration.
Following an upgrade, the IEC 61850 Configurator tool can be used to transmit a command, which authorises
activation of the new configuration contained in the inactive configuration bank. This is done by switching the
active and inactive configuration banks. The capability of switching the configuration banks is also available using
the IEC61850 CONFIG. column of the HMI.
The SCL Name and Revision attributes of both configuration banks are available in the IEC61850 CONFIG. column
of the HMI.
6.5.10.2 IEC 61850 NETWORK CONNECTIVITY

Configuration of the IP parameters and SNTP (Simple Network Time Protocol) time synchronisation parameters is
performed by the IEC 61850 Configurator tool. If these parameters are not available using an SCL (Substation
Configuration Language) file, they must be configured manually.
Every IP address on the Local Area Network must be unique. Duplicate IP addresses result in conflict and must be
avoided. Most IEDs check for a conflict on every IP configuration change and at power up and they raise an alarm
if an IP conflict is detected.
The IED can be configured to accept data from other networks using the Gateway setting. If multiple networks are
used, the IP addresses must be unique across networks.
6.5.11 SELECTION OF THE IEC 61850 EDITION

From Software Version 90 onwards, it is possible to select between edition 1 and edition 2. edition 1 and edition 2
implementations have different IEC 61850 data models and different ICD files. Only one can be active at any time
in the product, so the selection is a decision related to system engineering.
Selection of edition 1 or edition 2 is done based on the configuration file (MCL) that is sent to the product and
activated.
P64x-TM-EN-4.1 391
To configure the product for edition 1, start with the edition 1 ICD file. This can be done in one of two ways:
1. Using the system engineering process of an IEC 61850 system. In this case, import either the edition 1 ICD
file (for example “P545____91A_ED1.ICD”) or the edition 2 ICD file (for example “P545____91A_ED2.ICD”), as
applicable, into the System Configuration Tool. Perform the system configuration, then export the
configured file (.SCD or CID). Import this configured file into MiCOM S1 Agile’s IEC 61850 Configurator.
2. Using the IED Configurator tool to manually configure the product. Launch the IED Configurator tool. Select
File, New and then check only the Edition 1 or Edition 2 box, as applicable, and then proceed to select the
product model and software version. Configure the parameters manually and save the MCL file.
In either case, the edition 1 or edition 2 configuration is activated in the product by sending the configuration file to
the product from the IED Configurator and switching it to the Active Bank, after which the Ethernet application will
restart with the new configuration.
6.5.12 IEC 61850 EDITION 2

Many parts of the IEC 61850 standard have now been released as the second edition. This offers some significant
enhancements including:
● Improved interoperability
● Many new logical nodes
● Better defined testing; it is now possible to perform off-line testing and simulation of functions
Edition 2 implementation requires use of version 3.8 of the IEC 61850 configurator, which is installed with version
2.0.1 of MiCOM S1 Agile.
6.5.12.1 BACKWARD COMPATIBILITY
IEC61850 System - Backward compatibility

An Edition 1 IED can operate with an Edition 2 IEC 61850 system, provided that the Edition 1 IEDs do not subscribe
to GOOSE messages with data objects or data attributes which are only available in Edition 2.
The following figure explains this concept:
392 P64x-TM-EN-4.1
Ed2
MMS
IED1 IED2 IED3

C
C C
L/ R
Ed1 Ed1 Ed2
GOOSE
BAY
Ed1 devices in Ed2 system:
 GOOSE OK
 MMS OK
 TOOLS (SCL files) OK V01056
Figure 169: Edition 2 system - backward compatibility
An Edition 2 IED cannot normally operate within an Edition 1 IEC 61850 system. An Edition 2 IED can work for
GOOSE messaging in a mixed system, providing the client is compatible with Edition 2.
Ed1
MMS
IED1 IED2 IED3

C
C C
L/ R
Ed1 Ed1 Ed2
GOOSE
BAY
Ed1 devices in Ed2 system:
 GOOSE OK
 MMS Not OK
 TOOLS (SCL files) Not OK V01057
Figure 170: Edition 1 system - forward compatibility issues
P64x-TM-EN-4.1 393
6.5.12.2 EDITION-2 COMMON DATA CLASSES

The following common data classes (CDCs) are new to Edition 2 and therefore should not be used in GOOSE control
blocks in mixed Edition 1 and Edition 2 systems
● Histogram (HST)
● Visible string status (VSS)
● Object reference setting (ORG)
● Controllable enumerated status (ENC)
● Controllable analogue process value (APC)
● Binary controlled analogue process value (BAC)
● Enumerated status setting (ENG)
● Time setting group (TSG)
● Currency setting group (CUG)
● Visible string setting (VSG)
● Curve shape setting (CSG)
Of these, only ENS and ENC types are available from a MiCOM P40 IED when publishing GOOSE messages, so Data
Objects using these Common Data Classes should not be published in mixed Edition 1 and Edition 2 systems.
For compatibility between Edition 1 and Edition 2 IEDs, SCL files using SCL schema version 2.1 must be used. For a
purely Edition 2 system, use the schema version 3.1.
6.5.12.3 STANDBY PROTECTION REDUNDANCY

With digital substation architectures, measurements can be shared freely on the process bus across the
substation and between different devices without any additional wiring. This is because there are no longer any
electrical connections to instruments transformers that restrict the location of IEDs.
The new IEC 61850 Edition 2 test modes enable the introduction of standby protection IEDs at any location within
the substation, which has access to both station and process buses. In the case of failure, these devices can
temporarily replace the protection functions inside other IEDs.
MPx MP1 MP2 MP1 MP2
Standby
BAY(S) BAY1 BAY N
Station/Process Bus
Yard Yard
SC MU1 SC MU2 SC MU1 SC MU2
MU1 MU2 MU1 MU2

V01059
Figure 171: Example of Standby IED
394 P64x-TM-EN-4.1
See the example below. If a failure occurs in the Bay 1 protection IED (MP2), we could disable this device and
activate a standby protection IED to replace its functionality.
MP2 MP1 MP2 (1) MP1 MP2
Standby
BAY(S) BAY1 BAY N
(5) (2)
Station/Process Bus
(4)
Yard Yard
Test
Device SC MU1 SC MU2 SC MU1 SC MU2
MU1 MU2 MU1 MU2

V01060
Figure 172: Standby IED Activation Process
The following sequence would occur under this scenario:

1. During the installation phase, a spare standby IED is installed in the substation. This can remain inactive,
until it is needed to replace functions in one of several bays. The device is connected to the process bus, but
does not have any subscriptions enabled.
2. If a failure occurs (in this example, bay 1), first isolate the faulty device by disabling its process bus and
station bus interfaces. You do this by turning off the attached network interfaces.
3. Retrieve the configuration that the faulty device normally uses, and load this into the standby redundant
IED.
4. Place the IED into the "Test Blocked" mode, as defined in IEC 61850-7-4 Edition Two. This allows test signals
to be injected into the network, which will check that the configuration is correct. GOOSE signals issued by
the device will be flagged as "test" so that subscribing switchgear controllers know not to trip during this
testing. In this way the protection can be tested all the way up to the switchgear control merging units
without having to operate primary circuit breakers, or by carrying out any secondary injection.
5. Take the standby IED out of "Test-Blocked" mode and activate it so that it now replaces the protection
functions that were disabled from the initial device failure.
The standby IED reduces downtime in the case of device failure, as protection functions can be restored quickly
before the faulted device is replaced.
P64x-TM-EN-4.1 395
7 READ ONLY MODE

With IEC 61850 and Ethernet/Internet communication capabilities, security has become an important issue. For
this reason, all relevant General Electric IEDs have been adapted to comply with the latest cyber-security
standards.
In addition to this, a facility is provided which allows you to enable or disable the communication interfaces. This
feature is available for products using Courier, IEC 60870-5-103, or IEC 61850.
7.1 IEC 60870-5-103 PROTOCOL BLOCKING

If Read-Only Mode is enabled for RP1 or RP2 with IEC 60870-5-103, the following commands are blocked at the
interface:
● Write parameters (=change setting) (private ASDUs)
● General Commands (ASDU20), namely:
○ INF16 auto-recloser on/off
○ INF19 LED reset
○ Private INFs (for example: CB open/close, Control Inputs)
The following commands are still allowed:
● Poll Class 1 (Read spontaneous events)
● Poll Class 2 (Read measurands)
● GI sequence (ASDU7 'Start GI', Poll Class 1)
● Transmission of Disturbance Records sequence (ASDU24, ASDU25, Poll Class 1)
● Time Synchronisation (ASDU6)
● General Commands (ASDU20), namely:
○ INF23 activate characteristic 1
Note:
For IEC 60870-5-103, Read Only Mode function is different from the existing Command block feature.
7.2 COURIER PROTOCOL BLOCKING

If Read-Only Mode is enabled for RP1 or RP2 with Courier, the following commands are blocked at the interface:
● Write settings
● All controls, including:Reset Indication (Trip LED)
○ Operate Control Inputs
○ CB operations
○ Auto-reclose operations
○ Reset demands
○ Clear event/fault/maintenance/disturbance records
○ Test LEDs & contacts
396 P64x-TM-EN-4.1

● Read settings, statuses, measurands
● Read records (event, fault, disturbance)
● Time Synchronisation
● Change active setting group
7.3 IEC 61850 PROTOCOL BLOCKING

If Read-Only Mode is enabled for the Ethernet interfacing with IEC 61850, the following commands are blocked at
the interface:
● All controls, including:
○ Enable/disable protection
○ Operate Control Inputs
○ CB operations (Close/Trip, Lock)
○ Reset LEDs
● Read statuses, measurands
● Generate reports
● Extract disturbance records
● Time synchronisation
● Change active setting group
7.4 READ-ONLY SETTINGS

The following settings are available for enabling or disabling Read Only Mode.
● RP1 Read Only
● RP2 Read Only (only for products that have RP2)
● NIC Read Only (where Ethernet is available)
7.5 READ-ONLY DDB SIGNALS

The remote read only mode is also available in the PSL using three dedicated DDB signals:
● RP1 Read Only
● RP2 Read Only (only for products that have RP2)
● NIC Read Only (where Ethernet is available)
Using the PSL, these signals can be activated by opto-inputs, Control Inputs and function keys if required.
P64x-TM-EN-4.1 397
8 TIME SYNCHRONISATION
In modern protection schemes it is necessary to synchronise the IED's real time clock so that events from different
devices can be time stamped and placed in chronological order. This is achieved in various ways depending on the
chosen options and communication protocols.
● Using the IRIG-B input (if fitted)
● Using the SNTP time protocol (for Ethernet IEC 61850 versions + DNP3 OE)
● By using the time synchronisation functionality inherent in the data protocols
8.1 DEMODULATED IRIG-B

IRIG stands for Inter Range Instrumentation Group, which is a standards body responsible for standardising
different time code formats. There are several different formats starting with IRIG-A, followed by IRIG-B and so on.
The letter after the "IRIG" specifies the resolution of the time signal in pulses per second (PPS). IRIG-B, the one which
we use has a resolution of 100 PPS. IRIG-B is used when accurate time-stamping is required.
The following diagram shows a typical GPS time-synchronised substation application. The satellite RF signal is
picked up by a satellite dish and passed on to receiver. The receiver receives the signal and converts it into time
signal suitable for the substation network. IEDs in the substation use this signal to govern their internal clocks and
event recorders.
GPS satellite
GPS time signal
IRIG-B
Satellite dish Receiver IED IED IED
V01040
Figure 173: GPS Satellite timing signal
The IRIG-B time code signal is a sequence of one second time frames. Each frame is split up into ten 100 mS slots
as follows:
● Time-slot 1: Seconds
● Time-slot 2: Minutes
● Time-slot 3: Hours
● Time-slot 4: Days
● Time-slot 5 and 6: Control functions
● Time-slots 7 to 10: Straight binary time of day
398 P64x-TM-EN-4.1
The first four time-slots define the time in BCD (Binary Coded Decimal). Time-slots 5 and 6 are used for control
functions, which control deletion commands and allow different data groupings within the synchronisation strings.
Time-slots 7-10 define the time in SBS (Straight Binary Second of day).
8.1.1 IRIG-B IMPLEMENTATION

Depending on the chosen hardware options, the product can be equipped with an IRIG-B input for time
synchronisation purposes. The IRIG-B interface is implemented either on a dedicated card, or together with other
communication functionality such as Ethernet. The IRIG-B connection is presented by a connector is a BNC
connector. IRIG-B signals are usually presented as an RF-modulated signal. There are two types of input to our
IRIG-B boards: demodulated or modulated. A board that accepts a demodulated input is used where the IRIG-B
signal has already been demodulated by another device before being fed to the IED. A board that accepts a
modulated input has an on-board demodulator.
To set the device to use IRIG-B, use the setting IRIG-B Sync cell in the DATE AND TIME column.
The IRIG-B status can be viewed in the IRIG-B Status cell in the DATE AND TIME column.
8.2 SNTP
SNTP is used to synchronise the clocks of computer systems over packet-switched, variable-latency data
networks, such as IP. SNTP can be used as the time synchronisation method for models using IEC 61850 over
Ethernet.
The device is synchronised by the main SNTP server. This is achieved by entering the IP address of the SNTP server
into the IED using the IEC 61850 Configurator software described in the settings application software manual. A
second server is also configured with a different IP address for backup purposes.
This function issues an alarm when there is a loss of time synchronisation on the SNTP server. This could be
because there is no response or no valid clock signal.
The HMI menu does not contain any configurable settings relating to SNTP, as the only way to configure it is using
the IEC 61850 Configurator. However it is possible to view some parameters in the COMMUNICATIONS column
under the sub-heading SNTP parameters. Here you can view the SNTP server addresses and the SNTP poll rate in
the cells SNTP Server 1, SNTP Server 2 and SNTP Poll rate respectively.
The SNTP time synchronisation status is displayed in the SNTP Status cell in the DATE AND TIME column.
8.3 IEEE 1588 PRECISION TIME PROTOCOL

The MiCOM P40 modular products support the IEEE C37.238 (Power Profile) of IEEE 1588 Precision Time Protocol
(PTP) as a slave-only clock. This can be used to replace or supplement IRIG-B and SNTP time synchronisation so
that the IED can be synchronised using Ethernet messages from the substation LAN without any additional
physical connections being required.
A dedicated DDB signal (PTP Failure) his provided to indicate failure of failure of PTP.
8.3.1 ACCURACY AND DELAY CALCULATION

A time synchronisation accuracy of within 5 ms is possible. Both peer-to-peer or end-to-end mode delay
measurement can be used.
In peer-to-peer mode, delays are measured between each link in the network and are compensated for. This
provides greater accuracy, but requires that every device between the Grand Master and Slaves supports the
peer-to-peer delay measurement.
In end-to-end mode, delays are only measured between each Grand Master and Slave. The advantage of this
mode is that the requirements for the switches on the network are lower; they do not need to independently
calculate delays. The main disadvantage is that more inaccuracy is introduced, because the method assumes that
forward and reverse delays are always the same, which may not always be correct.
P64x-TM-EN-4.1 399
When using end-to-end mode, the IED can be connected in a ring or line topology using RSTP or Self Healing
Protocol without any additional Transparent Clocks. But because the IED is a slave-only device, additional
inaccuracy is introduced. The additional error will be less than 1ms for a network of eight devices.
Grand Master
L o c k e d
A la rm
PTP Aware Network
RSTP Network
<8 Hops, so <1ms
additional timing error
V01061
Figure 174: Timing error using ring or line topology
8.3.2 PTP DOMAINS

PTP traffic can be segregated into different domains using Boundary Clocks. These allow different PTP clocks to
share the same network while maintaining independent synchronisation within each grouped set.
8.4 TIME SYNCHRONISATION USING THE COMMUNICATION PROTOCOLS

All communication protocols have in-built time synchronisation mechanisms. If an external time synchronisation
mechanism such as IRIG-B, SNTP, or IEEE 1588 PTP is not used to synchronise the devices, the time synchronisation
mechanism within the relevant serial protocol is used. The real time is usually defined in the master station and
communicated to the relevant IEDs via one of the rear serial ports using the chosen protocol. It is also possible to
define the time locally using settings in the DATE AND TIME column.
The time synchronisation for each protocol is described in the relevant protocol description section.
400 P64x-TM-EN-4.1
CHAPTER 17
CYBER-SECURITY
Chapter 17 - Cyber-Security P64x
402 P64x-TM-EN-4.1
P64x Chapter 17 - Cyber-Security
1 OVERVIEW
In the past, substation networks were traditionally isolated and the protocols and data formats used to transfer
information between devices were often proprietary.
For these reasons, the substation environment was very secure against cyber-attacks. The terms used for this
inherent type of security are:
● Security by isolation (if the substation network is not connected to the outside world, it cannot be accessed
from the outside world).
● Security by obscurity (if the formats and protocols are proprietary, it is very difficult to interpret them).
The increasing sophistication of protection schemes, coupled with the advancement of technology and the desire
for vendor interoperability, has resulted in standardisation of networks and data interchange within substations.
Today, devices within substations use standardised protocols for communication. Furthermore, substations can be
interconnected with open networks, such as the internet or corporate-wide networks, which use standardised
protocols for communication. This introduces a major security risk making the grid vulnerable to cyber-attacks,
which could in turn lead to major electrical outages.
Clearly, there is now a need to secure communication and equipment within substation environments. This
chapter describes the security measures that have been put in place for our range of Intelligent Electronic Devices
(IEDs).
Note:
Cyber-security compatible devices do not enforce NERC compliance, they merely facilitate it. It is the responsibility of the user
to ensure that compliance is adhered to as and when necessary.

Overview 403
The Need for Cyber-Security 404
Standards 405
Cyber-Security Implementation 409
Roles and Permissions 410
Authentication 413
Security Event Management 424
P64x-TM-EN-4.1 403
2 THE NEED FOR CYBER-SECURITY

Cyber-security provides protection against unauthorised disclosure, transfer, modification, or destruction of
information or information systems, whether accidental or intentional. To achieve this, there are several security
requirements:
● Confidentiality (preventing unauthorised access to information)
● Integrity (preventing unauthorised modification)
● Availability / Authentication (preventing the denial of service and assuring authorised access to information)
● Non-repudiation (preventing the denial of an action that took place)
● Traceability / Detection (monitoring and logging of activity to detect intrusion and analyse incidents)
The threats to cyber-security may be unintentional (e.g. natural disasters, human error), or intentional (e.g. cyber-
attacks by hackers).
Good cyber-security can be achieved with a range of measures, such as closing down vulnerability loopholes,
implementing adequate security processes and procedures and providing technology to help achieve this.
Examples of vulnerabilities are:
● Indiscretions by personnel (users keep passwords on their computer)
● Bad practice (users do not change default passwords, or everyone uses the same password to access all
substation equipment)
● Bypassing of controls (users turn off security measures)
● Inadequate technology (substation is not firewalled)
Examples of availability issues are:

● Equipment overload, resulting in reduced or no performance
● Expiry of a certificate preventing access to equipment
To help tackle these issues, standards organisations have produced various standards. Compliance with these
standards significantly reduces the threats associated with lack of cyber-security.
404 P64x-TM-EN-4.1
3 STANDARDS
There are several standards, which apply to substation cyber-security. The standards currently applicable to
General Electric IEDs are NERC and IEEE1686.
Standard Country Description
NERC CIP (North American Electric Reliability
USA Framework for the protection of the grid critical Cyber Assets
Corporation)
BDEW (German Association of Energy and Water Requirements for Secure Control and Telecommunication
Germany
Industries) Systems
ICS oriented then Relevant for EPU completing existing standard
ANSI ISA 99 USA
and identifying new topics such as patch management
International Standard for substation IED cyber-security
IEEE 1686 International
capabilities
IEC 62351 International Power system data and Comm. protocol
ISO/IEC 27002 International Framework for the protection of the grid critical Cyber Assets
NIST SP800-53 (National Institute of Standards and
USA Complete framework for SCADA SP800-82and ICS cyber-security
Technology)
CPNI Guidelines (Centre for the Protection of National Clear and valuable good practices for Process Control and SCADA
UK
Infrastructure) security
3.1 NERC COMPLIANCE

The North American Electric Reliability Corporation (NERC) created a set of standards for the protection of critical
infrastructure. These are known as the CIP standards (Critical Infrastructure Protection). These were introduced to
ensure the protection of 'Critical Cyber Assets', which control or have an influence on the reliability of North
America’s electricity generation and distribution systems.
These standards have been compulsory in the USA for several years now. Compliance auditing started in June
2007, and utilities face extremely heavy fines for non-compliance.
NERC CIP standards

CIP standard Description
CIP-002-1 Critical Cyber Assets Define and document the Critical Assets and the Critical Cyber Assets
Define and document the Security Management Controls required to protect the
CIP-003-1 Security Management Controls
Critical Cyber Assets
Define and Document Personnel handling and training required protecting Critical
CIP-004-1 Personnel and Training
Cyber Assets
Define and document logical security perimeters where Critical Cyber Assets reside.
CIP-005-1 Electronic Security Define and document measures to control access points and monitor electronic
access
Define and document Physical Security Perimeters within which Critical Cyber Assets
CIP-006-1 Physical Security
reside
Define and document system test procedures, account and password management,
CIP-007-1 Systems Security Management security patch management, system vulnerability, system logging, change control
and configuration required for all Critical Cyber Assets
Define and document procedures necessary when Cyber-security Incidents relating
CIP-008-1 Incident Reporting and Response Planning
to Critical Cyber Assets are identified
CIP-009-1 Recovery Plans Define and document Recovery plans for Critical Cyber Assets
P64x-TM-EN-4.1 405
3.1.1 CIP 002

CIP 002 concerns itself with the identification of:
● Critical assets, such as overhead lines and transformers
● Critical cyber assets, such as IEDs that use routable protocols to communicate outside or inside the
Electronic Security Perimeter; or are accessible by dial-up
Power utility responsibilities: General Electric's contribution:

We can help the power utilities to create this asset register automatically.
Create the list of the assets
We can provide audits to list the Cyber assets
3.1.2 CIP 003

CIP 003 requires the implementation of a cyber-security policy, with associated documentation, which
demonstrates the management’s commitment and ability to secure its Critical Cyber Assets.
The standard also requires change control practices whereby all entity or vendor-related changes to hardware
and software components are documented and maintained.

We can help the power utilities to have access control to its critical assets by
providing centralized Access control.
To create a Cyber-security Policy
We can help the customer with its change control by providing a section in the
documentation where it describes changes affecting the hardware and software.
3.1.3 CIP 004

CIP 004 requires that personnel with authorized cyber access or authorized physical access to Critical Cyber
Assets, (including contractors and service vendors), have an appropriate level of training.

To provide appropriate training of its personnel We can provide cyber-security training
3.1.4 CIP 005

CIP 005 requires the establishment of an Electronic Security Perimeter (ESP), which provides:
● The disabling of ports and services that are not required
● Permanent monitoring and access to logs (24x7x365)
● Vulnerability Assessments (yearly at a minimum)
● Documentation of Network Changes

To monitor access to the ESP
To disable all ports not used in the IED
To perform the vulnerability assessments
To monitor and record all access to the IED
To document network changes
3.1.5 CIP 006

CIP 006 states that Physical Security controls, providing perimeter monitoring and logging along with robust
access controls, must be implemented and documented. All cyber assets used for Physical Security are considered
critical and should be treated as such:
406 P64x-TM-EN-4.1

Provide physical security controls and perimeter
monitoring.
General Electric cannot provide additional help with this aspect.
Ensure that people who have access to critical cyber
assets don’t have criminal records.
3.1.6 CIP 007

CIP 007 covers the following points:
● Test procedures
● Ports and services
● Security patch management
● Antivirus
● Account management
● Monitoring
● An annual vulnerability assessment should be performed

Test procedures, we can provide advice and help on testing.
Ports and services, our devices can disable unused ports and services
To provide an incident response team and have Security patch management, we can provide assistance
appropriate processes in place Antivirus, we can provide advise and assistance
Account management, we can provide advice and assistance
Monitoring, our equipment monitors and logs access
3.1.7 CIP 008

CIP 008 requires that an incident response plan be developed, including the definition of an incident response
team, their responsibilities and associated procedures.

To provide an incident response team and have
General Electric cannot provide additional help with this aspect.
appropriate processes in place.
3.1.8 CIP 009

CIP 009 states that a disaster recovery plan should be created and tested with annual drills.

To provide guidelines on recovery plans and backup/restore
To implement a recovery plan
documentation
3.2 IEEE 1686-2013

IEEE 1686-2013 is an IEEE Standard for substation IEDs' cyber-security capabilities. It proposes practical and
achievable mechanisms to achieve secure operations.
The following features described in this standard apply:
● Passwords are 8 characters long and can contain upper-case, lower-case, numeric and special characters.
● Passwords are never displayed or transmitted to a user.
P64x-TM-EN-4.1 407
● IED functions and features are assigned to different password levels. The assignment is fixed.
● The audit trail is recorded, listing events in the order in which they occur, held in a circular buffer.
● Records contain all defined fields from the standard and record all defined function event types where the
function is supported.
● No password defeat mechanism exists. Instead a secure recovery password scheme is implemented.
● Unused ports (physical and logical) may be disabled.
408 P64x-TM-EN-4.1
4 CYBER-SECURITY IMPLEMENTATION
General Electric IEDs have always been and will continue to be equipped with state-of-the-art security measures.
Due to the ever-evolving communication technology and new threats to security, this requirement is not static.
Hardware and software security measures are continuously being developed and implemented to mitigate the
associated threats and risks.
From Software Version 90 onwards, the MiCOM P40 Agile products provide enhanced security through the
following features:
● An Authentication, Authorization, Accounting (AAA) Remote Authentication Dial-In User Service (RADIUS)
client that is managed centrally, enables user attribution, provides accounting of all user activities, and uses
secure standards based on strong cryptography for authentication and credential protection. In other
words, this option uses a RADIUS.
● Server for user authentication. There is provision for both remote (RADIUS) and local (device) authentication.
● A Role-Based Access Control (RBAC) system that provides a permission model that allows access to the
device operations and configurations based on specific roles and individual user accounts configured on
the AAA server. That is, Administrator, Engineer, Operator, and Viewer roles are used.
● Security event reporting through both proprietary event logs and the Syslog protocol for supporting Security
Information Event Management (SIEM) systems for centralised cybersecurity monitoring.
● Encryption of passwords – stored within the IED, in network messages between the MiCOM S1 Agile
software and the IED, and in network messages between the RADIUS server and the IED (subject to the
RADIUS server configuration).
4.1 INITIAL SETUP

The requirements for initial setup of the IED for cyber-security and RBAC will depend on:
1. which interfaces, if any, the cyber-security is required,
2. the intended authentication method, as defined in the setting Auth. Method’ in SECURITY CONFIG column
(see the Authentication methods section).
When the authentication method is configured as Device Only, there are four pre-defined usernames, VIEWER,
OPERATOR, ENGINEER, and ADMINISTRATOR that align with the VIEWER, OPERATOR, ENGINEER and
ADMINISTRATOR roles (see the Device Users section).
When the authentication method is configured as ‘Server Only’ or ‘Server + Device’, users must be set up on the
Radius server (see the RADIUS users section). These users are separate from the pre-defined Device users. RADIUS
server information must be configured in the IED to connect to the RADIUS server(s) for Server authentication (see
the RADIUS server settings section). It is recommended that the Radius shared secret be changed from the default
(see the RADIUS client-server validation section).
Whatever the authentication method, it is strongly recommended that the password for the Administrator be
changed from the default. Changing the passwords for the other roles is optional.
P64x-TM-EN-4.1 409
5 ROLES AND PERMISSIONS
5.1 ROLES
The P40 Agile products provide 4 specific roles to which individual user accounts can be configured:
● VIEWER (Level 0) Read some, Write minimal
● OPERATOR (Level 1) Read All, Write Few
● ENGINEER (Level 2) Read All, Write Some
● ADMINISTRATOR (Level 3) Read All, Write All
Only one role of one type is allowed to be logged in at a time. For example, one Operator can be logged in but not
a second Operator at the same time. This prevents subsets of settings from being changed at the same time.
Roles are mapped to Access Level definitions:
VIEWER - No password required - Read access to Security features, Model Number, Serial Number, S/W version,
Description, Plant reference, Security code (UI Only), Encryption key (UI Only), User Banner and security related cells.
This role will allow maximum concurrent access provided by P40. Viewer is the default role
OPERATOR – Operator password required - Read access to all data and settings. Write access to Primary/
Secondary selector, Operator password setting, Password reset cell and log extraction cells (record selector). This
role will not allow concurrent access.
ENGINEER – Engineer password required - Read access to all data and settings. Write access to Reset demands
and counters. This role will not allow concurrent access.
ADMINISTRATOR – Administrator password required - Read access to all data and settings. Write access to All
settings, PSL, IED Config, Security settings (port disabling etc). This role can enable the bypass mode and forcefully
logout any other role. This role will not allow concurrent access.
The IED defines the following roles with reference to the roles defined by IEC 62351-8.
P40 Roles IEC 62351- 8 Roles Access Level
VIEWER VIEWER Level 0
OPERATOR OPERATOR Level 1
ENGINEER ENGINEER Level 2
ADMINISTRATOR SECADM + SECAUD Level 3
By default, the IED is delivered with default factory roles account and passwords. These default passwords are
shown in the below table.
Role Default Password
ADMINISTRATOR ChangeMe1#
ENGINEER ChangeMe1#
OPERATOR ChangeMe1#
VIEWER NA
Note:
It is strongly recommended that the password for the Administrator be changed from the default. Changing the passwords
for the other roles is optional.
410 P64x-TM-EN-4.1
Administrators have the following rights as well:

● Setting the Bypass mode
● Forcefully logging out any other role
● Setting Authentication Method
'Firmware lock' is not supported by the P40 Agile IED. Firmware upgrade is not managed by the main software. The
process involves using a dedicated firmware loading software tool. There is no access or control to this process via
the main product firmware.
5.2 PERMISSIONS
Authentication and authorization are two different processes. An authenticated user cannot perform any action on
the IED unless a privilege has been explicit granted to him/her to do so. This is the concept of “least privileges”
access.
Privileges must be granted to users through roles. A role is a collection of privileges, and roles are granted to users.
Each user is associated to only one role. The privilege/role matrix is stored on the IED. This is known as Role-Based-
Access Control (RBAC).
On successful user authentication, the IED will load the user’s role list. If the user’s role changes, the user must
logout and log back in to exercise his/her privileges.
Existing User level/permission mapping in P40 are:
Role Meaning Read Operation Write Operation
SYSTEM DATA column:
Description
Plant Reference
Model Number
Serial Number
S/W Ref.
Read Some
Access Level Password Entry
VIEWER Write
Security Feature LCD Contrast (UI only)
Minimal
SECURITY CONFIG column:
User Banner
Attempts Remain
Blk Time Remain
Fallback PW level
Security Code (UI only)
All data and settings are All items writeable at "Viewer".
Read All
OPERATOR readable. Select Event, Main and Fault (upload)
Write Few
Poll Measurements Extract Events (e.g. via MiCOM S1 Agile)
All items writeable at "Operator".
Setting Cells that change visibility (Visible/Invisible).
Setting Values (Primary/Secondary) selector
Read All All data and settings are
Commands:
ENGINEER Write readable.
Reset Indication
Some Poll Measurements
Reset Demand
Reset Statistics
Reset CB Data / counters
P64x-TM-EN-4.1 411
Role Meaning Read Operation Write Operation

All items writeable at "Engineer".
Change all Setting cells
Operations:
Extract and download Setting file.
Extract and download PSL
Extract and download MCL (IEC 61850)
Extraction of Disturbance Recorder
Courier/Modbus Accept Event (auto event extraction, e.g.
via AE2R)
All data and settings are
Read All Commands:
ADMINISTRATOR readable.
Write All Change Active Group setting
Poll Measurements
Close / Open CB
Change Comms device address.
Set Date & Time
Switch MCL banks / Switch Conf. Bank in UI (IEC 61850)
Enable / Disable Device ports (in SECURITY CONFIG
column)
All password settings
Bypass Enable/disable
Change Authentication Method
The table below shows the predefined permissions assignment for the predefined Roles according to IEC 62351-8
File File File Setting
Role View Read Dataset Report Control Config. Security
Read Write Mngt Group
VIEWER x x
OPERATOR x x x x
ENGINEER x x x x x x x
ADMINISTRATOR x x x x x x x x x x x
The table below shows the predefined permissions description according to IEC 62351-8
Permission Description
Allows the subject/role to discover what objects are present within a Logical Device by presenting the type ID of those
VIEW
objects.
Allows the subject/role to obtain all or some of the values in addition to the type and ID of objects that are present within
READ
a Logical-Device
DATASET Allows the subject/role to have full management rights for both permanent and non-permanent DataSets
REPORTING Allows a subject/role to use buffered reporting as well as un-buffered reporting
FILEREAD Allows the subject/role to have read rights for file objects
FILEWRITE Allows the subject/role to have write rights for file objects. This right includes the FILEREAD right
FILEMNGT Allows the role to transfer files to the Logical-Device, as well as delete existing files on the Logical-Device
CONTROL Allows a subject to perform control operations
CONFIG Allows a subject to locally or remotely configure certain aspects of the server
SETTINGGROUP Allows a subject to remotely configure Settings Groups
SECURITY Allows a subject/role to perform security functions at both a Server/Service Access Point and Logical-Device basis
412 P64x-TM-EN-4.1
6 AUTHENTICATION
6.1 AUTHENTICATION METHODS

The IED supports Bypass (no authentication), Device authentication and Server authentication.
Authentication
Description
Method
IED does not provide security, any user (Local/Remote) can login to the IED. IED does not validate user and
Bypass Auth.
password. In this case, there is no need to enter user-id and password to login.
Device Only IED allows role access using local authentication.
Server Only IED uses RADIUS server to validate access.
IED uses server authentication to validate user first. And it allows fallback to device authentication if the
Server + Device
RADIUS server(s) are unavailable.
If Bypass Auth. is enabled, the IED ignores the Auth. Method setting.
The Auth. Method setting offers the following options for user authentication:
• Server + Device (This is the default setting for IEC 61850+Courier; IEC 61850+103; DNP3OE)
• Device Only (This is the default setting for Courier/IEC 60870-5-103/Modbus/DNP3)
• Server Only
Only an ADMINISTRATOR role may change the Auth. Method setting. If Administrator changes it, the role remains
logged in. But only when the user log-out, their access-level is revoked.
If Authentication method is Server Only and RADIUS Server IP addresses are configured, no device user has
access to the IED (only the RADIUS users will have access). Only the RADIUS Administrator role will be able to
switch to "Server and Device auth". When the setting is “Server Only” but RADIUS Server IP are not configured (both
Primary & Secondary are 0.0.0.0), the IED will automatically fall back to Device authentication.
When Authentication method is Server Only, if the RADIUS server(s) are unavailable, the user should first take
actions to recover the RADIUS connection. If both RADIUS servers ultimately failed to recover, the user should
follow the password reset procedure to reset the Auth. Method setting to Device Only.
6.2 BYPASS
In Bypass Auth. mode, the IED does not provide security - any user can login. IED does not validate user and
password. The bypass security feature provides an easier access, with no authentication and encryption for
situations when this is considered safe. Only the Administrator can enable Bypass mode.
There are five modes for authentication bypass:
1. Disabled – no interfaces in Bypass Auth. mode (normal authentication is active)
2. Local & Remote
a. Front Panel;
b. Front Port
c. Rear Ports
d. Ethernet
P64x-TM-EN-4.1 413
3. Local – will bypass authentication for

a. Front Panel;
b. Front Port
4. Remote – will bypass authentication for
a. Ethernet
b. Rear Ports
5. HMI-Only – will bypass authentication only for front panel
Bypass authentication for
Front panel Front Port Rear Port Ethernet
Bypass mode:
Disabled
Local & Remote X X X X
Local X X
Remote X X
HMI-Only X
The DDB signal Security Bypass is available to indicate that the IED is in Bypass Auth. mode.
6.3 LOGIN
A user can only login through the following methods:
● Front Panel User Interface
● Using MiCOM S1 Agile, connected to either the Front Port, Rear Port 1 or 2, or NIC (Ethernet) interface.
The interfaces/protocols implemented in P40 are listed in the following table.

The product supports both RBAC (with Server + Device authentication) and original Access Level. The Courier
Interfaces / HMI use the RBAC whilst other protocols such as Modbus, IEC 60870-5-103, DNP3 use the original
Access Level to authenticate.
The following table shows different product variants that supports different protocols on Rear ports and Network
port.
Front
Local Access Rear Port (1/2) NIC (Ethernet) Port Supported Auth. mechanism
Port
HMI Courier Courier Courier - Device
IEC 61850 + SNMP + Courier
HMI Courier Courier Courier Server and Device
tunnel
Modbus
Device
HMI Courier Courier (no server, device auth only, old -
Old Access level for Modbus
access levels)
IEC 60870-5-103
Device
Old Access level for 103
access levels)
IEC 60870-5-103
IEC 61850 + SNMP + Courier Server and Device
HMI Courier Courier (no server, device auth only, old
tunnel Old Access level for 103
access levels)
DNP3
Device
Old Access level for DNP3
access levels)
Server and Device
HMI Courier Courier Courier DNP3 + SNMP + Courier tunnel
Old Access level for DNP3
414 P64x-TM-EN-4.1
6.3.1 FRONT PANEL LOGIN

Front panel User Interface supports both Device authentication and Server authentication. The P40 gives the user
the option to enter a username in HMI panel.
The user can type their password in the password cell.
For Device authentication, the user must enter one of the pre-defined usernames VIEWER, OPERATOR, ENGINEER,
ADMINISTRATOR. The user can scroll through these names using either of the hotkeys. Users must then enter their
password.
For Server authentication, the user can enter any valid pre-defined Radius server username. Using the front panel
User Interface, the user can change the displayed character type (digit, uppercase letter, lowercase letter, special
character) by either of the hotkeys. For ease of typing, it is preferable to do Server authentication login using
MiCOM S1 Agile.
After successful log in, a confirmation message is displayed, showing the logged in username. For example:
LOGIN SUCCESS
OPERATOR
6.3.2 MICOM S1 LOGIN

When the user attempts to login, MiCOM S1 Agile will prompt the user with a login dialog box that contains a
username text entry field and a password text entry field. The username field is a combo-dropdown style text field
that includes the fixed usernames (Administrator, Engineer, Operator, Viewer) for Device authentication – the
user can pick one of these if they wish, or type any other pre-defined username for Radius authentication in the
textbox.
6.3.3 WARNING BANNER

After successful authentication and authorisation to access the IED, MiCOM S1 Agile will display a security warning
banner to the user.
If I Agree is selected, the integrated authentication and authorisation is completed. Selecting I Disagree causes
the program to close and the login user to logout.
6.3.4 LOGIN FAILED

When Device authentication fails, a failure message is displayed:
LOGIN FAILED
For front panel authentication, this is shown for 2 seconds on the LCD.
For S1 Agile authentication, this is a pop-up dialog that the user must click to acknowledge.
6.4 USER SESSIONS

Open sessions will be automatically closed by the IED after a configurable session timeout.
The inactivity timer configuration setting defines the period of time that the IED waits in idleness before a logged in
user is automatically logged out.
If there is any data change that does not commit to IED, the data change is discarded when user logged out. If
there is any access that does not finish, the access will fail when user logged out. Front panel will display the
default page when user reaches the defined inactivity time.
P64x-TM-EN-4.1 415
If the keypad is inactive for configured UI inactivity timer, user logout message is displayed. And front panel user
interface reverts to the Viewer access level.
Currently in the P40, the inactivity timer for both front port and HMI is fixed to 15 minutes. Already, RP1
InactivTimer and RP2 InactivTimer settings control the inactivity timer for RP1 and RP2. There are two new
settings to support configurable inactivity timer for front port and front panel user interface:
● FP InactvTimer
● UI InactivTimer
Administrator, Operator and Engineer roles will accept only one session to the device at one time. Only Viewer
allows 4 concurrent sessions at one time.
Only one user session is allowed from all the access methods mentioned below:
● Front Panel Push buttons
● Front Port (serial) FP1
● Rear Port 1 (RP1)
● Rear Port 2 (RP2)
● Ethernet Port (NIC)
Minimum
Setting Name Description Min Max Default Units
Permissions
Number of failed authentications before the device blocks
0 (lockout
Attempts Limit subsequent authentication attempts for the lockout period. A 99 3 - Administrator
disabled)
value of 0 means Lockout is disabled.
The period of time in seconds a user is prevented from logging
Lockout Period 1 5940 5 sec Administrator
in, after being locked out.
FP Inactivity Timer is the time of idleness on Front Port before 0 (no
FP InactivTimer a logged in user is automatically logged out and revert the Inactivity 30 10 min Administrator
access level to the viewer role Timeout)
UI Inactivity Timer is the time of idleness on Front Panel 0 (no
UI InactivTimer before a logged in user is automatically logged out and revert Inactivity 30 10 min Administrator
the access level to the viewer role Timeout)
The recommended settings for Attempts Limit is 3 and Lockout Period is 5 sec to discourage brute force
attacks. If the Lockout period is too large, anybody can lockout Device users.
6.5 USER LOCKING POLICY

A local user locking policy is implemented for Device access:
● This user locking policy applies to both Device users.
● The account is unlocked at the first successful login after the Lockout Period
● By default, if the user consecutively fails to login 3 times, the user account will be locked for 3 minutes.
Each user account records how long it has been locked if the account is locked.
Each user account records how many times it has consecutively failed to login. User account failed times include
all interfaces login attempts. For example, if the Attempts Limit setting is 3 and the operator failed to login from
front panel 2 times, and they changed to login from the Courier interface, but failed again, then the Operator
would be locked out.
When the IED is powered on, these Attempts Limit counter resets to zero.
When the user account exceeds the Attempts Limit it is locked for Lockout period, at that time Attempt limit
resets to zero.
The locked user account will be unlocked automatically, after the configured “Lockout Period” is expired.
416 P64x-TM-EN-4.1
All user accounts need to wait until the lockout period expires. No user can unlock the locked account.
If the locked account attempts to login the IED from the Front Panel, the following text is displayed (example):
OPERATOR
IS LOCKED
Usernames are specific to each user account, such as Engineer, Operator and Administrator for Device
authentication.
When supporting both RBAC enabled interfaces and non-RBAC interfaces (such as Modbus), the P40 handles
features such as user-locking feature as follows
● If an RBAC user exceeds the invalid password limit, that user gets locked for all the interfaces.
● On a non-RBAC interface, if an Access Level exceeds the invalid password limit, P40 only blocks that.
6.6 LOGOUT
Each user should Log out after reading or configuring the IED.
Both S1 Agile and the Front Panel provide a one-step logout.
The user can only log out from the front panel, if they logged in from the front panel. If the user logged in from S1
Agile, they have to logout from S1 Agile.
6.6.1 FRONT PANEL LOGOUT

Go up to the top of the menu tree. When you are at the Column Heading level and you press the Up button, you
may be prompted to log out with the following display:
ENTER TO LOGOUT
CLEAR TO CANCEL
If you confirm, the following message is displayed for 2 seconds:
LOGGED OUT <ROLE

NAME>
LOGGED OUT
ADMINISTRATOR
If you decide not to log out (i.e. you cancel), the following message is displayed for 2 seconds.
LOGOUT CANCELLED
ADMINISTRATOR
6.6.2 MICOM S1 LOGOUT

Right-click on the device name in the System Explorer panel in MiCOM S1 Agile and select Log Off.
In the Log Off confirmation dialog, click Yes.
6.7 DEVICE USERS

For device authentication, the user must enter one of the pre-defined usernames VIEWER, OPERATOR, ENGINEER,
or ADMINISTRATOR. This means that device users and roles are same in the P40, and therefore there can be only
one user for each role.
P64x-TM-EN-4.1 417
6.8 PASSWORD POLICY

Cyber-security requires strong passwords and validation for NERC compliance.
The NERC password complexity policy requires an alpha-numeric password (for all accesses, front panel, and
network/local port) that meets the following mandatory requirements:
1. Passwords cannot contain the user's account name or parts of the user's full name that exceed two
consecutive characters.
2. Passwords must be at least eight characters in length, but not exceed 16 characters in length.
3. Passwords must contain characters from all four categories:
a. English uppercase characters (A through Z).
b. English lowercase characters (a through z).
c. Numeric (digits 0 through 9).
d. Special non-alphanumeric characters (such as @,!,#,{, but not limited to only those)
For Device authentication, the IED will enforce that configured passwords meet these requirements.
For Server authentication, the password complexity and user locking policy is defined in the external Radius server.
6.9 CHANGE PASSWORD

In the Device authentication mode, VIEWER does not have a password associated with it.
The password can be changed either from the front panel User Interface, or from MiCOM S1 Agile using the
Change/Set Password option in the Supervise Device dialog box.
Caution:
It is recommended that user passwords are changed periodically.
6.10 RADIUS
When the Auth. Method setting is configured as Server Only or Server + Device, a user must log in with a
username and password that has been predefined on the Radius server.
This log in can be performed from any interface, as described in the Login section. The IED will authenticate the
user to the active RADIUS server, over the Ethernet connection.
Groups User
Access Request
User login RADIUS
IED Client
Access
Accept
(User Role)
User RADIUS Server Active Directory
V01100
Figure 175: RADIUS server/client communication
6.10.1 RADIUS USERS

For Server authentication, RADIUS users and passwords are created in the server (in the Active Directory).
418 P64x-TM-EN-4.1
The username must consist of uppercase letters (A to Z) and digits (0 to 9) only. No lowercase letters or special
characters are allowed.
Each RADIUS user must have a password that meets the password policy of the Active Directory (not the password
policy of the P40) and have one of the four roles assigned in the Active Directory.
The number of RADIUS users is not limited by the IED.
RADIUS password changes are done in the Active Directory (after password expiration).
6.10.2 RADIUS CLIENT

Two Radius servers are supported by the IED in the configuration for redundancy. The IED will try each in sequence
until one responds.
The IED will first try server 1 up to the configured number of retries, leaving a request timeout between each
request. If, after this point there is still no valid answer from server 1, the IED will switch to server 2 and repeat for
up to the configured number of retries.
If the number of retries for the second server is exceeded, the IED will give up entirely on Server authentication. If
Authentication Method is Server + Device, the IED will fallback to Device authentication. A RADIUS Server
unavailable security event is also logged under this condition.
The RADIUS implementation supports the following authentication protocols:
● EAP-TTLS-MSCHAP2
● PAP
● EAP-PEAP-MSCHAP2
● PAP EAP-TTLS-PAP (Default)
The RADIUS implementation queries the Role ID vendor attribute and establish the logged in user security context
with that role.
RADIUS Config. Value
Vendor ID 2910
Vendor Attribute 1
P40 Role Values
Administrator 3
Engineer 2
Operator 1
Viewer 0
6.10.3 RADIUS SERVER SETTINGS

The following RADIUS server information must be configured in the IED to connect to the RADIUS server(s) for
Server authentication.
Setting Minimum
Description Min Max Default Units
Name Permissions
IP address of Server 1. Default value
RADIUS
indicates no Primary Radius server is 0.0.0.0 255.255.255.255 0.0.0.0 - Administrator
Pri IP
configured, and so Radius is disabled.
IP address of Server 2. Default value
RADIUS
indicates no Secondary Radius server is 0.0.0.0 255.255.255.255 0.0.0.0 - Administrator
Sec IP
configured
RADIUS
Radius authentication port 1 65535 1812 - Administrator
Auth Port
P64x-TM-EN-4.1 419
Setting Minimum
Description Min Max Default Units
Name Permissions
EAP-TTLS-MSCHAP2
RADIUS Authentication protocol to be used by PAP PAP EAP-TTLS-
- Administrator
Security Radius server. EAP-PEAP-MSCHAP2 PAP
PAP EAP-TTLS-PAP
RADIUS Timeout in seconds between re-
1 900 2 sec Administrator
Timeout transmission requests
RADIUS
Number of retries before giving up 1 99 10 - Administrator
Retries
RADIUS Shared Secret used in authentication. It is
1 character 16 characters ChangeMe1# - Administrator
Secret only displayed as asterisks.
The data cell RADIUS Status indicates the status of the currently-selected RADIUS server. This will display either
Disabled, Server OK, or Failed.
6.10.4 RADIUS ACCOUNTING

Radius accounting is not supported by the IED. The user can achieve accounting through syslog (see the SYSLOG
section).
6.10.5 RADIUS CLIENT-SERVER VALIDATION

Client-server validation is achieved using a shared secret. The IED must be configured with the RADIUS Secret
setting to match the shared secret configured in the RADIUS server. It is recommended (but not enforced) that this
setting meets the P40 password requirements.
Note:
It is recommended that the shared secret be changed from the default before using Radius authentication.
The IED does not support exchange of CA certificates. The RADIUS server may send a certificate but the IED will not
verify it.
6.11 RECOVERY
6.11.1 RESTORE TO LOCAL FACTORY DEFAULT

The Restore Defaults setting is available to facilitate NERC CIP compliance requirements for decommissioning
critical cyber devices. Only the Administrator role can change this setting.
The Restore Defaults setting under the CONFIGURATION column is used to restore a setting group to factory
default settings.
0 = No Operation
1 = All Settings
2 = Setting Group 1
3 = Setting Group 2
4 = Setting Group 3
5 = Setting Group 4
To restore the default values to the settings in any setting group, set the Restore Defaults setting to the relevant
Group number. Alternatively, it is possible to set the Restore Defaults setting to All Settings to restore the
default values to all the IEDs settings, not only one setting group.
420 P64x-TM-EN-4.1
Note:
Restoring defaults to all settings includes the rear communication port settings, which may result in communication via the
rear port being disrupted if the new (default) settings do not match those of the master station.
Data (events, DR, fault records, protection counters etc) is left untouched. When decommissioning critical cyber
IEDs, users may want to clear all data and events as well.
6.11.2 PASSWORD RESET PROCEDURE

If you mislay a devices password (if Administrator forgets their password), the passwords can be reset to default
using a recovery password. To obtain the recovery password you must contact the Contact Centre and supply the
Serial Number and the security code. The Contact Centre will use these items to generate a Recovery Password.
The security code is a 16-character string of uppercase characters. It is a read-only parameter. The device
generates its own security code randomly. A new code is generated under the following conditions:
● On power up
● Whenever settings are set back to default
● On expiry of validity timer (see below)
● When the recovery password is entered
This reset procedure can be only accomplished through front panel exclusively and cannot be done over any other
interface. As soon as the security code is displayed on the front panel User Interface, a validity timer is started. This
validity timer is set to 72 hours and is not configurable. This provides enough time for the Contact Centre to
manually generate and send a recovery password. The Service Level Agreement (SLA) for recovery password
generation is one working day, so 72 hours is sufficient time, even allowing for closure of the Contact Centre over
weekends and bank holidays.
The procedure is:
The security code is displayed on confirmation. The validity timer is then started. The security code can only be
read from the front panel.
This reset procedure can be only accomplished through front panel exclusively and cannot be done over the
Ethernet/serial port, but only when physically present in front of the IED. In the event of losing all passwords (if the
Administrator forgets their password) the user could reset the IED to default passwords, following the procedure
below:
1. User navigates to Security Code cell in SECURITY CONFIG column
2. To prevent accidental reading of the IED Security Code, the cell will initially display a warning message:
PRESS ENTER TO
READ SEC. CODE
3. Press Enter to read the Security Code.

4. User sends an email to the Contact Centre providing the full IED serial number and displayed Security Code,
using a recognisable corporate email account
5. Contact Centre emails the user with the Recovery Password. The recovery password is intended for recovery
only. It is not a replacement password that can be used continually. It can only be used once – for password
recovery.
6. User logs in with the username ADMINISTRATOR and the recovery password in to the Password setting in
SYSTEM DATA column.
P64x-TM-EN-4.1 421
7. Then IED will prompt
RESET PASSWORD?
ENTER or CLEAR
8. Press Enter to continue the reset procedure

9. If the recovery password successfully validates, the default passwords are restored for each access level for
Device authentication.
10. Change Auth. Method setting to Server + Device if applicable.
Note:
Restoring passwords to defaults does not affect any other settings and does not provoke reboot of the IED. The protection and
control functions of the IED are always maintained.
6.11.3 ACCESS LEVEL DDBS

The current level of access for each interface is available for use in the Programming Scheme Logic (PSL) as these
DDB signals:
● HMI Access Lvl 1
● HMI Access Lvl 2
● FPort AccessLvl1
● FPort AccessLvl2
● RPrt1 AccessLvl1
Each pair of DDB signals indicates the access level as follows:

● Level 1 off, Level 2 off = 0
● Level 1 on, Level 2 off = 1
● Level 1 off, Level 2 on = 2
● Level 1 on, Level 2 on = 3
KEY:
HMI = Human Machine Interface
FPort = Front Port
RPrt = Rear Port
Lvl = Level
6.12 DISABLING PHYSICAL PORTS

It is possible to disable unused physical ports. A level 3 password is needed to perform this action.
To prevent accidental disabling of a port, a warning message is displayed according to whichever port is required
to be disabled. For example, if rear port 1 is to be disabled, the following message appears:
422 P64x-TM-EN-4.1
REAR PORT 1 TO BE
DISABLED.CONFIRM
The following ports can be disabled, depending on the model.

● Front port (Front Port setting)
● Rear port 1 (Rear Port 1 setting)
● Rear port 2 (Rear Port 2 setting)
● Ethernet port (Ethernet Port setting)
Note:
It is not possible to disable a port from which the disabling port command originates.
We do not generally advise disabling the physical Ethernet port.
6.13 DISABLING LOGICAL PORTS

It is possible to disable unused logical ports. A level 3 password is needed to perform this action.
Note:
The port disabling setting cells are not provided in the settings file. It is only possible to do this using the HMI front panel.
The following protocols can be disabled:

● IEC 61850 (IEC 61850 setting)
● DNP3 Over Ethernet (DNP3 OE setting)
● Courier Tunnelling (Courier Tunnel setting)
Note:
If any of these protocols are enabled or disabled, the Ethernet card will reboot.
P64x-TM-EN-4.1 423
7 SECURITY EVENT MANAGEMENT

To implement NERC-compliant cyber-security, a range of security events are logged in the Security Event file.
7.1 SECURITY EVENTS: COURIER

Event Value Display
USER LOGGED IN
PASSWORD LEVEL UNLOCKED
ON {int} LEVEL {n}
USER LOGGED OUT
PASSWORD LEVEL RESET
ON {int} LEVEL {n}
P/WORD SET BLANK
PASSWORD SET BLANK
BY {int} LEVEL {p}
P/WORD NOT-NERC
PASSWORD SET NON-COMPLIANT
BY {int} LEVEL {p}
PASSWORD CHANGED
PASSWORD MODIFIED
BY {int} LEVEL {p}
PASSWORD BLOCKED
PASSWORD ENTRY BLOCKED
ON {int}
P/WORD UNBLOCKED
PASSWORD ENTRY UNBLOCKED
ON {int}
INV P/W ENTERED
INVALID PASSWORD ENTERED
ON <int}
P/WORD EXPIRED
PASSWORD EXPIRED
ON {int}
P/W ENT WHEN BLK
PASSWORD ENTERED WHILE BLOCKED
ON {int}
RCVY P/W ENTERED
RECOVERY PASSWORD ENTERED
ON {int}
IED SEC CODE RD
IED SECURITY CODE READ
ON {int}
IED SEC CODE EXP
IED SECURITY CODE TIMER EXPIRED
-
PORT DISABLED
PORT DISABLED
BY {int} PORT {prt}
PORT ENABLED
PORT ENABLED
BY {int} PORT {prt}
DEF. DISPLAY NOT NERC COMPLIANT DEF DSP NOT-NERC
PSL STNG D/LOAD
PSL SETTINGS DOWNLOADED
BY {int} GROUP {grp}
DNP STNG D/LOAD
DNP SETTINGS DOWNLOADED
BY {int}
TRACE DAT D/LOAD
TRACE DATA DOWNLOADED
BY {int}
IED CONFG D/LOAD
IEC 61850 CONFIG DOWNLOADED
BY {int}
USER CRV D/LOAD
USER CURVES DOWNLOADED
BY {int} GROUP {crv}
424 P64x-TM-EN-4.1
Event Value Display

PSL CONFG D/LOAD
PSL CONFIG DOWNLOADED
SETTINGS D/LOAD
SETTINGS DOWNLOADED
PSL STNG UPLOAD
PSL SETTINGS UPLOADED
DNP STNG UPLOAD
DNP SETTINGS UPLOADED
BY {int}
TRACE DAT UPLOAD
TRACE DATA UPLOADED
BY {int}
IED CONFG UPLOAD
IEC 61850 CONFIG UPLOADED
BY {int}
USER CRV UPLOAD
USER CURVES UPLOADED
BY {int} GROUP {crv}
PSL CONFG UPLOAD
PSL CONFIG UPLOADED
SETTINGS UPLOAD
SETTINGS UPLOADED
EVENTS EXTRACTED
EVENTS HAVE BEEN EXTRACTED
BY {int} {nov} EVNTS
ACTIVE GRP CHNGE
ACTIVE GROUP CHANGED
C & S CHANGED
CS SETTINGS CHANGED
BY {int}
DR CHANGED
DR SETTINGS CHANGED
BY {int}
SETTINGS CHANGED
SETTING GROUP CHANGED
POWER ON
POWER ON
-
S/W DOWNLOADED
SOFTWARE_DOWNLOADED
-
where:
● int is the interface definition (UI, FP, RP1, RP2, TNL, TCP)
● prt is the port ID (FP, RP1, RP2, TNL, DNP3, IEC, ETHR)
● grp is the group number (1, 2, 3, 4)
● crv is the Curve group number (1, 2, 3, 4)
● n is the new access level (0, 1, 2, 3)
● p is the password level (1, 2, 3)
● nov is the number of events (1 – nnn)
Each new event has an incremented unique number, therefore missing events appear as gap in the sequence. The
unique identifier forms part of the event record that is read or uploaded from the IED.
Note:
It is no longer possible to clear Event, Fault, Maintenance, and Disturbance Records.
P64x-TM-EN-4.1 425
7.2 SYSLOG
Security events are also logged to a remote syslog server.
All login and logout attempts from local and central authentication, whether successful or failed, are logged. The
contents of each successful or failed, login and logout security event include a specific username.
The security log cannot be cleaned by any of the available roles.
The contents of each login and/or logout security event include the relevant interface. The following interfaces are
supported:
Interface Abbr.
Front Port FP
Rear Port 1 RP1
Rear Port 2 RP2
Ethernet NET
Front Panel UI
The following events are available to be logged to the syslog server:
Event Categorisation Severity
Login - Authentication successful Informational (6)
Login - Authentication Failure Informational (6)
Logout Informational (6)
RADIUS Server Unavailable Alert (1)
Session timeout Informational (6)
Account Locked Notice (5)
User accessed while locked Notice (5)
ByPass Activate Notice (5)
ByPass Deactivate Notice (5)
Password Change Notice (5)
Recovery password is entered to reset the passwords Notice (5)
Settings / Configuration Changed Notice (5)
Settings / Configuration uploaded
Notice (5)
(to S1 Agile)
Event Records uploaded Notice (5)
Default settings restored Notice (5)
Notice (5)
Notice (5)
Active Setting Group Changed
Notice (5)
Notice (5)
Notice (5)
Default user curves restored
Notice (5)
Notice (5)
7.3 SYSLOG CLIENT

The IED supports security event reporting through the Syslog protocol for supporting Security Information Event
Management (SIEM) systems for centralized cyber security Monitoring over UDP protocol.
426 P64x-TM-EN-4.1
The IED is a Syslog client that supports two Syslog servers. The following settings are available in the
COMMUNICATIONS column.
Min.
Setting Name Description Min Max Default Units
Permission
The IP address of the target Syslog
SysLog Pri IP 0.0.0.0 223.255.255.254 0.0.0.0 - Administrator
server (Primary)
The IP address of the target Syslog
SysLog Sec IP 0.0.0.0 223.255.255.254 0.0.0.0 - Administrator
server (Secondary)
The UDP port number of the target
SysLog Port 1 65535 514 - Administrator
Syslog server
7.4 SYSLOG FUNCTIONALITY

The P40 supports the RFC 5424 UDP protocol.
The table below shows the format of a Syslog event.
Header <PRIVAL>1 YYYY-MM-DDTHH:mm:ss.fffZ IEDName userlog - MSGID
PRIVAL 32 + [event severity]
32 is derived from the facility number 4 (meaning security/authorization messages)
Event severity is derived from the received message.
YYYY 4 Digit year; i.e. 2018
Derived from the received message timestamp.
MM 2 Digit month; 01 to 12 (for January to December).
DD 2 Digit day of month; 01 to 31 (depending upon the month)
HH 2 Digit hour of day; 00 to 23
mm 2 Digit count of minutes elapsed in the current hour; 00 to 59
ss 2 Digit count of seconds elapsed in the current minute; 00 to 59
fff 3 Digit fraction of seconds (millisecond resolution); 0 to 999
IP Addr IP Address assigned to the Ethernet Board.
MSGID Unique message type identity
Derived from the received message event type.
Data [timeQuality tzKnown=X]
(common) X Timezone quality attribute for event timestamp (in header)
0; indicating Local Time offset and DST settings are not enabled (i.e. timestamp is UTC)
P64x-TM-EN-4.1 427
Data [gePlatformEvt channel=IFACE accessLevel=AL evtid=UUID extra=EDATA] DETAIL

(Platform IFACE Channel access type
event)
Copied from the received message interface name.
AL Access Level
Copied from the received message access level.
UUID Unique event identification
Copied from the received message unique id.
EDATA Extra event data – meaning of which is specific to the event type (see MSGID in header)
Copied from the received message extra info.
DETAIL Event details.
Derived from the received message event text and value.
Data [geUserInfo channel=IFACE loginId=USER] DETAIL
(Enhanced IFACE Channel access type
event)
Copied from the received message interface name.
USER Logged in username who generated the event
Copied from the received message user id.
DETAIL Event details.
Copied from the received message event text.
Formatted <38>1 2018-02-06T11:46:32.074Z Feeder1 userlog - 5120 [timeQuality tzKnown=0][gePlatformEvt channel=UI
Examples: accessLevel=3 evtid=4 extra=0] User Logged In on UI Level 3User Logged In on UI Level 3
<38>1 2018-02-06T11:46:32.074Z Feeder1 userlog - 9999 [timeQuality tzKnown=0][geUserInfo channel=UI
loginId=user1] Login - Authentication successful
Sample Syslog messages are shown below:
Event Access Method Syslog Message (As from Syslog Server)
04-17-2019 14:43:32 Auth.Info 192.168.1.30 1 1994-01-23T21:34:06.102Z
Authentication
UI 192.168.1.30 userlog - 9999 [timeQuality tzKnown=0][geUserInfo
Successful
channel=FP loginid=ADMINISTRATOR] Login - Authentication successful
04-19-201913:36:08Auth.Info192.168.1.301 1994-01-25T20:26:42.872Z 192.168.1.30
Authentication
Serial userlog - 9999 [timeQuality tzKnown=0][geUserInfo channel=RP1 loginid=ENGINEER] Login
Failure
- Authentication fail
Courier Tunnel 04-17-201915:29:20Auth.Info192.168.1.301 1994-01-23T22:19:58.168Z 192.168.1.30
Network Login
(device userlog - 9999 [timeQuality tzKnown=0][geUserInfo channel=NET loginid=ENGINEER]
Success
authentication) Login - Authentication successful
04-19-201913:52:08Auth.Info192.168.1.301 1994-01-25T20:42:42.782Z 192.168.1.30
Logout Serial userlog - 9999 [timeQuality tzKnown=0][geUserInfo channel=RP1
loginid=ADMINISTRATOR] Logout
04-18-201912:40:14Auth.Alert192.168.1.301 1994-01-24T19:30:55.839Z 192.168.1.30
Radius
FP userlog - 5163 [timeQuality tzKnown=0][gePlatformEvt channel=FP accessLevel=0
Unavailable
evtid=3715 extra=0] RADIUS UnAvailbl
04-18-201912:39:19Auth.Warning192.168.1.301 1994-01-24T19:30:00.573Z 192.168.1.30
Bypass
FP userlog - 9998 [timeQuality tzKnown=0][geUserInfo channel=FP loginid=ADMINISTRATOR]
Activated
ByPass Activated
04-18-201911:52:35Auth.Notice192.168.1.301 1994-01-24T18:43:16.537Z 192.168.1.30
Settings
Courier Tunnel userlog - 5149 [timeQuality tzKnown=0][gePlatformEvt channel=NET accessLevel=3
modified
evtid=3677 extra=0] Settings Upload By TNL
428 P64x-TM-EN-4.1
CHAPTER 18
INSTALLATION
Chapter 18 - Installation P64x
430 P64x-TM-EN-4.1
P64x Chapter 18 - Installation
1 CHAPTER OVERVIEW
This chapter provides information about installing the product.
Handling the Goods 432
Mounting the Device 433
Cables and Connectors 435
Case Dimensions 440
P64x-TM-EN-4.1 431
2 HANDLING THE GOODS

Our products are of robust construction but require careful treatment before installation on site. This section
discusses the requirements for receiving and unpacking the goods, as well as associated considerations regarding
product care and personal safety.
Caution:
Before lifting or moving the equipment you should be familiar with the Safety
Information chapter of this manual.
2.1 RECEIPT OF THE GOODS

On receipt, ensure the correct product has been delivered. Unpack the product immediately to ensure there has
been no external damage in transit. If the product has been damaged, make a claim to the transport contractor
and notify us promptly.
For products not intended for immediate installation, repack them in their original delivery packaging.
2.2 UNPACKING THE GOODS

When unpacking and installing the product, take care not to damage any of the parts and make sure that
additional components are not accidentally left in the packing or lost. Do not discard any CDROMs or technical
documentation. These should accompany the unit to its destination substation and put in a dedicated place.
The site should be well lit to aid inspection, clean, dry and reasonably free from dust and excessive vibration. This
particularly applies where installation is being carried out at the same time as construction work.
2.3 STORING THE GOODS

If the unit is not installed immediately, store it in a place free from dust and moisture in its original packaging. Keep
any dehumidifier bags included in the packing. The dehumidifier crystals lose their efficiency if the bag is exposed
to ambient conditions. Restore the crystals before replacing it in the carton. Ideally regeneration should be carried
out in a ventilating, circulating oven at about 115°C. Bags should be placed on flat racks and spaced to allow
circulation around them. The time taken for regeneration will depend on the size of the bag. If a ventilating,
circulating oven is not available, when using an ordinary oven, open the door on a regular basis to let out the
steam given off by the regenerating silica gel.
On subsequent unpacking, make sure that any dust on the carton does not fall inside. Avoid storing in locations of
high humidity. In locations of high humidity the packaging may become impregnated with moisture and the
dehumidifier crystals will lose their efficiency.
The device can be stored between –25º to +70ºC for unlimited periods or between -40°C to + 85°C for up to 96
hours (see technical specifications).
To avoid deterioration of electrolytic capacitors, power up units that are stored in a de-energised state once a year,
for one hour continuously.
2.4 DISMANTLING THE GOODS

If you need to dismantle the device, always observe standard ESD (Electrostatic Discharge) precautions. The
minimum precautions to be followed are as follows:
● Use an antistatic wrist band earthed to a suitable earthing point.
● Avoid touching the electronic components and PCBs.
432 P64x-TM-EN-4.1
3 MOUNTING THE DEVICE

The products are dispatched either individually or as part of a panel or rack assembly.
Individual products are normally supplied with an outline diagram showing the dimensions for panel cut-outs and
hole centres.
The products are designed so the fixing holes in the mounting flanges are only accessible when the access covers
are open.
If you use a P991 or MMLG test block with the product, when viewed from the front, position the test block on the
right-hand side of the associated product. This minimises the wiring between the product and test block, and
allows the correct test block to be easily identified during commissioning and maintenance tests.
3.1 FLUSH PANEL MOUNTING

Panel-mounted devices are flush mounted into panels using M4 SEMS Taptite self-tapping screws with captive
3 mm thick washers (also known as a SEMS unit).
Caution:
Do not use conventional self-tapping screws, because they have larger heads and could
damage the faceplate.
Alternatively, you can use tapped holes if the panel has a minimum thickness of 2.5 mm.
For applications where the product needs to be semi-projection or projection mounted, a range of collars are
available.
If several products are mounted in a single cut-out in the panel, mechanically group them horizontally or vertically
into rigid assemblies before mounting in the panel.
Caution:
Do not fasten products with pop rivets because this makes them difficult to remove if
repair becomes necessary.
3.2 RACK MOUNTING

Panel-mounted variants can also be rack mounted using single-tier rack frames (our part number FX0021 101), as
shown in the figure below. These frames are designed with dimensions in accordance with IEC 60297 and are
supplied pre-assembled ready to use. On a standard 483 mm (19 inch) rack this enables combinations of case
widths up to a total equivalent of size 80TE to be mounted side by side.
The two horizontal rails of the rack frame have holes drilled at approximately 26 mm intervals. Attach the products
by their mounting flanges using M4 Taptite self-tapping screws with captive 3 mm thick washers (also known as a
SEMS unit).
Caution:
Risk of damage to the front cover molding. Do not use conventional self-tapping
screws, including those supplied for mounting MiDOS products because they have
slightly larger heads.
Once the tier is complete, the frames are fastened into the racks using mounting angles at each end of the tier.
P64x-TM-EN-4.1 433
Figure 176: Rack mounting of products
Products can be mechanically grouped into single tier (4U) or multi-tier arrangements using the rack frame. This
enables schemes using products from different product ranges to be pre-wired together before mounting.
Use blanking plates to fill any empty spaces. The spaces may be used for installing future products or because the
total size is less than 80TE on any tier. Blanking plates can also be used to mount ancillary components. The part
numbers are as follows:
Case size summation Blanking plate part number

5TE GJ2028 101
10TE GJ2028 102
15TE GJ2028 103
20TE GJ2028 104
25TE GJ2028 105
30TE GJ2028 106
35TE GJ2028 107
40TE GJ2028 108
434 P64x-TM-EN-4.1
4 CABLES AND CONNECTORS

This section describes the type of wiring and connections that should be used when installing the device. For pin-
out details please refer to the Hardware Design chapter or the wiring diagrams.
Caution:
Before carrying out any work on the equipment you should be familiar with the Safety
Section and the ratings on the equipment’s rating label.
4.1 TERMINAL BLOCKS

The device may use one or more of the terminal block types shown in the following diagram. The terminal blocks
are fastened to the rear panel with screws.
● Heavy duty (HD) terminal blocks for CT and VT circuits
● Medium duty (MD) terminal blocks for the power supply, relay outputs and rear communications port
● MiDOS terminal blocks for CT and VT circuits
● RTD/CLIO terminal block for connection to analogue transducers
Figure 177: Terminal block types
MiCOM products are supplied with sufficient M4 screws for making connections to the rear mounted terminal
blocks using ring terminals, with a recommended maximum of two ring terminals per terminal.
If required, M4 90° crimp ring terminals can be supplied in three different sizes depending on wire size. Each type is
available in bags of 100.
Part number Wire size Insulation color
ZB9124 901 0.25 - 1.65 mm2 (22 – 16 AWG) Red
ZB9124 900 1.04 - 2.63 mm2 (16 – 14 AWG) Blue
P64x-TM-EN-4.1 435
4.2 POWER SUPPLY CONNECTIONS

These should be wired with 1.5 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
The wire should have a minimum voltage rating of 300 V RMS.
Caution:
Protect the auxiliary power supply wiring with a maximum 16 A high rupture capacity
(HRC) type NIT or TIA fuse.
4.3 EARTH CONNNECTION

Every device must be connected to the cubicle earthing bar using the M4 earth terminal.
Use a wire size of at least 2.5 mm2 terminated with a ring terminal.
Due to the physical limitations of the ring terminal, the maximum wire size you can use is 6.0 mm2 using ring
terminals that are not pre-insulated. If using pre insulated ring terminals, the maximum wire size is reduced to 2.63
mm2 per ring terminal. If you need a greater cross-sectional area, use two wires in parallel, each terminated in a
separate ring terminal.
Note:
To prevent any possibility of electrolytic action between brass or copper ground conductors and the rear panel of the product,
precautions should be taken to isolate them from one another. This could be achieved in several ways, including placing a
nickel-plated or insulating washer between the conductor and the product case, or using tinned ring terminals.
4.4 CURRENT TRANSFORMERS

Current transformers would generally be wired with 2.5 mm2 PVC insulated multi-stranded copper wire terminated
with M4 ring terminals.
Due to the physical limitations of the ring terminal, the maximum wire size you can use is 6.0 mm2 using ring
terminals that are not pre-insulated. If using pre insulated ring terminals, the maximum wire size is reduced to 2.63
mm2 per ring terminal. If you need a greater cross-sectional area, use two wires in parallel, each terminated in a
separate ring terminal.
Caution:
Current transformer circuits must never be fused.
Note:
If there are CTs present, spring-loaded shorting contacts ensure that the terminals into which the CTs connect are shorted
before the CT contacts are broken.
Note:
For 5A CT secondaries, we recommend using 2 x 2.5 mm2 PVC insulated multi-stranded copper wire.
436 P64x-TM-EN-4.1
4.5 VOLTAGE TRANSFORMER CONNECTIONS

Voltage transformers should be wired with 2.5 mm2 PVC insulated multi-stranded copper wire terminated with M4
ring terminals.
4.6 WATCHDOG CONNECTIONS

These should be wired with 1 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
4.7 EIA(RS)485 AND K-BUS CONNECTIONS

For connecting the EIA(RS485) / K-Bus ports, use 2-core screened cable with a maximum total length of 1000 m or
200 nF total cable capacitance.
To guarantee the performance specifications, you must ensure continuity of the screen, when daisy chaining the
connections.
Two-core screened twisted pair cable should be used. It is important to avoid circulating currents, which can cause
noise and interference, especially when the cable runs between buildings. For this reason, the screen should be
continuous and connected to ground at one end only, normally at the master connection point.
The K-Bus signal is a differential signal and there is no signal ground connection. If a signal ground connection is
present in the bus cable then it must be ignored. At no stage should this be connected to the cable's screen or to
the product’s chassis. This is for both safety and noise reasons.
A typical cable specification would be:
● Each core: 16/0.2 mm2 copper conductors, PVC insulated
● Nominal conductor area: 0.5 mm2 per core
● Screen: Overall braid, PVC sheathed
4.8 IRIG-B CONNECTION

The IRIG-B input and BNC connector have a characteristic impedance of 50 ohms. We recommend that
connections between the IRIG-B equipment and the product are made using coaxial cable of type RG59LSF with a
halogen free, fire retardant sheath.
4.9 OPTO-INPUT CONNECTIONS

These should be wired with 1 mm2 PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
Each opto-input has a selectable preset ½ cycle filter. This makes the input immune to noise induced on the wiring.
This can, however slow down the response. If you need to switch off the ½ cycle filter, either use double pole
switching on the input, or screened twisted cable on the input circuit.
Caution:
Protect the opto-inputs and their wiring with a maximum 16 A high rupture capacity
(HRC) type NIT or TIA fuse.
4.10 OUTPUT RELAY CONNECTIONS

These should be wired with 1 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
P64x-TM-EN-4.1 437
4.11 ETHERNET METALLIC CONNECTIONS

If the device has a metallic Ethernet connection, it can be connected to either a 10Base-T or a 100Base-TX
Ethernet hub. Due to noise sensitivity, we recommend this type of connection only for short distance connections,
ideally where the products and hubs are in the same cubicle. For increased noise immunity, CAT 6 (category 6) STP
(shielded twisted pair) cable and connectors can be used.
The connector for the Ethernet port is a shielded RJ-45. The pin-out is as follows:
Pin Signal name Signal definition
1 TXP Transmit (positive)
2 TXN Transmit (negative)
3 RXP Receive (positive)
4 - Not used
5 - Not used
6 RXN Receive (negative)
7 - Not used
8 - Not used
4.12 ETHERNET FIBRE CONNECTIONS

We recommend the use of fibre-optic connections for permanent connections in a substation environment. The
100 Mbps fibre optic port uses type ST connectors (one for Tx and one for Rx), compatible with 50/125 µm or
62.5/125 µm multimode fibres at 1300 nm wavelength.
Note:
For models equipped with redundant Ethernet connections the product must be partially dismantled to set the fourth octet of
the second IP address. This ideally, should be done before installation.
4.13 USB CONNECTION

The IED has a type B USB socket inside the bottom compartment. A standard USB printer cable (type A one end,
type B the other end) can be used to connect a local PC to the IED. This cable is the same as that used for
connecting a printer to a PC.
4.14 GPS FIBRE CONNECTION

Some products use a GPS 1 PPS timing signal. If applicable, this is connected to a fibre-optic port on the
coprocessor board in slot B. The fibre-optic port uses an ST type connector, compatible with fibre multimode
50/125 µm or 62.5/125 µm – 850 nm.
4.15 FIBRE COMMUNICATION CONNECTIONS

The fibre optic port consists of one or two channels using ST type connectors (one for Tx and one for Rx). The type
of fibre used depends on the option selected.
850 nm and 1300 nm multimode systems use 50/125 µm or 62.5/125 µm multimode fibres. 1300 nm and 1550 nm
single mode systems use 9/125 µm single mode fibres.
4.16 RTD CONNECTIONS

Resistance Temperature Detector (RTD) inputs use screw clamp connectors. The connection block is situated at the
rear of the IED. It can accept wire sizes from 0.1 mm2 to 1.5 mm2. The connections between the IED and the RTDs
438 P64x-TM-EN-4.1
must be made using a screened 3-core cable with a total resistance less than 10 Ω. The cable should have a
minimum voltage rating of 300 V RMS.
A 3-core cable should be used even for 2-wire RTD applications, as it allows for the cable’s resistance to be
removed from the overall resistance measurement. In such cases the third wire is connected to the second wire at
the point where the cable is joined to the RTD.
The screen of each cable must only be earthed (grounded) at one end, preferably at the IED end and must be
continuous. Multiple earthing (grounding) of the screen can cause circulating current to flow along the screen. This
induces noise and is also unsafe.
You should minimize the noise pick-up in the RTD cables by keeping them close to earthed (grounded) metal
casings and avoid areas of high electromagnetic and radio interference. The RTD cables should not be run
adjacent to or in the same conduit as other high voltage or current cables.
A typical cable specification would be:
● Each core: 7/0.2 mm copper conductors heat resistant PVC insulated
● Nominal conductor area: 0.22 mm2 per core
● Screen: Nickel-plated copper wire braid heat resistant PVC sheathed
The following extract may be useful in defining cable recommendations for the RTDs:
Noise pick up by cables can be categorized into three types:
● Resistive
● Capacitive
● Inductive
Resistive coupling requires an electrical connection to the noise source. Assuming the wire and cable insulation are
in good condition and the junctions are clean, this can be dismissed. Capacitive coupling requires sufficient
capacitance to the noise source. This is a function of the dielectric strength between the signal cable on the noise
source and the power of the noise source. Inductive coupling occurs when the signal cable is adjacent to a wire
carrying the noise or it is exposed to a radiated EMF.
Standard screened cable is normally used to protect against capacitively-coupled noise. However for this to be
effective, the screen should only be bonded to the system ground at one point. Otherwise a current could flow and
the noise would be coupled into the signal wires of the cable. There are different types of screening available, but
the most commonly used are aluminium foil wrap, or tin-copper braid. Foil screens are good for low to medium
frequencies and braid is good for high frequencies. High-fidelity screen cables provide both types.
Protection against inductive coupling requires careful cable routing and magnetic shielding. The latter can be
achieved with steel-armoured cable and steel cable trays. The cable armour must be grounded at both ends so
the EMF of the induced current cancels the field of the noise source and shields the cables conductors from it.
However, the system ground must be designed such that it does not bridge two isolated ground systems. This
could be hazardous and defeat the objectives of the original grounding design. The cable should be laid in the
cable trays as close as possible to the metal of the tray. Under no circumstance should any power cable be in or
near to the tray. Power cables should only cross the signal cables at 90 degrees and never be adjacent to them.
Both the capacitive and inductive screens must be contiguous from the RTD probes to the IED terminals. The best
types of cable are those provided by the RTD manufacturers. These are usually three conductors, known as a triad,
which are screened with foil. Such triad cables are available in armoured forms as well as multi-triad armoured
forms.
4.17 CLIO CONNECTIONS

Current Loop Inputs and Outputs (CLIO) use screw clamp connectors. The connection block is situated at the rear
of the IED. It can accept wire sizes from 0.1 mm2 to 1.5 mm2. We recommend screened cable, and it should have a
minimum voltage rating of 300 V RMS.
P64x-TM-EN-4.1 439
5 CASE DIMENSIONS
Not all products are available in all case sizes.
5.1 CASE DIMENSIONS 40TE

Sealing
155.40 8 off holes Dia. 3.4 strip
23.30
AB BA
168.00
177.0
159.00 (4U)
AB BA
10.35 181.30 483 (19” rack)

202.00
A = Clearance holes Flush mouting panel

Panel cut-out details
B = Mouting holes
200.00
Note: If mouting plate is required
use flush mounting cut out
dimensions
All dimensons in mm
240.00
Front view Incl. wiring
177.00
157.5
max.
C
Side view
206.00 25.00 E01411
Figure 178: 40TE case dimensions
440 P64x-TM-EN-4.1
E01409
P64x-TM-EN-4.1 441

74.95 116.55 142.45 12 OFF HOLES 3.40
FLUSH MOUNTING PANEL

CUT-OUT DETAIL
159.00 168.00
62.00 155.40 129.50

4.50
408.90
407.10
MOUNTING SCREW : M4 X 12 SEM UNIT STEEL THREAD

FORMING SCREW.
TERMINAL SCREWS : M4 X 7 BRASS CHEESE HEAD SCREWS WITH

222.00 LOCK WASHERS PROVIDED.
240.00
Incl. wiring
157.5
177.00 max.
SIDE VIEW
413.2
25.00
FRONT VIEW
E01410
442 P64x-TM-EN-4.1
CHAPTER 19
COMMISSIONING INSTRUCTIONS
Chapter 19 - Commissioning Instructions P64x
444 P64x-TM-EN-4.1
P64x Chapter 19 - Commissioning Instructions
1 CHAPTER OVERVIEW
General Guidelines 446
Commissioning Test Menu 447
Commissioning Equipment 450
Product Checks 452
Setting Checks 462
IEC 61850 Edition 2 Testing 464
Checking the Differential Element 469
Protection Timing Checks 472
Onload Checks 474
Final Checks 476
P64x-TM-EN-4.1 445
2 GENERAL GUIDELINES
General Electric IEDs are self-checking devices and will raise an alarm in the unlikely event of a failure. This is why
the commissioning tests are less extensive than those for non-numeric electronic devices or electro-mechanical
relays.
To commission the devices, you (the commissioning engineer) do not need to test every function. You need only
verify that the hardware is functioning correctly and that the application-specific software settings have been
applied. You can check the settings by extracting them using the settings application software, or by means of the
front panel interface (HMI panel).
The menu language is user-selectable, so you can change it for commissioning purposes if required.
Note:
Remember to restore the language setting to the customer’s preferred language on completion.
Caution:
Before carrying out any work on the equipment you should be familiar with the
contents of the Safety Section or Safety Guide SFTY/4LM as well as the ratings on the
equipment’s rating label.
Warning:
With the exception of the CT shorting contacts check, do not disassemble the device
during commissioning.
446 P64x-TM-EN-4.1
3 COMMISSIONING TEST MENU

The IED provides several test facilities under the COMMISSION TESTS menu heading. There are menu cells that
allow you to monitor the status of the opto-inputs, output relay contacts, internal Digital Data Bus (DDB) signals
and user-programmable LEDs. This section describes these commissioning test facilities.
3.1 OPTO I/P STATUS CELL (OPTO-INPUT STATUS)

This cell can be used to monitor the status of the opto-inputs while they are sequentially energised with a suitable
DC voltage. The cell is a binary string that displays the status of the opto-inputs where '1' means energised and '0'
means de-energised. If you move the cursor along the binary numbers, the corresponding label text is displayed
for each logic input.
3.2 RELAY O/P STATUS CELL (RELAY OUTPUT STATUS)

This cell can be used to monitor the status of the relay outputs. The cell is a binary string that displays the status of
the relay outputs where '1' means energised and '0' means de-energised. If you move the cursor along the binary
numbers, the corresponding label text is displayed for each relay output.
The cell indicates the status of the output relays when the IED is in service. You can check for relay damage by
comparing the status of the output contacts with their associated bits.
Note:
When the Test Mode cell is set to Contacts Blocked, the relay output status indicates which contacts would operate if
the IED was in-service. It does not show the actual status of the output relays, as they are blocked.
3.3 TEST MODE CELL

This cell allows you to perform secondary injection testing. It also lets you test the output contacts directly by
applying menu-controlled test signals.
To go into test mode, select the Test Mode option in the Test Mode cell. This takes the IED out of service causing
an alarm condition to be recorded and the Out of Service LED to illuminate. This also freezes any information
stored in the CB CONDITION column. In IEC 60870-5-103 versions, it changes the Cause of Transmission (COT) to
Test Mode.
In Test Mode, the output contacts are still active. To disable the output contacts you must select the Contacts
Blocked option.
Once testing is complete, return the device back into service by setting the Test Mode Cell back to Disabled.
Caution:
When the cell is in Test Mode, the Scheme Logic still drives the output relays, which
could result in tripping of circuit breakers. To avoid this, set the Test Mode cell to
Contacts Blocked.
Note:
Test mode and Contacts Blocked mode can also be selected by energising an opto-input mapped to the Test Mode
signal, and the Contact Block signal respectively.
P64x-TM-EN-4.1 447
3.4 TEST PATTERN CELL

The Test Pattern cell is used to select the output relay contacts to be tested when the Contact Test cell is set to
Apply Test. The cell has a binary string with one bit for each user-configurable output contact, which can be
set to '1' to operate the output and '0' to not operate it.
3.5 CONTACT TEST CELL

When the Apply Test command in this cell is issued, the contacts set for operation change state. Once the test
has been applied, the command text on the LCD will change to No Operation and the contacts will remain in the
Test state until reset by issuing the Remove Test command. The command text on the LCD will show No
Operation after the Remove Test command has been issued.
Note:
When the Test Mode cell is set to Contacts Blocked the Relay O/P Status cell does not show the current status of the
output relays and therefore cannot be used to confirm operation of the output relays. Therefore it will be necessary to monitor
the state of each contact in turn.
3.6 TEST LEDS CELL

When the Apply Test command in this cell is issued, the user-programmable LEDs illuminate for approximately
2 seconds before switching off, and the command text on the LCD reverts to No Operation.
3.7 RED AND GREEN LED STATUS CELLS

These cells contain binary strings that indicate which of the user-programmable red and green LEDs are
illuminated when accessing from a remote location. A '1' indicates that a particular LED is illuminated.
Note:
When the status in both Red LED Status and Green LED Status cells is ‘1’, this indicates the LEDs illumination is yellow.
3.8 PSL VERIFICIATION
3.8.1 TEST PORT STATUS CELL

This cell displays the status of the DDB signals that have been allocated in the Monitor Bit cells. If you move the
cursor along the binary numbers, the corresponding DDB signal text string is displayed for each monitor bit.
By using this cell with suitable monitor bit settings, the state of the DDB signals can be displayed as various
operating conditions or sequences are applied to the IED. This allows you to test the Programmable Scheme Logic
(PSL).
3.8.2 MONITOR BIT 1 TO 8 CELLS

The eight Monitor Bit cells allows you to select eight DDB signals that can be observed in the Test Port Status cell or
downloaded via the front port.
Each Monitor Bit cell can be assigned to a particular DDB signal. You set it by entering the required DDB signal
number from the list of available DDB signals.
The pins of the monitor/download port used for monitor bits are as follows:
Monitor Bit 1 2 3 4 5 6 7 8
Monitor/Download Port Pin 11 12 15 13 20 21 23 24
448 P64x-TM-EN-4.1
The signal ground is available on pins 18, 19, 22 and 25.
Caution:
The monitor/download port is not electrically isolated against induced voltages on
the communications channel. It should therefore only be used for local
communications.
3.8.3 USING A MONITOR PORT TEST BOX

A test box containing eight LEDs and a switchable audible indicator is available. It is housed in a small plastic box
with a 25-pin male D-connector that plugs directly into the monitor/download port. There is also a 25-pin female
D-connector which allows other connections to be made to the monitor/download port while the monitor/
download port test box is in place.
Each LED corresponds to one of the monitor bit pins on the monitor/download port. Monitor Bit 1 is on the left-
hand side when viewed from the front of the IED. The audible indicator can be selected to sound if a voltage
appears on any of the eight monitor pins. Alternatively it can be set to remain silent, using only the LEDs.
P64x-TM-EN-4.1 449
4 COMMISSIONING EQUIPMENT
Specialist test equipment is required to commission this product. We recognise three classes of equipment for
commissioning :
● Recommended
● Essential
● Advisory
Recommended equipment constitutes equipment that is both necessary, and sufficient, to verify correct
performance of the principal protection functions.
Essential equipment represents the minimum necessary to check that the product includes the basic expected
protection functions and that they operate within limits.
Advisory equipment represents equipment that is needed to verify satisfactory operation of features that may be
unused, or supplementary, or which may, for example, be integral to a distributed control/automation scheme.
Operation of such features may, perhaps, be more appropriately verified as part of a customer defined
commissioning requirement, or as part of a system-level commissioning regime.
4.1 RECOMMENDED COMMISSIONING EQUIPMENT

The minimum recommended equipment is a multifunctional three-phase AC current and voltage injection test set
featuring :
● Controlled three-phase AC current and voltage sources,
● Transient (dynamic) switching between pre-fault and post-fault conditions (to generate delta conditions),
● Dynamic impedance state sequencer (capable of sequencing through 4 impedance states),
● Integrated or separate variable DC supply (0 - 250 V)
● Integrated or separate AC and DC measurement capabilities (0-440V AC, 0-250V DC)
● Integrated and/or separate timer,
● Integrated and/or separate test switches.
In addition, you will need :

● A portable computer, installed with appropriate software to liaise with the equipment under test (EUT).
Typically this software will be proprietary to the product’s manufacturer (for example MiCOM S1 Agile).
● Suitable electrical test leads.
● Electronic or brushless insulation tester with a DC output not exceeding 500 V
● Continuity tester
● Verified application-specific settings files
4.2 ESSENTIAL COMMISSIONING EQUIPMENT

As an absolute minimum, the following equipment is required:
● AC current source coupled with AC voltage source
● Variable DC supply (0 - 250V)
● Multimeter capable of measuring AC and DC current and voltage (0-440V AC, 0-250V DC)
● Timer
● Test switches
● Suitable electrical test leads
● Continuity tester
450 P64x-TM-EN-4.1
4.3 ADVISORY TEST EQUIPMENT

Advisory test equipment may be required for extended commissioning procedures:
● Current clamp meter
● Multi-finger test plug:
○ P992 for test block type P991
○ MMLB for test block type MMLG blocks
● Electronic or brushless insulation tester with a DC output not exceeding 500 V
● KITZ K-Bus - EIA(RS)232 protocol converter for testing EIA(RS)485 K-Bus port
● EIA(RS)485 to EIA(RS)232 converter for testing EIA(RS)485 Courier/MODBUS/IEC60870-5-103/DNP3 port
● A portable printer (for printing a setting record from the portable PC) and or writeable, detachable memory
device.
● Phase angle meter
● Phase rotation meter
● Fibre-optic power meter.
● Fibre optic test leads (minimum 2). 10m minimum length, multimode 50/125 µm or 62.5µm terminated with
BFOC (ST) 2.5 connectors for testing the fibre-optic RP1 port.
P64x-TM-EN-4.1 451
5 PRODUCT CHECKS
These product checks are designed to ensure that the device has not been physically damaged prior to
commissioning, is functioning correctly and that all input quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the IED prior to commissioning, you should make a copy of
the settings. This will allow you to restore them at a later date if necessary. This can be done by:
● Obtaining a setting file from the customer.
● Extracting the settings from the IED itself, using a portable PC with appropriate setting software.
If the customer has changed the password that prevents unauthorised changes to some of the settings, either the
revised password should be provided, or the original password restored before testing.
Note:
If the password has been lost, a recovery password can be obtained from General Electric.
5.1 PRODUCT CHECKS WITH THE IED DE-ENERGISED
Warning:
The following group of tests should be carried out without the auxiliary supply being
applied to the IED and, if applicable, with the trip circuit isolated.
The current and voltage transformer connections must be isolated from the IED for these checks. If a P991 test
block is provided, the required isolation can be achieved by inserting test plug type P992. This open circuits all
wiring routed through the test block.
Before inserting the test plug, you should check the scheme diagram to ensure that this will not cause damage or
a safety hazard (the test block may, for example, be associated with protection current transformer circuits). The
sockets in the test plug, which correspond to the current transformer secondary windings, must be linked before
the test plug is inserted into the test block.
Warning:
Never open-circuit the secondary circuit of a current transformer since the high
voltage produced may be lethal and could damage insulation.
If a test block is not provided, the voltage transformer supply to the IED should be isolated by means of the panel
links or connecting blocks. The line current transformers should be short-circuited and disconnected from the IED
terminals. Where means of isolating the auxiliary supply and trip circuit (for example isolation links, fuses and MCB)
are provided, these should be used. If this is not possible, the wiring to these circuits must be disconnected and the
exposed ends suitably terminated to prevent them from being a safety hazard.
5.1.1 VISUAL INSPECTION
452 P64x-TM-EN-4.1
Warning:
Check the rating information under the top access cover on the front of the IED.
Warning:
Check that the IED being tested is correct for the line or circuit.
Warning:
Record the circuit reference and system details.
Warning:
Check the CT secondary current rating and record the CT tap which is in use.
Carefully examine the IED to see that no physical damage has occurred since installation.
Ensure that the case earthing connections (bottom left-hand corner at the rear of the IED case) are used to
connect the IED to a local earth bar using an adequate conductor.
5.1.2 CURRENT TRANSFORMER SHORTING CONTACTS

Check the current transformer shorting contacts to ensure that they close when the heavy-duty terminal block is
disconnected from the current input board.
The heavy-duty terminal blocks are fastened to the rear panel using four crosshead screws. These are located two
at the top and two at the bottom.
Note:
Use a magnetic bladed screwdriver to minimise the risk of the screws being left in the terminal block or lost.
Pull the terminal block away from the rear of the case and check with a continuity tester that all the shorting
switches being used are closed.
5.1.3 INSULATION
Insulation resistance tests are only necessary during commissioning if explicitly requested.
Isolate all wiring from the earth and test the insulation with an electronic or brushless insulation tester at a DC
voltage not exceeding 500 V. Terminals of the same circuits should be temporarily connected together.
The insulation resistance should be greater than 100 MW at 500 V.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected to the IED.
5.1.4 EXTERNAL WIRING
Caution:
Check that the external wiring is correct according to the relevant IED and scheme
diagrams. Ensure that phasing/phase rotation appears to be as expected.
5.1.5 WATCHDOG CONTACTS

Using a continuity tester, check that the Watchdog contacts are in the following states:
P64x-TM-EN-4.1 453
Terminals Contact state with product de-energised

11 - 12 on power supply board Closed
13 - 14 on power supply board Open
5.1.6 POWER SUPPLY

Depending on its nominal supply rating, the IED can be operated from either a DC only or an AC/DC auxiliary
supply. The incoming voltage must be within the operating range specified below.
Without energising the IED measure the auxiliary supply to ensure it is within the operating range.
Nominal supply rating Nominal supply rating
DC operating range AC operating range
DC AC RMS
24 - 54 V N/A 19 to 65 V N/A
48 - 125 V 30 - 100 V 37 to 150 V 24 - 110 V
110 - 250 V 100 - 240 V 87 to 300 V 80 to 265 V
Note:
The IED can withstand an AC ripple of up to 12% of the upper rated voltage on the DC auxiliary supply.
Warning:
Do not energise the IED or interface unit using the battery charger with the battery
disconnected as this can irreparably damage the power supply circuitry.
Caution:
Energise the IED only if the auxiliary supply is within the specified operating ranges.
If a test block is provided, it may be necessary to link across the front of the test plug
to connect the auxiliary supply to the IED.
5.2 PRODUCT CHECKS WITH THE IED ENERGISED
Warning:
The current and voltage transformer connections must remain isolated from the IED
for these checks. The trip circuit should also remain isolated to prevent accidental
operation of the associated circuit breaker.
The following group of tests verifies that the IED hardware and software is functioning correctly and should be
carried out with the supply applied to the IED.
5.2.1 WATCHDOG CONTACTS

Using a continuity tester, check that the Watchdog contacts are in the following states when energised and
healthy.
Terminals Contact state with product energised
11 - 12 on power supply board Open
13 - 14 on power supply board Closed
454 P64x-TM-EN-4.1
5.2.2 TEST LCD

The Liquid Crystal Display (LCD) is designed to operate in a wide range of substation ambient temperatures. For
this purpose, the IEDs have an LCD Contrast setting. The contrast is factory pre-set, but it may be necessary to
adjust the contrast to give the best in-service display.
To change the contrast, you can increment or decrement the LCD Contrast cell in the CONFIGURATION column.
Caution:
Before applying a contrast setting, make sure that it will not make the display so
light or dark such that menu text becomes unreadable. It is possible to restore the
visibility of a display by downloading a setting file, with the LCD Contrast set within
the typical range of 7 - 11.
5.2.3 DATE AND TIME

The date and time is stored in memory, which is backed up by a supercapacitor.
The method for setting the date and time depends on whether an IRIG-B signal is being used or not. The IRIG-B
signal will override the time, day and month settings, but not the initial year setting. For this reason, you must
ensure you set the correct year, even if the device is using IRIG-B to maintain the internal clock.
You set the Date and Time by one of the following methods:
● Using the front panel to set the Date and Time cells respectively
● By sending a courier command to the Date/Time cell (Courier reference 0801)
Note:
If the auxiliary supply fails, the time and date will be maintained by the supercapacitor. Therefore, when the auxiliary supply is
restored, you should not have to set the time and date again. To test this, remove the IRIG-B signal, and then remove the
auxiliary supply. Leave the device de-energised for approximately 30 seconds. On re energisation, the time should be correct.
When using IRIG-B to maintain the clock, the IED must first be connected to the satellite clock equipment (usually a
P594/RT430), which should be energised and functioning.
1. Set the IRIG-B Sync cell in the DATE AND TIME column to Enabled.
2. Ensure the IED is receiving the IRIG-B signal by checking that cell IRIG-B Status reads Active.
3. Once the IRIG-B signal is active, adjust the time offset of the universal co coordinated time (satellite clock
time) on the satellite clock equipment so that local time is displayed.
4. Check that the time, date and month are correct in the Date/Time cell. The IRIG-B signal does not contain
the current year so it will need to be set manually in this cell.
5. Reconnect the IRIG-B signal.
If the time and date is not being maintained by an IRIG-B signal, ensure that the IRIG-B Sync cell in the DATE AND
TIME column is set to Disabled.
1. Set the date and time to the correct local time and date using Date/Time cell or using the serial protocol.
5.2.4 TEST LEDS

On power-up, all LEDs should first flash yellow. Following this, the green "Healthy" LED should illuminate indicating
that the device is healthy.
The IED's non-volatile memory stores the states of the alarm, the trip, and the user-programmable LED indicators
(if configured to latch). These indicators may also illuminate when the auxiliary supply is applied.
P64x-TM-EN-4.1 455
If any of these LEDs are ON then they should be reset before proceeding with further testing. If the LEDs
successfully reset (the LED goes off), no testing is needed for that LED because it is obviously operational.
5.2.5 TEST ALARM AND OUT-OF-SERVICE LEDS

The alarm and out of service LEDs can be tested using the COMMISSION TESTS menu column.
1. Set the Test Mode cell to Contacts Blocked.
2. Check that the out of service LED illuminates continuously and the alarm LED flashes.
It is not necessary to return the Test Mode cell to Disabled at this stage because the test mode will be required
for later tests.
5.2.6 TEST TRIP LED

The trip LED can be tested by initiating a manual circuit breaker trip. However, the trip LED will operate during the
setting checks performed later. Therefore no further testing of the trip LED is required at this stage.
5.2.7 TEST USER-PROGRAMMABLE LEDS

To test these LEDs, set the Test LEDs cell to Apply Test. Check that all user-programmable LEDs illuminate.
5.2.8 TEST OPTO-INPUTS

This test checks that all the opto-inputs on the IED are functioning correctly.
The opto-inputs should be energised one at a time. For terminal numbers, please see the external connection
diagrams in the "Wiring Diagrams" chapter. Ensuring correct polarity, connect the supply voltage to the
appropriate terminals for the input being tested.
The status of each opto-input can be viewed using either the Opto I/P Status cell in the SYSTEM DATA column, or
the Opto I/P Status cell in the COMMISSION TESTS column.
A '1' indicates an energised input and a '0' indicates a de-energised input. When each opto-input is energised, one
of the characters on the bottom line of the display changes to indicate the new state of the input.
5.2.9 TEST OUTPUT RELAYS

This test checks that all the output relays are functioning correctly.
1. Ensure that the IED is still in test mode by viewing the Test Mode cell in the COMMISSION TESTS column.
Ensure that it is set to Contacts Blocked.
2. The output relays should be energised one at a time. To select output relay 1 for testing, set the Test Pattern
cell as appropriate.
3. Connect a continuity tester across the terminals corresponding to output relay 1 as shown in the external
connection diagram.
4. To operate the output relay set the Contact Test cell to Apply Test.
5. Check the operation with the continuity tester.
6. Measure the resistance of the contacts in the closed state.
7. Reset the output relay by setting the Contact Test cell to Remove Test.
8. Repeat the test for the remaining output relays.
9. Return the IED to service by setting the Test Mode cell in the COMMISSION TESTS menu to Disabled.
5.2.10 RTD INPUTS

This test checks that all the RTD inputs are functioning correctly, if the RTD board is fitted.
456 P64x-TM-EN-4.1
Please refer to the wiring diagrams for details of the terminal connections.
1. You should connect a 100 ohm resistor across each RTD in turn. The resistor needs to have a very small
tolerance (0.1%). You must connect the RTD common return terminal to the correct RTD input, otherwise the
device will report an RTD error.
2. Check that the corresponding temperature displayed in the MEASUREMENTS 3 column of the menu is 0°C
+/-2°C. This range takes into account the 0.1% resistor tolerance and device accuracy of +/-1°C. If a resistor
of lower accuracy is used during testing, the acceptable setting range needs to be increased.
5.2.11 CURRENT LOOP OUTPUTS

This test checks that all the current loop outputs are functioning correctly, if the board is fitted.
Please refer to the wiring diagrams for details of the terminal connections. Note that for the current loop outputs,
the physical connection of the 1 mA output is different from that of the other types.
1. Enable the current loop output to be tested.
2. Note the current loop output type (CLO Type) for the application.
3. Note the current loop output parameter (CLO Parameter)
4. Note the current loop output minimum and maximum settings (CLO Minimum and CLO Maximum)
5. Apply the appropriate analog input quantity to match the CLO Parameter at a value equal to (CLO
maximum + CLO minimum)/2. The current loop output should be at 50% of its maximum rated output.
6. Using a precision resistive current shunt and a high-resolution voltmeter, check that the current loop output
is at 50% of its maximum rated output according to the range as follows:
0.5 mA (0 to 1 mA CLO)
5 mA (0 to 10 mA CLO)
10 mA (0 to 20, 4 to 20 mA CLO)
7. The accuracy should be within +/-0.5% of full scale + meter accuracy.
5.2.12 CURRENT LOOP INPUTS

This test checks that all the current loop inputs are functioning correctly, if the board is fitted.
Please refer to the wiring diagrams for details of the terminal connections. Note that for the current loop inputs,
the physical connection of the 1 mA input is different from that of the other types.
You can use an accurate DC current source to apply various current levels to the current loop inputs. One
approach to this is to use a current loop output as a DC current sources. If you stimulate the current loop output by
applying an appropriate signal to the input to which it has been assigned with the CLO Parameter setting, you will
get an appropriate DC signal if the output is enabled.
1. Enable the current loop input to be tested.
2. Note the CLIx minimum and maximum settings and the CLIx Input type for the application.
3. Apply a DC current to the current loop input at 50% of the CLI input maximum range, 0.5 mA (0 to 1 mA CLI),
5 mA (0 to 10 mA CLI) or 10 mA (0 to 20, 4 to 20 mA CLI).
4. Check the accuracy of the current loop input using the CLIO Input 1/2/3/4 cells in the MEASUREMENTS 3
column. The display should show (CLIx maximum + CLIx minimum)/2 +/-1% full scale accuracy.
5.2.13 TEST SERIAL COMMUNICATION PORT RP1

You need only perform this test if the IED is to be accessed from a remote location with a permanent serial
connection to the communications port. The scope of this test does not extend to verifying operation with
connected equipment beyond any supplied protocol converter. It verifies operation of the rear communication port
(and if applicable the protocol converter) and varies according to the protocol fitted.
P64x-TM-EN-4.1 457
5.2.13.1 CHECK PHYSICAL CONNECTIVITY

The rear communication port RP1 is presented on terminals 16, 17 and 18 of the power supply terminal block.
Screened twisted pair cable is used to make a connection to the port. The cable screen should be connected to pin
16 and pins 17 and 18 are for the communication signal:
Figure 181: RP1 physical connection
For K-Bus applications, pins 17 and 18 are not polarity sensitive and it does not matter which way round the wires
are connected. EIA(RS)485 is polarity sensitive, so you must ensure the wires are connected the correct way round
(pin 18 is positive, pin 17 is negative).
If K-Bus is being used, a Kitz protocol converter (KITZ101, KITZ102 OR KITZ201) will have been installed to convert
the K-Bus signals into RS232. Likewise, if RS485 is being used, an RS485-RS232 converter will have been installed.
In the case where a protocol converter is being used, a laptop PC running appropriate software (such as MiCOM S1
Agile) can be connected to the incoming side of the protocol converter. An example for K-bus to RS232 conversion
is shown below. RS485 to RS232 would follow the same principle, only using a RS485-RS232 converter. Most
modern laptops have USB ports, so it is likely you will also require a RS232 to USB converter too.
458 P64x-TM-EN-4.1
C C C
IED IED IED
RS232 K-Bus
Computer RS232-USB converter KITZ protocol converter

V01001
Figure 182: Remote communication using K-bus
Fibre Connection
Some models have an optional fibre optic communications port fitted (on a separate communications board). The
communications port to be used is selected by setting the Physical Link cell in the COMMUNICATIONS column, the
values being Copper or K-Bus for the RS485/K-bus port and Fibre Optic for the fibre optic port.
5.2.13.2 CHECK LOGICAL CONNECTIVITY

The logical connectivity depends on the chosen data protocol, but the principles of testing remain the same for all
protocol variants:
1. Ensure that the communications baud rate and parity settings in the application software are set the same
as those on the protocol converter.
2. For Courier models, ensure that you have set the correct RP1 address
3. Check that communications can be established with this IED using the portable PC/Master Station.
5.2.14 TEST SERIAL COMMUNICATION PORT RP2

RP2 is an optional second serial port board providing additional serial connectivity. It provides two 9-pin D-type
serial port connectors SK4 and SK5. Both ports are configured as DTE (Date Terminal Equipment) ports. That means
they can be connected to communications equipment such as a modem with a straight-through cable.
SK4 can be configured as an EIA(RS232), EIA(RS485), or K-Bus connection for Courier protocol only, whilst SK5 is
fixed to EIA(RS)232 for InterMiCOM signalling only.
It is not the intention of this test to verify the operation of the complete communication link between the IED and
the remote location, just the IED's rear communication port and, if applicable, the protocol converter.
The only checks that need to be made are as follows:
1. Set the RP2 Port Config cell in the COMMUNICATIONS column to the required physical protocol; (K-Bus,
EIA(RS)485, or EIA(RS)232.
2. Set the IED's Courier address to the correct value (it must be between 1 and 254).
P64x-TM-EN-4.1 459
5.2.15 TEST ETHERNET COMMUNICATION

For products that employ Ethernet communications, we recommend that testing be limited to a visual check that
the correct ports are fitted and that there is no sign of physical damage.
If there is no board fitted or the board is faulty, a NIC link alarm will be raised (providing this option has been set in
the NIC Link Report cell in the COMMUNICATIONS column).
5.3 SECONDARY INJECTION TESTS

Secondary injection testing is carried out to verify the integrity of the VT and CT readings. All devices leave the
factory set for operation at a system frequency of 50 Hz. If operation at 60 Hz is required, you must set this in the
Frequency cell in the SYSTEM DATA column.
The PMU must be installed and connected to a 1pps fibre optic synchronising signal and a demodulated IRIG-B
signal, provided by a device such as a P594 or a REASON RT430.
Connect the current and voltage outputs of the test set to the appropriate terminals of the first voltage and current
channel and apply nominal voltage and current with the current lagging the voltage by 90 degrees.
5.3.1 TEST CURRENT INPUTS

This test verifies that the current measurement inputs are configured correctly.
1. Using secondary injection test equipment such as an Omicron, apply and measure nominal rated current to
each CT in turn.
2. Check its magnitude using a multi-meter or test set readout. Check this value against the value displayed
on the HMI panel (usually in MEASUREMENTS 1 column).
3. Record the displayed value. The measured current values will either be in primary or secondary Amperes. If
the Local Values cell in the MEASURE’T SETUP column is set to Primary, the values displayed should be
equal to the applied current multiplied by the corresponding current transformer ratio (set in the CT AND VT
RATIOS column). If the Local Values cell is set to Secondary, the value displayed should be equal to the
applied current.
Note:
If a PC connected to the IED using the rear communications port is being used to display the measured current, the process
will be similar. However, the setting of the Remote Values cell in the MEASURE’T SETUP column will determine whether the
displayed values are in primary or secondary Amperes.
The measurement accuracy of the IED is +/- 1%. However, an additional allowance must be made for the accuracy
of the test equipment being used.
5.3.1.1 CHECK POLARITY OF THREE-PHASE CTS

This test checks the polarity of all three-phase CTs associated with a winding.
1. Apply the same current to phases A, B, and C, phase displaced as for a balanced 3-phase set with standard
ABC phase rotation (phase A = 0°, phase B = -120°, phase C = +120°).
2. Starting from CT input 1, apply the balanced current and check the measured residual current in the
relevant cell. This will be IN-TN1 Deriv Mag, IN-TN2 Deriv Mag, or IN-TN3 Deriv Mag depending on the
transformer winding to which the current input is assigned.
3. The residual current measured should be less than 0.05 p.u. If high residual current is measured, one or
more of the CT circuits for the end concerned may have a problem (for example, an inverted connection).
Repeat the same test on the rest of the CT inputs.
460 P64x-TM-EN-4.1
5.3.2 TEST VOLTAGE INPUTS

This test verifies that the voltage measurement inputs are configured correctly.
1. Using secondary injection test equipment, apply and measure the rated voltage to each voltage
transformer input in turn.
2. Check its magnitude using a multimeter or test set readout. Check this value against the value displayed on
the HMI panel (usually in MEASUREMENTS 1 column).
3. Record the value displayed. The measured voltage values will either be in primary or secondary Volts. If the
Local Values cell in the MEASURE’T SETUP column is set to Primary, the values displayed should be equal
to the applied voltage multiplied by the corresponding voltage transformer ratio (set in the CT AND VT
RATIOS column). If the Local Values cell is set to Secondary, the value displayed should be equal to the
applied voltage.
Note:
If a PC connected to the IED using the rear communications port is being used to display the measured current, the process
will be similar. However, the setting of the Remote Values cell in the MEASURE’T SETUP column will determine whether the
displayed values are in primary or secondary Amperes.
The measurement accuracy of the IED is +/- 1%. However, an additional allowance must be made for the accuracy
of the test equipment being used.
P64x-TM-EN-4.1 461
6 SETTING CHECKS
The setting checks ensure that all of the application-specific settings (both the IED’s function and programmable
scheme logic settings) have been correctly applied.
Note:
If applicable, the trip circuit should remain isolated during these checks to prevent accidental operation of the associated
circuit breaker.
6.1 APPLY APPLICATION-SPECIFIC SETTINGS

There are two different methods of applying the settings to the IED
● Transferring settings to the IED from a pre-prepared setting file using MiCOM S1 Agile
● Enter the settings manually using the IED’s front panel HMI
6.1.1 TRANSFERRING SETTINGS FROM A SETTINGS FILE

This is the preferred method for transferring function settings. It is much faster and there is a lower margin for
error.
1. Connect a PC running the Settings Application Software to the IED's front port, or a rear Ethernet port.
Alternatively connect to the rear Courier communications port, using a KITZ protocol converter if necessary.
2. Power on the IED
3. Enter the IP address of the device if it is Ethernet enabled
4. Right-click the appropriate device name in the System Explorer pane and select Send
5. In the Send to dialog select the setting files and click Send
Note:
The device name may not already exist in the system shown in System Explorer. In this case, perform a Quick Connect to the
IED, then manually add the settings file to the device name in the system. Refer to the Settings Application Software help for
details of how to do this.
6.1.2 ENTERING SETTINGS USING THE HMI

1. Starting at the default display, press the Down cursor key to show the first column heading.
2. Use the horizontal cursor keys to select the required column heading.
3. Use the vertical cursor keys to view the setting data in the column.
4. To return to the column header, either press the Up cursor key for a second or so, or press the Cancel key
once. It is only possible to move across columns at the column heading level.
5. To return to the default display, press the Up cursor key or the Cancel key from any of the column headings.
If you use the auto-repeat function of the Up cursor key, you cannot go straight to the default display from
one of the column cells because the auto-repeat stops at the column heading.
6. To change the value of a setting, go to the relevant cell in the menu, then press the Enter key to change the
cell value. A flashing cursor on the LCD shows that the value can be changed. You may be prompted for a
password first.
7. To change the setting value, press the vertical cursor keys. If the setting to be changed is a binary value or a
text string, select the required bit or character to be changed using the left and right cursor keys.
462 P64x-TM-EN-4.1
8. Press the Enter key to confirm the new setting value or the Clear key to discard it. The new setting is
automatically discarded if it is not confirmed within 15 seconds.
9. For protection group settings and disturbance recorder settings, the changes must be confirmed before
they are used. When all required changes have been entered, return to the column heading level and press
the down cursor key. Before returning to the default display, the following prompt appears.
Update settings?
ENTER or CLEAR
10. Press the Enter key to accept the new settings or press the Clear key to discard the new settings.
Note:
If the menu time-out occurs before the setting changes have been confirmed, the setting values are also discarded.
Control and support settings are updated immediately after they are entered, without the Update settings prompt.
It is not possible to change the PSL using the IED’s front panel HMI.
Caution:
Where the installation needs application-specific PSL, the relevant .psl files, must be
transferred to the IED, for each and every setting group that will be used. If you do
not do this, the factory default PSL will still be resident. This may have severe
operational and safety consequences.
P64x-TM-EN-4.1 463
7 IEC 61850 EDITION 2 TESTING
7.1 USING IEC 61850 EDITION 2 TEST MODES

In a conventional substation, functionality typically resides in a single device. It is usually easy to physically isolate
these functions, as the hardwired connects can simply be removed. Within a digital substation architecture
however, functions may be distributed across many devices. This makes isolation of these functions difficult,
because there are no physical wires that can be disconnected on a Ethernet network. Logical isolation of the
various functions is therefore necessary.
With devices that support IEC 61850 Edition 2, it is possible to use a test mode to conduct online testing, which
helps with the situation. The advantages of this are as follows:
● The device can be placed into a test mode, which can disable the relay outputs when testing the device
with test input signals.
● Specific protection and control functions can be logically isolated.
● GOOSE messages can be tagged so that receiving devices can recognise they are test signals.
● An IED receiving simulated GOOSE or Sampled Value messages from test devices can differentiate these
from normal process messages, and be configured to respond appropriately.
7.1.1 IED TEST MODE BEHAVIOUR

Test modes define how the device responds to test messages, and whether the relay outputs are activated or not.
You can select the mode of operation by:
● Using the front panel HMI, with the setting IED Test Mode under the COMMISSION TESTS column.
● Using an IEC 61850 control service to System/LLN0.Mod
● Using an opto-input via PSL with the signal Block Contacts
The following table summarises the IED behaviour under the different modes:
IED Test Mode Setting Result
Disabled ● Normal IED behaviour
● Protection remains enabled
● Output from the device is still active
Test ● IEC 61850 message output has the 'quality' parameter set to 'test'
● The device only responds to IEC61850 MMS messages from the client with the
'test' flag set
● Protection remains enabled
● Output from the device is disabled
Contacts Blocked ● IEC 61850 message output has quality set to ‘test’
● The device only responds to IEC 61850 MMS messages from the client with the
'test' flag set
Setting the Test or Contacts Blocked mode puts the whole IED into test mode. The IEC 61850 data object Beh in all
Logical Nodes (except LPHD and any protection Logical Nodes that have Beh = 5 (off) due to the function being
disabled) will be set to 3 (test) or 4 (test/blocked) as applicable.
7.1.2 SAMPLED VALUE TEST MODE BEHAVIOUR

The SV Test Mode defines how the device responds to test sampled value messages. You can select the mode of
operation by using the front panel HMI, with the setting SV Test Mode under the IEC 61850-9.2LE column.
The following table summarises the behaviour for sampled values under the different modes:
464 P64x-TM-EN-4.1
SV Test Mode Setting Result

● Normal IED behaviour
● All sampled value data frames received with an IEC 61850 Test quality bit set
Disabled are treated as invalid
● The IED will display the measurement values for sampled values with the
Simulated flag set but the protection elements within the IED will be blocked
● All sampled value data frames received are treated as good, no matter if they
Enabled
have an IEC 61850-9-2 Simulated flag set or not
7.2 SIMULATED INPUT BEHAVIOUR

Simulated GOOSE messages and sampled value streams can be used during testing.
The Subscriber Sim setting in the COMMISSION TESTS column controls whether a device listens to simulated
signals or to real ones. An IEC 61850 control service to System/LPHD.Sim can also be used to change this value.
The device may be presented with both real signals and test signals. An internal state machine is used to control
how the device switches between signals:
● The IED will continue subscribing to the ‘real’ GOOSE1 (in green) until it receives the first simulated GOOSE 1
(in red). This will initiate subscription changeover.
● After changeover to this new state, the IED will continue to subscribe to the simulated GOOSE 1 message (in
red). Even if this simulated GOOSE 1 message disappears, the real GOOSE 1 message (in green) will still not
be processed. This means all Virtual Inputs derived from the GOOSE 1 message will go to their default state.
● The only way to bring the IED out of this state is to set the Subscriber Sim setting back to False. The IED will
then immediately stop processing the simulated messages and start processing real messages again.
● During above steps, IED1 will continuously process the real GOOSE 2 and GOOSE 3 messages as normal
because it has not received any simulated messages for these that would initiate a changeover.
The process is represented in the following figure:
LPHD1
Sim stVal=true Beh stVal=on

Simulated GOOSE 1 messages
Simulation bit goes TRUE
Real GOOSE 1 messages

Simulation bit was FALSE
Incoming data
processed
Reception buffer
V01058
Figure 183: Simulated input behaviour
7.3 TESTING EXAMPLES

These examples show how you test the IED with and without simulated values. Depending on the IED Test Mode, it
may respond by operating plant (for example by tripping the circuit breaker) or it may not operate plant.
P64x-TM-EN-4.1 465
7.3.1 TEST PROCEDURE FOR REAL VALUES

This procedure is for testing with real values without operating plant.
1. Set device into 'Contacts Blocked' Mode
Select COMMISSION TESTS ® IED Test Mode ® Contacts Blocked
2. Confirm new behaviour has been enabled
View COMMISSION TESTS ® IED Mod/Beh, and check that it shows Test-blocked
3. Set device into Simulation Listening Mode
Select COMMISSION TESTS ® Subscriber Sim = Disabled
4. If using sampled values set the sampled values test mode
Select IEC 61850-9.2LE ® SV Test Mode ® Disabled
5. Inject real signals using a test device connected to the merging units. The device will continue to listen to
‘real’ GOOSE messages and ignore simulated messages received.
6. Verify function based on test signal outputs
Binary outputs (e.g. CB trips) will not operate. All transmitted GOOSE and MMS data items will be tagged with
the 'quality' parameter set to 'test', so that the receiver understands that they have been issued by a device
under test and can respond accordingly. This is summarised in the following diagram
Fully digital bay Hardwired

CB control
Station/Process Bus
q = test No output
Yard Yard
SC MU1 Switchgear
MU1 MU1
Test Test
Device Device
V01062
Figure 184: Test example 1
7.3.2 TEST PROCEDURE FOR SIMULATED VALUES - NO PLANT

This procedure is for testing with simulated values without operating plant.
Select COMMISSION TESTS ® IED Test Mode ® Contacts Blocked
View COMMISSION TESTS ® IED Mod/Beh, and check that it shows test-blocked
466 P64x-TM-EN-4.1

Select COMMISSION TESTS ® Subscriber Sim = Enabled
Select IEC 61850-9.2LE ® SV Test Mode ® Enabled
5. Inject simulated signals using a test device connected to the Ethernet network. The device will continue to
listen to ‘real’ GOOSE messages until a simulated message is received. Once the simulated messages are
received, the corresponding ‘real’ messages are ignored until the device is taken out of test mode. Each
message is treated separately, but sampled values are considered as a single message.
6. Verify function based on test signal outputs
Binary outputs (e.g. CB trips) will not operate. All transmitted GOOSE and MMS data items will be tagged with
the 'quality' parameter set to 'test', so that the receiver understands that they have been issued by a device
under test and can respond accordingly. This is summarised in the following diagram

CB control
Station/Process Bus
Simulated q = test No output
values
Yard Yard
Test
Device SC MU1 Switchgear
MU1 MU1
V01063
7.3.3 TEST PROCEDURE FOR SIMULATED VALUES - WITH PLANT

This procedure is for testing with simulated values with operating plant.
Select COMMISSION TESTS ® IED Test Mode ® Test
View COMMISSION TESTS ® IED Mod/Beh, and check that it shows Test
Select COMMISSION TESTS ® Subscriber Sim = Enabled
P64x-TM-EN-4.1 467

Select IEC 61850-9.2LE ® SV Test Mode ® Enabled
5. Inject simulated signals using a test device connected to the Ethernet network.
The device will continue to listen to ‘real’ GOOSE messages until a simulated message is received. Once the
simulated messages are received, the corresponding ‘real’ messages are ignored until the device is taken
out of IED test mode. Each message is treated separately, but sampled values are considered as a single
message.
6. Verify function based on test signal outputs.
Binary outputs (e.g. CB trips) will operate as normal. All transmitted GOOSE and MMS data items will be
tagged with the 'quality' parameter set to 'test', so that the receiver understands that they have been issued
by a device under test and can respond accordingly. This is summarised in the following diagram:

CB control
Station/Process Bus
Simulated q = test Trip output
values
Yard Yard
Test
Device SC MU1 Switchgear
MU1 MU1
V01064
7.3.4 CONTACT TEST

The Apply Test command in this cell is used to change the state of the contacts set for operation.
If the device has been put into 'Contact Blocked' mode using an input signal (via the Block Contacts DDB signal)
then the Apply Test command will not execute. This is to prevent a device that has been blocked by an external
process having its contacts operated by a local operator using the HMI.
If the Block Contacts DDB is not set and the Apply Test command in this cell is issued, contacts change state and
the command text on the LCD changes to No Operation. The contacts remain in the Test state until reset by
issuing the Remove Test command. The command text on the LCD shows No Operation after the Remove Test
command has been issued.
Note:
When the IED Test Mode cell is set to Contacts Blocked, the Relay O/P Status cell does not show the current status of the
output relays so cannot be used to confirm operation of the output relays. Therefore it is necessary to monitor the state of
each contact in turn.
468 P64x-TM-EN-4.1
8 CHECKING THE DIFFERENTIAL ELEMENT

Testing of the differential element during commissioning is not necessary unless explicitly requested.
To avoid spurious operation of any other protection elements, all protection elements except the transformer
differential protection should be disabled for the duration of the differential element tests. This is done in the
product’s CONFIGURATION column. Make a note of which elements need to be re-enabled after testing.
The following tests demonstrate correct operation of the differential protection. Testing should be performed on
individual current inputs of each phase and on each winding, but note that the timing test should only be
performed on the high voltage winding. Testing the low-set element is sufficient to test the correct operation of the
differential protection.
Using a suitable current injection method, slowly increase the current from 0 Amps and note the pick-up value at
which the element operates. Reduce the current slowly and note the drop-off value at which it resets. Check that
the pick-up and drop-off are within the range shown in the table below.
Current level
Pick-up 0.90 x In to 1.1 x In
Drop-off 0.90 x pick-up to 1 x pick-up
where In = Is1/(amplitude matching factor)

and Is1 is the low set setting which can be found in the Is1 cell in the DIFF PROTECTION column.
The amplitude matching factor is used to compensate for a mismatch in currents due to the line side current
transformer ratios. There is one amplitude matching factor for the high-voltage side, one for the low-voltage side
and one for the tertiary-voltage side. You will find these in the SYSTEM CONFIG column. Use the appropriate
amplitude matching factor to calculate the required injection current. This depends on whether it is being injected
into the HV, LV, or TV current transformer inputs.
1. Whilst connected to the HV windings, connect the output contacts for the low set differential protection
function to trip the test set and also to stop a timer.
2. Configure the test set so that when the current is applied, the timer starts.
3. Inject 5x In into the HV CT input.
4. Check that the element operates within the range of 30 ms to 35 ms and record the time.
Note:
If this test has been successfully performed there is no need to carry out the tests described in the protection timing checks
section.
8.1 USING THE OMICRON ADVANCED MODULE

In software versions 05 and onwards, transient bias can be disabled or enabled. In software version 06 onwards,
the CT Saturation function was separated from the No gap function.
Testing Differential Operating Characteristics

When testing the differential operating characteristic, it is important to first disable transient bias. The CT
saturation and No Gap settings may be either disabled or enabled. An example is shown below:
P64x-TM-EN-4.1 469
V01503
Figure 187: Operating Characteristic Diagram
Testing Differential Tripping Time Characteristics

When testing the differential tripping time characteristic, transient bias, CT saturation and No Gap settings may be
either disabled or enabled. An example is shown below:
V01504
Figure 188: Trip Time Test Plane
470 P64x-TM-EN-4.1
Testing Harmonic Restraint

When testing 2nd or 5th harmonic restraint, transient bias may be either enabled or disabled, but the CT
Saturation and No Gap settings must be disabled. This is because harmonic blocking is used to unblock the
protection during normal energization of the transformer, while No Gap Detection and CT Saturation Detection is
used to unblock the protection during an internal fault. An example is shown below:
Harmonic Restraint Test Plane

Idiff/In [In]
I2f/Idiff [%]
V01505
Figure 189: Harmonic Restraint Test Plane
P64x-TM-EN-4.1 471
9 PROTECTION TIMING CHECKS

There is no need to check every protection function. Only one protection function needs to be checked as the
purpose is to verify the timing on the processor is functioning correctly.
9.1 BYPASSING THE ALL POLE DEAD BLOCKING CONDITION

Some protection functions and control functions are blocked when all poles are dead. When these conditions are
met, an All Poles Dead signal is asserted, blocking the said conditions. If you wish to test these these elements
during commissioning, you must bypass this blocking condition. You can do this by modifying the default PSL,
placing a NOT gate between the CB1 Closed signal and opto-input 7, so that when this input is not energised, CB1
is assumed to be closed.
9.2 OVERCURRENT CHECK

If the overcurrent protection function is being used, test the overcurrent protection for stage 1.
1. Check for any possible dependency conditions and simulate as appropriate.
2. In the CONFIGURATION column, disable all protection elements other than the one being tested.
3. Make a note of which elements need to be re-enabled after testing.
4. Connect the test circuit.
5. Perform the test.
6. Check the operating time.
9.3 CONNECTING THE TEST CIRCUIT

1. Use the PSL to determine which output relay will operate when an overcurrent trip occurs.
2. Use the output relay assigned to Trip Output A.
3. Use the PSL to map the protection stage under test directly to an output relay.
Note:
If using the default PSL, use output relay 3 as this is already mapped to the DDB signal Trip Command Out.
4. Connect the output relay so that its operation will trip the test set and stop the timer.
5. Connect the current output of the test set to the A-phase current transformer input.
If the I>1 Directional cell in the OVERCURRENT column is set to Directional Fwd, the current should
flow out of terminal 2. If set to Directional Rev, it should flow into terminal 2.
If the I>1 Directional cell in the OVERCURRENT column has been set to Directional Fwd or
Directional Rev, the rated voltage should be applied to terminals 20 and 21.
6. Ensure that the timer starts when the current is applied.
Note:
If the timer does not stop when the current is applied and stage 1 has been set for directional operation, the connections may
be incorrect for the direction of operation set. Try again with the current connections reversed.
472 P64x-TM-EN-4.1
9.4 PERFORMING THE TEST

1. Ensure that the timer is reset.
2. Apply a current of twice the setting shown in the I>1 Current Set cell in the OVERCURRENT column.
3. Note the time displayed when the timer stops.
4. Check that the red trip LED has illuminated.
9.5 CHECK THE OPERATING TIME

Check that the operating time recorded by the timer is within the range shown below.
For all characteristics, allowance must be made for the accuracy of the test equipment being used.
Operating time at twice current setting and time multiplier/
Characteristic
time dial setting of 1.0
Nominal (seconds) Range (seconds)
DT I>1 Time Delay setting Setting ±2%
IEC S Inverse 10.03 9.53 - 10.53
IEC V Inverse 13.50 12.83 - 14.18
IEC E Inverse 26.67 24.67 - 28.67
UK LT Inverse 120.00 114.00 - 126.00
IEEE M Inverse 3.8 3.61 - 4.0
IEEE V Inverse 7.03 6.68 - 7.38
IEEE E Inverse 9.50 9.02 - 9.97
US Inverse 2.16 2.05 - 2.27
US ST Inverse 12.12 11.51 - 12.73
Note:
With the exception of the definite time characteristic, the operating times given are for a Time Multiplier Setting (TMS) or Time
Dial Setting (TDS) of 1. For other values of TMS or TDS, the values need to be modified accordingly.
Note:
For definite time and inverse characteristics there is an additional delay of up to 0.02 second and 0.08 second respectively.
You may need to add this the IED's acceptable range of operating times.
Caution:
On completion of the tests, you must restore all settings to customer specifications.
P64x-TM-EN-4.1 473
10 ONLOAD CHECKS
Warning:
Onload checks are potentially very dangerous and may only be carried out by
qualified and authorised personnel.
Onload checks can only be carried out if there are no restrictions preventing the energisation of the plant, and the
other devices in the group have already been commissioned.
Remove all test leads and temporary shorting links, then replace any external wiring that has been removed to
allow testing.
Warning:
If any external wiring has been disconnected for the commissioning process, replace
it in accordance with the relevant external connection or scheme diagram.
10.1 CONFIRM CURRENT CONNECTIONS

1. Measure the current transformer secondary values for each input either by:
a. reading from the device's HMI panel (providing it has first been verified by a secondary injection test)
b. using a current clamp meter
2. Check that the current transformer polarities are correct by measuring the phase angle between the
current and voltage, either against a phase meter already installed on site and known to be correct or by
determining the direction of power flow by contacting the system control centre.
3. Ensure the current flowing in the neutral circuit of the current transformers is negligible.
If the Local Values cell is set to Secondary, the values displayed should be equal to the applied secondary
voltage. The values should be within 1% of the applied secondary voltages. However, an additional allowance must
be made for the accuracy of the test equipment being used.
If the Local Values cell is set to Primary, the values displayed should be equal to the applied secondary voltage
multiplied the corresponding voltage transformer ratio set in the CT & VT RATIOS column. The values should be
within 1% of the expected values, plus an additional allowance for the accuracy of the test equipment being used.
10.2 CONFIRM VOLTAGE CONNECTIONS

1. Using a multimeter, measure the voltage transformer secondary voltages to ensure they are correctly rated.
2. Check that the system phase rotation is correct using a phase rotation meter.
3. Compare the values of the secondary phase voltages with the measured voltage magnitude values, which
can be found in the MEASUREMENTS 1 menu column.
Cell in MEASUREMENTS 1 Column Corresponding VT ratio in CT/VT RATIOS column

VAB MAGNITUDE
VBC MAGNITUDE
VCA MAGNITUDE
Main VT Primary / Main VT Sec'y
VAN MAGNITUDE
VBN MAGNITUDE
VCN MAGNITUDE
C/S Voltage Mag CS VT Primary / CS VT Secondary
474 P64x-TM-EN-4.1
If the Local Values cell is set to Secondary, the values displayed should be equal to the applied secondary
voltage. The values should be within 1% of the applied secondary voltages. However, an additional allowance must
be made for the accuracy of the test equipment being used.
If the Local Values cell is set to Primary, the values displayed should be equal to the applied secondary voltage
multiplied the corresponding voltage transformer ratio set in the CT & VT RATIOS column. The values should be
within 1% of the expected values, plus an additional allowance for the accuracy of the test equipment being used.
10.3 ON-LOAD DIRECTIONAL TEST

This test ensures that directional overcurrent and fault locator functions have the correct forward/reverse
response to fault and load conditions. For this test you must first know the actual direction of power flow on the
system. If you do not already know this you must determine it using adjacent instrumentation or protection
already in-service.
● For load current flowing in the Forward direction (power export to the remote line end), the cells A Phase
Watts HV, A Phase Watts LV , and A Phase Watts TV in the MEASUREMENTS 2 column should show positive
power signing.
● For load current flowing in the Reverse direction (power import from the remote line end), the cells A Phase
Watts LV in the MEASUREMENTS 2 column should show negative power signing.
Note:
This check applies only for Measurement Modes 0 (default), and 2. This should be checked in the MEASURE’T. SETUP column
(Measurement Mode = 0 or 2). If measurement modes 1 or 3 are used, the expected power flow signing would be opposite to
that shown above.
In the event of any uncertainty, check the phase angle of the phase currents with respect to their phase voltage.
P64x-TM-EN-4.1 475
11 FINAL CHECKS
1. Remove all test leads and temporary shorting leads.
2. If you have had to disconnect any of the external wiring in order to perform the wiring verification tests,
replace all wiring, fuses and links in accordance with the relevant external connection or scheme diagram.
3. The settings applied should be carefully checked against the required application-specific settings to ensure
that they are correct, and have not been mistakenly altered during testing.
4. Ensure that all protection elements required have been set to Enabled in the CONFIGURATION column.
5. Ensure that the IED has been restored to service by checking that the Test Mode cell in the COMMISSION
TESTS column is set to Disabled.
6. If the IED is in a new installation or the circuit breaker has just been maintained, the circuit breaker
maintenance and current counters should be zero. These counters can be reset using the Reset All Values
cell. If the required access level is not active, the device will prompt for a password to be entered so that the
setting change can be made.
7. If the menu language has been changed to allow accurate testing it should be restored to the customer’s
preferred language.
8. If a P991/MMLG test block is installed, remove the P992/MMLB test plug and replace the cover so that the
protection is put into service.
9. Ensure that all event records, fault records, disturbance records, alarms and LEDs and communications
statistics have been reset.
Note:
Remember to restore the language setting to the customer’s preferred language on completion.
476 P64x-TM-EN-4.1
CHAPTER 20
MAINTENANCE AND TROUBLESHOOTING

Chapter 20 - Maintenance and Troubleshooting P64x
478 P64x-TM-EN-4.1
P64x Chapter 20 - Maintenance and Troubleshooting
1 CHAPTER OVERVIEW
The Maintenance and Troubleshooting chapter provides details of how to maintain and troubleshoot products
based on the Px4x and P40Agile platforms. Always follow the warning signs in this chapter. Failure to do so may
result injury or defective equipment.
Caution:
contents of the Safety Section or the Safety Guide SFTY/4LM and the ratings on the
The troubleshooting part of the chapter allows an error condition on the IED to be identified so that appropriate
corrective action can be taken.
If the device develops a fault, it is usually possible to identify which module needs replacing. It is not possible to
perform an on-site repair to a faulty module.
If you return a faulty unit or module to the manufacturer or one of their approved service centres, you should
include a completed copy of the Repair or Modification Return Authorization (RMA) form.
Maintenance 480
Troubleshooting 488
Repair and Modification Procedure 492
P64x-TM-EN-4.1 479
2 MAINTENANCE
2.1 MAINTENANCE CHECKS

In view of the critical nature of the application, General Electric products should be checked at regular intervals to
confirm they are operating correctly. General Electric products are designed for a life in excess of 20 years.
The devices are self-supervising and so require less maintenance than earlier designs of protection devices. Most
problems will result in an alarm, indicating that remedial action should be taken. However, some periodic tests
should be carried out to ensure that they are functioning correctly and that the external wiring is intact. It is the
responsibility of the customer to define the interval between maintenance periods. If your organisation has a
Preventative Maintenance Policy, the recommended product checks should be included in the regular program.
Maintenance periods depend on many factors, such as:
● The operating environment
● The accessibility of the site
● The amount of available manpower
● The importance of the installation in the power system
● The consequences of failure
Although some functionality checks can be performed from a remote location, these are predominantly restricted
to checking that the unit is measuring the applied currents and voltages accurately, and checking the circuit
breaker maintenance counters. For this reason, maintenance checks should also be performed locally at the
substation.
Caution:
contents of the Safety Section or the Safety Guide SFTY/4LM and the ratings on the
2.1.1 ALARMS
First check the alarm status LED to see if any alarm conditions exist. If so, press the Read key repeatedly to step
through the alarms.
After dealing with any problems, clear the alarms. This will clear the relevant LEDs.
2.1.2 OPTO-ISOLATORS
Check the opto-inputs by repeating the commissioning test detailed in the Commissioning chapter.
2.1.3 OUTPUT RELAYS

Check the output relays by repeating the commissioning test detailed in the Commissioning chapter.
2.1.4 MEASUREMENT ACCURACY

If the power system is energised, the measured values can be compared with known system values to check that
they are in the expected range. If they are within a set range, this indicates that the A/D conversion and the
calculations are being performed correctly. Suitable test methods can be found in Commissioning chapter.
Alternatively, the measured values can be checked against known values injected into the device using the test
block, (if fitted) or injected directly into the device's terminals. Suitable test methods can be found in the
Commissioning chapter. These tests will prove the calibration accuracy is being maintained.
480 P64x-TM-EN-4.1
2.2 REPLACING THE DEVICE

If your product should develop a fault while in service, depending on the nature of the fault, the watchdog
contacts will change state and an alarm condition will be flagged. In the case of a fault, you can replace either the
complete device or just the faulty PCB, identified by the in-built diagnostic software.
If possible you should replace the complete device, as this reduces the chance of damage due to electrostatic
discharge and also eliminates the risk of fitting an incompatible replacement PCB. However, we understand it may
be difficult to remove an installed product and you may be forced to replace the faulty PCB on-site. The case and
rear terminal blocks are designed to allow removal of the complete device, without disconnecting the scheme
wiring.
Caution:
Replacing PCBs requires the correct on-site environment (clean and dry) as well as
suitably trained personnel.
Caution:
If the repair is not performed by an approved service centre, the warranty will be
invalidated.
Caution:
Before carrying out any work on the equipment, you should be familiar with the
contents of the Safety Information section of this guide or the Safety Guide SFTY/4LM,
as well as the ratings on the equipment’s rating label. This should ensure that no
damage is caused by incorrect handling of the electronic components.
Warning:
Before working at the rear of the device, isolate all voltage and current supplying it.
Note:
The current transformer inputs are equipped with integral shorting switches which will close for safety reasons, when the
terminal block is removed.
To replace the complete device:

1. Carefully disconnect the cables not connected to the terminal blocks (e.g. IRIG-B, fibre optic cables, earth),
as appropriate, from the rear of the device.
2. Remove the terminal block screws using a magnetic screwdriver to minimise the risk of losing the screws or
leaving them in the terminal block.
3. Without exerting excessive force or damaging the scheme wiring, pull the terminal blocks away from their
internal connectors.
4. Remove the terminal block screws that fasten the device to the panel and rack. These are the screws with
the larger diameter heads that are accessible when the access covers are fitted and open.
5. Withdraw the device from the panel and rack. Take care, as the device will be heavy due to the internal
transformers.
6. To reinstall the device, follow the above instructions in reverse, ensuring that each terminal block is
relocated in the correct position and the chassis ground, IRIG-B and fibre optic connections are replaced.
The terminal blocks are labelled alphabetically with ‘A’ on the left hand side when viewed from the rear.
Once the device has been reinstalled, it should be re-commissioned as set out in the Commissioning chapter.
P64x-TM-EN-4.1 481
Caution:
If the top and bottom access covers have been removed, some more screws with
smaller diameter heads are made accessible. Do NOT remove these screws, as they
secure the front panel to the device.
Note:
There are four possible types of terminal block: RTD/CLIO input, heavy duty, medium duty, and MiDOS. The terminal blocks are
fastened to the rear panel with slotted or cross-head screws depending on the type of terminal block. Not all terminal block
types are present on all products.
Figure 190: Possible terminal block types
2.3 REPAIRING THE DEVICE

If your product should develop a fault while in service, depending on the nature of the fault, the watchdog
contacts will change state and an alarm condition will be flagged. In the case of a fault, either the complete unit or
just the faulty PCB, identified by the in-built diagnostic software, should be replaced.
Replacement of printed circuit boards and other internal components must be undertaken by approved Service
Centres. Failure to obtain the authorization of after-sales engineers prior to commencing work may invalidate the
product warranty.
We recommend that you entrust any repairs to Automation Support teams, which are available world-wide.
2.4 REMOVING THE FRONT PANEL
Warning:
Before removing the front panel to replace a PCB, you must first remove the auxiliary
power supply and wait 5 seconds for the internal capacitors to discharge. You should
also isolate voltage and current transformer connections and trip circuit.
482 P64x-TM-EN-4.1
Caution:
Before removing the front panel, you should be familiar with the contents of the Safety
Information section of this guide or the Safety Guide SFTY/4LM, as well as the ratings
on the equipment’s rating label.
To remove the front panel:

1. Open the top and bottom access covers. You must open the hinged access covers by more than 90° before
they can be removed.
2. If fitted, remove the transparent secondary front cover.
3. Apply outward pressure to the middle of the access covers to bow them and disengage the hinge lug, so the
access cover can be removed. The screws that fasten the front panel to the case are now accessible.
4. Undo and remove the screws. The 40TE case has four cross-head screws fastening the front panel to the
case, one in each corner, in recessed holes. The 60TE/80TE cases have an additional two screws, one
midway along each of the top and bottom edges of the front plate.
5. When the screws have been removed, pull the complete front panel forward to separate it from the metal
case. The front panel is connected to the rest of the circuitry by a 64-way ribbon cable.
6. The ribbon cable is fastened to the front panel using an IDC connector; a socket on the cable and a plug
with locking latches on the front panel. Gently push the two locking latches outwards which eject the
connector socket slightly. Remove the socket from the plug to disconnect the front panel.
Caution:
Do not remove the screws with the larger diameter heads which are accessible when
the access covers are fitted and open. These screws hold the relay in its mounting
(panel or cubicle).
Caution:
The internal circuitry is now exposed and is not protected against electrostatic
discharge and dust ingress. Therefore ESD precautions and clean working conditions
must be maintained at all times.
2.5 REPLACING PCBS

1. To replace any of the PCBs, first remove the front panel.
2. Once the front panel has been removed, the PCBs are accessible. The numbers above the case outline
identify the guide slot reference for each printed circuit board. Each printed circuit board has a label stating
the corresponding guide slot number to ensure correct relocation after removal. To serve as a reminder of
the slot numbering there is a label on the rear of the front panel metallic screen.
3. Remove the 64-way ribbon cable from the PCB that needs replacing
4. Remove the PCB in accordance with the board-specific instructions detailed later in this section.
Note:
To ensure compatibility, always replace a faulty PCB with one of an identical part number.
2.5.1 REPLACING THE MAIN PROCESSOR BOARD

The main processor board is situated in the front panel. This board contains application-specific settings in its non-
volatile memory. You may wish to take a backup copy of these settings. This could save time in the re-
commissioning process.
P64x-TM-EN-4.1 483
To replace the main processor board:

1. Remove front panel.
2. Place the front panel with the user interface face down and remove the six screws from the metallic screen,
as shown in the figure below. Remove the metal plate.
3. Remove the screws that hold the main processor board in position.
4. Carefully disconnect the ribbon cable. Take care as this could easily be damaged by excessive twisting.
5. Replace the main processor board
6. Reassemble the front panel using the reverse procedure. Make sure the ribbon cable is reconnected to the
main processor board and that all eight screws are refitted.
7. Refit the front panel.
8. Refit and close the access covers then press the hinge assistance T-pieces so they click back into the front
panel moulding.
9. Once the unit has been reassembled, carry out the standard commissioning procedure as defined in the
Commissioning chapter.
Note:
After replacing the main processor board, all the settings required for the application need to be re-entered. This may be done
either manually or by downloading a settings file.
V01601
Figure 191: Front panel assembly
2.5.2 REPLACEMENT OF COMMUNICATIONS BOARDS

Most products will have at least one communications board of some sort fitted. There are several different boards
available offering various functionality, depending on the application. Some products may even be fitted two
boards of different types.
To replace a faulty communications board:
2. Disconnect all connections at the rear.
3. The board is secured in the relay case by two screws, one at the top and another at the bottom. Remove
these screws carefully as they are not captive in the rear panel.
4. Gently pull the communications board forward and out of the case.
5. Before fitting the replacement PCB check that the number on the round label next to the front edge of the
PCB matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write the
correct slot number on the label.
484 P64x-TM-EN-4.1
6. Fit the replacement PCB carefully into the correct slot. Make sure it is pushed fully back and that the
securing screws are refitted.
7. Reconnect all connections at the rear.
panel moulding.
10. Once the unit has been reassembled, commission it according to the Commissioning chapter.
2.5.3 REPLACEMENT OF THE INPUT MODULE

Depending on the product, the input module consists of two or three boards fastened together and is contained
within a metal housing. One board contains the transformers and one contains the analogue to digital conversion
and processing electronics. Some devices have an additional auxiliary transformer contained on a third board.
To replace an input module:
2. The module is secured in the case by two screws on its right-hand side, accessible from the front, as shown
below. Move these screws carefully as they are not captive in the front plate of the module.
3. On the right-hand side of the module there is a small metal tab which brings out a handle (on some
modules there is also a tab on the left). Grasp the handle(s) and pull the module firmly forward, away from
the rear terminal blocks. A reasonable amount of force is needed due to the friction between the contacts of
the terminal blocks.
4. Remove the module from the case. The module may be heavy, because it contains the input voltage and
current transformers.
5. Slot in the replacement module and push it fully back onto the rear terminal blocks. To check that the
module is fully inserted, make sure the v-shaped cut-out in the bottom plate of the case is fully visible.
6. Refit the securing screws.
panel moulding.
Caution:
With non-mounted IEDs, the case needs to be held firmly while the module is
withdrawn. Withdraw the input module with care as it suddenly comes loose once the
friction of the terminal blocks is overcome.
Note:
If individual boards within the input module are replaced, recalibration will be necessary. We therefore recommend
replacement of the complete module to avoid on-site recalibration.
2.5.4 REPLACEMENT OF THE POWER SUPPLY BOARD
Caution:
Before removing the front panel, you should be familiar with the contents of the Safety
Information section of this guide or the Safety Guide SFTY/4LM, as well as the ratings
on the equipment’s rating label.
P64x-TM-EN-4.1 485
The power supply board is fastened to an output relay board with push fit nylon pillars. This doubled-up board is
secured on the extreme left hand side, looking from the front of the unit.
2. Pull the power supply module forward, away from the rear terminal blocks and out of the case. A
reasonable amount of force is needed due to the friction between the contacts of the terminal blocks.
3. Separate the boards by pulling them apart carefully. The power supply board is the one with two large
electrolytic capacitors.
4. Before reassembling the module, check that the number on the round label next to the front edge of the
PCB matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write the
correct slot number on the label
5. Reassemble the module with a replacement PCB. Push the inter-board connectors firmly together. Fit the
four push fit nylon pillars securely in their respective holes in each PCB.
6. Slot the power supply module back into the housing. Push it fully back onto the rear terminal blocks.
panel moulding.
2.5.5 REPLACEMENT OF THE I/O BOARDS

There are several different types of I/O boards, which can be used, depending on the product and application.
Some boards have opto-inputs, some have relay outputs and others have a mixture of both.
2. Gently pull the board forward and out of the case
3. If replacing the I/O board, make sure the setting of the link above IDC connector on the replacement board
is the same as the one being replaced.
4. Before fitting the replacement board check the number on the round label next to the front edge of the
board matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write
the correct slot number on the label.
5. Carefully slide the replacement board into the appropriate slot, ensuring that it is pushed fully back onto the
rear terminal blocks.
7. Refit and close the access covers then press at the hinge assistance T-pieces so they click back into the
front panel moulding.
2.6 RECALIBRATION
Recalibration is not needed when a PCB is replaced, unless it is one of the boards in the input module. If any of the
boards in the input module is replaced, the unit must be recalibrated.
Although recalibration is needed when a board inside the input module is replaced, it is not needed if the input
module is replaced in its entirety.
Although it is possible to carry out recalibration on site, this requires special test equipment and software. We
therefore recommend that the work be carried out by the manufacturer, or entrusted to an approved service
centre.
486 P64x-TM-EN-4.1
2.7 CLEANING
Warning:
Before cleaning the device, ensure that all AC and DC supplies and transformer
connections are isolated, to prevent any chance of an electric shock while cleaning.
Only clean the equipment with a lint-free cloth dampened with clean water. Do not use detergents, solvents or
abrasive cleaners as they may damage the product's surfaces and leave a conductive residue.
P64x-TM-EN-4.1 487
3 TROUBLESHOOTING
3.1 SELF-DIAGNOSTIC SOFTWARE

The device includes several self-monitoring functions to check the operation of its hardware and software while in
service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.
If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.
The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot-
up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.
3.2 POWER-UP ERRORS

If the IED does not appear to power up, use the following to determine whether the fault is in the external wiring,
auxiliary fuse, IED power supply module or IED front panel.
Test Check Action
Measure the auxiliary voltage on terminals 1 and 2.
Verify the voltage level and polarity against the rating If the auxiliary voltage is correct, go to test 2. Otherwise check the wiring
1
label on the front. and fuses in the auxiliary supply.
Terminal 1 is –dc, 2 is +dc
If the LEDs and LCD backlight switch on, or the contact closes and no error
Check the LEDs and LCD backlight switch on at code is displayed, the error is probably on the main processor board in the
2 power-up. Also check the N/O (normally open) front panel.
watchdog contact for closing. If the LEDs and LCD backlight do not switch on and the contact does not
close, go to test 3.
If there is no field voltage, the fault is probably in the IED power supply
3 Check the output (nominally 48 V DC)
module.
3.3 ERROR MESSAGE OR CODE ON POWER-UP

The IED performs a self-test during power-up. If it detects an error, a message appears on the LCD and the power-
up sequence stops. If the error occurs when the IED application software is running, a maintenance record is
created and the device reboots.
Test Check Action
If the IED locks up and displays an error code permanently, go to test 2.
Is an error message or code permanently displayed
1 If the IED prompts for user input, go to test 4.
during power up?
If the IED reboots automatically, go to test 5.
Record whether the same error code is displayed when the IED is
Record displayed error, and then remove and re-apply rebooted. If no error code is displayed, contact the local service centre
2
IED auxiliary supply. stating the error code and IED information. If the same code is
displayed, go to test 3.
488 P64x-TM-EN-4.1
Test Check Action

Error Code Identification
The following text messages (in English) are displayed if a
These messages indicate that a problem has been detected on the IED’s
fundamental problem is detected, preventing the system
main processor board in the front panel.
from booting:
Bus Fail – address lines
3 SRAM Fail – data lines
FLASH Fail format error
FLASH Fail checksum
Code Verify Fail
The following hex error codes relate to errors detected in
specific IED modules:
3.1 0c140005/0c0d0000 Input Module (including opto-isolated inputs)
3.2 0c140006/0c0e0000 Output IED Cards
Other error codes relate to hardware or software problems on the main
3.3 The last four digits provide details on the actual error.
processor board. Contact with details of the problem for a full analysis.
The IED displays a message for corrupt settings and The power-up tests have detected corrupted IED settings. Restore the
4 prompts for the default values to be restored for the default settings to allow the power-up to complete, and then reapply
affected settings. the application-specific settings.
Error 0x0E080000, programmable scheme logic error due to excessive
execution time. If the IED powers up successfully, check the
The IED resets when the power-up is complete. A record
5 programmable logic for feedback paths.
error code is displayed
Other error codes relate to software errors on the main processor
board.
3.4 OUT OF SERVICE LED ON AT POWER-UP
Test Check Action

Using the IED menu, confirm the Commission Test or Test If the setting is Enabled, disable the test mode and make sure the Out of
1
Mode setting is Enabled. If it is not Enabled, go to test 2. Service LED is OFF.
Check for the H/W Verify Fail maintenance record. This indicates a
discrepancy between the IED model number and the hardware. Examine
Select the VIEW RECORDS column then view the last
2 the Maint Data; cell. This indicates the causes of the failure using bit
maintenance record from the menu.
fields:
Bit Meaning
The application type field in the model number does not
0
match the software ID
The application field in the model number does not match
1
the software ID
The variant 1 field in the model number does not match the
2
software ID
The variant 2 field in the model number does not match the
3
software ID
The protocol field in the model number does not match the
4
software ID
The language field in the model number does not match the
5
software ID
The VT type field in the model number is incorrect (110 V VTs
6
fitted)
The VT type field in the model number is incorrect (440 V VTs
7
fitted)
The VT type field in the model number is incorrect (no VTs
8
fitted)
P64x-TM-EN-4.1 489
3.5 ERROR CODE DURING OPERATION

The IED performs continuous self-checking. If the IED detects an error it displays an error message, logs a
maintenance record and after a short delay resets itself. A permanent problem (for example due to a hardware
fault) is usually detected in the power-up sequence. In this case the IED displays an error code and halts. If the
problem was transient, the IED reboots correctly and continues operation. By examining the maintenance record
logged, the nature of the detected fault can be determined.
3.6 MAL-OPERATION DURING TESTING
3.6.1 FAILURE OF OUTPUT CONTACTS

An apparent failure of the relay output contacts can be caused by the configuration. Perform the following tests to
identify the real cause of the failure. The self-tests verify that the coils of the output relay contacts have been
energized. An error is displayed if there is a fault in the output relay board.
Test Check Action
If this LED is ON, the relay may be in test mode or the protection has
1 Is the Out of Service LED ON?
been disabled due to a hardware verify error.
Examine the Contact status in the Commissioning If the relevant bits of the contact status are operated, go to test 4; if not,
2
section of the menu. go to test 3.
If the protection element does not operate, check the test is correctly
Examine the fault record or use the test port to check the applied.
3
protection element is operating correctly. If the protection element operates, check the programmable logic to
make sure the protection element is correctly mapped to the contacts.
Using the Commissioning or Test mode function, apply a If the output relay operates, the problem must be in the external wiring
test pattern to the relevant relay output contacts. to the relay. If the output relay does not operate the output relay
4 Consult the correct external connection diagram and use contacts may have failed (the self-tests verify that the relay coil is being
a continuity tester at the rear of the relay to check the energized). Ensure the closed resistance is not too high for the continuity
relay output contacts operate. tester to detect.
3.6.2 FAILURE OF OPTO-INPUTS

The opto-isolated inputs are mapped onto the IED's internal DDB signals using the programmable scheme logic. If
an input is not recognised by the scheme logic, use the Opto I/P Status cell in the COMMISSION TESTS column to
check whether the problem is in the opto-input itself, or the mapping of its signal to the scheme logic functions.
If the device does not correctly read the opto-input state, test the applied signal. Verify the connections to the
opto-input using the wiring diagram and the nominal voltage settings in the OPTO CONFIG column. To do this:
1. Select the nominal voltage for all opto-inputs by selecting one of the five standard ratings in the Global
Nominal V cell.
2. Select Custom to set each opto-input individually to a nominal voltage.
3. Using a voltmeter, check that the voltage on its input terminals is greater than the minimum pick-up level
(See the Technical Specifications chapter for opto pick-up levels).
If the signal is correctly applied, this indicates failure of an opto-input, which may be situated on standalone opto-
input board, or on an opto-input board that is part of the input module. Separate opto-input boards can simply be
replaced. If, however, the faulty opto-input board is part of the input module, the complete input module should be
replaced. This is because the analogue input module cannot be individually replaced without dismantling the
module and recalibration of the IED.
490 P64x-TM-EN-4.1
3.6.3 INCORRECT ANALOGUE SIGNALS

If the measured analogue quantities do not seem correct, use the measurement function to determine the type of
problem. The measurements can be configured in primary or secondary terms.
1. Compare the displayed measured values with the actual magnitudes at the terminals.
2. Check the correct terminals are used.
3. Check the CT and VT ratios set are correct.
4. Check the phase displacement to confirm the inputs are correctly connected.
3.7 PSL EDITOR TROUBLESHOOTING

A failure to open a connection could be due to one or more of the following:
● The IED address is not valid (this address is always 1 for the front port)
● Password in not valid
● Communication set-up (COM port, Baud rate, or Framing) is not correct
● Transaction values are not suitable for the IED or the type of connection
● The connection cable is not wired correctly or broken
● The option switches on any protocol converter used may be incorrectly set
3.7.1 DIAGRAM RECONSTRUCTION

Although a scheme can be extracted from an IED, a facility is provided to recover a scheme if the original file is
unobtainable.
A recovered scheme is logically correct but much of the original graphical information is lost. Many signals are
drawn in a vertical line down the left side of the canvas. Links are drawn orthogonally using the shortest path from
A to B. Any annotation added to the original diagram such as titles and notes are lost.
Sometimes a gate type does not appear as expected. For example, a single-input AND gate in the original scheme
appears as an OR gate when uploaded. Programmable gates with an inputs-to-trigger value of 1 also appear as
OR gates
3.7.2 PSL VERSION CHECK

The PSL is saved with a version reference, time stamp and CRC check (Cyclic Redundancy Check). This gives a
visual check whether the default PSL is in place or whether a new application has been downloaded.
P64x-TM-EN-4.1 491
4 REPAIR AND MODIFICATION PROCEDURE

Please follow these steps to return an Automation product to us:
1. Get the Repair and Modification Return Authorization (RMA) form
An electronic version of the RMA form is available from the following:
[email protected]
2. Fill in the RMA form
Fill in only the white part of the form.
Please ensure that all fields marked (M) are completed such as:
○ Equipment model
○ Model No. and Serial No.
○ Description of failure or modification required (please be specific)
○ Value for customs (in case the product requires export)
○ Delivery and invoice addresses
○ Contact details
3. Send the RMA form to your local contact
For a list of local service contacts worldwide, email us at:
[email protected]
4. The local service contact provides the shipping information
Your local service contact provides you with all the information needed to ship the product:
○ Pricing details
○ RMA number
○ Repair centre address
If required, an acceptance of the quote must be delivered before going to the next stage.
5. Send the product to the repair centre
○ Address the shipment to the repair centre specified by your local contact
○ Make sure all items are packaged in an anti-static bag and foam protection
○ Make sure a copy of the import invoice is attached with the returned unit
○ Make sure a copy of the RMA form is attached with the returned unit
○ E-mail or fax a copy of the import invoice and airway bill document to your local contact.
492 P64x-TM-EN-4.1
CHAPTER 21
TECHNICAL SPECIFICATIONS
Chapter 21 - Technical Specifications P64x
494 P64x-TM-EN-4.1
P64x Chapter 21 - Technical Specifications
1 CHAPTER OVERVIEW
This chapter describes the technical specifications of the product.
Interfaces 496
Performance of Transformer Differential Protection and Monitoring Functions 499
Performance of Current Protection Functions 501
Performance of Voltage Protection Functions 504
Performance of Frequency Protection Functions 505
Performance of Monitoring and Control Functions 506
Measurements and Recording 508
Regulatory Compliance 510
Mechanical Specifications 511
Ratings 512
Power Supply 513
Input / Output Connections 515
Environmental Conditions 517
Type Tests 518
Electromagnetic Compatibility 519
P64x-TM-EN-4.1 495
2 INTERFACES
2.1 FRONT USB PORT
Front USB port

Use For local connection to laptop for configuration purposes and firmware downloads
Connector USB type B
Isolation Isolation to ELV level
Constraints Maximum cable length 5 m
2.2 REAR SERIAL PORT 1
Rear serial port 1 (RP1)

Use For SCADA communications (multi-drop)
Standard EIA(RS)485, K-bus
Connector General purpose block, M4 screws (2 wire)
Cable Screened twisted pair (STP)
Supported Protocols * Courier, IEC-60870-5-103, DNP3.0, MODBUS
Isolation Isolation to SELV level
* Not all models support all protocols - see ordering options
2.3 FIBRE REAR SERIAL PORT 1
Optional fibre rear serial port (RP1)

Main Use Serial SCADA communications over fibre
Connector IEC 874-10 BFOC 2.5 –(ST®) (1 each for Tx and Rx)
Fibre type Multimode 50/125 µm or 62.5/125 µm
Supported Protocols Courier, IEC870-5-103, DNP 3.0, MODBUS
Wavelength 850 nm
2.4 REAR SERIAL PORT 2
Optional rear serial port (RP2)

Use For SCADA communications (multi-drop)
Standard EIA(RS)485, K-bus, EIA(RS)232
Designation SK4
Connector 9 pin D-type female connector
Cable Screened twisted pair (STP)
Supported Protocols Courier
Constraints Maximum cable length 1000 m for RS485 and K-bus, 15 m for RS232
496 P64x-TM-EN-4.1
2.5 IRIG-B (DEMODULATED)
IRIG-B Interface (Demodulated)

Use External clock synchronisation signal
Standard IRIG 200-98 format B00X
Connector BNC
Cable type 50 ohm coaxial
Input signal TTL level
Input impedance 10 k ohm at dc
Accuracy +/- 1 ms
2.6 IRIG-B (MODULATED)
IRIG-B Interface (Modulated)

Use External clock synchronisation signal
Standard IRIG 200-98 format B12X
Connector BNC
Cable type 50 ohm coaxial
Input signal peak to peak, 200 mV to 20 mV
Input impedance 6 k ohm at 1000 Hz
Accuracy +/- 1 ms
2.7 REAR ETHERNET PORT COPPER
Rear Ethernet port using CAT 5/6/7 wiring

Main Use Substation Ethernet communications
Standard IEEE 802.3 10BaseT/100BaseTX
Connector RJ45
Cable type Screened twisted pair (STP)
Isolation 1.5 kV
Supported Protocols IEC 61850, DNP3.0 OE
2.8 REAR ETHERNET PORT FIBRE
Rear Ethernet port using fibre-optic cabling

Main Use Substation Ethernet communications
Connector IEC 874-10 BFOC 2.5 –(ST®) (1 each for Tx and Rx)
Standard IEEE 802.3 100 BaseFX
Fibre type Multimode 50/125 µm or 62.5/125 µm
Supported Protocols IEC 61850, DNP3.0
P64x-TM-EN-4.1 497
Rear Ethernet port using fibre-optic cabling

Rapid spanning tree protocol (RSTP)
Self-healing protocol (SHP)
Optional Redundancy Protocols Supported
Dual homing protocol (DHP)
Parallel Redundancy Protocol (PRP)
Wavelength 1300 nm
2.8.1 100 BASE FX RECEIVER CHARACTERISTICS
Parameter Sym Min. Typ. Max. Unit

Input Optical Power Minimum at
PIN Min. (W) -33.5 –31 dBm avg.
Window Edge
Input Optical Power Minimum at
PIN Min. (C) -34.5 -31.8 Bm avg.
Eye Center
Input Optical Power Maximum PIN Max. -14 -11.8 dBm avg.
Conditions: TA = 0°C to 70°C
2.8.2 100 BASE FX TRANSMITTER CHARACTERISTICS
Parameter Sym Min. Typ. Max. Unit

Output Optical Power BOL 62.5/125 µm -19
PO -16.8 -14 dBm avg.
NA = 0.275 Fibre EOL -20
Output Optical Power BOL 50/125 µm -22.5
PO -20.3 -14 dBm avg.
NA = 0.20 Fibre EOL -23.5
10 %
Optical Extinction Ratio
-10 dB
Output Optical Power at Logic "0" State PO -45 dBm avg.
Conditions: TA = 0°C to 70°C
498 P64x-TM-EN-4.1
3 PERFORMANCE OF TRANSFORMER DIFFERENTIAL PROTECTION AND

MONITORING FUNCTIONS
3.1 TRANSFORMER DIFFERENTIAL PROTECTION
Accuracy
Pick-up Formula +/-5% or 20 mA, whichever is greater
Drop-off 0.95 x formula +/- 5%
Pick-up and drop-off repeatability < 1%
Low set differential element operate time (High
< 33 ms (currents applied at 1.2x pickup level or higher)
Break contact)
Low set differential element operate time (Standard
< 36 ms (currents applied at 1.2x pickup level or higher)
Contact)
High set 1 differential element operate time
< 15 ms (currents applied at 2x pickup level or higher)
(Transient Bias disabled)
High set 2 differential element operate time
< 25 ms (currents applied at 2x pickup level or higher)
(High Break contact)
< 33 ms, whichever is greater (currents applied at 1.2x pickup level or
DT operate time (High Break contact)
higher
< 36 ms, whichever is greater (currents applied at 1.2x pickup level or
DT operate time (Standard contact)
higher
Operate time repeatability < 2 ms
Disengagement time < 15 ms
2nd harmonic blocking pick-up Setting +/-5% of setting
2nd harmonic blocking drop-off 0.95 x setting +/-5%
5th harmonic blocking pick-up Setting +/-5% of setting
5th harmonic blocking drop-off 0.95 x setting +/-5%
3.2 MATCHING FACTORS
Matching factor for typical setting

CT Type Max. sensitivity Permitted Matching Factor range
Is1 = 0.2 pu
Standard 43 mA 0.05 - 15 4.65
Sensitive 13 mA 0.05 - 20 15.38
3.3 CIRCUITRY FAULT ALARM
Pick-up Formula +/-5%

DT operate < 26 ms (currents applied at 2.5x pickup level or higher)
P64x-TM-EN-4.1 499
Timer +/- 2% or 50 ms, whichever is greater
3.4 THROUGH FAULT MONITORING
Overcurrent pick-up Setting +/-5% or 50 mA, whichever greater

Overcurrent drop-off 0.95 x setting +/- 5% or 50 mA, whichever is greater
Heating pickup (I2t) Setting +/-2% or 5 A2s, whichever greater
3.5 THERMAL OVERLOAD
Expected pick-up time +/-5% or 50 ms, whichever greater.

Hotspot pick-up (Expected pick-up time is the time required to reach the temperature
setting)
Hotspot operate DT +/-5% or <= 50 ms, whichever greater
Top Oil pick-up Expected pick-up time +/-5% or 50 ms, whichever greater
Top Oil operate DT +/-5% or <= 50 ms, whichever greater
Repeatability < 2.5%
3.6 LOW IMPEDANCE RESTRICTED EARTH FAULT

Operate time < 45 ms (currents applied at 2x pickup level or higher)
3.7 HIGH IMPEDANCE RESTRICTED EARTH FAULT

Operate time < 30 ms
500 P64x-TM-EN-4.1
4 PERFORMANCE OF CURRENT PROTECTION FUNCTIONS
4.1 TRANSIENT OVERREACH AND OVERSHOOT
Accuracy
Additional tolerance due to increasing X/R ratios +/-5% over the X/R ratio of 1 to 120
Overshoot of overcurrent elements < 40 ms
4.2 THREE-PHASE OVERCURRENT PROTECTION
Accuracy
IDMT pick-up 1.05 x Setting +/-5%
DT pick-up Setting +/-5% or 20 mA, whichever is greater
Drop-off (IDMT and DT) 0.95 x setting +/-5% or 20 mA, whichever is greater
IDMT operate +/-5% of expected operating time or 40 ms, whichever is greater
IEEE reset +/-5% or 50 ms, whichever is greater
DT operate +/-2% of setting or 50 ms, whichever is greater
DT reset Setting +/-5%
Characteristic UK IEC 60255-3 1998
Characteristic US IEEE C37.112 1996
4.2.1 THREE-PHASE OVERCURRENT DIRECTIONAL PARAMETERS
Accuracy
Directional boundary pickup (RCA +/-90%) +/-2°
Directional boundary hysteresis < 3°
Directional boundary repeatability <1%
Directional voltage pick-up +/-5% or 50 mV, whichever is greater
Directional voltage drop-off 0.95 x setting +/-5% or 50 mV, whichever is greater
Directional voltage repeatability <3%
4.3 VOLTAGE DEPENDENT OVERCURRENT PROTECTION
Accuracy
Voltage threshold pick-up Setting +/- 5%
Voltage threshold drop-off 1.05 x setting +/- 5%
Current threshold pick-up Formula +/- 5%
Current threshold drop-off 0.95 x formula +/- 5%
4.4 EARTH FAULT PROTECTION
Accuracy
IDMT pick-up 1.05 x Setting +/-5%
P64x-TM-EN-4.1 501
Accuracy
DT pick-up Setting +/-5%, or 20 mA, whichever is greater
Measured drop-off (IDMT and DT) 0.95 x setting +/-5% or 20 mA, whichever is greater
Derived drop-off (IDMT and DT) 0.9 x setting +/-5% or 20 mA, whichever is greater
IDMT Operate +/-5% or 40 ms, whichever is greater*
IEEE reset +/-5% or 40 ms, whichever is greater
DT operate time +/-2% or 50 ms, whichever is greater
DT reset time +/- 5%
Note:
Reference conditions: TMS = 1, TD = 1, IN> = 1A, operating range = 2-16In
4.4.1 EARTH FAULT DIRECTIONAL PARAMETERS
Measured and Derived

Vpol pick-up Vpol +/-5% or 50 mV, whichever is greater
Vpol drop-off 0.95 x Vpol +/-5% or 50 mV, whichever is greater
Directional boundary pickup (RCA +/-90%) +/- 2°
Directional boundary repeatability < 1%
4.5 NEGATIVE SEQUENCE OVERCURRENT PROTECTION
Pick-up (IDMT and DT) Setting +/-5% or 20 mA, whichever is greater

Drop-off (IDMT and DT) 0.95 x Setting +/-5% or 20 mA, whichever is greater
DT operate +/- 2% or 60 ms, whichever is greater
4.5.1 NPSOC DIRECTIONAL PARAMETERS
Directional boundary pick-up (RCA +/-90%) +/-2°

Directional boundary repeatability < 2%
Vpol pickup Setting +/-5% or 50 mV, whichever is greater
Vpol drop-off 0,95 x setting +/-5% or 50 mV, whichever is greater
502 P64x-TM-EN-4.1
4.6 CIRCUIT BREAKER FAIL PROTECTION
I< Pick-up 1.1 X setting +/- 5% or 20 mA, whichever is greater

I< Drop-off Setting +/- 5% or 20 mA, whichever is greater
Timers +/- 2% or 50 ms, whichever is greater
Reset time < 15 ms (fully offset current waveform considered)
P64x-TM-EN-4.1 503
5 PERFORMANCE OF VOLTAGE PROTECTION FUNCTIONS
5.1 UNDERVOLTAGE PROTECTION (P643/5)
Pick-up (IDMT and DT) Setting +/- 5%

Drop-off (IDMT and DT) 1.02 x Setting +/-5%
Operate (IDMT and DT) +/- 2% or 50 ms, whichever is greater
Reset < 50 ms
Repeatability < 1%
5.2 OVERVOLTAGE PROTECTION
Pick-up (IDMT and DT) Setting +/- 5%

Operate (IDMT and DT) +/- 2% or 50 ms, whichever is greater
Reset < 50 ms
Repeatability < 1%
5.3 RESIDUAL OVERVOLTAGE PROTECTION (P643/5)
Pick-up (IDMT and DT) Setting +/- 5% or 50 mV, whichever is greater

IDMT operate +/- 2% or 55 ms, whichever is greater
DT operate +/- 2% or 70 ms or whichever is greater
Reset time < 50 ms
Pick-up and drop-off repeatability <1%
Timer repeatability < 10 ms
5.4 NEGATIVE SEQUENCE VOLTAGE PROTECTION
DT Pick-up Setting +/- 5%

DT Drop-off 0.95 x Setting +/-5%
+/- 2% or 50 ms, whichever is greater (accelerated mode)
DT operate
+/- 2% or 60 ms, whichever is greater (normal mode)
Disengagement time <35 ms
Operating time Repeatability < 5 ms
Operating threshold repeatability < 1%
504 P64x-TM-EN-4.1
6 PERFORMANCE OF FREQUENCY PROTECTION FUNCTIONS
6.1 OVERFREQUENCY PROTECTION
Pick-up Setting +/- 10 mHz

Drop-off Setting -25 mHz +/- 10 mHz
+/- 2% or 70 ms, whichever is greater (excluding frequency
DT operate
tracking time delay)
Repeatability < 1%
6.2 UNDERFREQUENCY PROTECTION
Pick-up Setting +/- 10 mHz

Drop-off Setting +25 mHz +/- 10 mHz
+/- 2% or 70 ms, whichever is greater (excluding frequency
DT Operate
tracking time delay)
Repeatability < 1%
6.3 OVERFLUXING PROTECTION
Pick-up Setting +/- 5%

Drop-off Setting -2% +/- 5%
Repeatability (operating threshold) < 1%
IDMT operate +/- 5% or 50 ms, whichever is greater
DT operate +/- 2% or 50 ms, whichever is greater
Instantaneous operation < 50 ms
Repeatability (operating times) < 10 ms
V / Hz measurement +/- 1%
Reset time +/- 2% or 50 ms, whichever is greater
P64x-TM-EN-4.1 505
7 PERFORMANCE OF MONITORING AND CONTROL FUNCTIONS
7.1 VOLTAGE TRANSFORMER SUPERVISION
VTS I> pick-up Setting +/- 5% or 50 mA, whichever is greater

VTS I> drop-off 0.9 x Setting +/- 5% or 50 mA, whichever is greater
VTS I2> pick-up Setting +/- 5% or 50 mA, whichever is greater
VTS I> drop-off 0.95 x Setting +/- 5% or 50 mA, whichever is greater
VTS V< pick-up (P642) 70V +/- 5%
VTS V< pick-up (P643/5) 10V +/- 5%
VTS V< drop-off (P642) 95V +/- 5%
VTS V< drop-off (P643/5) 30V +/- 5%
VTS V2> pick-up (P642/3/5) 10V +/- 5%
VTS V2> drop-off (P642/3/5) 9.5V +/- 5%
Fast block operation < 25 ms
Fast block reset < 30 ms
Time delay Setting +/- 2% or 50 ms, whichever is greater
7.2 CURRENT TRANSFORMER SUPERVISION
CTS I1 pick-up ratio Setting +/- 5% or 20 mA, whichever is greater

CTS I2/I1>1 pick-up ratio 0.95 x Setting +/- 5% or 20 mA, whichever is greater
CTS I2/I1>2 pick-up ratio 1.05 x setting +/- 5% or 20 mA, whichever is greater
CTS I1 drop-off ratio 0.95 x setting +/-5% or 20 mA, whichever is greater
CTS I2/I1>1 drop-off ratio Setting +/-5% or 20 mA, whichever is greater
CTS I2/I1>2 drop-off ratio Setting +/-5% or 20 mA, whichever is greater
Time delay operation Setting +/-2% or 50 ms, whichever is greater
CTS terminal block operation < 25 ms
CTS differential block operation < 30 ms
CTS reset time < 25 ms
CTS disengagement time < 30 ms
7.3 POLE DEAD PROTECTION
Current pick-up 50 mA +/- 20 mA

Current drop-off 55 mA +/- 20 mA
Voltage pick-up 10V +/- 5%
Voltage drop-off 30V +/- 5%
DT operate < 50 ms
506 P64x-TM-EN-4.1
7.4 PSL TIMERS
Output conditioner timer Setting +/- 2% or 50 ms, whichever is greater

Dwell conditioner timer Setting +/- 2% or 50 ms, whichever is greater
Pulse conditioner timer Setting +/- 2% or 50 ms, whichever is greater
P64x-TM-EN-4.1 507
8 MEASUREMENTS AND RECORDING
8.1 GENERAL
General Measurement Accuracy

General measurement accuracy Typically +/- 1%, but +/- 0.5% between 0.2 - 2 In/Vn
Phase 0° to 360° +/- 5.0%
Current (0.05 to 3 In) +/- 1.0% of reading, or 4mA (1A input), or 20mA (5A input)
Voltage (0.05 to 2 Vn) +/- 1.0% of reading
Frequency (5 to 70 Hz) +/- 0.025 Hz
Power (W) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading at unity power factor
Reactive power (Vars) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading at zero power factor
Apparent power (VA) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading
Energy (Wh) (0.2 to 2 Vn and 0.2 to 3 In) +/- 5.0% of reading at zero power factor
Energy (Varh) (0.2 to 2 Vn and 0.2 to 3) In +/- 5.0% of reading at zero power factor
8.2 DISTURBANCE RECORDS
Disturbance Records Measurement Accuracy

Minimum record duration 0.1 s
Maximum record duration 10.5 s
Minimum number of records at 10.5 seconds 8
Magnitude and relative phases accuracy +/- 5% of applied quantities
Duration accuracy +/- 2%
Trigger position accuracy +/- 2% (minimum Trigger 100 ms)
8.3 EVENT, FAULT AND MAINTENANCE RECORDS
Event, Fault & Maintenance Records

Record location Supercapacitor-backed memory
Viewing method Front panel display or Settings Application Software
Extraction method Extracted via the front USB port
Number of Event records Up to 512 time tagged event records (newest overwrites oldest)
Number of Fault Records Up to 5
Number of Maintenance Records Up to 10
Event time stamp resolution 1 ms
8.4 CURRENT LOOP INPUTS/OUTPUTS
CLIO
Current loop input accuracy +/- 1% of full scale
Current loop input drop-off under threshold Setting +/- 1% of full scale
Current loop input drop-off over threshold Setting +/- 1% of full scale
Current loop input sampling interval 50 ms
508 P64x-TM-EN-4.1
CLIO
20 Hz to 70 Hz: +/- 2% setting or 150 ms, whichever is greater
Current loop input DT operate time
5 Hz to 20 Hz: +/- 2% setting or 200 ms, whichever is greater
20 Hz to 70 Hz: < 200 ms, whichever is greater
Current loop input instantaneous operate time
5 Hz to 20 Hz: < 300 ms, whichever is greater
Current loop output conversion interval 50 mS
< 1.07 s (1 s refresh rate)
Current loop output latency
< 70 ms (0.5 cycle refresh rate)
Current loop output accuracy +/- 5% of full scale
Repeatability < 5%
< 4 kohms (0-1 mA)
Current loop input load resistance
< 300 ohms (0-10 mA / 0-20mA / 4-20mA)
Isolation between input channels and case/earth/other
2 kV RMS for 1 minute
circuits
10 V (0-1 mA / 0-10 mA)
Current loop output compliance voltage
8.8V (0-20 mA / 4-20 mA)
Current loop output open circuit voltage < 15V
P64x-TM-EN-4.1 509
9 REGULATORY COMPLIANCE
Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file.
9.1 EMC COMPLIANCE: 2014/30/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformity
assessment used to demonstrate compliance with the EMC directive.
9.2 LVD COMPLIANCE: 2014/35/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonized standard(s) or conformity
assessment used to demonstrate compliance with the LVD directive.
Safety related information, such as the installation I overvoltage category, pollution degree and operating
temperature ranges are specified in the Technical Data section of the relevant product documentation and/or on
the product labelling.
Unless otherwise stated in the Technical Data section of the relevant product documentation, the equipment is
intended for indoor use only. Where the equipment is required for use in an outdoor location, it must be mounted
in a specific cabinet or housing to provide the equipment with the appropriate level of protection from the
expected outdoor environment.
9.3 R&TTE COMPLIANCE: 2014/53/EU

Radio and Telecommunications Terminal Equipment (R&TTE) directive 2014/53/EU.
Conformity is demonstrated by compliance to both the EMC directive and the Low Voltage directive, to zero volts.
9.4 UL/CUL COMPLIANCE

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.
The relevant UL file number and ID is shown on the equipment.
510 P64x-TM-EN-4.1
10 MECHANICAL SPECIFICATIONS
10.1 PHYSICAL PARAMETERS
40TE
Case Types* 60TE
80TE
Weight (40TE case) 7 kg – 8 kg (depending on chosen options)
Weight (60TE case) 9 kg – 12 kg (depending on chosen options)
Weight (80TE case) 13 kg - 16 kg (depending on chosen options)
Dimensions in mm (w x h x l) (40TE case) W: 206.0 mm H: 177.0 mm D: 243.1 mm
Dimensions in mm (w x h x l) (60TE case) W: 309.6 mm H: 177.0 mm D: 243.1 mm
Dimensions in mm (w x h x l) (80TE case) W 413.2 mm H 177.0 mm D 243.1 mm
Mounting Panel, rack, or retrofit
Note:
*Case size is product dependent.
10.2 ENCLOSURE PROTECTION
Against dust and dripping water (front face) IP52 as per IEC 60529:1989/A2:2013
Protection against dust (whole case) IP50 as per IEC 60529:1989/A2:2013
Protection for sides of the case (safety) IP30 as per IEC 60529:1989/A2:2013
Protection for rear of the case (safety) IP10 as per IEC 60529:1989/A2:2013
10.3 MECHANICAL ROBUSTNESS
Vibration test per EN 60255-21-1:1998 Response: class 2, Endurance: class 2

Shock response: class 2, Shock withstand: class 1, Bump withstand:
Shock and bump immunity per EN 60255-21-2:1988
class 1
Seismic test per EN 60255-21-3: 1993 Class 2
10.4 TRANSIT PACKAGING PERFORMANCE
Primary packaging carton protection ISTA 1C

Vibration tests 3 orientations, 7 Hz, amplitude 5.3 mm, acceleration 1.05g
10 drops from 610 mm height on multiple carton faces, edges and
Drop tests
corners
P64x-TM-EN-4.1 511
11 RATINGS
11.1 AC MEASURING INPUTS
AC Measuring Inputs
Nominal frequency 50 Hz or 60 Hz (settable)
Operating range 45 to 65 Hz
Phase rotation ABC or CBA
11.2 CURRENT TRANSFORMER INPUTS

AC Current Inputs
Nominal current (In) 1A or 5A dual rated*
Nominal burden per phase < 0.01 VA at In
20 A (continuous operation)
AC current thermal withstand 150 A (for 10 s)
500 A (for 1 s)
Linearity (standard CT) Linear up to 64In (non-offset)
Linear up to 64In (for 1 A secondary and non-offset)
Linearity (sensitive CT)
Linear up to 32In (for 5 A secondary and non-offset)
Note:
* A single input is used for both 1A and 5A applications. 1 A or 5 A operation is determined by means of software in the
product’s database.
Note:
These specifications are applicable to all CTs.
11.3 VOLTAGE TRANSFORMER INPUTS
AC Voltage Inputs
Nominal voltage 100 V to 120 V
Nominal burden per phase < 0.06 VA at Vn
2 x Vn (continuous operation)
Thermal withstand
2.6 x Vn (for 10 seconds)
Linear up to 200 V (100/120 V supply)
Linearity
Linear up to 800 V (380/400 V supply)
512 P64x-TM-EN-4.1
12 POWER SUPPLY
12.1 AUXILIARY SUPPLY VOLTAGE
Cortec option (DC only)

24 to 48 V DC
Cortec option (rated for AC or DC operation)
48 to 110 V DC
Nominal operating range
40 to 100 V AC rms
110 to 250 V DC
100 to 240 V AC rms
Cortec option (DC only)
19 to 65 V DC
37 to 150 V DC
Maximum operating range
32 to 110 V AC rms
87 to 300 V DC
80 to 265 V AC rms
Frequency range for AC supply 45 to 65 Hz
Ripple <15% for a DC supply (compliant with IEC 60255-26:2013)
Power up time < 11 seconds
12.2 NOMINAL BURDEN
Quiescent burden 11 W
2nd rear communications port 1.25 W
Each relay output burden 0.13 W per output relay
Each opto-input burden (24 – 27 V) 0.065 W max
12.3 POWER SUPPLY INTERRUPTION
Standard IEC 60255-26:2013 (DC and AC)

20 ms at 24 V (half and full load)
24-48V DC SUPPLY
100% interruption without de-energising
20 ms at 37V (half and full load)
48-110V DC SUPPLY
100 ms at 72 V (half load)
100 ms at 85 V (full load)
P64x-TM-EN-4.1 513
110-250V DC SUPPLY
40-100V AC SUPPLY 50 ms at 32 V (half load)
100% voltage dip without de-energising 10 ms at 32 V (full load)
100-240V AC SUPPLY
50 ms at 80 V (full and half load)
100% voltage dip without de-energising
Note:
Maximum loading = all inputs/outputs energised.
Note:
Quiescent or 1/2 loading = 1/2 of all inputs/outputs energised.
12.4 SUPERCAPACITOR
Discharge time >14 days
514 P64x-TM-EN-4.1
13 INPUT / OUTPUT CONNECTIONS
13.1 ISOLATED DIGITAL INPUTS
Opto-isolated digital inputs (opto-inputs)

Compliance ESI 48-4
Rated nominal voltage 24 to 250 V dc
Operating range 19 to 265 V dc
Withstand 300 V dc
Recognition time with half-cycle ac
< 2 ms
immunity filter removed
Recognition time with filter on < 12 ms
13.1.1 NOMINAL PICKUP AND RESET THRESHOLDS
Nominal battery
Logic levels: 60-80% DO/PU Logic Levels: 50-70% DO/PU Logic Levels: 58-75% DO/PU
voltage
24/27 V Logic 0 < 16.2V, Logic 1 > 19.2V Logic 0 <12V, Logic 1 > 16.8V Logic 0 <15.7V, Logic 1 > 18V
30/34 Logic 0 < 20.4V, Logic 1 > 24V Logic 0 < 15V, Logic 1 > 21V Logic 0 < 19.7V, Logic 1 > 22.5V
48/54 Logic 0 < 32.4V, Logic 1 > 38.4V Logic 0 < 24V, Logic 1 > 33.6V Logic 0 < 31.3V, Logic 1 > 36V
110/125 Logic 0 < 75V, Logic 1 > 88V Logic 0 < 55.V, Logic 1 > 77V Logic 0 < 72.5V, Logic 1 > 82.5V
220/250 Logic 0 < 150V, Logic 1 > 176V Logic 0 < 110V, Logic 1 > 154V Logic 0 < 145V, Logic 1 > 165V
Note:
Filter is required to make the opto-inputs immune to induced AC voltages.
13.2 STANDARD OUTPUT CONTACTS
Compliance In accordance with IEC 60255-1:2009

Use General purpose relay outputs for signalling, tripping and alarming
Rated voltage 300 V
Maximum continuous current 10 A
30 A for 3 s
Short duration withstand carry
250 A for 30 ms
Make and break, dc resistive 50 W
Make and break, dc inductive 62.5 W (L/R = 50 ms)
Make and break, ac resistive 2500 VA resistive (cos phi = unity)
Make and break, ac inductive 2500 VA inductive (cos phi = 0.7)
Make and carry, dc resistive 30 A for 3 s, 10000 operations (subject to a maximum load of 7500W))
4 A for 1.5 s, 10000 operations (subject to the above limit for make and break, dc
Make, carry and break, dc resistive
resistive load)
0.5 A for 1 s, 10000 operations (subject to the above limit for make and break, dc
Make, carry and break, dc inductive
inductive load)
Make, carry and break ac resistive 30 A for 200 ms, 2000 operations (subject to the above limits)
P64x-TM-EN-4.1 515
Make, carry and break ac inductive 10 A for 1.5 s, 10000 operations (subject to the above limits)
Loaded contact 10000 operations min.
Unloaded contact 100000 operations min.
Operate time < 5 ms
Reset time < 10 ms
13.3 HIGH BREAK OUTPUT CONTACTS
Compliance In accordance with IEC 60255-1:2009

Use For applications requiring high rupture capacity
Rated voltage 300 V
Maximum continuous current 10 A DC
30 A DC for 3 s
Short duration withstand carry
250 A for 30 ms
Make and break, dc resistive 7500 W
Make and break, dc inductive 2500 W (L/R = 50 ms)
Make and carry, dc resistive 30 A for 3 s, 10000 operations (subject to the above limits)
30 A for 3 s, 5000 operations (subject to the above limit for make and break, dc
resistive load)
Make, carry and break, dc resistive
30 A for 200 ms, 10000 operations (subject to the above limit for make and break,
dc resistive load)
10 A for 40 ms, 10000 operations (subject to the above limit for make and break,
dc inductive load)
Make, carry and break, dc inductive
10 A for 20 ms (250V, 4 shots per second, subject to the above limit for make and
break, dc inductive load)
Loaded contact 10,000 operations minimum.
Unloaded contact 100,000 operations minimum.
Operate time < 0.2 ms
Reset time < 8 ms
MOV Protection Maximum voltage 330 V DC
13.4 WATCHDOG CONTACTS
Use Non-programmable contacts for relay healthy/relay fail indication

Breaking capacity, dc resistive 30 W
Breaking capacity, dc inductive 15 W (L/R = 40 ms)
Breaking capacity, ac inductive 375 VA inductive (cos phi = 0.7)
516 P64x-TM-EN-4.1
14 ENVIRONMENTAL CONDITIONS
14.1 AMBIENT TEMPERATURE RANGE
Compliance IEC 60255-27: 2013

Test Method IEC 60068-2-1:2007 and IEC 60068-2-2 2007
Operating temperature range -25°C to +55°C (continuous)
Storage and transit temperature range -25°C to +70°C (continuous)
14.2 TEMPERATURE ENDURANCE TEST
Temperature Endurance Test

Test Method IEC 60068-2-1: 2007 and 60068-2-2: 2007
-40°C (96 hours)
Operating temperature range
+70°C (96 hours)
-40°C (96 hours)
Storage and transit temperature range
+70°C (96 hours)
14.3 AMBIENT HUMIDITY RANGE
Compliance IEC 60068-2-78: 2013 and IEC 60068-2-30: 2005

Durability 56 days at 93% relative humidity and +40°C
Damp heat cyclic six (12 + 12) hour cycles, 93% RH, +25 to +55°C
14.4 CORROSIVE ENVIRONMENTS
Compliance IEC 60068-2-42: 2003, IEC 60068-2-43: 2003

Industrial corrosive environment/poor environmental 21 days exposure to elevated concentrations (25ppm) of SO2 at
control, Sulphur Dioxide 75% relative humidity and +25°C
Industrial corrosive environment/poor environmental 21 days exposure to elevated concentrations (10ppm) of H2S at
control, Hydrogen Sulphide 75% relative humidity and +25°C
Salt mist IEC 60068-2-52: 1996 KB severity 3
P64x-TM-EN-4.1 517
15 TYPE TESTS
15.1 INSULATION

Insulation resistance > 100 M ohm at 500 V DC (Using only electronic/brushless insulation tester)
15.2 CREEPAGE DISTANCES AND CLEARANCES

Pollution degree 3
Overvoltage category lll
Impulse test voltage (not RJ45) 5 kV
Impulse test voltage (RJ45) 1 kV
15.3 HIGH VOLTAGE (DIELECTRIC) WITHSTAND
IEC Compliance IEC 60255-27: 2013

Between all independent circuits 2 kV ac rms for 1 minute
Between independent circuits and protective earth conductor terminal 2 kV ac rms for 1 minute
Between all case terminals and the case earth 2 kV ac rms for 1 minute
Across open watchdog contacts 1 kV ac rms for 1 minute
Across open contacts of changeover output relays 1 kV ac rms for 1 minute
Between all RJ45 contacts and protective earth 1 kV ac rms for 1 minute
Between all screw-type EIA(RS)485 contacts and protective earth 1 kV ac rms for 1 minute
ANSI/IEEE Compliance ANSI/IEEE C37.90-2005
Across open contacts of normally open output relays 1.5 kV ac rms for 1 minute
Across open contacts of normally open changeover output relays 1 kV ac rms for 1 minute
Across open watchdog contacts 1 kV ac rms for 1 minute
15.4 IMPULSE VOLTAGE WITHSTAND TEST

Between all independent circuits Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
Between terminals of all independent circuits Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
Between all independent circuits and protective
Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
earth conductor terminal
Note:
Exceptions are communications ports and normally-open output contacts, where applicable.
518 P64x-TM-EN-4.1
16 ELECTROMAGNETIC COMPATIBILITY
16.1 1 MHZ BURST HIGH FREQUENCY DISTURBANCE TEST
Compliance IEC 60255-22-1: 2008, Class III, IEC 60255-26:2013

Common-mode test voltage (level 3) 2.5 kV
Differential test voltage (level 3) 1.0 kV
16.2 DAMPED OSCILLATORY TEST
EN61000-4-18: 2011: Level 3, 100 kHz and 1 MHz. Level 4: 3 MHz,

Compliance
10 MHz and 30 MHz, IEC 60255-26:2013
Differential mode test voltage 1.0 kV
16.3 IMMUNITY TO ELECTROSTATIC DISCHARGE
Compliance IEC 60255-26:2013, IEC 61000-4-2:2009

Class 4 Condition 15 kV discharge in air to user interface, display, and exposed metalwork
Class 3 Condition 8 kV discharge in air to all communication ports
16.4 ELECTRICAL FAST TRANSIENT OR BURST REQUIREMENTS

Applied to communication inputs Amplitude: 2 kV, burst frequency 5 kHz and 100 KHz (level 4)
Applied to power supply and all other inputs
Amplitude: 4 kV, burst frequency 5 kHz and 100 KHz (level 4)
except for communication inputs
16.5 SURGE WITHSTAND CAPABILITY
Compliance IEEE/ANSI C37.90.1: 2002

4 kV fast transient and 2.5 kV oscillatory applied common mode and differential
Condition 1
mode to opto inputs, output relays, CTs, VTs, power supply
4 kV fast transient and 2.5 kV oscillatory applied common mode to communications,
Condition 2
IRIG-B
P64x-TM-EN-4.1 519
16.6 SURGE IMMUNITY TEST
Compliance IEC 60255-26:2013, IEC 61000-4-5:2014+AMD1:2017

Pulse duration Time to half-value: 1.2/50 µs
Between all groups and protective earth conductor terminal Amplitude 4 kV
Between terminals of each group (excluding communications ports,
Amplitude 2 kV
where applicable)
16.7 IMMUNITY TO RADIATED ELECTROMAGNETIC ENERGY
Compliance IEC 60255-26:2013, IEC 61000-4-3:2006 + A2:2010

Frequency band 80 MHz to 3.0 GHz
Spot tests at 80, 160, 380, 450, 900, 1850, 2150 MHz
Test field strength 10 V/m
Test using AM 1 kHz @ 80%
Compliance IEEE/ANSI C37.90.2: 2004
Frequency band 80 MHz to 1 GHz
Spot tests at 80, 160, 380, 450 MHz
Waveform 1 kHz @ 80% am and pulse modulated
Field strength 35 V/m
16.8 RADIATED IMMUNITY FROM DIGITAL COMMUNICATIONS
Compliance IEC 61000-4-3:2006 + A2:2010

Frequency bands 800 to 960 MHz, 1.4 to 2.0 GHz
Test using AM 1 kHz / 80%
16.9 RADIATED IMMUNITY FROM DIGITAL RADIO TELEPHONES
Compliance IEC 60255-26:2013, IEC 61000-4-3:2006 + A2:2010

Frequency bands 900 MHz and 1.89 GHz
16.10 IMMUNITY TO CONDUCTED DISTURBANCES INDUCED BY RADIO FREQUENCY

FIELDS
Compliance IEC 60255-26:2013, IEC 61000-4-6:2013 Level 3

Frequency bands 150 kHz to 80 MHz
520 P64x-TM-EN-4.1
Test disturbance voltage 10 V rms

Test using AM 1 kHz @ 80%
Spot tests 27 MHz and 68 MHz
16.11 MAGNETIC FIELD IMMUNITY
IEC 61000-4-8:2009 Level 5

Compliance IEC 61000-4-9:2016 Level 5
IEC 61000-4-10:2016 Level 5
IEC 61000-4-8 test 100 A/m applied continuously, 1000 A/m applied for 3 s
IEC 61000-4-9 test 1000 A/m applied in all planes
100 A/m applied in all planes at 100 kHz/1 MHz with a burst duration of 2
IEC 61000-4-10 test
seconds
16.12 CONDUCTED EMISSIONS
Compliance IEC 60255-26:2013, EN 55016-2-1:2014

Power supply test 1 0.15 - 0.5 MHz, 79 dBµV (quasi peak) 66 dBµV (average)
Power supply test 2 0.5 – 30 MHz, 73 dBµV (quasi peak) 60 dBµV (average)
RJ45 test 1 (where applicable) 0.15 - 0.5 MHz, 97 dBµV (quasi peak) 84 dBµV (average)
RJ45 test 2 (where applicable) 0.5 – 30 MHz, 87 dBµV (quasi peak) 74 dBµV (average)
16.13 RADIATED EMISSIONS
Compliance IEC 60255-26:2013

Test 1 30 – 230 MHz, 40 dBµV/m at 10 m measurement distance
Test 2 230 – 1 GHz, 47 dBµV/m at 10 m measurement distance
Test 3 1 – 2 GHz, 76 dBµV/m at 10 m measurement distance
16.14 POWER FREQUENCY

Opto-inputs (Compliance is achieved using the opto-input 300 V common-mode (Class A)
filter) 150 V differential mode (Class A)
Note:
Compliance is achieved using the opto-input filter.
P64x-TM-EN-4.1 521
522 P64x-TM-EN-4.1
APPENDIX A
ORDERING OPTIONS
Appendix A - Ordering Options P64x
524 P64x-TM-EN-4.1
P64x Appendix A - Ordering Options
Variants Order Number

P642 Transformer Protection P642 **
Vx Aux Rating :
24 - 54Vdc 7
48 - 125Vdc (40 - 100Vac) 8
110 - 250 Vdc (100 - 240 Vac) 9
In/Vn Rating :
HV-LV (In = 1A/5A), (Vn = 100/120V) (8CT/1VT) 1
HV-LV (In = 1A/5A), (Vn = 100/120V) (8CT/2VT) 2
Hardware Options :
Standard - no options 1
IRIG-B only (modulated) 2
IRIG-B (modulated) & fibre optic converter 4
Ethernet (100Mbit/s) 6
Second Rear Comms Port (Courier EIA232/EIA485/k-bus) 7
Second Rear Comms Port + IRIG-B (modulated) (Courier EIA232/EIA485/k-bus) 8
Ethernet (100Mbit/s) plus IRIG-B (Modulated) A
Ethernet (100Mbit/s) plus IRIG-B (Un-modulated) B
IRIG-B (Un-modulated) C
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Modulated IRIG-B G
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Un-modulated IRIG-B H
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Modulated IRIG-B J
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Un-modulated IRIG-B K
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Modulated IRIG-B L
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Un-modulated IRIG-B M
Redundant Ethernet PRP/HSR, 2 fibre ports + Modulated IRIG-B N
Redundant Ethernet PRP/HSR, 2 fibre ports + Unmodulated IRIG-B P
Redundant Ethernet PRP/HSR/RSTP/Hot Standby, 2 multi-mode fibre ports + Modulated/Un-Modulated IRIG-B R
Redundant Ethernet PRP/HSR/RSTP/Hot Standby, 2 copper ports RJ45 + Modulated/Un-Modulated IRIG-B S
Single Ethernet, PRP/HSR/RSTP/Hot Standby, 1 copper port RJ45 & 1 multi-mode fibre port + Modulated/Un-Modulated IRIG T
Product Specific Options :

Size 8 (40TE) Case, 8 Optos + 8 Relays A
Size 8 (40TE) Case, 8 Optos + 8 Relays + RTD B
Size 8 (40TE) Case, 8 Optos + 8 Relays + CLIO (mA I/O) C
Size 8 (40TE) Case, 12 Optos + 12 Relays D
Size 8 (40TE) Case, 8 Optos + 12 Relays (including 4 High Break) E
Protocol Options :
K-Bus/Courier 1
Modbus 2
IEC60870-5-103 3
DNP3.0 4
IEC 61850 over Ethernet and Courier via rear K-Bus/RS485 6
DNP3.0 over Ethernet and Courier via rear K-Bus/RS485 8
Mounting Options :
Flush/Panel Mounting with Harsh Env.Coating, White Front Panel M
Flush/Panel Mounting with Harsh Env. Coating, with USB Port, Black and Silver Front Panel S
Panel Mounting, with harsh environment coating P
Language Options :
English, French, German, Spanish 0
English, French, German, Russian 5
Chinese, English or French via HMI, with English or French only via Communications port C
Software Version Options :
Unless specified the latest version will be delivered **
Customisation :
Default 0
Customer Settings A
Design Suffix :
Factory Determined
P64x-TM-EN-4.1 A1

P643 Transfromer Protection P643 **
Vx Aux Rating :
24 - 54Vdc 7
48 - 125Vdc (40 - 100Vac) 8
110 - 250 Vdc (100 - 240 Vac) 9
In/Vn Rating :
HV-LV In = 1A/5A, Vn = (100/120V) (12CT/1VT) Standard CT 1
HV-LV In = 1A/5A, Vn = (100/120V) (12CT/1VT) Sensitive CT 3
Hardware Options :
Standard - no options 1
IRIG-B only (modulated) 2
IRIG-B (modulated) & fibre optic converter 4
Second Rear Comms Port (Courier EIA232/EIA485/kbus) 7
Second Rear Comms Port + IRIG-B (modulated) (Courier EIA232/EIA485/kbus) 8

Size 12 (60TE) case, 16 optos + 16 relays A
Size 12 (60TE) case, 16 optos + 16 relays + RTD B
Size 12 (60TE) case, 16 optos + 16relays + CLIO (mA I/O) C
Size 12 (60TE) case, 24 optos + 16 relays D
Size 12 (60TE) case, 16 optos + 24 relays E
Size 12 (60TE) case, 16 optos + 20 relays (including 4 High Break) F
Size 16 (80TE) case, 40 optos + 24 relays G
Size 16 (80TE) case, 40 optos + 16 relays + RTD H
Size 16 (80TE) case, 40 optos + 16 relays + CLIO (mA I/O) J
Size 16 (80TE) case, 40 optos + 8 relays + RTD + CLIO (mA I/O) K
Size 16 (80TE) case, 40 optos + 20 relays (including 4 High Break) L
Size 16 (80TE) case, 40 optos + 12 relays (including 4 High Break) + RTD M
Size 16 (80TE) case, 40 optos + 12 relays (including 4 High Break) + CLIO (mA I/O) N
Protocol Options :
K-Bus/Courier 1
Modbus 2
IEC60870-5-103 3
DNP3.0 4
Mounting Options :
19" Rack Mounting with Harsh Env. Coating, White Front Panel N
19" Rack Mounting with Harsh Env. Coating, with USB Port, Black and Silver Front Panel T
Language Options :
Settings Files Options :
Default 0
Customer Specific A
Design Suffix :
Factory determined
A2 P64x-TM-EN-4.1
P64x Appendix A - Ordering Options

P645 Transformer Protection P645 **
Vx Aux Rating :
24 - 54Vdc 7
48 - 125Vdc (40 - 100Vac) 8
110 - 250 Vdc (100 - 240 Vac) 9
In/Vn Rating :
IEC 61850-9-2LE Sampled Analogue Values Ethernet board * C
* Only available with '12'/'20'/'22' Software on 80TE/40TE models

Hardware Options :
Standard : no options 1
IRIG-B (Modulated) only 2
IRIG-B (Modulated) & Fibre Optic Converter 4
Second Rear Comms Port (Courier EIA232/EIA485/k-bus) 7
Second Rear Comms Port + IRIG-B (modulated) (Courier EIA232/EIA485/k-bus) 8

Size 12 (60TE) case, 16 optos + 16 relays A
Size 12 (60TE) case, 16 optos + 16 relays + RTD B
Size 12 (60TE) case, 16 optos + 16 relays + CLIO (mA I/O) C
Size 12 (60TE) case, 24 optos + 16 relays D
Size 12 (60TE) case, 16 optos + 24 relays E
Size 16 (80TE) case, 24 optos + 24 relays or Size 8 (40TE) 8 optos 8 relays Mounting Opt R F
Size 16 (80TE) case, 24 optos + 24 relays + RTD G
Size 16 (80TE) case, 24 optos + 24 relays + CLIO (mA I/O) H
Size 16 (80TE) case, 24 optos + 24 relays + RTD + CLIO (mA I/O) J
Size 12 (60TE) case, 16 optos + 20 relays (including 4 high break) K
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) L
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + RTD M
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + CLIO (mA I/O) N
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + RTD + CLIO (mA I/O) P
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) Q
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + RTD R
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + CLIO (mA I/O) S
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + RTD + CLIO (mA I/O) T
Size 16 (80TE) case, 40 optos + 24 relays U
Size 16 (80TE) case, 40 optos + 16 relays + RTD V
Size 16 (80TE) case, 40 optos + 16 relays + CLIO (mA I/O) W
Size 16 (80TE) case, 40 optos + 8 relays + RTD + CLIO (mA I/O) X
Size 16 (80TE) case, 40 optos + 20 relays (including 4 High Break) Y
Size 16 (80TE) case, 40 optos + 12 relays (including 4 High Break) + RTD Z
Size 16 (80TE) case, 40 optos + 12 relays (including 4 High Break) + CLIO (mA I/O) 1
Protocol Options :
K-Bus/Courier 1
Modbus 2
IEC60870-5-103 3
DNP3.0 4
Mounting Options :
19" Rack Mounting with Harsh Env. Coating, White Front Panel N
40TE Case (9-2LE models only) Flush/Panel Mounting with Harsh Env. Coating, White Front Panel R
19" Rack Mounting with Harsh Env. Coating, with USB Port, Black and Silver Front Panel T
40TE Case (9-2LE models only) Flush/Panel Mounting with Harsh Env. Coating, with USB Port, Black and Silver Front Panel U
Language Options :
Settings Files Options :
P64x-TM-EN-4.1 A3

Default 0
Customer Specific A
Design Suffix :
Factory determined
A4 P64x-TM-EN-4.1
APPENDIX B
SETTINGS AND SIGNALS

Appendix B - Settings and Signals P64x
526 P64x-TM-EN-4.1
P64x Appendix B - Settings and Signals
MENU TEXT COL ROW DEFAULT SETTING AVAILABLE OPTIONS

DESCRIPTION
SYSTEM DATA 00 00
This column contains general system settings and records.
English
Francais
Language 00 01 English Deutsch
Espanol
[Indexed String]
This setting sets the default language used by the device.
8 registers for writing 16 character password
Each register contains a pair of characters
Each register is formatted as follows:-
Password 00 02 first character of a pair
second character of a pair
Each character is in the Courier range 33 - 122
[ASCII Password(16 plain text)]
This setting sets the device default password
Trip led self reset (1 = enable self reset)
Sys Fn Links 00 03 0 = Latched
[Binary Flag (8 bits);Indexed Strings]
This setting allows the fixed function trip LED to be self resetting (set to 1 to extinguish the LED after a period of healthy restoration of load
current). Only bit 0 is used.
First character in high order 8 bits
Description 00 04 MiCOM P645 Second character in low order 8 bits
[ASCII Text (16 chars)]
In this cell, you can enter and edit a 16 character IED description.
Plant Reference 00 05 MiCOM Second character in low order 8 bits
In this cell, you can enter and edit a 16 character plant description.
Model Number 00 06 Model Number Second character in low order 8 bits
This cell displays the IED model number. This cannot be edited.
Serial Number 00 08 Serial Number Second character in low order 8 bits
This cell displays the IED serial number. This cannot be edited
50 or 60
Frequency 00 09 50
[Unsigned Integer (8 bits)]
This cell sets the mains frequency to either 50 Hz or 60 Hz
Comms Level
Comms Level 00 0A 2
This cell displays the Courier communications conformance level
From 0 to 255 in steps of 1
Relay Address 00 0B 255
This cell sets the first rear port IED address. Available settings are dependent on the protocol. This setting can also be made in the
COMMUNICATIONS column.
Data formatted as per data type G27.
BUS CB OPEN
BUS CB CLOSED
CB1 Open (0 = Off, 1 = On)
CB1 Closed (0 = Off, 1 = On)
Plant Status 00 0C 0 CB3 Open (0 = Off, 1 = On)
P64x-TM-EN-4.1 B1

DESCRIPTION
[Binary Flag (16 bits)]
This cell displays the circuit breaker plant status. The first two bits are used. One to indicate the 52A state and one to indicate the 52B state.
Control Status
Control Status 00 0D 0
This cell is not used
Active Group
Active Group 00 0E 1
This cell displays the active settings group
CB Trip/Close 00 10 No Operation
Supports trip and close commands if enabled in the Circuit Breaker Control menu. Visible to LCD+Front Port
Software Ref. 1
Software Ref. 1 00 11 <Software Ref. 1>
This cell displays the IED software version including the protocol and IED model.
Software Ref. 2
Software Ref. 2 00 12 <Software Ref. 2>
This cell displays the software version of the Ethernet card for models equipped with IEC 61850.
Opto 1 Input State (0=Off, 1=Energised)
Opto I/P Status 00 30 0
[Binary Flag;Indexed String]
This cell display the status of the available opto-inputs. This information is repeated for system purposes.
Opto I/P Status2 00 31 0
B2 P64x-TM-EN-4.1

DESCRIPTION
This cell display the status of the available opto-inputs. This information is repeated for system purposes.
Relay 1 (0=Not Operated, 1=Operated)
Relay O/P Status 00 40 0
P64x-TM-EN-4.1 B3

DESCRIPTION
This cell displays the status of the available output relays.This information is repeated for system purposes.
Setting Group selection by DDB inputs invalid
CB Status Alarm
RTD Thermal Alarm
RTD Open Circuit Failure
RTD Short Circuit Failure
RTD Data Inconsistency Error
RTD Board Failure
Current Loop Input 1 Alarm
Current Loop Input 1 Undercurrent Fail Alarm
Alarm Status 1 00 50 0
Out of Service Alarm
Frequency Out of Range Alarm
UNUSED
UNUSED
UNUSED
Current Loop Input Input Failure
Current Loop Input Output Failure
VCO1 Configuration Alarm
VCO2 Configuration Alarm
UNUSED
CTS Fail Alarm
Circuity FLT Alm
VTS VT Fail Alarm
Thermal Pretrp Alarm
FAA alarm
[Binary Flag (32 bits);Indexed String]
This cell displays the status of the first set of 32 alarms as a binary string, including fixed and user settable alarms.
Data formatted as per data type G27
LOL alarm
Breaker Fail Any Trip
CB Fail Alarm T1
CB Fail Alarm T2
CB Fail Alarm T3
CB Fail Alarm T4
CB Fail Alarm T5
CB Fail Alarm T6
CB Fail Alarm T7
CB Fail Alarm T8
CB Fail Alarm T9
CB Fail Alarm T10
CB Fail Alarm T11
Alarm Status 2 00 51 0 CB Fail Alarm T12
CB Fail Alarm T13
CB Fail Alarm T14
CB Fail Alarm T15
CB Fail Alarm T16
CB Fail Alarm T17
CB Fail Alarm T18
UNUSED
HV V/Hz>1 Alarm
HV V/Hz>2 PrTrp
LV V/Hz>1 Alarm
LV V/Hz>2 PrTrp
UNUSED
UNUSED
Frequency Protection Alarm
B4 P64x-TM-EN-4.1

DESCRIPTION
Through fault Alarm
Z1 Test Mode
Z2 Test Mode
UNUSED
This cell displays the status of the second set of 32 alarms as a binary string, including fixed and user settable alarms.
Data formatted as per data type G27
Battery Fail alarm indication
Field Voltage Failure
Enrolled GOOSE IED absent alarm indication
Network Interface Card not fitted/failed alarm
Network Interface Card not responding alarm
Network Interface Card fatal error alarm indication
Network Interface Card software reload alarm
Bad TCP/IP Configuration Alarm
Bad OSI Configuration Alarm
Network Interface Card link fail alarm indication
Main card/NIC software mismatch alarm indication
IP address conflict alarm indication
SNTP Failure Alarm
MMS libraries memory allocation fails.
This cell displays the status of the third set of 32 alarms as a binary string, including fixed and user settable alarms.
User Alarm 1 (0=Self-reset, 1=Manual reset)
This cell displays the status of the fourth set of 32 alarms as a binary string, including fixed and user settable alarms.
Access Level
Access Level 00 D0 2 = Read + Execute +Edit
This cell displays the current access level.
Password Level 1 00 D2 blank 8 registers for writing 16 character password
P64x-TM-EN-4.1 B5

DESCRIPTION
first character of a pair
This setting allows you to change password level 1.
Password Level 2 00 D3 BBBB first character of a pair
Password Level 3 00 D4 AAAA first character of a pair
Security Feature
Security Feature 00 DF 1
[Unsigned Integer(16 bits)]
This setting displays the level of cyber security implemented, 1 = phase 1.
Username 00 E0
There are three Authentication methods suppored by P40 Authentication framework.
• Legacy Device Authentication
• Device Authentication (RBAC)
• Server Authentication (RBAC)
Respectively, acceptable username are,
• Empty
• Enumaratrion including ADMINISTRATOR, ENGINEER, OPERATOR and VIEWER
• Usernames are restricted to a maximum of 16 characters. Only uppercase A to Z and numbers 0 to 9 are permissible username
characters.
8 registers for writing encrypted password
Password 00 E1 Registers can contain any bit pattern.
[Encrypted Password (16 cyphertext)]
This cell allows you to enter the encrypted password. It is nott visbile via the user interfaced.
Password Level 1 00 E2 Registers can contain any bit pattern.
This setting allows you to change the encrypted password level 1. This is not visbile via the user interface.
VIEW RECORDS 01 00
This column contains record configuration data and settings.
Select Event 01 01 0
This setting selects the required event record. A value of 0 corresponds to the latest event, 1 the second latest and so on.
Menu Cell Ref
Menu Cell Ref 01 02 (From Record)
[Cell Reference]
This cell indicates the type of event.
Time & Date 01 03 (From Record) Time & Date
B6 P64x-TM-EN-4.1

DESCRIPTION
[IEC870 Time & Date]
This cell shows the Time & Date of the event, given by the internal Real Time Clock.
Event Text
Event Text 01 04 32-character string
[Ascii String (32 chars)]
This cell shows the description of the event - up to 32 Characters over 2 lines.
Event Value
Event Value 01 05 32-bit binary string
[Unsigned Int / Binary Flag (32 bits)]
This cell displays a 32 bit binary flag representing the event.
Select Fault 01 06 0
This setting selects the required fault record from those stored. A value of 0 corresponds to the latest fault and so on.
Start A
Start B
Start C
Start N
Faulted Phase 01 07 0 Trip A
Trip B
Trip C
Trip N
[Binary Flag (8 Bits)]
This cell displays the faulted phase.
(For fault record use only. The associated Modbus
registers cannot be accessed unless a fault record is
selected.)
Id Bias Start A
Id Bias Start B
Id Bias Start C
DeadZone 1 Start
DeadZone 2 Start
DeadZone 3 Start
DeadZone 4 Start
DeadZone 5 Start
DeadZone 6 Start
DeadZone 7 Start
DeadZone 8 Start
DeadZone 9 Start
DeadZone10 Start
DeadZone11 Start
DeadZone12 Start
DeadZone13 Start
Start Elements1 01 08 0 DeadZone14 Start
DeadZone15 Start
DeadZone16 Start
DeadZone17 Start
DeadZone18 Start
T1 I>1 Start
T1 I>2 Start
T2 I>1 Start
T2 I>2 Start
T3 I>1 Start
T3 I>2 Start
T4 I>1 Start
T4 I>2 Start
T5 I>1 Start
T5 I>2 Start
T6 I>1 Start

selected.)
P64x-TM-EN-4.1 B7

DESCRIPTION
Id Bias Start A
Id Bias Start B
Id Bias Start C
Hot Spot>1 Start
Hot Spot>2 Start
Hot Spot>3 Start
Top Oil >1 start
Top Oil >2 start
Top Oil >3 start
POC1 I>1 Start
POC1 I>2 Start
POC1 I>3 Start
POC1 I>4 Start
POC2 I>1 Start
POC2 I>2 Start
POC2 I>3 Start
POC2 I>4 Start
POC3 I>1 Start
POC3 I>2 Start
POC3 I>3 Start
POC3 I>4 Start
VCO1 Start
VCO2 Start
EF1 IN>1 Start
EF1 IN>2 Start
EF1 IN>3 Start
EF1 IN>4 Start
EF2 IN>1 Start
EF2 IN>2 Start
EF2 IN>3 Start
EF2 IN>4 Start
EF3 IN>1 Start
This cell displays the status of the first set of 32 start signals.
selected.)
T6 I>2 Start
T7 I>1 Start
T7 I>2 Start
T8 I>1 Start
T8 I>2 Start
T9 I>1 Start
T9 I>2 Start
T10 I>1 Start
T10 I>2 Start
T11 I>1 Start
T11 I>2 Start
Start Elements2 01 09 0 T12 I>1 Start
T12 I>2 Start
T13 I>1 Start
T13 I>2 Start
T14 I>1 Start
T14 I>2 Start
T15 I>1 Start
T15 I>2 Start
T16 I>1 Start
T16 I>2 Start
T17 I>1 Start
T17 I>2 Start
T18 I>1 Start
T18 I>2 Start
T1 IN>1 Start
B8 P64x-TM-EN-4.1

DESCRIPTION
T1 IN>2 Start
T2 IN>1 Start
T2 IN>2 Start
T3 IN>1 Start
T3 IN>2 Start
T4 IN>1 Start

selected.)
EF3 IN>2 Start
EF3 IN>3 Start
EF3 IN>4 Start
REF HV Start
REF LV Start
REF TV Start
REF AUTO Start
NPOC1 I2>1 Start
NPOC1 I2>2 Start
NPOC1 I2>3 Start
NPOC1 I2>4 Start
NPOC2 I2>1 Start
NPOC2 I2>2 Start
NPOC2 I2>3 Start
NPOC2 I2>4 Start
NPOC3 I2>1 Start
NPOC3 I2>2 Start
NPOC3 I2>3 Start
NPOC3 I2>4 Start
V<1 Start
V<2 Start
V>1 Start
V>2 Start
VN>1 Start
VN>2 Start
NPSOV1 Start
EF4 IN>1 Start
EF4 IN>2 Start
EF4 IN>3 Start
EF4 IN>4 Start
This cell displays the status of the second set of 32 start signals.
selected.)
Data Format as per data type G27.
T4 IN>2 Start
T5 IN>1 Start
T5 IN>2 Start
T6 IN>1 Start
T6 IN>2 Start
Start Elements3 01 0A 0 (For fault record use only. The associated Modbus
selected.)
V/Hz> Alm Start1
V/Hz>1 Start1
V/Hz>2 Start1
V/Hz>3 Start1
V/Hz>4 Start1
V/Hz> Alm Start2
V/Hz>1 Start2
P64x-TM-EN-4.1 B9

DESCRIPTION
V/Hz>2 Start2
V/Hz>3 Start2
V/Hz>4 Start2
F<1 Start
F<2 Start
F<3 Start
F<4 Start
F>1 Start
F>2 Start
CLI1 Alarm Start
CLI2 Alarm Start
CLI3 Alarm Start
CLI4 Alarm Start
CLI1 Trip Start
CLI2 Trip Start
CLI3 Trip Start
CLI4 Trip Start
This cell displays the status of the third set of 32 start signals.
selected.)
Id Bias Trip A
Id Bias Trip B
Id Bias Trip C
DeadZone 1 Trip
DeadZone 2 Trip
DeadZone 3 Trip
DeadZone 4 Trip
DeadZone 5 Trip
DeadZone 6 Trip
DeadZone 7 Trip
DeadZone 8 Trip
DeadZone 9 Trip
DeadZone10 Trip
DeadZone11 Trip
DeadZone12 Trip
DeadZone13 Trip
DeadZone14 Trip
DeadZone15 Trip
Trip Elements1 01 10 0
DeadZone16 Trip
DeadZone17 Trip
DeadZone18 Trip
T1 I>1 Trip
T1 I>2 Trip
T2 I>1 Trip
T2 I>2 Trip
T3 I>1 Trip
T3 I>2 Trip
T4 I>1 Trip
T4 I>2 Trip
T5 I>1 Trip
T5 I>2 Trip
T6 I>1 Trip

selected.)
Id Bias Trip A
Id Bias Trip B
Id Bias Trip C
B10 P64x-TM-EN-4.1

DESCRIPTION
Hot Spot>1 Trip
Hot Spot>2 Trip
Hot Spot>3 Trip
Top Oil >1 Trip
Top Oil >2 Trip
Top Oil >3 Trip
POC1 I>1 Trip
POC1 I>2 Trip
POC1 I>3 Trip
POC1 I>4 Trip
POC2 I>1 Trip
POC2 I>2 Trip
POC2 I>3 Trip
POC2 I>4 Trip
POC3 I>1 Trip
POC3 I>2 Trip
POC3 I>3 Trip
POC3 I>4 Trip
VCO1 Trip
VCO2 Trip
EF1 IN>1 Trip
EF1 IN>2 Trip
EF1 IN>3 Trip
EF1 IN>4 Trip
EF2 IN>1 Trip
EF2 IN>2 Trip
EF2 IN>3 Trip
EF2 IN>4 Trip
EF3 IN>1 Trip
This cell displays the status of the first set of 32 trip signals.
selected.)
T6 I>2 Trip
T7 I>1 Trip
T7 I>2 Trip
T8 I>1 Trip
T8 I>2 Trip
T9 I>1 Trip
T9 I>2 Trip
T10 I>1 Trip
T10 I>2 Trip
T11 I>1 Trip
T11 I>2 Trip
T12 I>1 Trip
T12 I>2 Trip
T13 I>1 Trip
T13 I>2 Trip
T14 I>1 Trip
T14 I>2 Trip
T15 I>1 Trip
T15 I>2 Trip
T16 I>1 Trip
T16 I>2 Trip
T17 I>1 Trip
T17 I>2 Trip
T18 I>1 Trip
T18 I>2 Trip
T1 IN>1 Trip
T1 IN>2 Trip
T2 IN>1 Trip
T2 IN>2 Trip
P64x-TM-EN-4.1 B11

DESCRIPTION
T3 IN>1 Trip
T3 IN>2 Trip
T4 IN>1 Trip

selected.)
EF3 IN>2 Trip
EF3 IN>3 Trip
EF3 IN>4 Trip
REF HV Trip
REF LV Trip
REF TV Trip
REF AUTO Trip
NPSOC1 I2>1 Trip
NPSOC1 I2>2 Trip
NPSOC1 I2>3 Trip
NPSOC1 I2>4 Trip
NPSOC2 I2>1 Trip
NPSOC2 I2>2 Trip
NPSOC2 I2>3 Trip
NPSOC2 I2>4 Trip
NPSOC3 I2>1 Trip
NPSOC3 I2>2 Trip
NPSOC3 I2>3 Trip
NPSOC3 I2>4 Trip
V<1 Trip
V<2 Trip
V>1 Trip
V>2 Trip
VN>1 Trip
VN>2 Trip
NPSOV1 Trip
Idiff HS1 Trip A
Idiff HS1 Trip B
Idiff HS1 Trip C
Idiff HS2 Trip A
Idiff HS2 Trip B
Idiff HS2 Trip C
This cell displays the status of the second set of 32 trip signals.
selected.)
T4 IN>2 Trip
T5 IN>1 Trip
T5 IN>2 Trip
T6 IN>1 Trip
T6 IN>2 Trip
Idiff TripA Z1
Idiff TripB Z1
Idiff TripC Z1
Idiff TripA Z2
Idiff TripB Z2
Idiff TripC Z2
Idiff Trip Z1
Idiff Trip Z2

selected.)
B12 P64x-TM-EN-4.1

DESCRIPTION
V/Hz>1 Trip1
V/Hz>2 Trip1
V/Hz>3 Trip1
V/Hz>4 Trip1
V/Hz>1 Trip2
V/Hz>2 Trip2
V/Hz>3 Trip2
V/Hz>4 Trip2
F<1 Trip
F<2 Trip
F<3 Trip
F<4 Trip
F>1 Trip
F>2 Trip
RTD 1 Trip
RTD 2 Trip
RTD 3 Trip
RTD 4 Trip
RTD 5 Trip
RTD 6 Trip
RTD 7 Trip
RTD 8 Trip
RTD 9 Trip
RTD 10 Trip
CLI1 Trip Trip
CLI2 Trip Trip
CLI3 Trip Trip
CLI4 Trip Trip
This cell displays the status of the third set of 32 trip signals.
selected.)
CB1 ReTrip 3ph
CB1 BkTrip 3ph
CB2 ReTrip 3ph
CB2 BkTrip 3ph
CB3 ReTrip 3ph
CB3 BkTrip 3ph
CB4 ReTrip 3ph
CB4 BkTrip 3ph
CB5 ReTrip 3ph
CB5 BkTrip 3ph
DDB_VPERHZ_ALARM_1
VTS
Fault Alarms 01 50 0 CTS
Alarm RTD 1
Alarm RTD 2
Alarm RTD 3
Alarm RTD 4
Alarm RTD 5
Alarm RTD 6
Alarm RTD 7
Alarm RTD 8
Alarm RTD 9
Alarm RTD 10
Alarm CL Input 1
Alarm CL Input 2
Alarm CL Input 3
Alarm CL Input 4
DDB_VPERHZ_ALARM_2
P64x-TM-EN-4.1 B13

DESCRIPTION
selected.)
CB Fail Alm T1
CB Fail Alm T2
CB Fail Alm T3
CB Fail Alm T4
CB Fail Alm T5
CB Fail Alm T6
CB Fail Alm T7
CB Fail Alm T8
CB Fail Alm T9
CB Fail Alm T10
CB Fail Alm T11
CB Fail Alm T12
CB Fail Alm T13
CB Fail Alm T14
CB Fail Alm T15
CB Fail Alm T16
CB Fail Alm T17
CB Fail Alm T18
CBF Alarm Bus CB
CTS T1
CTS T2
CTS T3
CTS T4
CTS T5
CTS T6
This cell displays the status of the fault alarm signals.
Fault Time
Fault Time 01 51 (From Record)
This cell displays the time and date of the fault.
Internal
Fault Type 01 52 Data External
This cell displays the fault type.
Active Group
Active Group 01 53 Data
[Unsigned Integer]
This cell displays the active settings group.
System Frequency
System Frequency 01 54 Data
[Courier Number (frequency)]
This cell displays the system frequency.
Fault Duration
Fault Duration 01 55 Data
[Courier Number (time)]
This cell displays the duration of the fault time.
CB Operate Time
CB Operate Time 01 56 Data
This cell displays the CB operate time.
Relay Trip Time
Relay Trip Time 01 60 Data
This cell displays the time from protection start to protection trip.
IA-1 Magnitude
IA-1 Magnitude 01 62
[Courier Number (Current)]
This cell displays the magnitude of the A-phase current for the first CT (T1) at the time of the fault.
IB-1 Magnitude
IB-1 Magnitude 01 64
This cell displays the magnitude of the B-phase current for the first CT (T1) at the time of the fault.
IC-1 Magnitude
IC-1 Magnitude 01 66
B14 P64x-TM-EN-4.1

DESCRIPTION
This cell displays the magnitude of the C-phase current for the first CT (T1) at the time of the fault.
IA-2 Magnitude
This cell displays the magnitude of the A-phase current for the second CT (T2) at the time of the fault.
IB-2 Magnitude
IB-2 Magnitude 01 6A
This cell displays the magnitude of the B-phase current for the second CT (T2) at the time of the fault.
IC-2 Magnitude
IC-2 Magnitude 01 6C
This cell displays the magnitude of the C-phase current for the second CT (T2) at the time of the fault.
IA-3 Magnitude
IA-3 Magnitude 01 6E
This cell displays the magnitude of the A-phase current for the third CT (T3) at the time of the fault.
IB-3 Magnitude
This cell displays the magnitude of the B-phase current for the third CT (T3) at the time of the fault.
IC-3 Magnitude
This cell displays the magnitude of the C-phase current for the third CT (T3) at the time of the fault.
IA-4 Magnitude
This cell displays the magnitude of the A-phase current for the fourth CT (T4) at the time of the fault.
IB-4 Magnitude
This cell displays the magnitude of the B-phase current for the fourth CT (T4) at the time of the fault.
IC-4 Magnitude
This cell displays the magnitude of the C-phase current for the fourth CT (T4) at the time of the fault.
IA-5 Magnitude
IA-5 Magnitude 01 7A
This cell displays the magnitude of the A-phase current for the fifth CT (T5) at the time of the fault.
IB-5 Magnitude
IB-5 Magnitude 01 7C
This cell displays the magnitude of the B-phase current for the fifth CT (T5) at the time of the fault.
IC-5 Magnitude
IC-5 Magnitude 01 7E
This cell displays the magnitude of the C-phase current for the fifth CT (T5) at the time of the fault.
IA-HV Magnitude
IA-HV Magnitude 01 90
This cell displays the magnitude of the A-phase current for the HV winding at the time of the fault.
IB-HV Magnitude
IB-HV Magnitude 01 91
This cell displays the magnitude of the B-phase current for the HV winding at the time of the fault.
IC-HV Magnitude
IC-HV Magnitude 01 92
This cell displays the magnitude of the C-phase current for the HV winding at the time of the fault.
IA-LV Magnitude
IA-LV Magnitude 01 93
This cell displays the magnitude of the A-phase current for the LV winding at the time of the fault.
IB-LV Magnitude
IB-LV Magnitude 01 94
This cell displays the magnitude of the B-phase current for the LV winding at the time of the fault.
IC-LV Magnitude
IC-LV Magnitude 01 95
This cell displays the magnitude of the C-phase current for the LV winding at the time of the fault.
IA-TV Magnitude
IA-TV Magnitude 01 96
This cell displays the magnitude of the A-phase current for the TV winding at the time of the fault.
IB-TV Magnitude 01 97 IB-TV Magnitude
P64x-TM-EN-4.1 B15

DESCRIPTION
This cell displays the magnitude of the B-phase current for the TV winding at the time of the fault.
IC-TV Magnitude
IC-TV Magnitude 01 98
This cell displays the magnitude of the C-phase current for the TV winding at the time of the fault.
I2-HV Magnitude
I2-HV Magnitude 01 99
This cell displays the magnitude of the negative sequence current for the HV winding at the time of the fault.
I2-LV Magnitude
I2-LV Magnitude 01 9A
This cell displays the magnitude of the negative sequence current for the LV winding at the time of the fault.
I2-TV Magnitude
I2-TV Magnitude 01 9B
This cell displays the magnitude of the negative sequence current for the TV winding at the time of the fault.
IN-HV Measd Mag
IN-HV Measd Mag 01 9C
This cell displays the magnitude of the measured neutral current for the HV winding at the time of the fault.
IN-LV Measd Mag
IN-LV Measd Mag 01 9D
This cell displays the magnitude of the measured neutral current for the LV winding at the time of the fault.
IN-TV Measd Mag
IN-TV Measd Mag 01 9E
This cell displays the magnitude of the measured neutral current for the TV winding at the time of the fault.
VAN Magnitude
VAN Magnitude 01 A0
[Courier Number (voltage)]
This cell displays the VAN magnitude at the time of the fault.
VBN Magnitude
VBN Magnitude 01 A1
This cell displays the VBN magnitude at the time of the fault.
VCN Magnitude
VCN Magnitude 01 A2
This cell displays the VCN magnitude at the time of the fault.
Vx Magnitude
Vx Magnitude 01 A3
This cell displays the single phase VT input magnitude
V1 Magnitude
V1 Magnitude 01 A4
This cell displays the V1 (positive sequence voltage) magnitude at the time of the fault.
V2 Magnitude
V2 Magnitude 01 A5
This cell displays the V2 (negative sequence voltage) magnitude at the time of the fault.
VN Derived Mag
VN Derived Mag 01 A6
This cell displays the VN (neutral voltage) magnitude at the time of the fault.
VAB Magnitude
VAB Magnitude 01 A7
This cell displays the VAB magnitude at the time of the fault.
VBC Magnitude
VBC Magnitude 01 A8
This cell displays the VBC magnitude at the time of the fault.
VCA Magnitude
VCA Magnitude 01 A9
This cell displays the VCA magnitude at the time of the fault.
IADiff
IADiff 01 B0
[Courier Number (current)]
This cell displays the A-phase differential current at the time of the fault.
IBDiff
IBDiff 01 B1
This cell displays the B-phase differential current at the time of the fault.
B16 P64x-TM-EN-4.1

DESCRIPTION
ICDiff
ICDiff 01 B2
This cell displays the C-phase differential current at the time of the fault.
IABias
IABias 01 B3
This cell displays the A-phase bias current at the time of the fault.
IBBias
IBBias 01 B4
This cell displays the B-phase bias current at the time of the fault.
ICBias
ICBias 01 B5
This cell displays the C-phase bias current at the time of the fault.
REF HV LoZ Diff
REF HV LoZ Diff 01 B9
This cell displays the Low impedance REF differential current for the HV winding at the time of the fault.
REF HV LoZ Bias
REF HV LoZ Bias 01 BA
This cell displays the Low impedance REF bias current for the HV winding at the time of the fault.
REF LV LoZ Diff
REF LV LoZ Diff 01 BB
This cell displays the Low impedance REF differential current for the LV winding at the time of the fault.
REF LV LoZ Bias
REF LV LoZ Bias 01 BC
This cell displays the Low impedance REF bias current for the LV winding at the time of the fault.
REF TV LoZ Diff
REF TV LoZ Diff 01 BD
This cell displays the Low impedance REF differential current for the TV winding at the time of the fault.
REF TV LoZ Bias
REF TV LoZ Bias 01 BE
This cell displays the Low impedance REF bias current for the TV winding at the time of the fault.
REFAUTO LoZ Diff
REFAUTO LoZ Diff 01 BF
This cell displays the Low impedance REF differential current for autotransformer configuration at the time of the fault.
REFAUTO LoZ Bias
REFAUTO LoZ Bias 01 C0
This cell displays the Low impedance REF bias current for autotransformer configuration at the time of the fault.
REFHV HiZ Diff
REFHV HiZ Diff 01 C1
This cell displays the High impedance REF operating current for the HV winding at the time of the fault.
REFLV HiZ Diff
REFLV HiZ Diff 01 C2
This cell displays the High impedance REF operating current for the LV winding at the time of the fault.
REF TV HiZ Diff
REF TV HiZ Diff 01 C3
This cell displays the High impedance REF operating current for the TV winding at the time of the fault.
REFAUTO HiZ Diff
REFAUTO HiZ Diff 01 C4
This cell displays the High impedance REF operating current for autotransformer configuration at the time of the fault.
IA Peak
IA Peak 01 C5
This cell displays the A-phase Peak Magnitude at the time of the fault..
IB Peak
IB Peak 01 C6
This cell displays the B-phase Peak Magnitude at the time of the fault..
IC Peak
IC Peak 01 C7
This cell displays the C-phase Peak Magnitude at the time of the fault..
IA2t
IA2t 01 C8
[Courier Number (A2t)]
P64x-TM-EN-4.1 B17

DESCRIPTION
This cell displays the thermal heating value of the A-phase winding at the time of the fault.
IB2t
IB2t 01 C9
This cell displays the thermal heating value of the B-phase winding at the time of the fault.
IC2t
IC2t 01 CA
This cell displays the thermal heating value of the C-phase winding at the time of the fault.
RTD 1
RTD 1 01 D0
[Courier Number (Temperature)]
This cell displays the temperature associated with RTD1 at the time of the fault. record
RTD 2
RTD 2 01 D1
This cell displays the temperature associated with RTD2 at the time of the fault.
RTD 3
RTD 3 01 D2
RTD 4
RTD 4 01 D3
RTD 5
RTD 5 01 D4
RTD 6
RTD 6 01 D5
RTD 7
RTD 7 01 D6
RTD 8
RTD 8 01 D7
RTD 9
RTD 9 01 D8
RTD 10
RTD 10 01 D9
CLIO1
CLIO1 01 DA
[Courier Number (Decimal)]
This cell displays the measurement value associated with the CLIO1 input at the time of the fault.
CLIO2
CLIO2 01 DB
CLIO3
CLIO3 01 DC
CLIO4
CLIO4 01 DD
Hot Spot T
Hot Spot T 01 E0
This cell displays the hot spot temperature at the time of the fault.
Top Oil T
Top Oil T 01 E1
This cell displays the top oil temperature at the time of the fault.
Ambient T
Ambient T 01 E2
This cell displays the ambient temperature at the time of the fault.
B18 P64x-TM-EN-4.1

DESCRIPTION
EF1 Derived
EF1 Derived 01 E3
This cell displays EF1 derived current the at the time of the fault.
EF2 Derived
EF2 Derived 01 E4
EF3 Derived
EF3 Derived 01 E5
EF1 Measured
EF1 Measured 01 E6
This cell displays EF1 measured current the at the time of the fault.
EF2 Measured
EF2 Measured 01 E7
EF3 Measured
EF3 Measured 01 E8
3ph VperHz
3ph VperHz 01 E9
This cell displays 3ph overflux the at the time of the fault.
1ph VperHz
1ph VperHz 01 EA
This cell displays 1ph overflux the at the time of the fault.
EF4 Derived
EF4 Derived 01 EB
Manual override to select a From 0 to 9 in steps of 1
Select Maint 01 F0
fault record. [Unsigned Integer (16 bits)]
This setting selects the required maintenance report from those stored. A value of 0 corresponds to the latest report.
Maint Text
Maint Text 01 F1
[ASCII Text (32)]
This cell displays the description of the maintenance record.
Maint Type
Maint Type 01 F2
[UINT32]
This is the type of maintenance record.
Maint Data
Maint Data 01 F3
[UINT32]
This is the maintenance record data (error code).
Evt Iface Source
Evt Iface Source 01 FA
This cell displays the interface on which the event was logged
Evt Access Level
Evt Access Level 01 FB
Any security event that indicates that it came from an interface action, such as disabling a port, will also record the access level of the
interface that initiated the event. This access level is displayed in this cell.
Evt Extra Info
Evt Extra Info 01 FC
This cell provides supporting information for the event and can vary between the different event types.
High order word stored in 1st register
Evt Unique Id 01 FE Low order word stored in 2nd register
This cell displays the unique event ID associated with the event.
No
Reset Indication 01 FF No Yes
[Indexed String]
This command resets the trip LED indications provided that the relevant protection element has reset.
MEASUREMENTS 1 02 00
This column contains measurement parameters.
P64x-TM-EN-4.1 B19

DESCRIPTION
IA-1 Magnitude
IA-1 Magnitude 02 01 Data
This cell displays the A-phase current magnitude of the first CT (T1).
IA-1 Phase Angle
IA-1 Phase Angle 02 02 Data
[Courier Number (Angle)]
This cell displays the A-phase phase angle of the first CT (T1).
IB-1 Magnitude
IB-1 Magnitude 02 03 Data
This cell displays the B-phase current magnitude of the first CT (T1).
IB-1 Phase Angle
IB-1 Phase Angle 02 04 Data
This cell displays the B-phase phase angle of the first CT (T1).
IC-1 Magnitude
IC-1 Magnitude 02 05 Data
This cell displays the C-phase current magnitude of the first CT (T1).
IC-1 Phase Angle
IC-1 Phase Angle 02 06 Data
This cell displays the C-phase phase angle of the first CT (T1).
IA-2 Magnitude
This cell displays the A-phase current magnitude of the second CT (T2).
IA-2 Phase Angle
This cell displays the A-phase phase angle of the second CT (T2).
IB-2 Magnitude
This cell displays the B-phase current magnitude of the second CT (T2).
IB-2 Phase Angle
IB-2 Phase Angle 02 0A Data
This cell displays the B-phase phase angle of the second CT (T2).
IC-2 Magnitude
IC-2 Magnitude 02 0B Data
This cell displays the C-phase current magnitude of the second CT (T2).
IC-2 Phase Angle
IC-2 Phase Angle 02 0C Data
This cell displays the C-phase phase angle of the second CT (T2).
IA-3 Magnitude
IA-3 Magnitude 02 0D Data
This cell displays the A-phase current magnitude of the third CT (T3).
IA-3 Phase Angle
IA-3 Phase Angle 02 0E Data
This cell displays the A-phase phase angle of the third CT (T3).
IB-3 Magnitude
IB-3 Magnitude 02 0F Data
This cell displays the B-phase current magnitude of the third CT (T3).
IB-3 Phase Angle
This cell displays the B-phase phase angle of the third CT (T3).
IC-3 Magnitude
This cell displays the C-phase current magnitude of the third CT (T3).
IC-3 Phase Angle
This cell displays the C-phase phase angle of the third CT (T3).
IA-4 Magnitude
This cell displays the A-phase current magnitude of the fourth CT (T4).
IA-4 Phase Angle
B20 P64x-TM-EN-4.1

DESCRIPTION
This cell displays the A-phase phase angle of the fourth CT (T4).
IB-4 Magnitude
This cell displays the B-phase current magnitude of the fourth CT (T4).
IB-4 Phase Angle
This cell displays the B-phase phase angle of the fourth CT (T4).
IC-4 Magnitude
This cell displays the C-phase current magnitude of the fourth CT (T4).
IC-4 Phase Angle
This cell displays the C-phase phase angle of the fourth CT (T4).
IA-5 Magnitude
This cell displays the A-phase current magnitude of the fifth CT (T5).
IA-5 Phase Angle
IA-5 Phase Angle 02 1A Data
This cell displays the A-phase phase angle of the fifth CT (T5).
IB-5 Magnitude
IB-5 Magnitude 02 1B Data
This cell displays the B-phase current magnitude of the fifth CT (T5).
IB-5 Phase Angle
IB-5 Phase Angle 02 1C Data
This cell displays the B-phase phase angle of the fifth CT (T5).
IC-5 Magnitude
IC-5 Magnitude 02 1D Data
This cell displays the C-phase current magnitude of the fifth CT (T5).
IC-5 Phase Angle
IC-5 Phase Angle 02 1E Data
This cell displays the C-phase phase angle of the fifth CT (T5).
IA-HV Magnitude
IA-HV Magnitude 02 50 Data
This cell displays the A-phase current magnitude of the HV winding.
IA-HV Phase Ang
IA-HV Phase Ang 02 51 Data
This cell displays the A-phase phase angle of the HV winding.
IB-HV Magnitude
IB-HV Magnitude 02 52 Data
This cell displays the B-phase current magnitude of the HV winding.
IB-HV Phase Ang
IB-HV Phase Ang 02 53 Data
This cell displays the B-phase phase angle of the HV winding.
IC-HV Magnitude
IC-HV Magnitude 02 54 Data
This cell displays the C-phase current magnitude of the HV winding.
IC-HV Phase Ang
IC-HV Phase Ang 02 55 Data
This cell displays the C-phase phase angle of the HV winding.
IA-LV Magnitude
IA-LV Magnitude 02 56 Data
This cell displays the A-phase current magnitude of the LV winding.
IA-LV Phase Ang
IA-LV Phase Ang 02 57 Data
This cell displays the A-phase phase angle of the LV winding.
IB-LV Magnitude
IB-LV Magnitude 02 58 Data
This cell displays the B-phase current magnitude of the LV winding.
P64x-TM-EN-4.1 B21

DESCRIPTION
IB-LV Phase Ang
IB-LV Phase Ang 02 59 Data
This cell displays the B-phase phase angle of the LV winding.
IC-LV Magnitude
IC-LV Magnitude 02 5A Data
This cell displays the C-phase current magnitude of the LV winding.
IC-LV Phase Ang
IC-LV Phase Ang 02 5B Data
This cell displays the C-phase phase angle of the LV winding.
IA-TV Magnitude
IA-TV Magnitude 02 5C Data
This cell displays the A-phase current magnitude of the TV winding.
IA-TV Phase Ang
IA-TV Phase Ang 02 5D Data
This cell displays the A-phase phase angle of the TV winding.
IB-TV Magnitude
IB-TV Magnitude 02 5E Data
This cell displays the B-phase current magnitude of the TV winding.
IB-TV Phase Ang
IB-TV Phase Ang 02 5F Data
This cell displays the B-phase phase angle of the TV winding.
IC-TV Magnitude
IC-TV Magnitude 02 60 Data
This cell displays the C-phase current magnitude of the TV winding.
IC-TV Phase Ang
IC-TV Phase Ang 02 61 Data
This cell displays the C-phase phase angle of the TV winding.
I0-1 Magnitude
I0-1 Magnitude 02 62 Data
This cell displays the zero sequence current magnitude for the first CT (T1).
I1-1 Magnitude
This cell displays the positive sequence current magnitude for the first CT (T1).
I2-1 Magnitude
This cell displays the negative sequence current magnitude for the first CT (T1).
IN-TN1 Mea Mag
IN-TN1 Mea Mag 02 65 Data
This cell displays the measured neutral current magnitude of the TN1 winding.
IN-TN1 Mea Ang
IN-TN1 Mea Ang 02 66 Data
This cell displays the measured neutral phase angle of the TN1 winding.
IN-TN1 Deriv Mag
IN-TN1 Deriv Mag 02 67 Data
This cell displays the derived neutral current magnitude of the TN1 winding.
IN-TN1 Deriv Ang
IN-TN1 Deriv Ang 02 68 Data
This cell displays the derived neutral phase angle of the TN1 winding.
I0-2 Magnitude
This cell displays the zero sequence current magnitude for the second CT (T2).
I1-2 Magnitude
I1-2 Magnitude 02 6A Data
This cell displays the positive sequence current magnitude for the second CT (T2).
I2-2 Magnitude
I2-2 Magnitude 02 6B Data
This cell displays the negative sequence current magnitude for the second CT (T2).
IN-TN2 Mea Mag
IN-TN2 Mea Mag 02 6C Data
B22 P64x-TM-EN-4.1

DESCRIPTION
IN-TN2 Mea Ang
IN-TN2 Mea Ang 02 6D Data
IN-TN2 Deriv Mag
IN-TN2 Deriv Mag 02 6E Data
IN-TN2 Deriv Ang
IN-TN2 Deriv Ang 02 6F Data
I0-3 Magnitude
This cell displays the zero sequence current magnitude for the third CT (T3).
I1-3 Magnitude
This cell displays the positive sequence current magnitude for the third CT (T3).
I2-3 Magnitude
This cell displays the negative sequence current magnitude for the third CT (T3).
IN-TN3 Mea Mag
IN-TN3 Mea Mag 02 73 Data
IN-TN3 Mea Ang
IN-TN3 Mea Ang 02 74 Data
IN-TN3 Deriv Mag
IN-TN3 Deriv Mag 02 75 Data
IN-TN3 Deriv Ang
IN-TN3 Deriv Ang 02 76 Data
I0-4 Magnitude
This cell displays the zero sequence current magnitude for the fourth CT (T4).
I1-4 Magnitude
This cell displays the positive sequence current magnitude for the fourth CT (T4).
I2-4 Magnitude
This cell displays the negative sequence current magnitude for the fourth CT (T4).
I0-5 Magnitude
I0-5 Magnitude 02 7C Data
This cell displays the zero sequence current magnitude for the fifth CT (T5).
I1-5 Magnitude
I1-5 Magnitude 02 7D Data
This cell displays the positive sequence current magnitude for the fifth CT (T5).
I2-5 Magnitude
I2-5 Magnitude 02 7E Data
This cell displays the negative sequence current magnitude for the fifth CT (T5).
IA-HV RMS
IA-HV RMS 02 86 Data
This cell displays the A-phase RMS current of the HV winding.
IB-HV RMS
IB-HV RMS 02 87 Data
This cell displays the B-phase RMS current of the HV winding.
IC-HV RMS
IC-HV RMS 02 88 Data
This cell displays the C-phase RMS current of the HV winding.
P64x-TM-EN-4.1 B23

DESCRIPTION
IA-LV RMS
IA-LV RMS 02 89 Data
This cell displays the A-phase RMS current of the LV winding.
IB-LV RMS
IB-LV RMS 02 8A Data
This cell displays the B-phase RMS current of the LV winding.
IC-LV RMS
IC-LV RMS 02 8B Data
This cell displays the C-phase RMS current of the LV winding.
IA-TV RMS
IA-TV RMS 02 8C Data
This cell displays the A-phase RMS current of the TV winding.
IB-TV RMS
IB-TV RMS 02 8D Data
This cell displays the B-phase RMS current of the TV winding.
IC-TV RMS
IC-TV RMS 02 8E Data
This cell displays the C-phase RMS current of the TV winding.
VAN Magnitude
VAN Magnitude 02 8F Data
This cell displays the A-phase voltage magnitude with respect to Neutral (VAN)
VAN Phase Angle
VAN Phase Angle 02 90 Data
[Courier Number (angle)]
This cell displays the VAN phase angle
VBN Magnitude
VBN Magnitude 02 91 Data
This cell displays the B-phase voltage magnitude with respect to Neutral (VBN)
VBN Phase Angle
VBN Phase Angle 02 92 Data
This cell displays the VBN phase angle
VCN Magnitude
VCN Magnitude 02 93 Data
This cell displays the C-phase voltage magnitude with respect to Neutral (VCN)
VCN Phase Angle
VCN Phase Angle 02 94 Data
This cell displays the VCN phase angle
Vx Magnitude
Vx Magnitude 02 95 Data
This cell displays the single phase VT input magnitude
Vx Phase Angle
Vx Phase Angle 02 96 Data
This cell displays the Single phase VT input phase angle
V1 Magnitude
V1 Magnitude 02 97 Data
This cell displays the positive sequence voltage magnitude
V2 Magnitude
This cell displays the negative sequence voltage magnitude
V0 Magnitude
This cell displays the zero sequence voltage magnitude
VN Derived Mag
VN Derived Mag 02 9A Data
This cell displays the derived neutral voltage magnitude
VN Derived Angle
VN Derived Angle 02 9B Data
This cell displays the derived neutral phase voltage angle
VAB Magnitude
VAB Magnitude 02 9C Data
B24 P64x-TM-EN-4.1

DESCRIPTION
This cell displays the A-phase voltage magnitude with respect to B-phase (VAB)
VAB Phase Angle
VAB Phase Angle 02 9D Data
This cell displays the VAB phase angle
VBC Magnitude
VBC Magnitude 02 9E Data
This cell displays the B-phase voltage magnitude with respect to C-phase (VBC)
VBC Phase Angle
VBC Phase Angle 02 9F Data
This cell displays the VBC phase angle
VCA Magnitude
VCA Magnitude 02 A0 Data
This cell displays the C-phase voltage magnitude with respect to A-phase (VCA)
VCA Phase Angle
VCA Phase Angle 02 A1 Data
This cell displays the VCA phase angle
VAN RMS
VAN RMS 02 A2 Data
This cell displays the RMS value of VA with respect to Neutral
VBN RMS
VBN RMS 02 A3 Data
This cell displays the RMS value of VB with respect to Neutral
VCN RMS
VCN RMS 02 A4 Data
This cell displays the RMS value of VC with respect to Neutral
Frequency
Frequency 02 AA Data
[Courier Number (frequency)]
This cell displays the system frequency
This column contains measurement parameters
Aphase Watts HV
Aphase Watts HV 03 01 Data
[Courier Number (Power)]
This cell displays the A-phase Watts measurement for the HV winding.
Aphase Watts LV
Aphase Watts LV 03 02 Data
This cell displays the A-phase Watts measurement for the LV winding.
Aphase Watts TV
Aphase Watts TV 03 03 Data
This cell displays the A-phase Watts measurement for the TV winding.
Bphase Watts HV
Bphase Watts HV 03 04 Data
This cell displays the B-phase Watts measurement for the HV winding.
Bphase Watts LV
Bphase Watts LV 03 05 Data
This cell displays the B-phase Watts measurement for the LV winding.
Bphase Watts TV
Bphase Watts TV 03 06 Data
This cell displays the B-phase Watts measurement for the TV winding.
Cphase Watts HV
Cphase Watts HV 03 07 Data
This cell displays the C-phase Watts measurement for the HV winding.
Cphase Watts LV
Cphase Watts LV 03 08 Data
This cell displays the C-phase Watts measurement for the LV winding.
Cphase Watts TV
Cphase Watts TV 03 09 Data
This cell displays the C-phase Watts measurement for the TV winding.
Aphase Vars HV
Aphase Vars HV 03 0A Data
[Courier Number (VAr)]
P64x-TM-EN-4.1 B25

DESCRIPTION
This cell displays the A-phase VArs measurement for the HV winding.
Aphase Vars LV
Aphase Vars LV 03 0B Data
This cell displays the A-phase VArs measurement for the LV winding.
Aphase Vars TV
Aphase Vars TV 03 0C Data
This cell displays the A-phase VArs measurement for the TV winding.
Bphase Vars HV
Bphase Vars HV 03 0D Data
This cell displays the B-phase VArs measurement for the HV winding.
Bphase Vars LV
Bphase Vars LV 03 0E Data
This cell displays the B-phase VArs measurement for the LV winding.
Bphase Vars TV
Bphase Vars TV 03 0F Data
This cell displays the B-phase VArs measurement for the TV winding.
Cphase Vars HV
Cphase Vars HV 03 10 Data
This cell displays the C-phase VArs measurement for the HV winding.
Cphase Vars LV
Cphase Vars LV 03 11 Data
This cell displays the C-phase VArs measurement for the LV winding.
Cphase Vars TV
Cphase Vars TV 03 12 Data
This cell displays the C-phase VArs measurement for the TV winding.
Aphase VA HV
Aphase VA HV 03 13 Data
[Courier Number (VA)]
This cell displays the A-phase VA measurement for the HV winding.
Aphase VA LV
Aphase VA LV 03 14 Data
This cell displays the A-phase VA measurement for the LV winding.
Aphase VA TV
Aphase VA TV 03 15 Data
This cell displays the A-phase VA measurement for the TV winding.
Bphase VA HV
Bphase VA HV 03 16 Data
This cell displays the B-phase VA measurement for the HV winding.
Bphase VA LV
Bphase VA LV 03 17 Data
This cell displays the B-phase VA measurement for the LV winding.
Bphase VA TV
Bphase VA TV 03 18 Data
This cell displays the B-phase VA measurement for the TV winding.
Cphase VA HV
Cphase VA HV 03 19 Data
This cell displays the C-phase VA measurement for the HV winding.
Cphase VA LV
Cphase VA LV 03 1A Data
This cell displays the C-phase VA measurement for the LV winding.
Cphase VA TV
Cphase VA TV 03 1B Data
This cell displays the C-phase VA measurement for the TV winding.
3ph Watts HV
3ph Watts HV 03 1C Data
This cell displays the 3-phase Watts measurement for the HV winding.
3ph Watts LV
3ph Watts LV 03 1D Data
This cell displays the 3-phase Watts measurement for the LV winding.
B26 P64x-TM-EN-4.1

DESCRIPTION
3ph Watts TV
3ph Watts TV 03 1E Data
This cell displays the 3-phase Watts measurement for the TV winding.
3ph Vars HV
3ph Vars HV 03 1F Data
This cell displays the 3-phase VArs measurement for the HV winding.
3ph Vars LV
3ph Vars LV 03 20 Data
This cell displays the 3-phase VArs measurement for the LV winding.
3ph Vars TV
3ph Vars TV 03 21 Data
This cell displays the 3-phase VArs measurement for the TV winding.
3ph VA HV
3ph VA HV 03 22 Data
This cell displays the 3-phase VA measurement for the HV winding.
3ph VA LV
3ph VA LV 03 23 Data
This cell displays the 3-phase VA measurement for the LV winding.
3ph VA TV
3ph VA TV 03 24 Data
This cell displays the 3-phase VA measurement for the TV winding.
3Ph Power Factor
3Ph Power Factor 03 25 Data
[Courier Number (decimal)]
This cell displays the 3-phase Power Factor measurement.
APh Power Factor
APh Power Factor 03 26 Data
This cell displays the A-phase Power Factor measurement.
BPh Power Factor
BPh Power Factor 03 27 Data
This cell displays the B-phase Power Factor measurement.
CPh Power Factor
CPh Power Factor 03 28 Data
This cell displays the C-phase Power Factor measurement.
3Ph WHours Fwd
3Ph WHours Fwd 03 29 Data
[Courier Number (Wh)]
This cell displays the 3-phase Watt Hours forward measurement.
3Ph WHours Rev
3Ph WHours Rev 03 2A Data
[Courier Number (Wh)]
This cell displays the 3-phase Watt Hours reverse measurement.
3Ph VArHours Fwd
3Ph VArHours Fwd 03 2B Data
[Courier Number (VArh)]
This cell displays the 3-phase VAr Hours forward measurement.
3Ph VArHours Rev
3Ph VArHours Rev 03 2C Data
[Courier Number (VArh)]
This cell displays the 3-phase VAr Hours reverse measurement.
3Ph W Fix Demand
3Ph W Fix Demand 03 2D Data
This cell displays the 3-phase Watts Fixed Demand measurement.
3Ph VArs Fix Dem
3Ph VArs Fix Dem 03 2E Data
[Courier Number (Vars)]
This cell displays the 3-phase VArs Fixed Demand measurement.
3 Ph W Roll Dem
3 Ph W Roll Dem 03 2F Data
This cell displays the 3-phase Watts Rolling Demand measurement.
3Ph VArs RollDem
3Ph VArs RollDem 03 30 Data
This cell displays the 3-phase VArs Rolling Demand measurement.
3Ph W Peak Dem
3Ph W Peak Dem 03 31 Data
P64x-TM-EN-4.1 B27

DESCRIPTION
This cell displays the 3-phase Watts Peak Demand measurement.
3Ph VAr Peak Dem
3Ph VAr Peak Dem 03 32 Data
This cell displays the 3-phase VArs Peak Demand measurement.
No
Reset Demand 03 50 No Yes
[Indexed String]
This command resets all aquired Demand values whether rolled or fixed.
This column contains measurement parameters.
IA Differential
IA Differential 04 01 Data
This cell displays the A-phase differential current.
IB Differential
IB Differential 04 02 Data
This cell displays the B-phase differential current.
IC Differential
IC Differential 04 03 Data
This cell displays the C-phase differential current.
IA Bias
IA Bias 04 04 Data
This cell displays the A-phase bias current.
IB Bias
IB Bias 04 05 Data
This cell displays the B-phase bias current.
IC Bias
IC Bias 04 06 Data
This cell displays the C-phase bias current.
IA Diff 2H
IA Diff 2H 04 07 Data
This cell displays the A-phase differential 2nd harmonic current component.
IB Diff 2H
IB Diff 2H 04 08 Data
This cell displays the B-phase differential 2nd harmonic current component.
IC Diff 2H
IC Diff 2H 04 09 Data
This cell displays the C-phase differential 2nd harmonic current component.
IA Diff 5H
IA Diff 5H 04 0A Data
This cell displays the A-phase differential 5th harmonic current component.
IB Diff 5H
IB Diff 5H 04 0B Data
This cell displays the B-phase differential 5th harmonic current component.
IC Diff 5H
IC Diff 5H 04 0C Data
This cell displays the C-phase differential 5th harmonic current component.
REFHV LoZ Diff
REFHV LoZ Diff 04 0D Data
This cell displays the low impedance REF differential current for the HV winding.
REFHV LoZ Bias
REFHV LoZ Bias 04 0E Data
This cell displays the low impedance REF bias current for the HV winding.
REFLV LoZ Diff
REFLV LoZ Diff 04 0F Data
This cell displays the low impedance REF differential current for the LV winding.
REFLV LoZ Bias
REFLV LoZ Bias 04 10 Data
This cell displays the low impedance REF bias current for the LV winding.
B28 P64x-TM-EN-4.1

DESCRIPTION
REFTV LoZ Diff
REFTV LoZ Diff 04 11 Data.
This cell displays the low impedance REF differential current for the TV winding.
REFTV LoZ Bias
REFTV LoZ Bias 04 12 Data
This cell displays the low impedance REF bias current for the TV winding.
REFAuto LoZ Diff
REFAuto LoZ Diff 04 13 Data
This cell displays the low impedance REF differential current for autotransformer configuration.
REFAuto LoZ Bias
REFAuto LoZ Bias 04 14 Data
This cell displays the low impedance REF bias current for autotransformer configuration.
REFHV HiZ Diff
REFHV HiZ Diff 04 15 Data
This cell displays the high impedance REF current for the HV winding.
REFLV HiZ Diff
REFLV HiZ Diff 04 16 Data
This cell displays the high impedance REF current for the LV winding.
REFTV HiZ Diff
REFTV HiZ Diff 04 17 Data
This cell displays the high impedance REF current for the TV winding.
REFAuto HiZ Diff
REFAuto HiZ Diff 04 18 Data
This cell displays the high impedance REF current for autotransformer configuration.
IREF HV 2H Mag
IREF HV 2H Mag 04 19 Data
This cell displays the magnitude of the REF 2nd harmonic current component for the HV winding
IREF LV 2H Mag
IREF LV 2H Mag 04 1A Data
This cell displays the magnitude of the REF 2nd harmonic current component for the LV winding.
IREF TV 2H Mag
IREF TV 2H Mag 04 1B Data
This cell displays the magnitude of the REF 2nd harmonic current component for the TV winding.
IREF Auto 2H Mag
IREF Auto 2H Mag 04 1C Data
This cell displays the magnitude of the REF 2nd harmonic current component for autotransformer configuration.
Thermal Overload 04 27 Sub-Heading
This sub-heading relates to thermal overload measurements.
Hot Spot T
Hot Spot T 04 28 Data
[Courier Number (°C)]
This cell displays the Hot Spot temperature.
Top Oil T
Top Oil T 04 2A Data
This cell displays the Top oil temperature.
No
Reset Thermal 04 2B No Yes
[Indexed String]
This command resets the Thermal State.
Ambient T
Ambient T 04 2C Data
This cell displays the ambient temperature measurement.
TOL Pretrip left
TOL Pretrip left 04 2D Data
This cell displays the number of minutes left to trip under Thermal Over Load
LOL status
LOL status 04 2F Data
This cell displays the accumulated loss of life measurement in hours.
No
Reset LOL 04 30 No
Yes
P64x-TM-EN-4.1 B29

DESCRIPTION
[Indexed String]
This command resets the Loss Of Life accumulator.
Rate of LOL
Rate of LOL 04 31 Data
This cell displays the rate of Loss of Life measurement.
LOL Aging Factor
LOL Aging Factor 04 32 Data
This cell displays the Loss of Life Aging Factor.
Lres at designed
Lres at designed 04 33 Data
This cell displays the life remaining in hours. It is referenced to the hottest-spot temperature and is updated per hour.
FAA,m
FAA,m 04 34 Data
This cell displays the average aging acceleration factor and is updated per day.
Lres at FAA,m
Lres at FAA,m 04 35 Data
This cell displays the life remaining in hours. It is referenced to the average aging acceleration factor. This is updated per day.
Volts/Hz 04 38 Sub-Heading
This sub-heading relates to overfluxing measurements.
Volts/Hz 3ph
Volts/Hz 3ph 04 39 Data
[Courier Number (PU)]
This cell displays the per unit Volts/Hz for the 3-phase VT
V/Hz W1 pretrip
V/Hz W1 pretrip 04 3A Data
This cell displays the number of minutes left to trip under Overfluxing protection for the 3-phase VT
V/Hz W1 Thermal
V/Hz W1 Thermal 04 3B Data
This cell displays the thermal state in percent due to overfluxing for the 3-phase VT
No
V/Hz W1 Reset 04 3C No Yes
[Indexed String]
This command resets the overfluxing protection for the 3-phase VT
Volts/Hz 1ph
Volts/Hz 1ph 04 3D Data
[Courier Number (PU)]
This cell displays the per unit Volts/Hz for the 1-phase VT
V/Hz W2 pretrip
V/Hz W2 pretrip 04 3E Data
This cell displays the number of minutes left to trip under Overfluxing protection for the 1-phase VT
V/Hz W2 Thermal
V/Hz W2 Thermal 04 3F Data
No
V/Hz W2 Reset 04 40 No Yes
[Indexed String]
This command resets the overfluxing protection for the 1-phase VT
RTD 1
RTD 1 04 60 Data
This cell displays the label of RTD 1.
RTD 2
RTD 2 04 61 Data
RTD 3
RTD 3 04 62 Data
RTD 4
RTD 4 04 63 Data
RTD 5
RTD 5 04 64 Data
B30 P64x-TM-EN-4.1

DESCRIPTION
RTD 6
RTD 6 04 65 Data
RTD 7
RTD 7 04 66 Data
RTD 8
RTD 8 04 67 Data
RTD 9
RTD 9 04 68 Data
RTD 10
RTD 10 04 69 Data
RTD 1 label
RTD 2 label
RTD 3 label
RTD 4 label
RTD 5 label
RTD Open Cct 04 6A 0 RTD 6 label
RTD 7 label
RTD 8 label
RTD 9 label
RTD 10 label
This cell displays the open circuit status of the first eight RTDs. The Open Cct alarms are latched.
RTD 1 label
RTD 2 label
RTD 3 label
RTD 4 label
RTD 5 label
RTD Short Cct 04 6B 0 RTD 6 label
RTD 7 label
RTD 8 label
RTD 9 label
RTD 10 label
This cell displays the short circuit status of the frist eight RTDs. The short circuit alarms are latched.
RTD 1 label
RTD 2 label
RTD 3 label
RTD 4 label
RTD 5 label
RTD Data Error 04 6C 0 RTD 6 label
RTD 7 label
RTD 8 label
RTD 9 label
RTD 10 label
This cell displays the Data Error status of the first eight RTDs. The Data Error alarms are latched.
No
Reset RTD Flags 04 6D No Yes
[Indexed string]
This command resets the RTD alarms.
CLIO1
CLIO1 04 70 Data
This cell displays the measurement value associated with the CLIO1 input.
CLIO2
CLIO2 04 71 Data
P64x-TM-EN-4.1 B31

DESCRIPTION
CLIO3
CLIO3 04 72 Data
CLIO4
CLIO4 04 73 Data
This column contains measurement parameters
IA-1 2H Mag
IA-1 2H Mag 05 01 Data
This cell displays the magnitude of the A-phase current second harmonic component for T1
IB-1 2H Mag
IB-1 2H Mag 05 02 Data
This cell displays the magnitude of the B-phase current second harmonic component for T1
IC-1 2H Mag
IC-1 2H Mag 05 03 Data
This cell displays the magnitude of the C-phase current second harmonic component for T1
IA-2 2H Mag
IB-2 2H Mag
IC-2 2H Mag
IA-3 2H Mag
IB-3 2H Mag
IC-3 2H Mag
IA-4 2H Mag
IA-4 2H Mag 05 0A Data
IB-4 2H Mag
IB-4 2H Mag 05 0B Data
IC-4 2H Mag
IC-4 2H Mag 05 0C Data
IA-5 2H Mag
IA-5 2H Mag 05 0D Data
IB-5 2H Mag
IB-5 2H Mag 05 0E Data
IC-5 2H Mag
IC-5 2H Mag 05 0F Data
IA-HV 2H Mag
IA-HV 2H Mag 05 10 Data
This cell displays the magnitude of the A-phase current second harmonic component for the HV input
IB-HV 2H Mag
IB-HV 2H Mag 05 11 Data
B32 P64x-TM-EN-4.1

DESCRIPTION
This cell displays the magnitude of the B-phase current second harmonic component for the HV input
IC-HV 2H Mag
IC-HV 2H Mag 05 12 Data
This cell displays the magnitude of the C-phase current second harmonic component for the HV input
IA-LV 2H Mag
IA-LV 2H Mag 05 13 Data
This cell displays the magnitude of the A-phase current second harmonic component for the LV input
IB-LV 2H Mag
IB-LV 2H Mag 05 14 Data
This cell displays the magnitude of the B-phase current second harmonic component for the LV input
IC-LV 2H Mag
IC-LV 2H Mag 05 15 Data
This cell displays the magnitude of the C-phase current second harmonic component for the LV input
IA-TV 2H Mag
IA-TV 2H Mag 05 16 Data
This cell displays the magnitude of the A-phase current second harmonic component for the TV input
IB-TV 2H Mag
IB-TV 2H Mag 05 17 Data
This cell displays the magnitude of the B-phase current second harmonic component for the TV input
IC-TV 2H Mag
IC-TV 2H Mag 05 18 Data
This cell displays the magnitude of the C-phase current second harmonic component for the TV input
I0-1 2H Mag
I0-1 2H Mag 05 19 Data
This cell displays the magnitude of the zero sequence current second harmonic component for T1
I0-2 2H Mag
I0-2 2H Mag 05 1A Data
I0-3 2H Mag
I0-3 2H Mag 05 1B Data
I0-4 2H Mag
I0-4 2H Mag 05 1C Data
I0-5 2H Mag
I0-5 2H Mag 05 1D Data
IN-HV Mea 2H Mag
IN-HV Mea 2H Mag 05 20 Data
This cell displays the magnitude of the measured neutral current second harmonic component for the HV winding
IN-HV Der 2H Mag
IN-HV Der 2H Mag 05 21 Data
This cell displays the magnitude of the derived neutral current second harmonic component for the HV winding
IN-LV Mea 2H Mag
IN-LV Mea 2H Mag 05 22 Data
This cell displays the magnitude of the measured neutral current second harmonic component for the LV winding
IN-LV Der 2H Mag
IN-LV Der 2H Mag 05 23 Data
This cell displays the magnitude of the derived neutral current second harmonic component for the LV winding
IN-TV Mea 2H Mag
IN-TV Mea 2H Mag 05 24 Data
This cell displays the magnitude of the measured neutral current second harmonic component for the TV winding
IN-TV Der 2H Mag
IN-TV Der 2H Mag 05 25 Data
This cell displays the magnitude of the derived neutral current second harmonic component for the TV winding
CB CONTROL 07 00
This column controls the circuit Breaker Control configuration
CB Control by 07 01 Disabled
[Indexed String]
P64x-TM-EN-4.1 B33

DESCRIPTION
Selects the type of circuit breaker control to be used
From 0.1 to 50 in steps of 0.01
Close Pulse Time 07 02 0.5
Defines the duration of the close pulse within which CB should close when close command is issued. If CB fails to close after elapse of this
time, CB close fail alarm is set.
Trip Pulse Time 07 03 0.5
Defines the duration of the trip pulse within which CB should trip when manual or protection trip command is issued. If CB does not trip
within set Trip Pulse Time, CB failed to trip alarm is set.
Man Close Delay 07 05 10
This defines the delay time before the close pulse is executed.
CB Healthy Time 07 06 5
Settable time delay for manual closure with this circuit breaker check. If the circuit breaker does not indicate a healthy condition in this time
period following a close command then the IED will lockout and alarm. CB Healthy is required for manual and auto reclosure.
DATE AND TIME 08 00
This column contains DATE AND TIME parameters.
Date/Time 08 01
This setting defines the IED’s current date and time.
Date
Date 12/01/1998 08 N/A
12/01/1998
This setting defines the IED’s current date.
Time
Time 12:00:00 08 N/A
12:00:00
This setting defines the IED’s current time.
Disabled
IRIG-B Sync 08 04 Disabled Enabled
[Indexed String]
This cell enables or disables the IRIG-B time synchronization.
Card not fitted
Card failed
IRIG-B Status 08 05 Signal healthy
No signal
[Indexed String]
This cell displays the IRIG-B status
Dead
Battery Status 08 06 Healthy
[Indexed String]
This cell displays whether the battery is healthy or not
Disabled
Battery Alarm 08 07 Enabled Enabled
[Indexed String]
This cell enables or disables battery alarm. The battery alarm needs to be disabled when a battery is removed or not used
Disabled
Trying Server 1
Trying Server 2
Server 1 OK
SNTP Status 08 13
Server 2 OK
No response
No valid clock
[Indexed String]
This cell displays the SNTP time synchronisation status for IEC61850 or DNP3 over Ethernet versions.
Disabled
Fixed
LocalTime Enable 08 20 Flexible
Flexible
[Indexed String]
Disabled: No local time zone will be maintained
Fixed - Local time zone adjustment can be defined (all interfaces)
Flexible - Local time zone adjustment can be defined (non-local interfaces)
B34 P64x-TM-EN-4.1

DESCRIPTION
From -720 to 720 in steps of 15
LocalTime Offset 08 21 0
[Courier Number (Time Minutes)]
This setting specifies the offfset for the local time zone from -12 hours to +12 hrs in 15 minute intervals. This adjustment is applied to the time
based on the UTC/GMT master clock.
Disabled
DST Enable 08 22 Enabled Enabled
[Indexed String]
This setting turns daylight saving time adjustment on or off.
30 or 60
DST Offset 08 23 60
This setting defines the daylight saving offset used for the local time adjustment.
First
Second
Third
DST Start 08 24 Last
Fourth
Last
[Indexed String]
This setting specifies the week of the month in which daylight saving time adjustment starts.
Sunday
Monday
Tuesday
Wednesday
DST Start Day 08 25 Sunday
Thursday
Friday
Saturday
[Indexed String]
This setting specifies the day of the week in which daylight saving time adjustment starts
January
February
March
April
May
June
DST Start Month 08 26 March July
August
September
October
November
December
[Indexed String]
This setting specifies the month in which daylight saving time adjustment starts
DST Start Mins 08 27 60
Setting to specify the time of day in which daylight saving time adjustment starts. This is set relative to 00:00 hrs on the selected day when
time adjustment is to start
First
Second
Third
DST End 08 28 Last
Fourth
Last
[Indexed String]
This setting specifies the week of the month in which daylight saving time adjustment ends
Sunday
Monday
Tuesday
Wednesday
DST End Day 08 29 Sunday
Thursday
Friday
Saturday
[Indexed String]
This setting specifies the day of the week in which daylight saving time adjustment ends.
P64x-TM-EN-4.1 B35

DESCRIPTION
January
February
March
April
May
June
DST End Month 08 2A October July
August
September
October
November
December
[Indexed String]
This setting specifies the month in which daylight saving time adjustment ends.
DST End Mins 08 2B 60
This setting specifes the time of day in which daylight saving time adjustment ends. This is set relative to 00:00 hrs on the selected day when
time adjustment is to end.
UTC
RP1 Time Zone 08 30 UTC Local
[Indexed String]
Setting for the rear port 1 interface to specify if time synchronization received will be local or universal time co-ordinated.
UTC
RP2 Time Zone 08 31 UTC Local
[Indexed String]
Setting for the rear port 2 interface to specify if time synchronization received will be local or universal time co-ordinated
UTC
DNPOE Time Zone 08 32 UTC Local
[Indexed String]
This setting specifies whether DNP3.0 over Ethernet time synchronisation is coordinated by local time or universal time.
UTC
Tunnel Time Zone 08 33 UTC Local
[Indexed String]
This setting specifies whether tunnelled Courier time synchronisation is coordinated by local time or universal time.
CONFIGURATION 09 00
This column contains all the general configuration options
No Operation
All Settings
Setting Group 1
Restore Defaults 09 01 No Operation Setting Group 2
Setting Group 3
Setting Group 4
[Indexed String]
This setting restores the chosen setting groups to factory default values. Note: Restoring defaults to all settings may result in communication
via the rear port being disrupted if the new (default) settings do not match those of the master station.
Select via Menu
Setting Group 09 02 Select via Menu Select via PSL
[Indexed String]
This setting allows you to choose whether the setting group changes are to be initiated via an Opto-input or the HMI menu.
Group 1
Group 2
Active Settings 09 03 Group 1 Group 3
Group 4
[Indexed String]
This setting selects the active settings group.
No Operation
Save
Save Changes 09 04 No Operation
Abort
[Indexed String]
This command saves all IED settings.
Copy From 09 05 Group 1 Group 1
B36 P64x-TM-EN-4.1

DESCRIPTION
Group 2
Group 3
Group 4
[Indexed String]
This setting copies settings from a selected setting group.
No Operation
Group 1
Group 2
Copy To 09 06 No Operation
Group 3
Group 4
[Indexed String]
This command allows the displayed settings to be copied to a selected setting group.
Disabled
Setting Group 1 09 07 Enabled Enabled
[Indexed String]
This setting enables or disables settings Group 1.
Disabled
Setting Group 2 09 08 Disabled Enabled
[Indexed String]
Disabled
Setting Group 3 09 09 Disabled Enabled
[Indexed String]
Disabled
Setting Group 4 09 0A Disabled Enabled
[Indexed String]
Disabled
Diff Protection 09 0C Enabled Enabled
[Indexed String]
This setting enables or disables the Current Differntial Protection.
Disabled
REF Protection 09 0E Enabled Enabled
[Indexed String]
This setting enables or disables the Restricted Earth Fault Protection.
Disabled
Overcurrent 09 10 Enabled Enabled
[Indexed String]
This setting enables or disables the Overcurrent Protection.
Disabled
Neg Sequence O/C 09 11 Enabled Enabled
[Indexed String]
This setting enables or disables the Negative Sequence Overcurrent Protection.
Disabled
Thermal Overload 09 12 Enabled Enabled
[Indexed String]
This setting enables or disables the Thermal Overload Protection.
Disabled
Earth Fault 09 13 Enabled Enabled
[Indexed String]
This setting enables or disables the Earth Fault Protection.
Disabled
Residual O/V NVD 09 16 Enabled Enabled
[Indexed String]
This setting enables or disables the Residual Overvoltage Protection.
Disabled
Overfluxing 09 18 Disabled Enabled
[Indexed String]
This setting enables or disables the Overfluxing Protection.
P64x-TM-EN-4.1 B37

DESCRIPTION
Disabled
Through Fault 09 1B Disabled Enabled
[Indexed String]
This setting enables or disables Through-fault monitoring.
Disabled
Volt Protection 09 1D Disabled Enabled
[Indexed String]
This cell enables or disables the Voltage Protection.
Disabled
Freq Protection 09 1E Enabled Enabled
[Indexed String]
This cell enables or disables the Frequency Protection.
Disabled
RTD Inputs 09 1F Enabled Enabled
[Indexed String]
This cell enables or disables Residualo Temperature Device Protection.
Disabled
CB Fail 09 20 Disabled Enabled
[Indexed String]
This cell enables or disables Circuit Breaker Fail Protection.
Disabled
Supervision 09 21 Disabled Enabled
[Indexed String]
This setting enables or disables the Supervision (VTS & CTS) functions.
Invisible
Input Labels 09 25 Visible Visible
[Indexed String]
This setting hides or unhides the Input Labels menu from the IED display.
Invisible
Output Labels 09 26 Visible Visible
[Indexed String]
This setting hides or unhides the Output Labels menu from the IED display.
Invisible
RTD Lables 09 27 Visible Visible
[Indexed String]
This setting hides or unhides the RTD Labels menu from the IED display.
Invisible
CT and VT ratios 09 28 Visible Visible
[Indexed String]
This setting hides or unhides the Transformer Ratios menu from the IED display.
Invisible
Record Control 09 29 Visible Visible
[Indexed String]
This setting hides or unhides the Record Control menu from the IED display.
Invisible
Disturb Recorder 09 2A Visible Visible
[Indexed String]
This setting hides or unhides the Disturbance Recorder menu from the IED display.
Invisible
Measure't Setup 09 2B Visible Visible
[Indexed String]
This setting hides or unhides the Measurement Setup menu from the IED display.
Invisible
Comms Settings 09 2C Visible Visible
[Indexed String]
This setting hides or unhides the Communication Settings menu from the IED display.
Invisible
Commission Tests 09 2D Visible Visible
[Indexed String]
This setting hides or unhides the Commission Tests menu from the IED display.
B38 P64x-TM-EN-4.1

DESCRIPTION
Primary
Setting Values 09 2E Primary Secondary
[Indexed String]
This setting determines the reference for all settings dependent on the transformer ratios; either referenced to the primary or the secondary.
Invisible
Control Inputs 09 2F Visible Visible
[Indexed String]
Activates the Control Input status and operation menu further on in the IED setting menu.
Disabled
CLIO Inputs 09 30 Enabled Enabled
[Indexed String]
This setting enables or disables the CLIO (Current Loop Input Output) Inputs function.
Disabled
CLIO Outputs 09 31 Enabled Enabled
[Indexed String]
This setting enables or disables the CLIO (Current Loop Input Output) Outputs function.
Invisible
Control I/P Config 09 35 Visible Visible
[Indexed String]
Sets the Control Input Configuration menu visible further on in the IED setting menu.
Invisible
Ctrl I/P Labels 09 36 Visible Visible
[Indexed String]
Sets the Control Input Labels menu visible further on in the IED setting menu.
Disabled
Enabled
Direct Access 09 39 Enabled Hotkey Only
CB Ctrl Only
[Indexed String]
This setting enables or disables direct control of the Circuit Breakers from the IED's hotkeys.
Invisible
Protocol Cfg 09 47 Visible Visible
[Indexed String]
Sets the Protocol Cfg menu visible further on in the IED setting menu.
Invisible
IEC GOOSE 09 49 Visible Visible
[Indexed String]
This setting makes the IEC 61850 GOOSE menu visible.
Invisible
Function Keys 09 50 Visible Visible
[Indexed String]
This setting enables or disables the Function Key menu.
Disabled
RP1 Read Only 09 FB Disabled Enabled
[Indexed String]
This setting enables or disables Read Only Mode for Rear Port 1.
Disabled
RP2 Read Only 09 FC Disabled Enabled
[Indexed String]
This setting enables or disables Read Only Mode for Rear Port 2.
Disabled
NIC Read Only 09 FD Disabled Enabled
[Indexed String]
This setting enables or disables Read Only Mode of the Network Interface Card for Ethernet models.
LCD Contrast 09 FF 11
This setting sets the LCD contrast.
CT AND VT RATIOS 0A 00
This column contains multiplier settings for the transformer ratios
Main VT Location 0A 01 HV HV
P64x-TM-EN-4.1 B39

DESCRIPTION
LV
TV
[Indexed String]
This setting defines the Main VT Location.
HV
LV
Aux' VT Location 0A 02 HV
TV
[Indexed String]
This setting defines the Auxiliary VT Location.
Main VT Primary 0A 03 110
[Courier Number (Voltage)]
This setting sets the main voltage transformer input primary voltage.
From 80*V1 to 140*V1 in steps of 1*V1
Main VT Sec'y 0A 04 110
This setting sets the main voltage transformer input secondary voltage.
Aux' VT Primary 0A 07 110
This setting sets the auxiliary voltage transformer input primary voltage.
Aux' VT Sec'y 0A 08 110
This setting sets the auxiliary voltage transformer input secondary voltage.
T1 CT 0A 10 Sub-Heading
This sub-heading relates to CT1
Standard
T1 Polarity 0A 11 Standard Inverted
[Indexed String]
This setting sets the polarity with respect to the other CTs
T1 Primary 0A 12 300
This setting sets the CT's primary nominal current
1 or 5
T1 Secondary 0A 13 1
This setting sets the CT's secondary nominal current
Standard
[Indexed String]
1 or 5
T2Secondary 0A 17 1
Standard
[Indexed String]
T3 Primary 0A 1A 300
1 or 5
T3 Secondary 0A 1B 1
T4 CT 0A 1C Sub-Heading
B40 P64x-TM-EN-4.1

DESCRIPTION
Standard
T4 Polarity 0A 1D Standard Inverted
[Indexed String]
T4 Primary 0A 1E 300
1 or 5
T4 Secondary 0A 1F 1
Standard
[Indexed String]
1 or 5
T5 Secondary 0A 23 1
TN1 CT 0A 58 Sub-Heading
This sub-heading relates to the HV Earth Fault CT
Standard
TN1 Polarity 0A 59 Standard Inverted
[Indexed String]
TN1 Primary 0A 5A 300
1 or 5
TN1 Secondary 0A 5B 1
TN2 CT 0A 5D Sub-Heading
This sub-heading relates to the LV Earth Fault CT
Standard
TN2 Polarity 0A 5E Standard Inverted
[Indexed String]
TN2 Primary 0A 5F 300
1 or 5
TN2 Secondary 0A 60 1
TN3 CT 0A 62 Sub-Heading
This sub-heading relates to the TV Earth Fault CT
Standard
TN3 Polarity 0A 63 Standard Inverted
[Indexed String]
TN3 Primary 0A 64 300
1 or 5
TN3 Secondary 0A 65 1
RECORD CONTROL 0B 00
P64x-TM-EN-4.1 B41

DESCRIPTION
This column contains settings for Record Controls
No
Clear Events 0B 01 No Yes
[Indexed String]
Selecting Yes clears the existing event log and generates an event which shows the events have been erased
No
Clear Faults 0B 02 No Yes
[Indexed String]
Selecting Yes erases the existing fault records
No
Clear Maint 0B 03 No Yes
[Indexed String]
Selecting Yes erases the existing maintenance records
Disabled
Alarm Event 0B 04 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of an event on alarm. Disabling this setting means that no event is generated for alarms.
Disabled
Relay O/P Event 0B 05 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of an event for a change of state of output relay contact. Disabling this setting means that no
event will be generated for any change in logic output state.
Disabled
Opto Input Event 0B 06 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of an event for a change of state of opto-input. Disabling this setting means that no event will
be generated for any change in logic input state.
Disabled
General Event 0B 07 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of general events. Disabling this setting means that no general events are generated.
Disabled
Fault Rec Event 0B 08 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of fault record events. Disabling this setting means that no event will be generated for any
fault that produces a fault record.
Disabled
Maint Rec Event 0B 09 Enabled Enabled
[Indexed String]
This setting enables or disables the generation of maintenance record events. Disabling this setting means that no event will be generated
for any occurrence that produces a maintenance record.
Disabled
Protection Event 0B 0A Enabled Enabled
[Indexed String]
This setting enables or disables the generation of protection events. Disabling this setting means that any operation of protection elements
will not be logged as an event.
No
Clear Dist Recs 0B 30 No Yes
[Indexed String]
Selecting Yes erases the existing disturbance records
From 0xFFFFFFFF to 32 in steps of 1
DDB 31 - 0 0B 40 0xFFFFFFFF
These signals can be included or excluded from being stored as a Courier event record (assuming the DDB is capable of creating an event)
B42 P64x-TM-EN-4.1

DESCRIPTION
DDB 351 - 320 0B 4A 0xFFFFFFFF
DDB 383 - 352 0B 4B 0xFFFFFFFF
DDB 415 - 384 0B 4C 0xFFFFFFFF
DDB 447 - 416 0B 4D 0xFFFFFFFF
DDB 479 - 448 0B 4E 0xFFFFFFFF
DDB 511 - 480 0B 4F 0xFFFFFFFF
P64x-TM-EN-4.1 B43

DESCRIPTION
DDB 863 - 832 0B 5A 0xFFFFFFFF
DDB 895 - 864 0B 5B 0xFFFFFFFF
DDB 927 - 896 0B 5C 0xFFFFFFFF
DDB 959 - 928 0B 5D 0xFFFFFFFF
DDB 991 - 960 0B 5E 0xFFFFFFFF
DDB 1023 - 992 0B 5F 0xFFFFFFFF
DDB 1055-1024 0B 60 0xFFFFFFFF
B44 P64x-TM-EN-4.1

DESCRIPTION
DDB 1375-1344 0B 6A 0xFFFFFFFF
DDB 1407-1376 0B 6B 0xFFFFFFFF
DDB 1439-1408 0B 6C 0xFFFFFFFF
DDB 1471-1440 0B 6D 0xFFFFFFFF
DDB 1503-1472 0B 6E 0xFFFFFFFF
DDB 1535-1504 0B 6F 0xFFFFFFFF
DDB 1887-1856 0B 7A 0xFFFFFFFF
DDB 1919-1888 0B 7B 0xFFFFFFFF
DDB 1951-1920 0B 7C 0xFFFFFFFF
DDB 1983-1952 0B 7D 0xFFFFFFFF
P64x-TM-EN-4.1 B45

DESCRIPTION
DDB 2015-1984 0B 7E 0xFFFFFFFF
DDB 2047-2016 0B 7F 0xFFFFFFFF
DISTURB RECORDER 0C 00
This column contains settings for the Disturbance Recorder
From 0.1 to 10.5 in steps of 0.01
Duration 0C 52 1.5
[Courier Number (Time)]
This setting sets the overall recording time.
From 0 to 100 in steps of 0.1
Trigger Position 0C 54 33.3
[Courier Number (%)]
This setting sets the trigger point as a percentage of the duration. For example, the default setting, which is set to 33.3% (of 1.5s) gives 0.5s
pre-fault and 1s post fault recording times.
Single
Trigger Mode 0C 56 Single Extended
[Indexed String]
When set to single mode, if a further trigger occurs whilst a recording is taking place, the recorder will ignore the trigger. However, if this has
been set to Extended, the post trigger timer will be reset to zero, thereby extending the recording time.
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
Analog Channel 1 0C 58 G31 IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
B46 P64x-TM-EN-4.1

DESCRIPTION
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
This setting selects any available analogue input to be assigned to this channel.
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
Analog Channel 2 0C 59 G31 IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
Analog Channel 3 0C 5A G31
IA-1
IB-1
IC-1
IN-1
P64x-TM-EN-4.1 B47

DESCRIPTION
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
Analog Channel 4 0C 5B G31 IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
B48 P64x-TM-EN-4.1

DESCRIPTION
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
Analog Channel 5 0C 5C G31
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
P64x-TM-EN-4.1 B49

DESCRIPTION
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
Analog Channel 6 0C 5D G31 IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
Analog Channel 7 0C 5E G31 VCN
Vx
IA-1
B50 P64x-TM-EN-4.1

DESCRIPTION
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
Analog Channel 8 0C 5F G31
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
P64x-TM-EN-4.1 B51

DESCRIPTION
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
Analog Channel 9 0C 60 G31 IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
B52 P64x-TM-EN-4.1

DESCRIPTION
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
AnalogChannel 10 0C 61 G31 IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
AnalogChannel 11 0C 62 G31
VBN
P64x-TM-EN-4.1 B53

DESCRIPTION
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
AnalogChannel 12 0C 63 G31 IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
B54 P64x-TM-EN-4.1

DESCRIPTION
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
P64x-TM-EN-4.1 B55

DESCRIPTION
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
B56 P64x-TM-EN-4.1

DESCRIPTION
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
P64x-TM-EN-4.1 B57

DESCRIPTION
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
AnalogChannel 17 0C 68 G31 IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
B58 P64x-TM-EN-4.1

DESCRIPTION
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
P64x-TM-EN-4.1 B59

DESCRIPTION
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
AnalogChannel 19 0C 6A G31 IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
AnalogChannel 20 0C 6B G31 IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
B60 P64x-TM-EN-4.1

DESCRIPTION
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
AnalogChannel 21 0C 6C G31
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
P64x-TM-EN-4.1 B61

DESCRIPTION
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
AnalogChannel 22 0C 6D G31 IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
B62 P64x-TM-EN-4.1

DESCRIPTION
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
AnalogChannel 23 0C 6E G31 IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
AnalogChannel 24 0C 6F G31
IA-1
IB-1
IC-1
IN-1
P64x-TM-EN-4.1 B63

DESCRIPTION
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
AnalogChannel 25 0C 70 G31 IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
B64 P64x-TM-EN-4.1

DESCRIPTION
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
P64x-TM-EN-4.1 B65

DESCRIPTION
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
AnalogChannel 28 0C 73 G31 VCN
Vx
IA-1
B66 P64x-TM-EN-4.1

DESCRIPTION
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
IB-4
IC-4
IA-5
P64x-TM-EN-4.1 B67

DESCRIPTION
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
VAN
VBN
VCN
Vx
IA-1
IB-1
IC-1
IN-1
IA-2
IB-2
IC-2
IN-2
IA-3
IB-3
IC-3
IN-3
IA-4
AnalogChannel 30 0C 75 G31 IB-4
IC-4
IA-5
IB-5
IC-5
IA6
IB6
IC6
IA-DIFF
IB-DIFF
IC-DIFF
IA-BIAS
IB-BIAS
IC-BIAS
LoZREF-DIFF-HV
LoZREF-BIAS-HV
LoZREF-DIFF-LV
LoZREF-BIAS-LV
B68 P64x-TM-EN-4.1

DESCRIPTION
LoZREF-DIFF-TV
LoZREF-BIAS-TV
LoZREF-DIFF-AUTO
LoZREF-BIAS-AUTO
HiZREF-I-HV
HiZREF-I-LV
HiZREF-I-TV
HiZREF-I-Auto
Frequency
VAB
VBC
[Indexed String]
Not used (i.e. nothing recorded for the channel)
Digital Input 1 0C 80 Output R1 See separate G32 DDB Table
[Indexed String]
The digital channels may monitor any of the opto isolated inputs or output contacts, in addition to a number of internal IED digital signals,
such as protection starts, LEDs etc.
No Trigger
Trigger L/H
Input 1 Trigger 0C 81 No Trigger
Trigger H/L
[Indexed String]
Any of the digital channels may be selected to trigger the disturbance recorder on either a low to high or a high to low transition.
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Input 3 Trigger 0C 85 Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Input 5 Trigger 0C 89 No Trigger Trigger L/H
Trigger H/L
P64x-TM-EN-4.1 B69

DESCRIPTION
[Indexed String]
Digital Input 6 0C 8A Output R6 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 6 Trigger 0C 8B No Trigger
Trigger H/L
[Indexed String]
Digital Input 7 0C 8C Output R7 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 7 Trigger 0C 8D No Trigger
Trigger H/L
[Indexed String]
Digital Input 8 0C 8E Output R8 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 8 Trigger 0C 8F No Trigger
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
Digital Input 10 0C 92 Input L3 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
B70 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
Digital Input 14 0C 9A Input L7 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 14 Trigger 0C 9B No Trigger
Trigger H/L
[Indexed String]
Digital Input 15 0C 9C Input L8 See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 15 Trigger 0C 9D No Trigger
Trigger H/L
[Indexed String]
Digital Input 16 0C 9E Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 16 Trigger 0C 9F No Trigger
Trigger H/L
[Indexed String]
Digital Input 17 0C A0 Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 17 Trigger 0C A1 No Trigger
Trigger H/L
[Indexed String]
P64x-TM-EN-4.1 B71

DESCRIPTION
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
Digital Input 22 0C AA Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 22 Trigger 0C AB No Trigger
Trigger H/L
[Indexed String]
Digital Input 23 0C AC Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 23 Trigger 0C AD No Trigger
Trigger H/L
[Indexed String]
Digital Input 24 0C AE Unused Not used (i.e. nothing recorded for the channel)
B72 P64x-TM-EN-4.1

DESCRIPTION
See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 24 Trigger 0C AF No Trigger
Trigger H/L
[Indexed String]
Digital Input 25 0C B0 Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 25 Trigger 0C B1 No Trigger
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
[Indexed String]
No Trigger
Trigger L/H
Trigger H/L
[Indexed String]
Digital Input 30 0C BA Unused
See separate G32 DDB Table
P64x-TM-EN-4.1 B73

DESCRIPTION
[Indexed String]
No Trigger
Trigger L/H
Input 30 Trigger 0C BB No Trigger
Trigger H/L
[Indexed String]
Digital Input 31 0C BC Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 31 Trigger 0C BD No Trigger
Trigger H/L
[Indexed String]
Digital Input 32 0C BE Unused See separate G32 DDB Table
[Indexed String]
No Trigger
Trigger L/H
Input 32 Trigger 0C BF No Trigger
Trigger H/L
[Indexed String]
MEASURE'T SETUP 0D 00
This column contains settings for the measurement setup
HV Winding 3Ph + N Current
LV Winding 3Ph + N Current
TV Winding 3Ph + N Current
3 Ph-neutral Voltage
Power
Default Display 0D 01 User Banner Date and Time
Description
Plant Reference
Frequency
Access Level
[Indexed String]
This cell is used to show the default display option.
Primary
Local Values 0D 02 Primary Secondary
[Indexed String]
This setting controls whether local measured values (via HMI or front port) are displayed as primary or secondary quantities.
Primary
Remote Values 0D 03 Primary Secondary
[Indexed String]
This setting controls whether remote measured values (via rear comms ports) are displayed as primary or secondary quantities.
VA
VB
VC
Vx
IA1
Measurement Ref 0D 04 IA1 IB1
IC1
IA2
IB2
IC2
IA3
B74 P64x-TM-EN-4.1

DESCRIPTION
IB3
IC3
IA4
IB4
IC4
IA5
IB5
IC5
VAB
VBC
[Indexed String]
This setting sets the phase reference for all angular measurements (for Measurements 1 only).
Measurement Mode 0D 05 0
[Unsigned Integer]
This setting is used to control the signing of the real and reactive power quantities.
Fix Dem Period 0D 06 30
[Unsigned Integer]
This setting defines the length of the fixed demand window.
Roll Sub Period 0D 07 30
[Unsigned Integer]
The rolling demand window consists of several smaller sub periods. This setting defines the length of the sub period.
Num Sub Periods 0D 08 1
[Unsigned Integer]
This setting is used to set the number of rolling demand sub periods.
0 or 1
Remote 2 Values 0D 0B Primary
[Indexed String]
This setting controls whether measured values from the second rear communication port are displayed as primary or secondary quantities.
COMMUNICATIONS 0E 00
This column contains general communications settings
Courier
IEC870-5-103
RP1 Protocol 0E 01 Modbus
DNP 3.0
[Indexed String]
Indicates the communications protocol that will be used on the rear communications port.
RP1 Address 0E 02 255
[Unsigned integer (16 bits)]
This setting sets the address of RP1.
RP1 Address 0E 02 1
RP1 Address 0E 02 1
RP1 Address 0E 02 1
RP1 InactivTimer 0E 03 15
[Courier Number (Time-minutes)]
This setting defines the period of inactivity on RP1 before the IED reverts to its default state.
9600 bits/s
19200 bits/s
RP1 Baud Rate 0E 04 19200 bits/s
38400 bits/s
[Indexed String]
P64x-TM-EN-4.1 B75

DESCRIPTION
This setting sets the communication speed between the IED RP1 port and the master station. It is important that both IED and master station
are set at the same speed setting. This cell is applicable for the non-Courier protocols.
9600 bits/s
RP1 Baud Rate 0E 04 19200 bits/s 19200 bits/s
[Indexed String]
1200 bits/s
2400 bits/s
4800 bits/s
RP1 Baud Rate 0E 04 19200 bits/s 9600 bits/s
19200 bits/s
38400 bits/s
[Indexed String]
Odd
Even
RP1 Parity 0E 05 None
None
[Indexed String]
This setting controls the parity format used in the data frames of RP1. It is important that both IED and master station are set with the same
parity setting.
Odd
Even
RP1 Parity 0E 05 None
None
[Indexed String]
This setting controls the parity format used in the data frames of RP1. It is important that both IED and master station are set with the same
parity setting.
RP1 Meas Period 0E 06 15
This setting controls the time interval that the IED will use between sending measurement data to the master station for IEC60870-5-103
versions.
Copper
RP1 PhysicalLink 0E 07 Copper Fibre Optic
[Indexed String]
This cell defines whether an electrical EIA(RS) 485 or fibre optic connection is being used for communication between the master station and
IED. This cell is only visible if a fibre optic board is fitted.
Disabled
RP1 Time Sync 0E 08 Disabled Enabled
[Indexed String]
This setting is for DNP3.0 versions only. If set to Enabled the master station can be used to synchronize the time on the IED via RP1. If set to
Disabled either the internal free running clock or IRIG-B input are used.
(Modbus only)
Standard
Modbus IEC Time 0E 09 Standard
Reverse
[Indexed String]
When ‘Standard IEC’ is selected the time format complies with IEC60870-5-4 requirements such that byte 1 of the information is transmitted
first, followed by bytes 2 through to 7. If ‘Reverse’ is selected the transmission of information is reversed.
Disabled
Monitor Blocking
RP1 CS103Blcking 0E 0A Disabled
Command Blocking
[Indexed String]
This cell sets the blocking type for IEC60870-5-103. With monitor blocking, reading of the status information and disturbance records is not
permitted. When in this mode the IED returns a “termination of general interrogation” message to the master statio
K-Bus OK
EIA485 OK
RP1 Card Status 0E 0B
Fibre Optic OK
[Indexed String]
This setting displays the communication type and status of RP1
K-Bus
RP1 Port Config 0E 0C K-Bus
EIA485 (RS485)
B76 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
This seting selects the type of physical protocol for RP1 - either K-bus or RS485.
IEC60870 FT1.2
RP1 Comms Mode 0E 0D IEC60870 FT1.2 10-bit no parity
[Indexed String]
This setting determines the serial communication mode.
9600 bits/s
19200 bits/s
RP1 Baud Rate 0E 0E 19200 bits/s
38400 bits/s
[Indexed String]
This cell controls the communication speed between IED and master station. It is important that both IED and master station are set at the
same speed setting. This cell is applicable for the Courier protocol.
Meas Scaling 0E 0F Primary
[Indexed String]
This setting determines the scaling type of analogue quantities - in terms of primary, secondary or normalised, for DNP3 models
DNP Need Time 0E 11 10
This setting sets the duration of time waited before requesting another time sync from the master. DNP 3.0 versions only.
DNP App Fragment 0E 12 2048
[Unsigned Integer]
This setting sets the maximum message length (application fragment size) transmitted by the IED for DNP 3.0 versions.
DNP App Timeout 0E 13 2
This setting sets the maximum waiting time between sending a message fragment and reciving confirmation from the master. DNP 3.0
versions only.
DNP SBO Timeout 0E 14 10
This setting sets the maximum waiting time between receiving (sending?) a select command and awaiting an operate confirmation from the
master. DNP 3.0 versions only.
DNP Link Timeout 0E 15 0
This setting sets the maximum waiting time for a Data Link Confirm from the master. A value of 0 means data link support disabled. DNP 3.0
versions only.
UCA 2.0
UCA 2.0 GOOSE
NIC Protocol 0E 1F IEC61850 IEC61850
DNP3.0
[Indexed String]
This cell indicates whether IEC 61850 or DNP 3.0 over Ethernet are used on the rear Ethernet port.
NIC MAC Address
NIC MAC Address 0E 22 Ethernet MAC Addr
This setting displays the MAC address of the rear Ethernet port, if applicable.
NIC Tunl Timeout 0E 64 5.00 min
[Courier Number (time-minutes)]
This setting sets the maximum waiting time before an inactive tunnel to the application software is reset. DNP 3.0 over Ethernet versions
only.
Alarm
Event
NIC Link Report 0E 6A Alarm
None
[Indexed String]
This setting defines how a failed or unfitted network link is reported. DNP 3.0 over Ethernet versions only.
REAR PORT2 (RP2) 0E 80 Sub-Heading
This column contains configuration settings and information for RP2
RP2 Protocol
RP2 Protocol 0E 81 Courier
This cell indicates which protocol is used on RP2
Unsupported
Card Not Fitted
RP2 Card Status 0E 84
EIA232 OK
EIA485 OK
P64x-TM-EN-4.1 B77

DESCRIPTION
K-Bus OK
[Indexed String]
This setting displays the communication type and status of RP2
EIA232 (RS232)
EIA485 (RS485)
RP2 Port Config 0E 88 EIA232 (RS232)
K-Bus
[Indexed String]
This seting selects the type of physical protocol for RP2
IEC60870 FT1.2
RP2 Comms Mode 0E 8A IEC60870 FT1.2 10-bit no parity
[Indexed String]
This setting determines the serial communication mode.
RP2 Address 0E 90 255
9600 bits/s
19200 bits/s
RP2 Baud Rate 0E 94 19200 bits/s
38400 bits/s
[Indexed String]
are set at the same speed setting.
IP Address
IP Address 0E A1 0.0.0.0
[ASCII Text]
This cell displays the IED's IP address. DNP over Ethernet versions only.
Subnet Address
Subnet Address 0E A2 0.0.0.0
[ASCII Text]
This cell displays the the LAN's subnet address on which the IED is located. DNP 3.0 over Ethernet versions only.
Gateway
Gateway 0E A4 0.0.0.0
[ASCII Text]
This cell displays the LAN's gateway address on which the IED is located. DNP 3.0 over Ethernet versions only.
0 or 1
DNP Time Synch 0E A5 Disabled
[Indexed String]
If set to ‘Enabled’ the DNP3.0 master station can be used to synchronise the IED's time clock. If set to ‘Disabled’ either the internal free
running clock, or IRIG-B input are used. DNP 3.0 over Ethernet versions only.
Meas Scaling 0E A6 Primary
[Indexed String]
This setting determines the scaling type of analogue quantities - in terms of primary, secondary or normalised, for DNP3 models.
NIC Tunl Timeout
NIC Tunl Timeout 0E A7 5
This setting sets the maximum waiting time before an inactive tunnel to the application software is reset. DNP 3.0 over Ethernet versions
only.
NIC Link Report 0E A8 Alarm
[Indexed String]
This setting defines how a failed or unfitted network link is reported. DNP 3.0 over Ethernet versions only.
NIC Link Timeout
NIC Link Timeout 0E A9 60s
This setting determines the duration of time waited, after a failed network link is detected, before communication by an alternative media
interface is attempted.
SNTP PARAMETERS 0E AA SNTP PARAMETERS
The settings in this sub-menu are for models using DNP3 over Ethernet.
SNTP Server 1
SNTP Server 1 0E AB 0.0.0.0
[ASCII Text]
This cell indicates the SNTP Server 1 address. DNP 3.0 over Ethernet versions only.
SNTP Server 2
SNTP Server 2 0E AC 0.0.0.0
[ASCII Text]
This cell indicates the SNTP Server 2 address. DNP 3.0 over Ethernet versions only.
B78 P64x-TM-EN-4.1

DESCRIPTION
SNTP Poll Rate
SNTP Poll Rate 0E AD 64s
This cell displays the SNTP poll rate interval in seconds. DNP 3.0 over Ethernet versions only.
DNP Need Time 0E B1 10
This setting sets the duration of time waited before requesting another time sync from the master. DNP 3.0 versions only.
DNP App Fragment 0E B2 2048
[Unsigned Integer]
This setting sets the maximum message length (application fragment size) transmitted by the IED for DNP 3.0 versions.
DNP App Timeout 0E B3 2
This setting sets the maximum waiting time between sending a message fragment and reciving confirmation from the master. DNP 3.0
versions only.
DNP SBO Timeout 0E B4 10
This setting sets the maximum waiting time between receiving (sending?) a select command and awaiting an operate confirmation from the
master. DNP 3.0 versions only.
SYSLOG 0E BA
From 0.0.0.0 to 223.255.255.255 in steps of 1

SysLog Pri IP 0E BB 0.0.0.0
[IP Parameters]
External Security Log Server 1 configured to monitor security logging message on the network.
Setting this cell to 0.0.0.0 disables sending security logging message to Security Log Server 1.
SysLog Sec IP 0E BC 0.0.0.0
[IP Parameters]
External Security Log Server 2 configured to monitor security logging message on the network.
Setting this cell to 0.0.0.0 disables sending security logging message to Security Log Server 2
SysLog Port 0E BD 514
The destination UDP/IP port sent to both Primary and Secondary Syslog servers.
SysLog Status
SysLog Status 0E BE Disabled
[Indexed String]
COMMISSION TESTS 0F 00
This column contains commissioning test settings
Opto I/P Status 0F 01
P64x-TM-EN-4.1 B79

DESCRIPTION
This cell displays the status of the available opto-inputs.
Opto I/P Status2 0F 02
This cell displays the status of the available opto-inputs.
Relay O/P Status 0F 03 Relay 9 (0=Not Operated, 1=Operated)
B80 P64x-TM-EN-4.1

DESCRIPTION
This cell displays the status of the available output relays.
Warning; When in Test Mode, this cell cannot be used to confirm operation of the output relays, therefore it will be necessary to monitor the
state of each contact in turn.
Test Port Status
Test Port Status 0F 05
[Binary Flag(8 bits);Indexed String]
This is an 8-bit binary string that indicates which of the LEDs are ON
LED Status
LED Status 0F 06
[Binary Flag(8 bits)]
8-bit binary string that indicates which of the LEDs are ON
Monitor Bit 1 0F 07 64
[Unsigned Integer]
The ‘Monitor Bit’ cells allow the user to select which DDB signals can be observed in the ‘Test Port Status’ cell.
[Unsigned Integer]
[Unsigned Integer]
Monitor Bit 4 0F 0A 67
[Unsigned Integer]
Monitor Bit 5 0F 0B 68
[Unsigned Integer]
Monitor Bit 6 0F 0C 69
[Unsigned Integer]
Monitor Bit 7 0F 0D 70
[Unsigned Integer]
Monitor Bit 8 0F 0E 71
[Unsigned Integer]
Disabled
Test Mode
Test Mode 0F 0F Disabled
Blocked
[Indexed String]
This cell is used to allow secondary injection testing to be performed on the IED without operation of the trip contacts. It also enables a
facility to directly test the output contacts by applying menu controlled test signals.
Test Pattern 0F 10 0 Relay 3 (0=Not Operated, 1=Operated)
P64x-TM-EN-4.1 B81

DESCRIPTION
[Binary Flag (32bits)]
This cell is used to select the output relay contacts that will be tested when the ‘Contact Test’ cell is set to ‘Apply Test’.
No Operation
Apply Test
Contact Test 0F 11 No Operation
Remove Test
[Indexed String]
This command changes the state of the output relay contacts in the Test Pattern cell. After the test has been applied the command text on
the LCD changes to ‘No Operation’ and the contacts will remain in the Test State until reset.
No Operation
Test LEDs 0F 12 No Operation Apply Test
[Indexed String]
This command illuminates the user-programmable LEDs for approximately 2 seconds, before they extinguish and the command text on the
LCD reverts to ‘No Operation’.
DDB 31 - 0
DDB 31 - 0 0F 20
[Binary Flag(32)]
This cell displays the logic state of the DDB signals
DDB 63 - 32
DDB 63 - 32 0F 21
[Binary Flag(32)]
DDB 95 - 64
DDB 95 - 64 0F 22
[Binary Flag(32)]
DDB 127 - 96
DDB 127 - 96 0F 23
[Binary Flag(32)]
DDB 159 - 128
DDB 159 - 128 0F 24
[Binary Flag(32)]
DDB 191 - 160
DDB 191 - 160 0F 25
[Binary Flag(32)]
DDB 223 - 192
DDB 223 - 192 0F 26
[Binary Flag(32)]
B82 P64x-TM-EN-4.1

DESCRIPTION
DDB 255 - 224
DDB 255 - 224 0F 27
[Binary Flag(32)]
DDB 287 - 256
DDB 287 - 256 0F 28
[Binary Flag(32)]
DDB 319 - 288
DDB 319 - 288 0F 29
[Binary Flag(32)]
DDB 351 - 320
DDB 351 - 320 0F 2A
[Binary Flag(32)]
DDB 383 - 352
DDB 383 - 352 0F 2B
[Binary Flag(32)]
DDB 415 - 384
DDB 415 - 384 0F 2C
[Binary Flag(32)]
DDB 447 - 416
DDB 447 - 416 0F 2D
[Binary Flag(32)]
DDB 479 - 448
DDB 479 - 448 0F 2E
[Binary Flag(32)]
DDB 511 - 480
DDB 511 - 480 0F 2F
[Binary Flag(32)]
DDB 543 - 512
DDB 543 - 512 0F 30
[Binary Flag(32)]
DDB 575 - 544
DDB 575 - 544 0F 31
[Binary Flag(32)]
DDB 607 - 576
DDB 607 - 576 0F 32
[Binary Flag(32)]
DDB 639 - 608
DDB 639 - 608 0F 33
[Binary Flag(32)]
DDB 671 - 640
DDB 671 - 640 0F 34
[Binary Flag(32)]
DDB 703 - 672
DDB 703 - 672 0F 35
[Binary Flag(32)]
DDB 735 - 704
DDB 735 - 704 0F 36
[Binary Flag(32)]
DDB 767 - 736
DDB 767 - 736 0F 37
[Binary Flag(32)]
DDB 799 - 768
DDB 799 - 768 0F 38
[Binary Flag(32)]
DDB 831 - 800
DDB 831 - 800 0F 39
[Binary Flag(32)]
DDB 863 - 832
DDB 863 - 832 0F 3A
[Binary Flag(32)]
P64x-TM-EN-4.1 B83

DESCRIPTION
DDB 895 - 864
DDB 895 - 864 0F 3B
[Binary Flag(32)]
DDB 927 - 896
DDB 927 - 896 0F 3C
[Binary Flag(32)]
DDB 959 - 928
DDB 959 - 928 0F 3D
[Binary Flag(32)]
DDB 991 - 960
DDB 991 - 960 0F 3E
[Binary Flag(32)]
DDB 1023 - 992
DDB 1023 - 992 0F 3F
[Binary Flag(32)]
DDB 1055-1024
DDB 1055-1024 0F 40
[Binary Flag(32)]
DDB 1087-1056
DDB 1087-1056 0F 41
[Binary Flag(32)]
DDB 1119-1088
DDB 1119-1088 0F 42
[Binary Flag(32)]
DDB 1151-1120
DDB 1151-1120 0F 43
[Binary Flag(32)]
DDB 1183-1152
DDB 1183-1152 0F 44
[Binary Flag(32)]
DDB 1215-1184
DDB 1215-1184 0F 45
[Binary Flag(32)]
DDB 1247-1216
DDB 1247-1216 0F 46
[Binary Flag(32)]
DDB 1279-1248
DDB 1279-1248 0F 47
[Binary Flag(32)]
DDB 1311-1280
DDB 1311-1280 0F 48
[Binary Flag(32)]
DDB 1343-1312
DDB 1343-1312 0F 49
[Binary Flag(32)]
DDB 1375-1344
DDB 1375-1344 0F 4A
[Binary Flag(32)]
DDB 1407-1376
DDB 1407-1376 0F 4B
[Binary Flag(32)]
DDB 1439-1408 0F 4C 0xFFFFFFFF
DDB 1471-1440 0F 4D 0xFFFFFFFF
B84 P64x-TM-EN-4.1

DESCRIPTION
DDB 1503-1472 0F 4E 0xFFFFFFFF
DDB 1535-1504 0F 4F 0xFFFFFFFF
DDB 1567-1536 0F 50 0xFFFFFFFF
DDB 1887-1856 0F 5A 0xFFFFFFFF
DDB 1919-1888 0F 5B 0xFFFFFFFF
DDB 1951-1920 0F 5C 0xFFFFFFFF
DDB 1983-1952 0F 5D 0xFFFFFFFF
DDB 2015-1984 0F 5E 0xFFFFFFFF
DDB 2047-2016 0F 5F 0xFFFFFFFF
OPTO CONFIG 11 00
This column contains opto-input configuration settings
TN1
Global Nominal V 11 01 48-54V TN2
TN3
P64x-TM-EN-4.1 B85

DESCRIPTION
[Indexed String]
This setting sets the nominal DC voltage for all opto-inputs. The Custom settign allows you to set each opto-input to any voltage value
individually.
24/27V
30/34V
48/54V
Opto Input 1 11 02 48-54V
110/125V
220/250V
[Indexed String]
This cell sets the nominal voltage for opto-input 1
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
110/125V
220/250V
[Indexed String]
24/27V
Opto Input 9 11 0A 48-54V
30/34V
B86 P64x-TM-EN-4.1

DESCRIPTION
48/54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 10 11 0B 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 11 11 0C 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 12 11 0D 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 13 11 0E 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 14 11 0F 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 15 11 10 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 16 11 11 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 17 11 12 48-54V
110/125V
220/250V
[Indexed String]
P64x-TM-EN-4.1 B87

DESCRIPTION
24/27V
30/34V
48/54V
Opto Input 18 11 13 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 19 11 14 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 20 11 15 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 21 11 16 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 22 11 17 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 23 11 18 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 24 11 19 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 25 11 1A 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
Opto Input 26 11 1B 48-54V 48/54V
110/125V
220/250V
B88 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 27 11 1C 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 28 11 1D 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 29 11 1E 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 30 11 1F 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 31 11 20 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 32 11 21 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 33 11 22 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 34 11 23 48-54V
110/125V
220/250V
[Indexed String]
24/27V
Opto Input 35 11 24 48-54V 30/34V
48/54V
P64x-TM-EN-4.1 B89

DESCRIPTION
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 36 11 25 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 37 11 26 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 38 11 27 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 39 11 28 48-54V
110/125V
220/250V
[Indexed String]
24/27V
30/34V
48/54V
Opto Input 40 11 29 48-54V
110/125V
220/250V
[Indexed String]
OptoFilter Ctrl1 11 50 0xFFFFFFFF Opto 11 Input State (0=Off, 1=Energised)
B90 P64x-TM-EN-4.1

DESCRIPTION
This setting determines whether the in-built noise filter is off or on for each opto-input.
OptoFilter Ctrl2 11 51 0xFF
This setting determines whether the in-built noise filter is off or on for each opto-input.
Standard 60%-80%
Characteristic 11 80 Standard 60%-80% 50% - 70%
[Indexed String]
This setting selects the opto-inputs' pick-up and drop-off characteristics.
CONTROL INPUTS 12 00
This column contains settings for the type of control input
Control Input 1 (0 = Reset, 1 = Set)
Ctrl I/P Status 12 01 Control Input 4 (0 = Reset, 1 = Set)
P64x-TM-EN-4.1 B91

DESCRIPTION
This cell sets or resets the Control Inputs by scrolling and changing the status of selected bits. Alternatively, each of the 32 Control inputs can
be set and reset using the individual Control Input cells.
No Operation
Set
Control Input 1 12 02 No Operation
Reset
[Indexed String]
This command sets or resets Control Input 1
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
B92 P64x-TM-EN-4.1

DESCRIPTION
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Control Input 9 12 0A No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 10 12 0B No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 11 12 0C No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 12 12 0D No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 13 12 0E No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 14 12 0F No Operation
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
Control Input 20 12 15 No Operation No Operation
P64x-TM-EN-4.1 B93

DESCRIPTION
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
Control Input 25 12 1A No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 26 12 1B No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 27 12 1C No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 28 12 1D No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 29 12 1E No Operation
Reset
[Indexed String]
No Operation
Set
Control Input 30 12 1F No Operation
Reset
[Indexed String]
No Operation
Set
Reset
[Indexed String]
No Operation
Set
B94 P64x-TM-EN-4.1

DESCRIPTION
Reset
[Indexed String]
CTRL I/P CONFIG 13 00
This column contains configuration settings for the control inputs.
Control Input 01
Control Input 02
Control Input 03
Control Input 04
Control Input 05
Control Input 06
Control Input 07
Control Input 08
Control Input 09
Control Input 10
Control Input 11
Control Input 12
Control Input 13
Control Input 14
Control Input 15
Control Input 16
Hotkey Enabled 13 01 0xFFFFFFFF Control Input 17
Control Input 18
Control Input 19
Control Input 20
Control Input 21
Control Input 22
Control Input 23
Control Input 24
Control Input 25
Control Input 26
Control Input 27
Control Input 28
Control Input 29
Control Input 30
Control Input 31
Control Input 32
This setting allows the control inputs to be individually assigned to the Hotkey menu. The hotkey menu allows the control inputs to be set,
reset or pulsed without the need to enter the CONTROL INPUTS column.
Latched
Control Input 1 13 10 Latched Pulsed
[Indexed String]
This setting configures the control input as either ‘latched’ or ‘pulsed’.
ON/OFF
SET/RESET
Ctrl Command 1 13 11 SET/RESET IN/OUT
ENABLED/DISABLED
[Indexed String]
This setting allows you to select the text to be displayed on the hotkey menu.
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
Control Input 3 13 18 Latched
Pulsed
P64x-TM-EN-4.1 B95

DESCRIPTION
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
Control Input 4 13 1C Latched Pulsed
[Indexed String]
ON/OFF
SET/RESET
Ctrl Command 4 13 1D SET/RESET IN/OUT
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
B96 P64x-TM-EN-4.1

DESCRIPTION
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
P64x-TM-EN-4.1 B97

DESCRIPTION
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
Ctrl Command 21 13 61 SET/RESET ON/OFF
B98 P64x-TM-EN-4.1

DESCRIPTION
SET/RESET
IN/OUT
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
Ctrl Command 27 13 79 SET/RESET
SET/RESET
P64x-TM-EN-4.1 B99

DESCRIPTION
IN/OUT
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
Latched
[Indexed String]
Latched
[Indexed String]
Latched
[Indexed String]
ON/OFF
SET/RESET
ENABLED/DISABLED
[Indexed String]
FUNCTION KEYS 17 00
This column contains the function key definitions
Fn Key Status
Fn Key Status 17 01 0
This cell displays the status of each function key
Fn Key 1 17 02 Unlocked
[Indexed String]
This setting activates function key 1. The ‘Lock’ setting allows a function key, which is in toggle mode, to be locked in its current active state.
B100 P64x-TM-EN-4.1

DESCRIPTION
0 or 1
Fn Key 1 Mode 17 03 Toggled
[Indexed String]
This setting sets the function key mode. In ‘Toggle’ mode, a single key press set sand latches the function key output to ‘high’ or ‘low’ in the
PSL. In ‘Normal’ mode the function key output remains high as long as key is pressed.
Fn Key 1 Label 17 04 Function Key 1
This setting lets you change the function key text to something more suitable for the application.
[Indexed String]
0 or 1
Fn Key 2 Mode 17 06 Normal
[Indexed String]
[Indexed String]
0 or 1
[Indexed String]
Fn Key 3 Label 17 0A Function Key 3
Fn Key 4 17 0B Unlocked
[Indexed String]
0 or 1
Fn Key 4 Mode 17 0C Normal
[Indexed String]
Fn Key 4 Label 17 0D Function Key 4
Fn Key 5 17 0E Unlocked
[Indexed String]
0 or 1
Fn Key 5 Mode 17 0F Toggle
[Indexed String]
[Indexed String]
0 or 1
[Indexed String]
[Indexed String]
P64x-TM-EN-4.1 B101

DESCRIPTION
0 or 1
[Indexed String]
Fn Key 8 17 17 Locked
[Indexed String]
0 or 1
[Indexed String]
Fn Key 9 17 1A Unlocked
[Indexed String]
0 or 1
Fn Key 9 Mode 17 1B Normal
[Indexed String]
Fn Key 9 Label 17 1C Function Key 9
Fn Key 10 17 1D Unlocked
[Indexed String]
0 or 1
Fn Key 10 Mode 17 1E Normal
[Indexed String]
Fn Key 10 Label 17 1F Function Key 10
IED CONFIGURATOR 19 00
This column contains settings for the IEC61850 IED Configurator
No Action
Switch Conf.Bank 19 05 No Action Switch Banks
[Indexed String]
This command allows you to switch between the current configuration, held in the Active Memory Bank to the configuration held in the
Inactive Memory Bank.
No action
Restore MCL 19 0A No Action (0) Restore MCL
[Indexed String]
This command lets you restore the MCL (MiCOM Control Language).
Active Conf.Name
Active Conf.Name 19 10 Not Available
[ASCII Text]
This cell displays the name of the configuration in the Active Memory Bank (usually taken from the SCL file).
Active Conf.Rev
Active Conf.Rev 19 11 Not Available
[ASCII Text]
This cell displays the configuration revision number of the configuration in the Active Memory Bank (usually taken from the SCL file).
Active Conf.Ed
Active Conf.Ed 19 12
[ASCII text]
IEC61850 Active Configuration Edition
Inact.Conf.Name
Inact.Conf.Name 19 20 Not Available
[ASCII Text]
This cell displays the name of the configuration in the Inactive Memory Bank (usually taken from the SCL file).
B102 P64x-TM-EN-4.1

DESCRIPTION
Inact.Conf.Rev
Inact.Conf.Rev 19 21 Not Available
[ASCII Text]
This cell displays the configuration revision number of the configuration in the Inactive Memory Bank (usually taken from the SCL file).
Inact.Conf.Ed
Inact.Conf.Ed 19 22
[ASCII text]
IEC61850 Inactive Configuration Edition
IP PARAMETERS 19 30 Sub-Heading
The data in this sub-heading relates to the IEC61850 IP parameters
IP Address
IP Address 19 31 0.0.0.0
[ASCII Text]
This cell displays the IED's IP address.
Subnet Address
Subnet Address 19 32 0.0.0.0
[ASCII Text]
Ths cell displays the subnet mask, which defines the subnet on which the IED is located.
Gateway
Gateway 19 33 0.0.0.0
[ASCII Text]
Ths cell displays the gateway address of the LAN on which the IED is located.
SNTP PARAMETERS 19 40 Sub-Heading
The data and settings under this sub-heading relate to the IEC61850 SNTP parameters
SNTP Server 1
SNTP Server 1 19 41 0.0.0.0
[ASCII Text]
This cell displays the IP address of the primary SNTP server.
SNTP Server 2
SNTP Server 2 19 42 0.0.0.0
[ASCII Text]
This cell displays the IP address of the secondary SNTP server.
IEC 61850 SCL 19 50 Sub-Heading
IEC61850 versions only.
IED Name
IED Name 19 51 Not Available
[ASCII Text]
This setting displays the unique IED name used on the IEC 61850 network (usually taken from the SCL file).
IEC 61850 GOOSE 19 60 Sub-Heading
IEC61850 versions only.
GoEna 19 70 00000000(bin)
This setting enables the GOOSE publisher settings.
Publish Sim/Test 19 71 00000000(bin)
This setting allows the test pattern to be sent in the GOOSE message. With ‘Pass Through’, the data in the GOOSE message is sent as normal.
With ‘Forced’, the data sent in the GOOSE message follows the ‘VOP Test Pattern’ setting.
No
Ignore Test Flag 19 73 No Yes
[ASCII Text]
This cell allows you to ignore the test flag, if set.
PROTOCOL CFG 1A 00
This column contains Protocol Configuration settings
IEC60870-5-103 1A 01
0 or 1
Config Mode 1A 07 0
[Indexed String]
Setting to control the CS103 mode. Setting "Fixed" behaves as per original design, reporting CS103 information as per CS103 L&F info. When
"Std + UserConfig" is selected, this results in only the CS103 information that meets the CS103 Std Fun type is reported by default. All other
CS103 information is then user configurable. Please Note: CS103 information will follow the GI flag as per L&F. If it is configures for GI in L&F,
it will create spontaneous information plus GI, if not flagged for GI, it will only produce spontanous information.
DDB 31 - 0 1A 40 0x00000000 Low order word stored in 2nd register
[Binary Flag (32-Bit)]
Control the DDB signals enabled in CS103 response messages
P64x-TM-EN-4.1 B103

DESCRIPTION
DDB 95 - 64 1A 42 0x0000000F Low order word stored in 2nd register
DDB 351 - 320 1A 4A 0x00000000 Low order word stored in 2nd register
DDB 383 - 352 1A 4B 0x00000000 Low order word stored in 2nd register
DDB 415 - 384 1A 4C 0x00000000 Low order word stored in 2nd register
DDB 447 - 416 1A 4D 0x00000000 Low order word stored in 2nd register
DDB 479 - 448 1A 4E 0x20000000 Low order word stored in 2nd register
DDB 511 - 480 1A 4F 0x00000000 Low order word stored in 2nd register
B104 P64x-TM-EN-4.1

DESCRIPTION
DDB 959 - 928 1A 5D 0x01F00000 Low order word stored in 2nd register
P64x-TM-EN-4.1 B105

DESCRIPTION
B106 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B107

DESCRIPTION
SECURITY CONFIG 25 00
This column contains settings for the Cyber Security configuration
ACCESS ONLY FOR
User Banner 25 01 Second character in low order 8 bits
AUTHORISED USERS
[ASCII Text (32 characters)]
With this setting, you can enter text for the NERC compliant banner.
Attempts Limit 25 02 2
[Unsigned Integer (16 Bits)]
This setting defines the maximum number of failed password attempts before action is taken.
Lockout Period 25 04 5
Defines the time duration for which the user is blocked after exceeding the maximum attempts limit in Seconds
Disabled
Front Port 25 05 Enabled Enabled
[Indexed String]
This setting enables or disables the physical Front Port.
Disabled
Rear Port 1 25 06 Enabled Enabled
[Indexed String]
This setting enables or disables the primary physical rear port (RP1).
Disabled
Rear Port 2 25 07 Enabled Enabled
[Indexed String]
This setting enables or disables the secondary physical rear port (RP2).
Disabled
Ethernet Port 25 08 Enabled Enabled
[Indexed String]
This setting enables or disables the physical Ethernet Port
Disabled
Courier Tunnel 25 09 Enabled Enabled
[Indexed String]
This setting enables or disables the logical tunnelled Courier port
Disabled
IEC61850 25 0A Enabled Enabled
[Indexed String]
This setting enables or disables the logical IEC61850 port.
Disabled
DNP3 OE 25 0B Enabled Enabled
[Indexed String]
This setting enables or disables the logical DNP3 over Ethernet port.
No Operation
All Sessions
Front Port
HMI
Force Logout 25 0C No Operation
Rear Port1
Rear Port2
Tunnel Courier
[Indexed String]
The user in role of ADMINISTRATOR can force logout all the active sessions or on dedicated interface.
Attempts Remain
Attempts Remain 25 11 2
This cell displays the number of password attempts remaining
B108 P64x-TM-EN-4.1

DESCRIPTION
Blk Time Remain
Blk Time Remain 25 12 0
Blocking time remaining in Seconds
LOCAL SESSIONS 25 1A
FP InactivTimer 25 1B 10
A configurable period of time when a user is automatically logged out on Front Port if they remain inactive for. Once log out, resetting of the
entered access-level back to 0.
Setting the inactivity timer settings to 0 disables session management and the automatic-logout feature is disabled (i.e. a logged in user
remains logged in forever; or until the user manually logs out)
UI InactivTimer 25 1C 10
A configurable period of time when a user is automatically logged out on UI if they remain inactive for. Once log out, resetting of the entered
access-level back to 0.
Setting the inactivity timer settings to 0 disables session management and the automatic-logout feature is disabled (i.e. a logged in user
remains logged in forever; or until the user manually logs out)
RBAC 25 30
Server + Device
Server only
Auth. Method 25 31 Server + Device
Device only
[Indexed string]
Configure the active Authentication method
RADIUS Pri IP 25 32 0.0.0.0
[IP Parameters]
RADIUS Server 1 configured to provide Server Authentication service.
Setting this cell to 0.0.0.0 disables RADUIS Server 1
RADIUS Sec IP 25 33 0.0.0.0
[IP Parameters]
RADIUS Server 2 configured to provide Server Authentication service.
Setting this cell to 0.0.0.0 disables RADUIS Server 2
RADIUS Auth Port 25 34 1812
The destination TCP/IP port sent to both Primary and Secondary RADUIS servers.
On
On-blocked
Test
Test-blocked
Off
RADIUS Security 25 35 PAP EAP-TTLS-PAP
EAP-TTLS-MSCHAP2
PAP
EAP-PEAP-MSCHAP2
PAP EAP-TTLS-PAP
[Indexed string]
Option for choosing authentication scheme used by RADIUS server.
EAP-TTLS-MSCHAP2 - EAP Transport Layer Security (EAP-TLS) is an IETF open standard that uses the TLS protocol. Using TLS, a secure channel
is then established between Relay and Radius server.
The Microsoft version of Challenge-Handshake Authentication Protocol Version 2 (MS-CHAPv2) is a password based authentication method
that utilises the user account credentials (username and password) stored in Active Directory Domain Services to authenticate.
EAP-TTLS-MSCHAP2 represents the MSCHAPv2 method transferred over EAP-TTLS channel.
PAP - Password Authentication Protocol (PAP) is a password-based authentication protocol. PAP is considered a weak authentication scheme.
Protected Extensible Authentication Protocol (PEAP) is a protocol that encapsulates the Extensible Authentication Protocol (EAP) within an
encrypted and authenticated TLS tunnel.
EAP-PEAP-MSCHAP2 - represents the EAP-MSCHAPv2 method encapsulated by PEAP.
P64x-TM-EN-4.1 B109

DESCRIPTION
PAP EAP-TTLS-PAP - represents the PAP protocol transferred over EAP-TTLS channel.
RADIUS Timeout 25 36 2
[Courier Number (time-seconds)]
RADIUS Retries 25 37 10
Define the times Relay will retry to request authentication from Radius server if no response.
RADIUS Secret 25 38 ChangeMe1#
[ASCII Password (16)]
The shared secret is used by Radius server to verify the identity of IED.
Disabled
HMI-Only
Local
Bypass Auth. 25 40 Disabled
Remote
Local & Remote
[Indexed string]
Allow a user, when logged in as an administrator, to bypass the authentication requirements for specific interfaces.
RADIUS Status
RADIUS Status 25 FE Disabled
[Indexed string]
Reporting the status of Radius server.
Security Code
Security Code 25 FF
[ASCII Text (16 characters)]
This cell displays the 16-character security code required when requesting a recovery password. UI only cell.
USER ALARMS 28 00
This column contains settings for the User Alarms
Manual Reset 28 01 0x00000000
Set the user alarm is maunal reset or self reset
Labels 28 10 Sub-Heading
B110 P64x-TM-EN-4.1

DESCRIPTION
This sub-heading contains the user alarm labels
User Alarm 1 28 11 User Alarm 1
Here you can set a text label to describe each user alarm
User Alarm 10 28 1A User Alarm 10
User Alarm 11 28 1B User Alarm 11
User Alarm 12 28 1C User Alarm 12
User Alarm 13 28 1D User Alarm 13
User Alarm 14 28 1E User Alarm 14
User Alarm 15 28 1F User Alarm 15
P64x-TM-EN-4.1 B111

DESCRIPTION
User Alarm 26 28 2A User Alarm 26
User Alarm 27 28 2B User Alarm 27
User Alarm 28 28 2C User Alarm 28
User Alarm 29 28 2D User Alarm 29
User Alarm 30 28 2E User Alarm 30
User Alarm 31 28 2F User Alarm 31
CTRL I/P LABELS 29 00
This column contains settings for the Control Input Labels
Control Input 1 29 01 Control Input 1
In this cell you can enter a text label to describe the control input. This text is displayed when a control input is accessed by the hotkey menu
and in the programmable scheme logic description of the control input.
B112 P64x-TM-EN-4.1

DESCRIPTION
Control Input 10 29 0A Control Input 10
Control Input 11 29 0B Control Input 11
Control Input 12 29 0C Control Input 12
Control Input 13 29 0D Control Input 13
Control Input 14 29 0E Control Input 14
Control Input 15 29 0F Control Input 15
P64x-TM-EN-4.1 B113

DESCRIPTION
Control Input 26 29 1A Control Input 26
Control Input 27 29 1B Control Input 27
Control Input 28 29 1C Control Input 28
Control Input 29 29 1D Control Input 29
Control Input 30 29 1E Control Input 30
Control Input 31 29 1F Control Input 31
GROUP 1: SYSTEM
30 00
CONFIG
This column contains a range of system configuration settings .
HV+LV
Winding Config 30 01 HV+LV+TV HV+LV+TV
[Indexed String]
This setting indicates if the protected transformer is a two or three winding transformer.
Conventional
Winding Type 30 02 Conventional Auto
[Indexed String]
B114 P64x-TM-EN-4.1

DESCRIPTION
The winding type may be configured as Conventional or Auto. This setting is just for information.
"01"
"001"
"011"
"00001"
HV CT Terminals 30 03 01 (P642) "00011"
"00111"
"01011"
"01111"
[Indexed String]
This setting defines the current inputs to be used on the HV side. Each digit corresponds to a terminal. From right to left the current inputs are
T1, T2
0 = disabled, 1 = enabled.
"01"
"001"
"011"
"00001"
HV CT Terminals 30 03 001 (P643) "00011"
"00111"
"01011"
"01111"
[Indexed String]
T1, T2, T3
"01"
"001"
"011"
"00001"
HV CT Terminals 30 03 00001 (P645) "00011"
"00111"
"01011"
"01111"
[Indexed String]
T1, T2, T3, T4, T5
"10"
"110"
"100"
"10000"
LV CT Terminals 30 04 10 (P645) "11000"
"11100"
"11010"
"11110"
[Indexed String]
This setting defines the current inputs to be used on the LV side. Each digit corresponds to a terminal. From right to left the current inputs are
T1, T2
"10"
"110"
"100"
"10000"
LV CT Terminals 30 04 100 (P643) "11000"
"11100"
"11010"
"11110"
[Indexed String]
T1, T2, T3
LV CT Terminals 30 04 10000 (P645) "10"
P64x-TM-EN-4.1 B115

DESCRIPTION
"110"
"100"
"10000"
"11000"
"11100"
"11010"
"11110"
[Indexed String]
T1, T2, T3, T4, T5
"010"
"00100"
"00110"
TV CT Terminals 30 05 010 (P643)
"01100"
"01110"
[Indexed String]
This setting defines the current inputs to be used on the TV side. Each digit corresponds to a terminal. From right to left the current inputs are
T1, T2, T3
"010"
"00100"
"00110"
TV CT Terminals 30 05 00100 (P645)
"01100"
"01110"
[Indexed String]
This setting defines the current inputs to be used on the TV side. Each digit corresponds to a terminal. From right to left the current inputs are
T1, T2, T3, T4, T5
Used for floating point settings. The setting value is
represented as the number of step increments from
the minimum value (see also G35).
Ref Power S 30 07 100MVA Data formatted as per data type G1.
I.e. Setting value = (setting minimum) + ((register
value) x (setting step size))
This sets the Reference power used by the differential function to calculate the ratio correction factors
Ref Vector Group 30 08 0
[Unsigned Integer]
This setting is used to provide a reference vector group to which all other vector group definitions are referred.
D-Delta
Y-Wye
HV Connection 30 09 Y-Wye
Z-Zigzag
[Indexed String]
This setting defines the power transformer's HV winding connection type.
Grounded
HV Grounding 30 0A Grounded Ungrounded
[Indexed String]
This setting defines whether the winding is earthed or not earthed. It is used to decide whetehr zero sequency filtering is required or not
Grounded = zero sequence filtering required
Ungrounded = zero sequency filtering not required
From 100V to 1MV in steps of 1V
HV Nominal 30 0B 220kV
This setting determines the voltage of the HV winding, mid-tap voltage of the on-load tap changer, or no-load tap changer tap voltage.
HV Rating 30 0C 100MVA Data formatted as per data type G1.
B116 P64x-TM-EN-4.1

DESCRIPTION
This rating is used by the thermal overload function if the monitored winding is set to HV.
% Reactance 30 0D 0.1 Data formatted as per data type G1.
[Indexed String]
This sets the transformer leakage reactance.
LV Vector Group 30 0E 0
[Unsigned Integer]
This setting defines the vector group of the LV winding with respect to the reference vector group. It is is used to correct the phase shift
between HV and LV windings.
D-Delta
Y-Wye
LV Connection 30 0F Y-Wye
Z-Zigzag
[Indexed String]
This setting defines the power transformer's LV winding connection type.
Grounded
LV Grounding 30 10 Grounded Ungrounded
[Indexed String]
This setting defines whether the winding is earthed or not earthed. It is used to decide whether zero sequency filtering is required or not.
LV Nominal 30 11 220kV
This setting determines the voltage of the LV winding, mid-tap voltage of the on-load tap changer, or no-load tap changer tap voltage.
LV Rating 30 12 100MVA Data formatted as per data type G1.
This rating is used by the thermal overload function if the monitored winding is set to LV.
TV Vector Group 30 13 0 Data formatted as per data type G1.
[Indexed String]
This setting defines the vector group of the TV winding with respect to the reference vector group. It is is used to correct the phase shift
between HV and TV windings.
D-Delta
Y-Wye
TV Connection 30 14 Y-Wye
Z-Zigzag
[Indexed String]
This setting defines the power transformer's TV winding connection type.
Grounded
TV Grounding 30 15 Grounded Ungrounded
[Indexed String]
This setting defines whether the winding is earthed or not earthed. It is used to decide whetehr zero sequency filtering is required or not
TV Nominal 30 16 220kV
This setting determines the voltage of the TV winding, mid-tap voltage of the on-load tap changer, or no-load tap changer tap voltage.
TV Rating 30 17 100MVA represented as the number of step increments from
P64x-TM-EN-4.1 B117

DESCRIPTION
This rating is used by the thermal overload function if the monitored winding is set to TV.
DIFF 30 20 Sub-Heading
DIFF element for HV scaling factor
I.e. divide register value by 1000 to obtain actual
value.
Match Factor CT1 30 21 Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
Frequency 0.000 - 655.000Hz Resolution 0.001Hz
[Courier Number ()]
This cell displays the CT1 ratio correction factor used by the differential function.
value.
[Courier Number ()]
value.
[Courier Number ()]
value.
[Courier Number ()]
value.
[Courier Number ()]
HV REF 30 30 Sub-Heading
REF element for HV scaling factor
value.
Scaling Fac CT2 30 31 Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
This cell displays the CT2 ratio scaling factor used by the REF HV.
value.
[Courier Number ()]
value.
[Courier Number ()]
value.
Scaling Fac CTN1 30 34 Set by relay
Time Interval 0.000 - 655.000s Resolution 1ms
B118 P64x-TM-EN-4.1

DESCRIPTION
[Courier Number ()]
This cell displays the CTN1 ratio scaling factor used by the REF HV.
LV REF 30 38 Sub-Heading
REF element for LV scaling factor
value.
[Courier Number ()]
This cell displays the CT2 ratio scaling factor used by the REF LV.
value.
Scaling Fac CT3 30 3A Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
value.
Scaling Fac CT4 30 3B Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
value.
Scaling Fac CTN2 30 3C Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
This cell displays the CTN2 ratio scaling factor used by the REF LV.
TV REF 30 40 Sub-Heading
REF element for TV scaling factor
value.
[Courier Number ()]
This cell displays the CT2 ratio scaling factor used by the REF TV.
value.
[Courier Number ()]
This cell displays the CT4 ratio scaling factor used by the REF TV.
value.
Scaling Fac CTN3 30 43 Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
This cell displays the CTN3 ratio scaling factor used by the REF TV.
Auto REF 30 48 Sub-Heading
REF element for AUTO scaling factor
value.
[Courier Number ()]
This cell displays the CT2 ratio scaling factor used by the REF AUTO.
value.
Scaling Fac CT3 30 4A Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
P64x-TM-EN-4.1 B119

DESCRIPTION
value.
Scaling Fac CT4 30 4B Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
value.
Scaling Fac CT5 30 4C Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
value.
Scaling Fac CTN1 30 4D Set by relay Time Interval 0.000 - 655.000s Resolution 1ms
[Courier Number ()]
This cell displays the CTN1 ratio scaling factor used by the REF AUTO.
Standard ABC
Phase Sequence 30 5E Standard ABC Reverse ACB
[Indexed String]
This sets the phase rotation. It affects the positive and negative sequence quantities calculated by the relay. It also affects functions that are
dependent on phase quantities.
No Swap
A-B Swapped
VT Reversal 30 5F No Swap B-C Swapped
C-A Swapped
[Indexed String]
For applications where 2-phase current inputs are swapped.
No Swap
A-B Swapped
CT1 Reversal 30 60 No Swap B-C Swapped
C-A Swapped
[Indexed String]
No Swap
A-B Swapped
C-A Swapped
[Indexed String]
No Swap
A-B Swapped
C-A Swapped
[Indexed String]
No Swap
A-B Swapped
C-A Swapped
[Indexed String]
No Swap
A-B Swapped
C-A Swapped
[Indexed String]
GROUP 1: DIFF 31 00
B120 P64x-TM-EN-4.1

DESCRIPTION
PROTECTION
This column contains settings for the current differential protection
Disabled
Trans Diff 31 01 Enabled Enabled
[Indexed String]
This setting enables or disables differential protection.
Simple
Set Mode 31 02 Simple Advance
[Indexed String]
This setting defines the mode for setting certain parameters
Advanced: you can enable or disable zero sequence filtering manually and define HS1 and HS2
Simple: Zero sequence fitering, HS1 and HS2 are enabled or disabled automatically
Is1 31 03 0.2 Data formatted as per data type G1.
This sets the minimum differential current threshold required for the transformer differential protection to trip.
K1 31 04 0.3 Data formatted as per data type G1.
[Courier Number (Percentage)]
This setting defines the gradient of the first slope in the bias current characteristic
Is2 31 05 1 Data formatted as per data type G1.
This defines the bias current threshold at which the second slope of the bias current characteristic becomes active.
K2 31 06 0.8 Data formatted as per data type G1.
This setting defines the gradient of the second slope in the bias current characteristic
tDiff 31 07 0s Data formatted as per data type G1.
This sets the time delay for the transformer differential protection
Is-CTS 31 08 1.5 Data formatted as per data type G1.
If a CT failure is detected, Is1 setting is increased to Is-CTS to increase the restrain region of the bias current characteristic
Is-HS1 31 10 10.00pu Used for floating point settings. The setting value is
P64x-TM-EN-4.1 B121

DESCRIPTION
This setting defines the first High set threshold on the bias curent characteristic. This setting is only used in advanced mode.
Disabled
HS2 Status 31 11 Enabled Enabled
[Indexed String]
Enable or Disabled High set element two
Is-HS2 31 12 32 Data formatted as per data type G1.
This setting defines the second High set threshold on the bias curent characteristic. This setting is only used in advanced mode.
Disabled
Transient Bias 31 13 Enabled Enabled
[Indexed String]
This setting enables or disables the transient bias factor
Disabled
Zero seq filt HV 31 20 Enabled Enabled
[Indexed String]
This setting enables or disables zero sequence filtering on the HV winding. This setting is only visible and settable in advanced mode.
Disabled
Zero seq filt LV 31 21 Enabled Enabled
[Indexed String]
This setting enables or disables zero sequence filtering on the LV winding. This setting is only visible and settable in advanced mode.
Disabled
Zero seq filt TV 31 22 Enabled Enabled
[Indexed String]
This setting enables or disables zero sequence filtering on the TV winding. This setting is only visible and settable in advanced mode.
Disabled
IH2 Diff Block 31 28 Enabled Enabled
[Indexed String]
This setting enables or disables second harmonic blocking
IH2 Diff Set 31 29 0.2 Data formatted as per data type G1.
This seting defines the second harmonic blocking threshold
Disabled
Cross blocking 31 2A Enabled Enabled
[Indexed String]
This setting enables or disables cross blocking (cross blocking is where a 2nd harmonic blocking signal from any one phase, blocks all three
phases)
Disabled
CT saturation 31 2B Enabled Enabled
[Indexed String]
This setting enables or disables CT saturation detection
Disabled
No Gap 31 2C Disabled Enabled
[Indexed String]
This setting enables or disables CT Gap detection
IH5 Diff Block 31 33 Enabled Disabled
B122 P64x-TM-EN-4.1

DESCRIPTION
Enabled
[Indexed String]
This settting enables or disables 5th harmonic blocking
IH5 Diff Set 31 34 0.35 Data formatted as per data type G1.
This setting defines the fifth harmonic blocking threshold
Disabled
Circuitry Fail 31 40 Disabled Enabled
[Indexed String]
Thi setting enables or disables the circuitry fail alarm
Is-cctfail 31 41 0.1 Data formatted as per data type G1.
This seting defines the minimum differential threshold of the circuitry fail alarm
K-cctfail 31 42 0.1 Data formatted as per data type G1.
This setting defines the slope gradient for the circuitry fail alarm function
CctFail Delay 31 43 5s Data formatted as per data type G1.
This sets the circuitry fail alarm time delay
0 or 1
Phase Comparison 31 50 Disabled
[Indexed String]
Enable or disable phase comparison block function
Phase Comp Ratio 31 51 0.5
Phase Comparison algorithm takes effect only if Ibias > Ratio * Is2
GROUP 1: REF
32 00
PROTECTION
This column contains settings for the Restricted Earth Fault function.
Disabled
LowZ REF
REF HV status 32 01 LowZ REF
HighZ REF
[Indexed String]
This setting disables REF or selects the type of REF to be used (Low Impedance or High Impedance) for the HV winding
HV Winding
CT2
HV CT Terminals 32 02 HV Winding CT3
CT4
[Indexed String]
This sets which CT terminals shall be used for LowZ REF HV calculation.
IREF> Is1 HV 32 03 0.09
P64x-TM-EN-4.1 B123

DESCRIPTION
This sets the minimum differential current threshold required for the HV REF protection to trip.
IREF> Is2 HV 32 04 0.9 Data formatted as per data type G1.
This defines the bias current threshold at which the second slope of the bias current characteristic becomes active for the HV REF protection
IREF> k1 HV 32 05 0 Data formatted as per data type G1.
This setting defines the gradient of the first slope in the bias current characteristic for the HV REFprotection. A 0% setting gives maximum
sensitivity for internal faults.
IREF> k2 HV 32 06 1.5 Data formatted as per data type G1.
This setting defines the gradient of the second slope in the bias current characteristic for the HV REFprotection.
tREF HV 32 07 0s Data formatted as per data type G1.
This sets the time delay for the HV REF protection element
HV IREF>Is 32 08 0.09 Data formatted as per data type G1.
Minimum differential threshold of the HV HighZ restricted earth fault protection
0 or 1
IH2 REF Block HV 32 09 Disabled
[Indexed String]
This setting enables or disables second harmonic blocking for the HV element
IH2 REF Set HV 32 0A 0.2
This setting defines the second harmonic blocking threshold for the HV element
From 0.1A to 10A in steps of 0.01A
IREF> Is HV 32 0B 1A
This setting sets the current threshold at which 2nd harmonic blocking is removed for the HV REF element.
Disabled
LowZ REF
REF LV status 32 20 Disabled
HighZ REF
[Indexed String]
This setting disables REF or selects the type of REF to be used (Low Impedance or High Impedance) for the LV winding
B124 P64x-TM-EN-4.1

DESCRIPTION
LV Winding
CT2
LV CT Terminals 32 21 LV Winding CT3
CT4
[Indexed String]
This sets which CT terminals shall be used for LowZ REF LV calculation.
IREF> Is1 LV 32 22 0.09 Data formatted as per data type G1.
This sets the minimum differential current threshold required for the LV REF protection to trip.
IREF> Is2 LV 32 23 0.9 Data formatted as per data type G1.
This defines the bias current threshold at which the second slope of the bias current characteristic becomes active for the LV REF protection
IREF> k1 LV 32 24 0 Data formatted as per data type G1.
This setting defines the gradient of the first slope in the bias current characteristic for the LV REFprotection. A 0% setting gives maximum
IREF> k2 LV 32 25 1.5 Data formatted as per data type G1.
This setting defines the gradient of the second slope in the bias current characteristic for the LV REFprotection.
tREF LV 32 26 0s Data formatted as per data type G1.
This sets the time delay for the LV REF protection element
LV IREF>Is 32 27 0.09 Data formatted as per data type G1.
Minimum differential threshold of the LV HighZ restricted earth fault protection
0 or 1
IH2 REF Block LV 32 29 Disabled
[Indexed String]
This setting enables or disables second harmonic blocking for the LV element
IH2 REF Set LV 32 2A 0.2
This setting defines the second harmonic blocking threshold for the LV element
P64x-TM-EN-4.1 B125

DESCRIPTION
IREF> Is LV 32 2B 1A
This setting sets the current threshold at which 2nd harmonic blocking is removed for the LV REF element.
Disabled
LowZ REF
REF TV status 32 30 Disabled
HighZ REF
[Indexed String]
This setting disables REF or selects the type of REF to be used (Low Impedance or High Impedance) for the TV winding
TV Winding
CT2
TV CT Terminals 32 31 TV Winding
CT4
[Indexed String]
This sets which CT terminals shall be used for LowZ REF TV calculation.
IREF> Is1 TV 32 32 0.09 Data formatted as per data type G1.
This sets the minimum differential current threshold required for the TV REF protection to trip.
IREF> Is2 TV 32 33 0.9 Data formatted as per data type G1.
This defines the bias current threshold at which the second slope of the bias current characteristic becomes active for the TV REF protection
IREF> k1 TV 32 34 0 Data formatted as per data type G1.
This setting defines the gradient of the first slope in the bias current characteristic for the TV REFprotection. A 0% setting gives maximum
IREF> k2 TV 32 35 1.5 Data formatted as per data type G1.
This setting defines the gradient of the second slope in the bias current characteristic for the TV REFprotection.
tREF TV 32 36 0s Data formatted as per data type G1.
This sets the time delay for the TV REF protection element
TV IREF>Is 32 37 0.09 Data formatted as per data type G1.
B126 P64x-TM-EN-4.1

DESCRIPTION
Minimum differential threshold of the TV HighZ restricted earth fault protection
0 or 1
IH2 REF Block TV 32 39 Disabled
[Indexed String]
This setting enables or disables second harmonic blocking for the TV element
IH2 REF Set TV 32 3A 0.2
This setting defines the second harmonic blocking threshold for the TV element
IREF> Is TV 32 3B 1A
This setting sets the current threshold at which 2nd harmonic blocking is removed for the TV REF element.
Disabled
LowZ REF
REF Auto status 32 40 LowZ REF
HighZ REF
[Indexed String]
This setting disables REF or selects the type of REF to be used (Low Impedance or High Impedance) for autotransformer configuration
IREF> Is1 AT 32 42 0.09 Data formatted as per data type G1.
This sets the minimum differential current threshold required for the TV REF protection to trip for autotransformer configuration
IREF> Is2 AT 32 43 0.9 Data formatted as per data type G1.
This defines the bias current threshold at which the second slope of the bias current characteristic becomes active for the REF protection for
autotransformer configuration
IREF> k1 AT 32 44 0 Data formatted as per data type G1.
This setting defines the gradient of the first slope in the bias current characteristic for the REFprotection for autotransformer configuration.
A 0% setting gives maximum sensitivity for internal faults.
IREF> k2 AT 32 45 1.5 Data formatted as per data type G1.
This setting defines the gradient of the second slope in the bias current characteristic for the REFprotection for autotransformer
configuration
tREF AT 32 46 0s Data formatted as per data type G1.
This sets the time delay for the REF protection element for autotransformer configuration
Auto IREF>Is 32 47 0.09 represented as the number of step increments from
P64x-TM-EN-4.1 B127

DESCRIPTION
Minimum differential threshold of the AUTO HighZ restricted earth fault protection
0 or 1
IH2 REF Block AT 32 49 Disabled
[Indexed String]
This setting enables or disables second harmonic blocking for autotransformer configuration
IH2 REF Set AT 32 4A 0.2
This setting defines the second harmonic blocking threshold for autotransformer configuration
IREF> Is AT 32 4B 1A
This setting sets the current threshold at which 2nd harmonic blocking is removed for autotransformer configuration
GROUP 1: NEG SEQ O/C 34 00
This column contains settings for the Negative Sequence Overcurrent
Disabled
T1
T2
T3
T4
NPS O/C 1 34 01 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Negative Sequence Overcurrent 1
Disabled
I2>1 Status 34 02 Disabled Enabled
[Indexed String]
Enables or disables stage 1 of NPS OC 1
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
I2>1 Function 34 03 IEC S Inverse RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Slelect the stage 1 of NPSOC element 1 time characteristic
Non-Directional
Directional Fwd
I2>1 Direction 34 04 Non-Directional
Directional Rev
[Indexed String]
Determines the direction of measurement for this element
I2>1 Current Set 34 05 0.2*I1 Data formatted as per data type G1.
Current pick-up setting for the stage 1 NPS element 1
I2>1 Time Delay 34 06 10s represented as the number of step increments from
B128 P64x-TM-EN-4.1

DESCRIPTION
Operating time delay for the stage 1 NPS overcurrent element 1
I2>1 TMS 34 07 1s Data formatted as per data type G1.
Setting for the time multiplier setting to adjust the operating time of IEC IDMT characteristic
I2>1 Time Dial 34 08 1 Data formatted as per data type G1.
Setting for the time dial setting to adjust the operating time of IEEE/US IDMT characteristic
I2>1 K(RI) 34 09 1 Data formatted as per data type G1.
Setting for the time multiplier setting to adjust the oprating time for the RI IDMT characteristic
DT
I2>1 Reset Char 34 0A DT Inverse
[Indexed String]
Setting to determine the type of reset/release characteristic of the IEEE/US curves
I2>1 tReset 34 0B 0s Data formatted as per data type G1.
Setting that determine the reset/release time for definite time reset characteristic
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Slelect stage 2 of NPSOC element 1 time characteristic
Non-Directional
Directional Fwd
P64x-TM-EN-4.1 B129

DESCRIPTION
Directional Rev
[Indexed String]
I2>2 Time Delay 34 16 10s Data formatted as per data type G1.
DT
[Indexed String]
Disabled
[Indexed String]
Enables or disables stage 3 NPS definite time element 1
Non-Directional
Directional Fwd
B130 P64x-TM-EN-4.1

DESCRIPTION
Directional Rev
[Indexed String]
Disabled
[Indexed String]
Enables or disables stage 4 NPS definite time element 1
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I2>4 Time Delay 34 2A 10s Data formatted as per data type G1.
I2>1 VTS Block
I2>2 VTS Block
I2> VTS Block 34 2D 15 I2>3 VTS Block
I2>4 VTS Block
[Binary Flag]
Logic settings that determine whether VT supervision will block selected negative sequence overcurrent stages. VTS Block only affects
directional overcurrent protection. Setting 0 allows continued non-directional operation
I2> V2pol Set 34 2E 5*V1 Data formatted as per data type G1.
The minimum threshold above which the relay must detect a polarizing voltage for the negative phase sequence directional elements to
operate
I2> Char Angle 34 2F -60° Used for floating point settings. The setting value is
P64x-TM-EN-4.1 B131

DESCRIPTION
Characteristic angle for directionalized NPS fault protection
Disabled
T1
T2
T3
P642: T2
T4
NPS O/C 2 34 31 P643: T3
T5
P645: T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Negative Sequence Overcurrent 2
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I2>1 TMS 34 37 1s the minimum value (see also G35).
B132 P64x-TM-EN-4.1

DESCRIPTION
DT
[Indexed String]
Disabled
[Indexed String]
Enables or disables stage 2 NPS OC 2
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
P64x-TM-EN-4.1 B133

DESCRIPTION
DT
[Indexed String]
Disabled
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I2>3 Current Set 34 53 0.2 Data formatted as per data type G1.
B134 P64x-TM-EN-4.1

DESCRIPTION
Current pick-up setting for the stage 3 NPS OC 2
I2>3 Time Delay 34 54 10 Data formatted as per data type G1.
Operating time delay for the stage 3 NPS OC 2
Disabled
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
Current pick-up setting for the stage 4 OC 2
Operating time delay for the stage 4 NPS OC2
I2>1 VTS Block
I2>2 VTS Block
I2>4 VTS Block
[Binary Flag]
I2> V2pol Set 34 5E 5*V1 Data formatted as per data type G1.
operate
I2> Char Angle 34 5F -60° Data formatted as per data type G1.
Disabled
P643: T2
NPS O/C 3 34 61 T1
P645: T3
T2
P64x-TM-EN-4.1 B135

DESCRIPTION
T3
T4
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
P643 and P645 only.
Negetive Sequence Overcurrent 3
Disabled
[Indexed String]
P643 and P645 only.
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
P643 and P645 only.
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
B136 P64x-TM-EN-4.1

DESCRIPTION
P643 and P645 only.
P643 and P645 only.
DT
[Indexed String]
P643 and P645 only.
P643 and P645 only.
Disabled
[Indexed String]
P643 and P645 only.
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
P643 and P645 only.
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
P643 and P645 only.
I2>2 Current Set 34 75 0.2*I1
P64x-TM-EN-4.1 B137

DESCRIPTION
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
DT
[Indexed String]
P643 and P645 only.
P643 and P645 only.
Disabled
[Indexed String]
P643 and P645 only.
I2>3 Direction 34 82 Non-Directional Non-Directional
B138 P64x-TM-EN-4.1

DESCRIPTION
Directional Fwd
Directional Rev
[Indexed String]
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
Disabled
[Indexed String]
P643 and P645 only.
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
P643 and P645 only.
P643 and P645 only.
P643 and P645 only.
I2>1 VTS Block
I2>2 VTS Block
I2>4 VTS Block
[Binary Flag]
P643 and P645 only.
I2> V2pol Set 34 8E 5*V1 Used for floating point settings. The setting value is
P64x-TM-EN-4.1 B139

DESCRIPTION
P643 and P645 only.
operate
I2> Char Angle 34 8F -60° Data formatted as per data type G1.
P643 and P645 only.
GROUP 1:
35 00
OVERCURRENT
This column contains settings for the overcurrent elements
Disabled
T1
T2
T3
T4
Overcurrent1 35 01 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
This setting defines which CT is used for the first overcurrent element
Disabled
I>1 Status 35 02 Disabled Enabled
[Indexed String]
Setting to enable or disable the first stage overcurrent element
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
I>1 Function 35 03 IEC S Inverse RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the first stage overcurrent element
Non-Directional
Directional Fwd
I>1 Direction 35 04 Non-Directional
Directional Rev
[Indexed String]
This setting determines the direction of measurement for the first stage element
I>1 Current Set 35 05 1 Data formatted as per data type G1.
B140 P64x-TM-EN-4.1

DESCRIPTION
Pick-up setting for the first stage overcurrent element
I>1 Time Delay 35 06 1s Data formatted as per data type G1.
Setting for the time delay for the definite time setting if selected for the first stage element
I>1 TMS 35 07 1 Data formatted as per data type G1.
Setting for the time multiplier setting to adjust the operating time of the IEC IDMT characteristic
I>1 Time Dial 35 08 1 Data formatted as per data type G1.
Setting for the time multiplier setting to adjust the operating time of the IEEE/US IDMT curves
I>1 K (RI) 35 09 1 Data formatted as per data type G1.
Setting for the time multiplier to adjust the operating time for the RI curve
DT
I>1 Reset Char 35 0A DT Inverse
[Indexed String]
I>1 tRESET 35 0B 0 Data formatted as per data type G1.
Setting that determines the reset/release time for definite time reset characteristic
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
I>2 Function 35 13 DT (DT) RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
P64x-TM-EN-4.1 B141

DESCRIPTION
Setting for the tripping characteristic for the second stage overcurrent element
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
This setting determines the direction of measurement for the second stage element
Pick-up setting for the second stage overcurrent element
Setting for the time delay for the definite time setting if selected for the second stage element.
I>2 TMS 35 17 1s Data formatted as per data type G1.
DT
[Indexed String]
I>2 tRESET 35 1B 0s Data formatted as per data type G1.
Disabled
[Indexed String]
B142 P64x-TM-EN-4.1

DESCRIPTION
Setting to enable or disable the third stage overcurrent element
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
This setting determines the direction of measurement for the third stage element
Pick-up setting for the third stage overcurrent element
Setting for the time delay for the definite time setting if selected for the third stage element
Disabled
[Indexed String]
Setting to enable or disable the fourth stage overcurrent element
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
This setting determines the direction of measurement for the fourth stage element
Pick-up setting for the fourth stage overcurrent element
I>4 Time Delay 35 2A 0s Data formatted as per data type G1.
Setting for the time delay for the definite time setting if selected for the fourth stage element.
I> Char Angle 35 2D 30° Data formatted as per data type G1.
Setting for the relay characteristic angle used for the directional decision
IH2 I> Set 35 2E 0.2
Second harmonic percent threshold for overcurrent element 1
From 1A to 32A in steps of 0.01A
IH2 I> Unblock 35 2F 4*I1
Current threshold at which 2nd harmonic blocking is removed for overcurrent element 1
P64x-TM-EN-4.1 B143

DESCRIPTION
0 or 1
IH2 Cross Block 35 30 Disabled
[Indexed String]
Block mode of second harmonic for overcurrent element 1
VTS Block I>1
VTS Block I>2
VTS Block I>3
VTS Block I>4
I> Blocking 35 31 255 2H Block I>1
2H Block I>2
2H Block I>3
2H Block I>4
[Binary Flag]
Logic Settings that determine whether blocking signals from VT supervision and second harmonic block affect certain overcurrent stages
Disabled
T1
T2
T3
P642: T2
T4
Overcurrent2 35 41 P643: T3
T5
P645: T5
HV Winding
LV Winding
TV Winding
[Indexed String]
This setting defines which CT is used for the second overcurrent element
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
B144 P64x-TM-EN-4.1

DESCRIPTION
DT
[Indexed String]
I>1 tRESET 35 4B 0s Data formatted as per data type G1.
Disabled
[Indexed String]
Setting to enable or disable the second stage overcurrent element
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I>2 Current Set 35 55 1 Used for floating point settings. The setting value is
P64x-TM-EN-4.1 B145

DESCRIPTION
I>2 Time Delay 35 56 1 Data formatted as per data type G1.
DT
[Indexed String]
I>2 tRESET 35 5B 0 Data formatted as per data type G1.
Disabled
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I>3 Current Set 35 63 10 Used for floating point settings. The setting value is
B146 P64x-TM-EN-4.1

DESCRIPTION
I>3 Time Delay 35 64 0 Data formatted as per data type G1.
Disabled
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I>4 Time Delay 35 6A 0s Data formatted as per data type G1.
I> Char Angle 35 6D 30° Data formatted as per data type G1.
IH2 I> Set 35 6E 0.2
IH2 I> Unblock 35 6F 4*I1
0 or 1
IH2 Cross Block 35 70 Disabled
[Indexed String]
VTS Block I>1
VTS Block I>2
I> Blocking 35 71 255
VTS Block I>3
VTS Block I>4
P64x-TM-EN-4.1 B147

DESCRIPTION
2H Block I>1
2H Block I>2
2H Block I>3
2H Block I>4
[Binary Flag]
Disabled
T1
T2
T3
P643: T2 T4
Overcurrent3 35 81
P645: T3 T5
HV Winding
LV Winding
TV Winding
[Indexed String]
This setting defines which CT is used for the third overcurrent element
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
From 0.02*I1 to 4*I1 in steps of 0.01*I1
I>1 Current Set 35 85 1
From 0s to 100s in steps of 0.01s
I>1 Time Delay 35 86 1
I>1 TMS 35 87 1
I>1 Time Dial 35 88 1
I>1 K (RI) 35 89 1
DT
[Indexed String]
I>1 tRESET 35 8B 0
B148 P64x-TM-EN-4.1

DESCRIPTION
Disabled
[Indexed String]
Setting to enable or disable the second stage overcurrent element
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
I>2 Function 35 93 DT (DT) RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the second stage overcurrent element
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
I>2 Current Set 35 95 1
I>2 Time Delay 35 96 1
I>2 TMS 35 97 1
I>2 Time Dial 35 98 1
I>2 K (RI) 35 99 1
DT
[Indexed String]
I>2 tRESET 35 9B 0
Disabled
I>3 Status 35 A1 Disabled Enabled
[Indexed String]
Non-Directional
Directional Fwd
I>3 Direction 35 A2 Non-Directional
Directional Rev
[Indexed String]
I>3 Current Set 35 A3 10
I>3 Time Delay 35 A4 0
P64x-TM-EN-4.1 B149

DESCRIPTION
Disabled
I>4 Status 35 A7 Disabled Enabled
[Indexed String]
Non-Directional
Directional Fwd
I>4 Direction 35 A8 Non-Directional
Directional Rev
[Indexed String]
I>4 Current Set 35 A9 10
I>4 Time Delay 35 AA 0s
From -95° to 95° in steps of 1°
I> Char Angle 35 AD 30°
IH2 I> Set 35 AE 0.2
IH2 I> Unblock 35 AF 4*I1
0 or 1
IH2 Cross Block 35 B0 Disabled
[Indexed String]
VTS Block I>1
VTS Block I>2
VTS Block I>3
VTS Block I>4
I> Blocking 35 B1 255 2H Block I>1
2H Block I>2
2H Block I>3
2H Block I>4
[Binary Flag]
V Dependant O/C 35 C0 Sub-Heading
Sub-Heading for Voltage Dependant Over Current
Disabled
Voltage Controlled OC
V Dep OC Status 35 C1 Disabled
Voltage Restrained OC
[Indexed String]
Setting to enable either V Controlled O/C or V Restrained O/C function of V Dep O/C protection
Disabled
T1
T2
T3
T4
VCO>1 35 C2 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Select the Winding type for Voltage controlled overcurrent stage 1
DT (DT)
IEC S Inverse (TMS)
VCO>1 Char 35 C3 IEC S Inverse IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
B150 P64x-TM-EN-4.1

DESCRIPTION
Rectifier (TMS)
RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the first stage voltage controlled overcurrent element
Non-Directional
Directional Fwd
VCO>1 Direction 35 C4 Non-Directional
Directional Rev
[Indexed String]
VCO>1 Curr' Set 35 C5 1 Data formatted as per data type G1.
Current pick-up setting for first stage the voltage controlled over current
VCO>1 Time Delay 35 C6 1 Data formatted as per data type G1.
VCO>1 TMS 35 C7 1 Data formatted as per data type G1.
VCO>1 Time Dial 35 C8 1 Data formatted as per data type G1.
VCO>1 K(RI) 35 C9 1 Data formatted as per data type G1.
DT
VCO>1 Reset Char 35 CA DT Inverse
[Indexed String]
VCO>1 tReset 35 CB 0s represented as the number of step increments from
P64x-TM-EN-4.1 B151

DESCRIPTION
VCO>1 Char Angle 35 CC 30° Data formatted as per data type G1.
VCO>1 V<Setting 35 CD 80 Data formatted as per data type G1.
Setting for the under voltage set for voltage controlled over current
VCO>1 K Setting 35 CE 0.25 Data formatted as per data type G1.
Setting for the multiplier
Disabled
T1
T2
T3
T4
VCO>2 35 D2 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Select the Winding type for Voltage controlled overcurrent stage 2
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
VCO>2 Char 35 D3 IEC S Inverse RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the second stage voltage controlled overcurrent element
Non-Directional
Directional Fwd
VCO>2 Direction 35 D4 Non-Directional
Directional Rev
[Indexed String]
VCO>2 Curr' Set 35 D5 1 represented as the number of step increments from
B152 P64x-TM-EN-4.1

DESCRIPTION
Current pick-up setting for second stage the voltage controlled over current
VCO>2 Time Delay 35 D6 1 Data formatted as per data type G1.
Setting for the time delay for the definite time setting if selected for the second stage element
VCO>2 TMS 35 D7 1 Data formatted as per data type G1.
VCO>2 Time Dial 35 D8 1 Data formatted as per data type G1.
VCO>2 K(RI) 35 D9 1 Data formatted as per data type G1.
DT
VCO>2 Reset Char 35 DA DT Inverse
[Indexed String]
VCO>2 tReset 35 DB 0s Data formatted as per data type G1.
VCO>2 Char Angle 35 DC 30° Data formatted as per data type G1.
VCO>2 V<Setting 35 DD 80
P64x-TM-EN-4.1 B153

DESCRIPTION
Setting for the under voltage set for voltage controlled over current
VCO>2 K Setting 35 DE 0.25 Data formatted as per data type G1.
Disabled
T1
T2
T3
T4
VRO>1 35 E2 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Select the Winding type for Voltage restrained overcurrent stage 1
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
VRO>1 Char 35 E3 IEC S Inverse RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the first stage voltage restrained overcurrent element
Non-Directional
Directional Fwd
VRO>1 Direction 35 E4 Non-Directional
Directional Rev
[Indexed String]
VRO>1 Curr' Set 35 E5 1 Data formatted as per data type G1.
[Indexed String]
Current pick-up setting for the first stage of the Voltage Restrained overcurrent protection
VRO>1 Time Delay 35 E6 1 Data formatted as per data type G1.
[Indexed String]
VRO>1 TMS 35 E7 1
B154 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
VRO>1 Time Dial 35 E8 1 Data formatted as per data type G1.
[Indexed String]
VRO>1 K(RI) 35 E9 1 Data formatted as per data type G1.
DT
VRO>1 Reset Char 35 EA DT Inverse
[Indexed String]
VRO>1 tReset 35 EB 0s Data formatted as per data type G1.
VRO>1 Angle 35 EC 30° Data formatted as per data type G1.
VRO>1 V1<Setting 35 ED 80 Data formatted as per data type G1.
Setting for the under voltage set for voltage restrained over current
VRO>1 V2<Setting 35 EE 60 Data formatted as per data type G1.
VRO>1 K Setting 35 EF 0.25 the minimum value (see also G35).
P64x-TM-EN-4.1 B155

DESCRIPTION
Disabled
T1
T2
T3
T4
VRO>2 35 F2 T1
T5
HV Winding
LV Winding
TV Winding
[Indexed String]
Select the Winding type for Voltage restrained overcurrent stage 2
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
Rectifier (TMS)
VRO>2 Char 35 F3 IEC S Inverse RI (K)
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
[Indexed String]
Setting for the tripping characteristic for the second stage voltage restrained overcurrent element
Non-Directional
Directional Fwd
VRO>2 Direction 35 F4 Non-Directional
Directional Rev
[Indexed String]
VRO>2 Curr' Set 35 F5 1 Data formatted as per data type G1.
[Indexed String]
Current pick-up setting for the second stage of the Voltage Restrained overcurrent protection
VRO>2 Time Delay 35 F6 1 Data formatted as per data type G1.
[Indexed String]
Setting for the time delay for the definite time setting if selected the second stage element
VRO>2 TMS 35 F7 1 Data formatted as per data type G1.
[Indexed String]
VRO>2 Time Dial 35 F8 1 the minimum value (see also G35).
B156 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
VRO>2 K(RI) 35 F9 1 Data formatted as per data type G1.
DT
VRO>2 Reset Char 35 FA DT Inverse
[Indexed String]
VRO>2 tReset 35 FB 0s Data formatted as per data type G1.
VRO>2 Angle 35 FC 30° Data formatted as per data type G1.
VRO>2 V1<Setting 35 FD 80 Data formatted as per data type G1.
VRO>2 V2<Setting 35 FE 60 Data formatted as per data type G1.
VRO>2 K Setting 35 FF 0.25 Data formatted as per data type G1.
GROUP 1: THERMAL
37 00
OVERLOAD
This column contains settings for Thermal Overload
HV
MonitoredWinding 37 11 HV LV
Biased Current
P64x-TM-EN-4.1 B157

DESCRIPTION
TV
[Indexed String]
An overall through loading picture of the transformer is provided when the monitor winding is set to Biased Current
RTD1
RTD2
RTD3
RTD4
RTD5
RTD6
RTD7
RTD8
Ambient T Source 37 12 AVERAGE
RTD9
RTD10
AVERAGE
CLIO1
CLIO2
CLIO3
CLIO4
[Indexed String]
Ambient temperature
0-1mA
0-10mA
CLI Type Ambient 37 15 4-20mA 0-20mA
4-20mA
[Indexed String]
This setting is available when Ambient T is set to CLIOx
From -9999 to 9999 in steps of 0.1
CLI Min Ambient 37 16 0
CLI Max Ambient 37 17 100
Avg Ambient Temp 37 18 25 Data formatted as per data type G1.
This setting is available when Ambient T is set to Average
RTD1
RTD2
RTD3
RTD4
RTD5
RTD6
RTD7
RTD8
Top Oil T 37 21 CALCULATED
RTD9
RTD10
CALCULATED
CLIO1
CLIO2
CLIO3
CLIO4
[Indexed String]
The top oil temperature may be calculated by the relay, or it may be measured using RTD or CLIO inputs
0-1mA
0-10mA
CLI Type Top Oil 37 24 4-20mA 0-20mA
4-20mA
[Indexed String]
B158 P64x-TM-EN-4.1

DESCRIPTION
This setting is available when Top Oil T is set to CLIOx
CLI Min Top Oil 37 25 0
CLI Max Top Oil 37 26 100
Rated Current 37 29 1 Data formatted as per data type G1.
The relay uses this setting to calculate the ratio of ultimate load to rated load
Rated NoLoadLoss 37 2A 3 Data formatted as per data type G1.
Ratio of load loss at rated load to no-load loss (iron loss). The transformer manufacturer should provide this parameter
Hot Spot Overtop 37 2B 25 Data formatted as per data type G1.
Hottest spot temperature over top oil temperature setting. The transformer manufacturer should provide this parameter
Top Oil Overamb 37 2C 55 Data formatted as per data type G1.
Top oil temperature over ambient temperature setting. The transformer manufacturer should provide this parameter
Cooling Mode 1
Cooling Mode 2
Cooling Mode 3
Cooling Mode 37 2D Cooling Mode 1
Cooling Mode 4
Select via PSL
[Indexed String]
This setting is uesed to select the cooling Mode
COOLING MODE 1 37 2F Sub-Heading
This is the Sub-Heading for cooling mode 1. It is visible when cooling mode is selected to be cooling mode 1 or to be select from PSL
Winding exp m 37 30 0.8 Data formatted as per data type G1.
Winding exponient m for cooling mode 1, available when cooling mode is selected to be cooling mode 1 or select from PSL
Oil exp n 37 31 0.8 the minimum value (see also G35).
P64x-TM-EN-4.1 B159

DESCRIPTION
oil exponient n for cooling mode 1, available when cooling mode is selected to be cooling mode 1 or select from PSL
COOLING MODE 2 37 32 Sub-Heading
Oil exp n 37 34 0.8 Data formatted as per data type G1.
Oil exp n 37 37 0.8 Data formatted as per data type G1.
Oil exp n 37 3A 0.8 Data formatted as per data type G1.
HotspotRiseConst 37 3B 1
B160 P64x-TM-EN-4.1

DESCRIPTION
Hot spot rise co parameters used to calculate the hot spot temperature
TopOilRiseConst 37 3C 120 Data formatted as per data type G1.
Top oil reis co parameters used to calculate the top oil temperature
Disabled
HS&TO Status 37 40 Enabled Enabled
[Indexed String]
This setting enables or disables the three hot spot and the three top oil thermal stages
Hot Spot>1 Set 37 5E 110 deg C Data formatted as per data type G1.
Hot spot first stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 may be used to set it. See the application
chapter for suggested values
tHot Spot>1 Set 37 5F 10 mins Data formatted as per data type G1.
Hot spot first stage time delay setting
Hot Spot>2 Set 37 60 130 deg C Data formatted as per data type G1.
Hot spot second stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 may be used to set it. See the application
tHot Spot>2 Set 37 61 10 mins Data formatted as per data type G1.
Hot spot second stage time delay setting
Hot Spot>3 Set 37 62 150 deg C Data formatted as per data type G1.
Hot spot third stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 may be used to set it. See the application
tHot Spot>3 Set 37 63 10 mins
P64x-TM-EN-4.1 B161

DESCRIPTION
Hot spot third stage time delay setting
Top Oil>1 Set 37 64 70 deg C Data formatted as per data type G1.
Top oil first stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 may be used to set it. See the application chapter
for suggested values.
tTop Oil>1 Set 37 65 10 mins Data formatted as per data type G1.
Top oil second stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 (may be used to set it. See the application
Top oil second stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 (may be used to set it. See the application
Top oil second stage time delay setting
Top oil third stage setting. The suggested temperature limits given by IEEE Std. C57.91-1995 may be used to set it. See the application
Top oil third stage time delay setting
tPre-trip Set 37 6A 5 mins
B162 P64x-TM-EN-4.1

DESCRIPTION
After the tpre-trip timer has expired, a pre-trip alarm is given. This alarm indicates that if the load remains unchanged a thermal trip will be
asserted after the stage timer has expired
Disabled
LOL Status 37 80 Enable Enabled
[Indexed String]
Enables or disables the loss of life function
Life Hours at HS 37 81 180000 hrs Data formatted as per data type G27.
I.e. Setting value = (setting minimum) + (('G27' value) x
(setting step size))
Life hours at the reference hottest spot temperature. Advice from the transformer manufacturer may be required
Designed HS temp 37 82 110 deg C Data formatted as per data type G1.
The designed hottest spot temperature is 110°C for a transformer rated 65°C average winding rise, and 95°C for a transformer rated 55°C
average winding rise
Constant B Set 37 83 15000 Data formatted as per data type G27.
Constant B is associated to the life expectancy curve. It is based on modern experimental data, and it may be set to 15000 as suggested by
IEEE Std. C57.91-1995
FAA> Set 37 84 2 Data formatted as per data type G1.
Aging acceleration factor setting. If the aging acceleration factor calculated by the relay is above this setting and tFAA has expired, an FAA
alarm would be asserted. FAA calculation depends on constant B and the hottest temperature calculated by the thermal element
tFAA> Set 37 85 10 mins Data formatted as per data type G1.
Aging acceleration factor timer
LOL>1 Set 37 86 135000 hrs Data formatted as per data type G27.
Transformer loss of life setting. If the life already lost by the transformer is above this threshold, an LOL alarm would be asserted after tLOL
has expired. LOL calculation depends on the life hours at design hot spot temperature and the calculated residual life
P64x-TM-EN-4.1 B163

DESCRIPTION
tLOL> Set 37 87 10 mins Data formatted as per data type G1.
Loss of life timer
Reset Life Hours 37 88 0 hr Data formatted as per data type G27.
Resets the LOL status parameter to the set value when the loss of life reset command is executed. For new transformers Reset Life Hours is
zero, so that when the commissioning of the thermal element is over, the loss of life statistics calculations are reset to zero. For old
transformers this setting should indicate how much life the transformer has already lost; therefore, it should be set to the transformer loss of
life
GROUP 1: EARTH FAULT 38 00
This column contains settings for the earth fault elements
Disabled
Earth Fault 1 38 01 Enabled Enabled
[Indexed String]
This setting enables or disables the first earth fault element
Derived
EF 1 Input 38 02 Measured Measured
[Indexed String]
This setting selects either measured or derived neutral current
T1
T2
T3
T4
EF 1 Derived 38 03 T1 T5
HV Winding
LV Winding
TV Winding
[Indexed String]
This setting defines which CT is used for the first derived earth fault element
TN1
TN2
EF 1 Measured 38 04 TN1
TN3
[Indexed String]
This setting defines which CT is used for the first measured earth fault element
Disabled
IN>1 Status 38 05 Enabled Enabled
[Indexed String]
Setting to enable or disable the first stage definite time element. If the function is disabled, all associated settings with the exception of this
setting, are hidden
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>1 Function 38 06 IEC S Inverse
IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
B164 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
Tripping characteristic for the first stage earth fault element 1
Non-Directional
Directional Fwd
IN>1 Direction 38 07 Non-Directional
Directional Rev
[Indexed String]
Direction setting for the first stage earth fault protection 1
From 0.08*In to 4.0*In in steps of 0.01*In
IN>1 Current 38 08 0.2*In
Pick-up setting for the first stage earth fault element 1
IN>1 IDG Is 38 09 1.5
Multiple of IN>1 setting for the IDG curve (Scandinavia), determines the actual relay current threshold at which the element starts
IN>1 Time Delay 38 0A 1
Operating time delay setting for the first stage definite time element
IN>1 TMS 38 0B 1
Time multiplier setting to adjust the operating time of the IEC IDMT characteristic
IN>1 Time Dial 38 0C 1
Time multiplier setting to adjust the operating time of the IEEE/US IDMT curves
IN>1 K (RI) 38 0D 1
Time multiplier to adjust the operating time for the RI curve
IN>1 IDG Time 38 0E 1.2
Minimum operating time at high levels of fault current for the IDG curve
DT
IN>1 Reset Char 38 0F DT Inverse
[Indexed String]
Type of reset/release characteristic of the IEEE/US curves
IN>1 tRESET 38 10 0
Reset/release time setting for definite time reset characteristic
Disabled
IN>2 Status 38 15 Disabled Enabled
[Indexed String]
Setting to enable or disable the second stage definite time element. If the function is disabled, all associated settings with the exception of
this setting, are hidden
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>2 Function 38 16 DT IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the second stage earth fault protection 1
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
Direction setting for the second stage earth fault protection 1
IN>2 Current 38 18 0.2 From 0.08*I1 to 4.0*I1 in steps of 0.01*I1
P64x-TM-EN-4.1 B165

DESCRIPTION
Pick-up setting for the second stage earth fault element 1
IN>2 IDG Is 38 19 1.5
Operating time delay setting for the second stage definite time element
IN>2 TMS 38 1B 1
IN>2 K (RI) 38 1D 1
DT
[Indexed String]
IN>2 tRESET 38 20 0
Disabled
[Indexed String]
Setting to enable or disable the third stage definite time element. If the function is disabled, all associated settings with the exception of this
setting, are hidden
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
Direction setting for the third stage earth fault protection 1
IN>3 Current 38 27 0.5
Pick-up setting for the third stage earth fault element 1
IN>3 Time Delay 38 28 0
Operating time delay setting for the third stage definite time element
Disabled
IN>4 Status 38 2C Disabled Enabled
[Indexed String]
Setting to enable or disable the fourth stage definite time element. If the function is disabled, all associated settings with the exception of
Non-Directional
Directional Fwd
IN>4 Direction 38 2D Non-Directional
Directional Rev
[Indexed String]
Direction setting for the fourth stage earth fault protection 1
IN>4 Current 38 2E 0.5
Pick-up setting for the fourth stage earth fault element 1
IN>4 Time Delay 38 2F 0
Operating time delay setting for the fourth stage definite time element
IH2 IN> Set 38 31 0.2 From 0.05 to 0.5 in steps of 0.01
B166 P64x-TM-EN-4.1

DESCRIPTION
Second harmonic percent threshold for earth fault element 1
IH2 IN> Unblock 38 32 4*In
Current threshold at which 2nd harmonic blocking is removed for earth fault element 1
IN>1 VTS Block
IN>2 VTS Block
IN>3 VTS Block
IN>4 VTS Block
IN> Blocking 38 33 255 IN>1 2H Block
IN>2 2H Block
IN>3 2H Block
IN>4 2H Block
[Binary Flags]
Settings that determine whether VT supervision logic signals block selected earth fault stages. When set to 1, the VTS operation will block the
stage if directionalized. When set to 0, the stage will revert to non-directional on the operation of the VTS
IN> DIRECTIONAL 38 34 Sub-Heading
Sub-Heading for IN directional
IN> Char Angle 38 35 -60
[Courier Number(Angle)]
Zero Sequence
IN> Pol 38 36 Zero Sequence Neg Sequence
[Indexed String]
Setting that determines whether the directional function uses zero sequence or negative sequence voltage polarizing
From 0.5*V1 to 80*V1 in steps of 0.5*V1
IN> VNpol Set 38 37 5
Setting for the minimum zero sequence voltage polarizing quantity for directional decision
IN> V2pol Set 38 38 5
Setting for the minimum negative sequence voltage polarizing quantity for directional decision
IN> I2pol Set 38 39 0.08
Setting for the minimum negative sequence current polarizing quantity for directional decision
Disabled
[Indexed String]
This setting enables or disables the second earth fault element
Derived
[Indexed String]
T1
T2
T3
P642: T2 T4
EF 2 Derived 38 43 P643: T3 T5
P645: T5 HV Winding
LV Winding
TV Winding
[Indexed String]
This setting defines which CT is used for the second derived earth fault element
TN1
TN2
TN3
[Indexed String]
This setting defines which CT is used for the second measured earth fault element
Disabled
[Indexed String]
P64x-TM-EN-4.1 B167

DESCRIPTION
setting, are hidden
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>1 Function 38 46 IEC S Inverse IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the first stage earth fault protection 2
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
IN>1 IDG Is 38 49 1.5
IN>1 TMS 38 4B 1
IN>1 K (RI) 38 4D 1
Time multiplier setting to adjust the operating time for the RI curve
DT
[Indexed String]
IN>1 tRESET 38 50 0
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IN>2 Function 38 56 DT IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IEEE M Inverse (TD)
B168 P64x-TM-EN-4.1

DESCRIPTION
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the second stage earth fault protection 2
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
From 0.08*I1 to 4.0*I1 in steps of 0.01*I1
IN>2 IDG Is 38 59 1.5
IN>2 TMS 38 5B 1
IN>2 K (RI) 38 5D 1
DT
[Indexed String]
IN>2 tRESET 38 60 0
Disabled
[Indexed String]
setting, are hidden
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
IN>3 Time Delay 38 68 0
Disabled
IN>4 Status 38 6C Disabled Enabled
[Indexed String]
P64x-TM-EN-4.1 B169

DESCRIPTION
Non-Directional
Directional Fwd
IN>4 Direction 38 6D Non-Directional
Directional Rev
[Indexed String]
Direction setting for the fourth stage earth fault protection 2
IN>4 Current 38 6E 0.5
Pick-up setting for the fourth stage earth fault element 2
IN>4 Time Delay 38 6F 0
IH2 IN> Set 38 71 0.2
IH2 IN> Unblock 38 72 4*In
IN>1 VTS Block
IN>2 VTS Block
IN>3 VTS Block
IN>4 VTS Block
IN> Blocking 38 73 255 IN>1 2H Block
IN>2 2H Block
IN>3 2H Block
IN>4 2H Block
[Binary Flags]
IN> DIRECTIONAL 38 74 Sub-Heading
Sub-Heading for IN directional
IN> Char Angle 38 75 -60
Zero Sequence
IN> Pol 38 76 Zero Sequence Neg Sequence
[Indexed String]
IN> VNpol Set 38 77 5
IN> V2pol Set 38 78 5
IN> I2pol Set 38 79 0.08
Setting for the minimum negative sequence current polarizing quantity for directional Decision
Disabled
[Indexed String]
This setting enables or disables the second earth fault element
Derived
[Indexed String]
T1
T2
P643: T2
EF 3 Derived 38 83 T3
P645: T3
T4
T5
B170 P64x-TM-EN-4.1

DESCRIPTION
HV Winding
LV Winding
TV Winding
[Indexed String]
TN1
TN2
TN3
[Indexed String]
This setting defines which CT is used for the second measured earth fault element
Disabled
[Indexed String]
setting, are hidden
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>1 Function 38 86 IEC S Inverse IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the first stage earth fault protection
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
IN>1 IDG Is 38 89 1.5
IN>1 TMS 38 8B 1
IN>1 K (RI) 38 8D 1
DT
[Indexed String]
IN>1 tRESET 38 90 0
P64x-TM-EN-4.1 B171

DESCRIPTION
Disabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>2 Function 38 96 DT IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the second stage earth fault protection
Non-Directional
Directional Fwd
Directional Rev
[Indexed String]
IN>2 IDG Is 38 99 1.5
IN>2 TMS 38 9B 1
IN>2 K (RI) 38 9D 1
DT
[Indexed String]
IN>2 tRESET 38 A0 0
Disabled
IN>3 Status 38 A5 Disabled Enabled
[Indexed String]
setting, are hidden
Non-Directional
IN>3 Direction 38 A6 Non-Directional
Directional Fwd
B172 P64x-TM-EN-4.1

DESCRIPTION
Directional Rev
[Indexed String]
IN>3 Current 38 A7 0.5
IN>3 Time Delay 38 A8 0
Disabled
IN>4 Status 38 AC Disabled Enabled
[Indexed String]
Non-Directional
Directional Fwd
IN>4 Direction 38 AD Non-Directional
Directional Rev
[Indexed String]
Direction setting for the fourth stage TV winding earth fault protection
IN>4 Current 38 AE 0.5
Pick-up setting for the fourth stage earth fault element on the TV winding
IN>4 Time Delay 38 AF 0
IH2 IN> Set 38 B1 0.2
IH2 IN> Unblock 38 B2 4*In
IN>1 VTS Block
IN>2 VTS Block
IN>3 VTS Block
IN>4 VTS Block
IN> Blocking 38 B3 255 IN>1 2H Block
IN>2 2H Block
IN>3 2H Block
IN>4 2H Block
[Binary Flags]
IN> DIRECTIONAL 38 B4 Sub-Heading

IN> Char Angle 38 B5 -60
Zero Sequence
IN> Pol 38 B6 Zero Sequence Neg Sequence
[Indexed String]
IN> VNpol Set 38 B7 5
IN> V2pol Set 38 B8 5
IN> I2pol Set 38 B9 0.08
P64x-TM-EN-4.1 B173

DESCRIPTION
Disabled
Earth Fault 4 38 C1 Enabled Enabled
[Indexed String]
This setting enables or disables the fourth earth fault element
Derived
EF 4 Input 38 C2 Derived Measured
[Indexed String]
This setting selects derived neutral current
T1
T2
T3
T4
P643: T2
EF 4 Derived 38 C3 T5
P645: T3
HV Winding
LV Winding
TV Winding
[Indexed String]
Disabled
IN>1 Status 38 C5 Enabled Enabled
[Indexed String]
setting, are hidden
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>1 Function 38 C6 IEC S Inverse IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the first stage earth fault protection
Non-Directional
Directional Fwd
IN>1 Direction 38 C7 Non-Directional
Directional Rev
[Indexed String]
IN>1 Current 38 C8 0.2*In
IN>1 IDG Is 38 C9 1.5
IN>1 Time Delay 38 CA 1
IN>1 TMS 38 CB 1
IN>1 Time Dial 38 CC 1
IN>1 K (RI) 38 CD 1
IN>1 IDG Time 38 CE 1.2 From 1 to 2 in steps of 0.01
B174 P64x-TM-EN-4.1

DESCRIPTION
DT
IN>1 Reset Char 38 CF DT Inverse
[Indexed String]
IN>1 tRESET 38 D0 0
Disabled
IN>2 Status 38 D5 Disabled Enabled
[Indexed String]
DT (DT)
IEC S Inverse (TMS)
IEC V Inverse (TMS)
IEC E Inverse (TMS)
UK LT Inverse (TMS)
RI (K)
IN>2 Function 38 D6 DT IEEE M Inverse (TD)
IEEE V Inverse (TD)
IEEE E Inverse (TD)
US Inverse (TD)
US ST Inverse (TD)
IDG
[Indexed String]
Tripping characteristic for the second stage earth fault protection
Non-Directional
Directional Fwd
IN>2 Direction 38 D7 Non-Directional
Directional Rev
[Indexed String]
IN>2 Current 38 D8 0.2
IN>2 IDG Is 38 D9 1.5
IN>2 Time Delay 38 DA 1
IN>2 TMS 38 DB 1
IN>2 Time Dial 38 DC 1
IN>2 K (RI) 38 DD 1
IN>2 IDG Time 38 DE 1.2
DT
IN>2 Reset Char 38 DF DT Inverse
[Indexed String]
IN>2 tRESET 38 E0 0
P64x-TM-EN-4.1 B175

DESCRIPTION
Disabled
IN>3 Status 38 E5 Disabled Enabled
[Indexed String]
setting, are hidden
Non-Directional
Directional Fwd
IN>3 Direction 38 E6 Non-Directional
Directional Rev
[Indexed String]
IN>3 Current 38 E7 0.5
IN>3 Time Delay 38 E8 0
Disabled
IN>4 Status 38 EC Disabled Enabled
[Indexed String]
Non-Directional
Directional Fwd
IN>4 Direction 38 ED Non-Directional
Directional Rev
[Indexed String]
Direction setting for the fourth stage TV winding earth fault protection
IN>4 Current 38 EE 0.5
Pick-up setting for the fourth stage earth fault element on the TV winding
IN>4 Time Delay 38 EF 0
IH2 IN> Set 38 F1 0.2
IH2 IN> Unblock 38 F2 4*In
IN>1 VTS Block
IN>2 VTS Block
IN>3 VTS Block
IN>4 VTS Block
IN> Blocking 38 F3 255 IN>1 2H Block
IN>2 2H Block
IN>3 2H Block
IN>4 2H Block
[Binary Flags]
IN> DIRECTIONAL 38 F4 Sub-Heading

IN> Char Angle 38 F5 -60
Zero Sequence
IN> Pol 38 F6 Zero Sequence Neg Sequence
[Indexed String]
IN> VNpol Set 38 F7 5 From 0.5*V1 to 80*V1 in steps of 0.5*V1
B176 P64x-TM-EN-4.1

DESCRIPTION
IN> V2pol Set 38 F8 5
IN> I2pol Set 38 F9 0.08
GROUP 1: THROUGH
39 00
FAULT
This column contains settings for Through Fault monitoring
Disabled
Through Fault 39 01 Enabled Enabled
[Indexed String]
Enables or disables monitoring of through faults
HV
LV
Monitored Input 39 02 HV
TV
[Indexed String]
Selects the input winding to be monitored
TF I> Trigger 39 03 3.85pu Data formatted as per data type G1.
A through fault event is recorded if any of the phase currents is larger than this setting
TF I2t> Alarm 39 04 100 pu Data formatted as per data type G1.
[Courier Number (Courier)]
An alarm is asserted if the maximum cumulative I2t in the three phases exceeds this setting
GROUP 1: RESIDUAL
3B 00
O/V NVD
This column contains settings for Residual Overvoltage (Neutral Voltage Displacement)
Disabled
DT
VN>1 Function 3B 14 DT
IDMT
[Indexed String]
This setting determines the tripping characteristic for the first stage residual overvoltage element.
VN>1 Voltage Set 3B 16 5*V1
This setting sets the pick-up threshold for the first stage.
VN>1 Time Delay 3B 18 5s
This setting sets the operate time delay for the first stage.
VN>1 TMS 3B 1A 1
This setting sets the time multiplier setting for the IDMT characteristic.
VN>1 tReset 3B 1C 0s
This setting sets the DT reset time.
Disabled
VN>2 Status 3B 20 Disabled Enabled
[Indexed String]
This setting enables or disables the second stage SEF element. There is no choice of curves because this stage is DT only.
P64x-TM-EN-4.1 B177

DESCRIPTION
VN>2 Voltage Set 3B 26 10*V1
This setting sets the pick-up threshold for the second stage.
VN>2 Time Delay 3B 28 10s
This setting sets the operate time delay for the second stage.
GROUP 1:
3D 00
OVERFLUXING
This column contains settings for Overfluxing protection
Volts/Hz 3ph 3D 01 Sub-Heading
Volts/Hz Overfluxing element for the 3-phase VT.
Ref Voltage 3D 02 110
[Courier Number]
Reference voltage for normalizing
Disabled
V/HZ Alm Status 3D 03 Enabled Enabled
[Indexed String]
Enables or disables the V/Hz alarm element
V/HZ Alarm Set 3D 04 1.05 PU Data formatted as per data type G1.
[Courier Number]
Pick-up setting for the V/Hz element
V/Hz Alarm Delay 3D 05 10s Data formatted as per data type G1.
[Courier Number]
Operating time delay setting of the V/Hz alarm element
Disabled
V/Hz>1 Status 3D 10 Enabled Enabled
[Indexed String]
Enables or disables the V/Hz first stage trip element
DT
V/Hz>1 Trip Func 3D 13 DT IDMT
[Indexed String]
Tripping characteristic setting of the V/Hz first stage trip element
V/Hz>1 Trip Set 3D 16 1.1 PU Data formatted as per data type G1.
[Courier Number]
Pick-up setting for the V/Hz first stage trip element
V/Hz>1 Trip TMS 3D 19 0.1 Data formatted as per data type G1.
[Courier Number]
Setting for the Time Multiplier Setting (TMS) to adjust the operating time of the IDMT characteristic
V/Hz>1 Delay 3D 1A 60s represented as the number of step increments from
B178 P64x-TM-EN-4.1

DESCRIPTION
[Courier Number]
Operating time-delay setting of the V/Hz first stage trip element
V/Hz>1 tReset 3D 1B 60s Data formatted as per data type G1.
[Courier Number]
Reset time for the IDMT characteristic.
Disabled
[Indexed String]
Enables or disables the V/Hz second stage trip element
[Courier Number]
Pick-up setting for the V/Hz second stage trip element
V/Hz>2 Delay 3D 2A 3s Data formatted as per data type G1.
[Courier Number]
Disabled
[Indexed String]
Enables or disables the V/Hz third stage trip element
[Courier Number]
Pick-up setting for the V/Hz third stage trip element
V/Hz>3 Delay 3D 3A 2.00s Data formatted as per data type G1.
[Courier Number]
Disabled
[Indexed String]
Enables or disables the V/Hz fourth stage trip element
V/Hz>4 Trip Set 3D 45 1.4 PU
P64x-TM-EN-4.1 B179

DESCRIPTION
[Courier Number]
Pick-up setting for the V/Hz fourth stage trip element
[Courier Number]
TPre-trip Alm 3D 4F 200s Data formatted as per data type G1.
Pre-trip alarm time delay
Volts/Hz 1ph 3D 50
Volts/Hz Overfluxing element for the 1-phase VT.
Ref Voltage 3D 52 110
[Courier Number]
Reference voltage for normalizing
Disabled
V/HZ Alm Status 3D 53 Enabled Enabled
[Indexed String]
Enables or disables the V/Hz alarm element
V/HZ Alm Set 3D 54 1.05 PU Data formatted as per data type G1.
[Courier Number]
Pick-up setting for the V/Hz element
V/Hz Alarm Delay 3D 55 10s Data formatted as per data type G1.
[Courier Number]
Disabled
[Indexed String]
Enables or disables the V/Hz first stage trip element
DT
V/Hz>1 Function 3D 63 DT IDMT
[Indexed String]
Tripping characteristic setting of the V/Hz first stage trip element
[Courier Number]
Pick-up setting for the V/Hz first stage trip element
B180 P64x-TM-EN-4.1

DESCRIPTION
V/Hz>1 Trip TMS 3D 69 0.1 s Data formatted as per data type G1.
[Courier Number]
Setting for the time multiplier setting to adjust the operating time of the IDMT characteristic.
[Courier Number]
V/Hz>1 tReset 3D 6B 0s Data formatted as per data type G1.
[Courier Number]
Reset time for the IDMT characteristic.
Disabled
[Indexed String]
Enables or disables the V/Hz second stage trip element
[Courier Number]
Pick-up setting for the V/Hz second stage trip element
[Courier Number]
Disabled
[Indexed String]
Enables or disables the V/Hz third stage trip element
[Courier Number]
Pick-up setting for the V/Hz third stage trip element
V/Hz>3 Delay 3D 8A 2.00s the minimum value (see also G35).
P64x-TM-EN-4.1 B181

DESCRIPTION
[Courier Number]
Disabled
[Indexed String]
Enables or disables the V/Hz fourth stage trip element
[Courier Number]
Pick-up setting for the V/Hz fourth stage trip element
[Courier Number]
tPre-trip Alm 3D 9F 200s Data formatted as per data type G1.
Pre-trip alarm time delay
GROUP 1: VOLT
42 00
PROTECTION
This column contains settings for Voltage protection
UNDER VOLTAGE 42 01 Sub-Heading
The settings under this sub-heading relate to Undervoltage
Phase-Phase
V< Measur't Mode 42 02 Phase-Neutral Phase-Neutral
[Indexed String]
This set determines the voltage input mode - phase-to-phase or phase-to-neutral.
Any Phase
V< Operate Mode 42 03 Any Phase Three Phase
[Indexed String]
This setting determines whether any one of the phases or all three of the phases has to satisfy the undervoltage criteria before a decision is
made.
Disabled
DT
V<1 Function 42 04 DT
IDMT
[Indexed String]
This setting determines the tripping characteristic for the first stage undervoltage element.
V<1 Voltage Set 42 05 50V
This setting sets the pick-up threshold for the first stage undervoltage element.
V<1 Time Delay 42 06 10s
This setting sets the DT time delay for the first stage undervoltage element.
V<1 TMS 42 07 1
This is the Time Multiplier Setting to adjust the operate time of IEC IDMT curves.
Disabled
V<1 Poledead Inh 42 08 Enabled
Enabled
B182 P64x-TM-EN-4.1

DESCRIPTION
[Indexed String]
This setting enables or disables the Pole Dead inhibit logic.
Disabled
V<2 Status 42 09 Disabled Enabled
[Indexed String]
This setting enables or disables the second stage undervoltage element. There is no choice of curves because this stage is DT only.
V<2 Voltage Set 42 0A 38V
This setting sets the pick-up threshold for the second stage undervoltage element.
V<2 Time Delay 42 0B 5s
This setting sets the DT time delay for the second stage undervoltage element.
Disabled
V<2 Poledead Inh 42 0C Enabled Enabled
[Indexed String]
This setting enables or disables the Pole Dead inhibit logic.
OVERVOLTAGE 42 20 Sub-Heading
The settings under this sub-heading relate to Overvoltage
Phase-Phase
V> Measur't Mode 42 21 Phase-Phase Phase-Neutral
[Indexed String]
This set determines the voltage input mode - phase-to-phase or phase-to-neutral.
Any Phase
V> Operate Mode 42 22 Any Phase Three Phase
[Indexed String]
This setting determines whether any one of the phases or all three of the phases has to satisfy the overvoltage criteria before a decision is
made.
Disabled
DT
V>1 Function 42 23 DT
IDMT
[Indexed String]
This setting determines the tripping characteristic for the first stage overvoltage element.
V>1 Voltage Set 42 24 130V
This setting sets the pick-up threshold for the first stage overvoltage element.
V>1 Time Delay 42 25 10s
This setting sets the DT time delay for the first stage overvoltage element.
V>1 TMS 42 26 1
This is the Time Multiplier Setting to adjust the operate time of IEC IDMT curves.
Disabled
V>2 Status 42 27 Disabled Enabled
[Indexed String]
This setting enables or disables the second stage overvoltage element. There is no choice of curves because this stage is DT only.
V>2 Voltage Set 42 28 150V
This setting sets the pick-up threshold for the second stage overvoltage element.
V>2 Time Delay 42 29 0.5
This setting sets the DT time delay for the second stage overvoltage element.
NPS O/V 42 40 Sub-Heading
This sub-heading contains settings for Negative Phase Sequence Overvoltage
Disabled
V2> Status 42 41 Disabled Enabled
[Indexed String]
This setting enables or disables NPSOV.
V2> Voltage Set 42 42 15V represented as the number of step increments from
P64x-TM-EN-4.1 B183

DESCRIPTION
This setting sets the pick-up threshold for the NPSOV protection element.
V2> Time Delay 42 43 5s Data formatted as per data type G1.
This setting sets the operate time-delay for the NPSOV protection element.
GROUP 1: FREQ
43 00
PROTECTION
This column contains settings for Frequency
UNDER FREQUENCY 43 01 Sub-Heading
This sub-heading relates to Underfrequency settings
Disabled
F<1 Status 43 02 Enabled Enabled
[Indexed String]
This setting enables or disables the first stage underfrequency element.
F<1 Setting 43 03 49.5Hz
[Courier Number (Frequency)]
This setting determines the pick-up threshold for the first stage underfrequency element.
F<1 Time Delay 43 04 4s
This setting determines the minimum operating time-delay for the first stage underfrequency element.
Disabled
F<2 Status 43 05 Disabled Enabled
[Indexed String]
This setting enables or disables the second stage underfrequency element.
F<2 Setting 43 06 49Hz
This setting determines the pick-up threshold for the second stage underfrequency element.
F<2 Time Delay 43 07 3s
This setting determines the minimum operating time-delay for the second stage underfrequency element.
Disabled
F<3 Status 43 08 Disabled Enabled
[Indexed String]
This setting enables or disables the third stage underfrequency element.
F<3 Setting 43 09 48.5Hz
This setting determines the pick-up threshold for the third stage underfrequency element.
F<3 Time Delay 43 0A 2s
This setting determines the minimum operating time-delay for the third stage underfrequency element.
Disabled
F<4 Status 43 0B Disabled Enabled
[Indexed String]
This setting enables or disables the fourth stage underfrequency element.
F<4 Setting 43 0C 48Hz
This setting determines the pick-up threshold for the fourth stage underfrequency element.
F<4 Time Delay 43 0D 1s
This setting determines the minimum operating time-delay for the fourth stage underfrequency element.
OVER FREQUENCY 43 0F Sub-Heading
This sub-heading relates to Overfrequency settings
B184 P64x-TM-EN-4.1

DESCRIPTION
Disabled
F>1 Status 43 10 Enabled Enabled
[Indexed String]
This setting enables or disables the first stage overfrequency element.
F>1 Setting 43 11 50.5Hz
This setting determines the pick-up threshold for the first stage overfrequency element.
F>1 Time Delay 43 12 2s
This setting determines the minimum operating time-delay for the first stage overfrequency element.
Disabled
F>2 Status 43 13 Disabled Enabled
[Indexed String]
This setting enables or disables the second stage overfrequency element.
F>2 Setting 43 14 51Hz
This setting determines the pick-up threshold for the second stage overfrequency element.
F>2 Time Delay 43 15 1s
This setting determines the minimum operating time-delay for the second stage overfrequency element.
GROUP 1: RTD
44 00
PROTECTION
This column contains settings for RTD protection
RTD Input #1
RTD Input #2
RTD Input #3
RTD Input #4
RTD Input #5
Select RTD 44 01 0 RTD Input #6
RTD Input #7
RTD Input #8
RTD Input #9
RTD Input #10
[Binary Flags(10 bits)Indexed String]
RTD1 PROTECTION 44 02 Sub-Heading
RTD Alarm Set 44 03 80°C
RTD Alarm Dly 44 04 10 s
RTD Trip Set 44 05 85°C
RTD Trip Dly 44 06 1s
RTD Trip Set 44 0A 85°C
P64x-TM-EN-4.1 B185

DESCRIPTION
RTD Trip Dly 44 0B 1s
RTD3 PROTECTION 44 0C Sub-Heading
RTD Alarm Set 44 0D 80°C
RTD Alarm Dly 44 0E 10 s
RTD Trip Set 44 0F 85°C
RTD Trip Dly 44 1A 1s
RTD6 PROTECTION 44 1B Sub-Heading
RTD Alarm Set 44 1C 80°C
RTD Alarm Dly 44 1D 10 s
RTD Trip Set 44 1E 85°C
RTD Trip Dly 44 1F 1s
B186 P64x-TM-EN-4.1

DESCRIPTION
RTD9 PROTECTION 44 2A Sub-Heading
RTD Alarm Set 44 2B 80°C
RTD Alarm Dly 44 2C 10 s
RTD Trip Set 44 2D 85°C
RTD Trip Dly 44 2E 1s
RTD 10 PROTECTION 44 2F Sub-Heading
GROUP 1: CB FAIL 45 00
This column contains settings for CB Fail
T1 CBF Status 45 01 Disabled Disabled
P64x-TM-EN-4.1 B187

DESCRIPTION
Enabled
[Indexed String]
This setting enables or disables CB Fail for CT1
I< Current Set 45 02 0.1 Data formatted as per data type G1.
This setting determines the current threshold, which will reset the CB Fail timer for overcurrent based protection
Disabled
IN< Status 45 03 Disabled Enabled
[Indexed String]
This setting enables or disables earth fault undercurrent for this CT
Derived
IN< Input 45 04 Measured Measured
[Indexed String]
This setting sets the type of earth fault input
TN1
TN2
IN< Terminal 45 05 TN1
TN3
[Indexed String]
If for IN is measured, set the measured netrual current source
IN< Current Set 45 06 0.1
This setting determines the current threshold, which will reset the CB Fail timer for Earth Fault-based protection
Disabled
CB Fail 1 Status 45 07 Disabled Enabled
[Indexed String]
This setting enables or disables the first stage of the CB Fail protection.
CB Fail 1 Timer 45 08 0.05s
This setting sets the first stage CB Fail timer in which the CB opening must be detected.
Disabled
CB Fail 2 Status 45 09 Enabled Enabled
[Indexed String]
This setting enables or disables the second stage of the CB Fail protection.
CB Fail 2 Timer 45 0A 0.2s
This setting sets the second stage CB Fail timer in which the CB opening must be detected.
I< Only
CB Open & I<
Non I Prot Reset 45 0C CB Open & I<
Prot Reset & I<
[Indexed String]
This setting determines the elements that reset the circuit breaker fail time for non current-based protection functions (such as voltage and
frequency) initiating circuit breaker fail conditions
I< Only
CB Open & I<
Ext Prot Reset 45 0D CB Open & I<
Prot Reset & I<
[Indexed String]
This setting determines the elements that reset the circuit breaker fail time for external protection functions initiating circuit breaker fail
conditions
Disabled
ExtTrip Only Ini 45 0E Disabled Enabled
[Indexed String]
When Enabled, CB Fail timers will only be initiated by External Trip inputs.
Disabled
T2 CBF Status 45 11 Disabled Enabled
[Indexed String]
B188 P64x-TM-EN-4.1

DESCRIPTION
I< Current Set 45 12 0.1
Disabled
[Indexed String]
Derived
[Indexed String]
TN1
TN2
TN3
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
I< Only
CB Open & I<
CBF Non I Reset 45 1C CB Open & I<
Prot Reset & I<
[Indexed String]
I< Only
CB Open & I<
CBF Ext Reset 45 1D CB Open & I<
Prot Reset & I<
[Indexed String]
conditions
Disabled
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
P64x-TM-EN-4.1 B189

DESCRIPTION
Derived
[Indexed String]
TN1
TN2
TN3
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
conditions
Disabled
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
Derived
[Indexed String]
TN1
TN2
B190 P64x-TM-EN-4.1

DESCRIPTION
TN3
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
conditions
Disabled
[Indexed String]
Disabled
[Indexed String]
Disabled
[Indexed String]
Derived
[Indexed String]
TN1
TN2
TN3
[Indexed String]
CB Fail 1 Status 45 47 Disabled Disabled
P64x-TM-EN-4.1 B191

DESCRIPTION
Enabled
[Indexed String]
Disabled
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
I< Only
CB Open & I<
Prot Reset & I<
[Indexed String]
conditions
Disabled
[Indexed String]
GROUP 1: SUPERVISION 46 00
This column contains settings for Supervision.
VT SUPERVISION 46 01 Sub-Heading
The setings under this sub-heading relate to Voltage Transformer Supervision (VTS).
Blocking
Indication
VTS Status 46 02 Indication
Disabled
[Indexed String]
This setting determines which operations will occur upon VTS detection.
• VTS provides alarm indication only.
• VTS provides blocking of voltage dependent protection elements.
Manual
VTS Reset Mode 46 03 Manual Auto
[Indexed String]
There are two reset methods; Manual reset (via the front panel or remote communications), or Automatic reset (providing the VTS condition
has been removed and the 3 phase voltages have been restored for more than 240ms.
VTS Time Delay 46 04 5s Data formatted as per data type G1.
This setting that determines the operate time-delay upon detection of a VTS condition.
VTS I> Inhibit 46 05 10 Data formatted as per data type G1.
The setting is used to override a VTS blocking signal in the event of a phase fault occurring on the system that could trigger VTS logic.
B192 P64x-TM-EN-4.1

DESCRIPTION
VTS I2> Inhibit 46 06 0.05 Data formatted as per data type G1.
The setting is used to override a voltage supervision block in the event of a fault occurring on the system with negative sequence current
above this setting which could trigger the voltage supervision logic.
CT SUPERVISION 46 20 Sub-Heading
The setings under this sub-heading relate to Current Transformer Supervision (CTS).
Disabled
Diff CTS 46 21 Enable Enabled
[Indexed String]
This setting enables or disables the differential CTS function
Indication
Restrain
CTS Status 46 22 Restrain
Blocking
[Indexed String]
In Indication mode, the CTS alarm is issued without delay when a CT failure is detected. In restrain mode, the differential protection is
desensitised to the Is-CTS setting
CTS Time Delay 46 23 2s Data formatted as per data type G1.
Determines the operating time delay of the element on detection of a current transformer supervision condition
CTS I1 46 24 0.1 Data formatted as per data type G1.
This setting sets the release threshold
CTS I2/I1>1 46 25 0.05 Data formatted as per data type G1.
[Courier Number]
Low set ratio of negative to positive sequence current
CTS I2/I1>2 46 26 0.4 Data formatted as per data type G1.
[Courier Number]
High set ratio of negative to positive sequence current
GROUP 1: INPUT
4A 00
LABELS
This settings in this column define the opto-input labels
Opto Input 1 4A 01 Input L1
This setting defines the label for opto-input 1
P64x-TM-EN-4.1 B193

DESCRIPTION
Opto Input 10 4A 0A Input L10
Opto Input 11 4A 0B Input L11
Opto Input 12 4A 0C Input L12
Opto Input 13 4A 0D Input L13
Opto Input 14 4A 0E Input L14
Opto Input 15 4A 0F Input L15
Opto Input 22 4A 16 Input L22 From 32 to 163 in steps of 1
B194 P64x-TM-EN-4.1

DESCRIPTION
Opto Input 26 4A 1A Input L26
Opto Input 27 4A 1B Input L27
Opto Input 28 4A 1C Input L28
Opto Input 29 4A 1D Input L29
Opto Input 30 4A 1E Input L30
Opto Input 31 4A 1F Input L31
GROUP 1: OUTPUT
4B 00
LABELS
This settings in this column define the output relay labels
P64x-TM-EN-4.1 B195

DESCRIPTION
Relay 1 4B 01 Output R1 Not Used
This setting defines the label for output relay 1
Relay 10 4B 0A Output R10 Not Used
Relay 11 4B 0B Output R11 Not Used
Relay 12 4B 0C Output R12 Not Used
Relay 13 4B 0D Output R13 Not Used
Relay 14 4B 0E Output R14 Not Used
Relay 15 4B 0F Output R15 Not Used
B196 P64x-TM-EN-4.1

DESCRIPTION
Relay 26 4B 1A Output R26 Not Used
Relay 27 4B 1B Output R27 Not Used
Relay 28 4B 1C Output R28 Not Used
Relay 29 4B 1D Output R29 Not Used
Relay 30 4B 1E Output R30 Not Used
Relay 31 4B 1F Output R31 Not Used
GROUP 1: RTD LABELS 4C 00
This settings in this column define the RTD labels
RTD 1 4C 01 RTD 1
This setting defines the label for RTD 1
RTD 2 4C 02 RTD 2
RTD 3 4C 03 RTD 3
RTD 4 4C 04 RTD 4
RTD 5 4C 05 RTD 5
RTD 6 4C 06 RTD 6
RTD 7 4C 07 RTD 7
P64x-TM-EN-4.1 B197

DESCRIPTION
RTD 8 4C 08 RTD 8
RTD 9 4C 09 RTD 9
RTD 10 4C 0A RTD 10
GROUP 1: CLIO
4D 00
PROTECTION
This column contains settings for CLIO protection
CLI1 PROTECTION 4D 01 Sub-Heading
This sub-heading relates to CLI1
Disabled
CLI Input Status 4D 02 Enabled Enabled
[Indexed String]
This setting enables or disables CLI1
0-1mA
0-10mA
CLI Input Type 4D 04 4-20mA 0-20mA
4-20mA
[Indexed String]
This settings the Input type for CLI1
CLI Input Label 4D 06 CLIO Input 1
This setting defines the label for CLI1
CLI Minimum 4D 08 0
This sets the CLI1 minimum setting
CLI Maximum 4D 0A 100
This sets the CLI1 maximum setting
Disabled
CLI Alarm 4D 0C Disabled Enabled
[Indexed String]
This setting enables or disables the CL1 alarm element
Under
CLI Alarm Fn 4D 0E Over Over
[Indexed String]
This setting defines the operating mode for the CL1 alarm element
From MIN(CLI1Min, Max) to MAX(CLI1Min, Max) in
CLI Alarm Set 4D 10 50 steps of 0.1
This sets the pick-up threshold for the CL1 alarm element
CLI Alarm Delay 4D 12 1
This sets the operate time-delay setting for the CL1 alarm element
Disabled
CLI Trip 4D 14 Disabled Enabled
[Indexed String]
This setting enables or disables the CL1 trip element
Under
CLI Trip Fn 4D 16 Over Over
[Indexed String]
This setting defines the operating mode for the CL1 trip element
CLI Trip Set 4D 18 60 steps of 0.1
B198 P64x-TM-EN-4.1

DESCRIPTION
This sets the pick-up threshold for the CL1 trip element
CLI Trip Delay 4D 1A 0
This sets the operate time-delay setting for the CL1 trip element
Disabled
CLI I< Alarm 4D 1C Disabled Enabled
[Indexed String]
This setting enables or disables the CL1 undercurrent alarm element
From 0 to 0.004 in steps of 0.0001
CLI I< Alm Set 4D 1E 3.5mA
This sets the pick-up threshold for the CL1 undercurrent alarm element
Disabled
[Indexed String]
0-1mA
0-10mA
4-20mA
[Indexed String]
CLI Minimum 4D 28 0
Disabled
[Indexed String]
Under
[Indexed String]
CLI Alarm Delay 4D 32 1s
Disabled
[Indexed String]
Under
[Indexed String]
CLI Trip Delay 4D 3A 0s From 0 to 100 in steps of 0.1
P64x-TM-EN-4.1 B199

DESCRIPTION
Disabled
[Indexed String]
Disabled
[Indexed String]
0-1mA
0-10mA
4-20mA
[Indexed String]
CLI Minimum 4D 48 0
Disabled
[Indexed String]
Under
[Indexed String]
Disabled
[Indexed String]
Under
[Indexed String]
CLI Trip Delay 4D 5A 0s
B200 P64x-TM-EN-4.1

DESCRIPTION
Disabled
[Indexed String]
Disabled
[Indexed String]
0-1mA
0-10mA
4-20mA
[Indexed String]
CLI Minimum 4D 68 0
Disabled
[Indexed String]
Under
[Indexed String]
Disabled
[Indexed String]
Under
[Indexed String]
CLI Trip Delay 4D 7A 0s
Disabled
CLI I< Alarm 4D 7C Disabled
Enabled
P64x-TM-EN-4.1 B201

DESCRIPTION
[Indexed String]
CLO OUTPUT1 4D 9F Sub-Heading
This sub-heading relates to CLO1
Disabled
CLO Status 4D A0 Disabled Enabled
[Indexed String]
This setting enables or disables CLO1
0-1mA
0-10mA
CLO Type 4D A2 4-20mA 0-20mA
4-20mA
[Indexed String]
This settings the Output type for CLO1
Primary
CLO Set Values 4D A4 Primary Secondary
[Indexed String]
This setting decides whether the measured values from CLO1 are Primary or Secondary values
IA-1 Magnitude
IB-1 Magnitude
IC-1 Magnitude
IA-2 Magnitude
IB-2 Magnitude
IC-2 Magnitude
IA-3 Magnitude
IB-3 Magnitude
IC-3 Magnitude
IA-4 Magnitude
IB-4 Magnitude
IC-4 Magnitude
IA-5 Magnitude
IB-5 Magnitude
IC-5 Magnitude
I1-1 Magnitude
I2-1 Magnitude
I0-1 Magnitude
I1-2 Magnitude
I2-2 Magnitude
CLO Parameter 4D A6 IA Magnitude I0-2 Magnitude
I1-3 Magnitude
I2-3 Magnitude
I0-3 Magnitude
I1-4 Magnitude
I2-4 Magnitude
I0-4 Magnitude
I1-5 Magnitude
I2-5 Magnitude
I0-5 Magnitude
IA-HV Magnitude
IB-HV Magnitude
IC-HV Magnitude
IN-HV Mea Mag
IN-HV Deriv Mag
IA-LV Magnitude
IB-LV Magnitude
IC-LV Magnitude
IN-LV Mea Mag
IN-LV Deriv Mag
IA-TV Magnitude
B202 P64x-TM-EN-4.1

DESCRIPTION
IB-TV Magnitude
IC-TV Magnitude
IN-TV Mea Mag
IN-TV Deriv Mag
VAB Magnitude
VBC Magnitude
VCA Magnitude
VAN Magnitude
VBN Magnitude
VCN Magnitude
Vx Magnitude
VN Derived Mag
V1 Magnitude
V2 Magnitude
V0 Magnitude
VAN RMS
VBN RMS
VCN RMS
Frequency
RTD 1
RTD 2
RTD 3
RTD 4
RTD 5
RTD 6
RTD 7
RTD 8
RTD 9
RTD 10
CL Input 1
CL Input 2
CL Input 3
CL Input 4
Volts/Hz 3ph
V/Hz W1 Thermal
Volts/Hz 1ph
V/Hz W2 Thermal
Hot Spot T
Top Oil T
Ambient T
LOL status
[Indexed String]
This setting defines the measured quantity assigned to CLO1
CLO Minimum 4D A8
This sets the CLO1 minimum setting
CLO Maximum 4D AA
This sets the CLO1 maximum setting
CLO OUTPUT2 4D AF Sub-Heading
Disabled
CLO Status 4D B0 Disabled Enabled
[Indexed String]
Enable or disables the current loop (transducer) output 1 element
0-1mA
0-10mA
CLO Type 4D B2 4-20mA 0-20mA
4-20mA
[Indexed String]
Current loop 1 output type
Primary
CLO Set Values 4D B4 Primary Secondary
[Indexed String]
P64x-TM-EN-4.1 B203

DESCRIPTION
This setting controls if the measured values from current loop output 1 are Primary or Secondary values
IA-1 Magnitude
IB-1 Magnitude
IC-1 Magnitude
IA-2 Magnitude
IB-2 Magnitude
IC-2 Magnitude
IA-3 Magnitude
IB-3 Magnitude
IC-3 Magnitude
IA-4 Magnitude
IB-4 Magnitude
IC-4 Magnitude
IA-5 Magnitude
IB-5 Magnitude
IC-5 Magnitude
I1-1 Magnitude
I2-1 Magnitude
I0-1 Magnitude
I1-2 Magnitude
I2-2 Magnitude
I0-2 Magnitude
I1-3 Magnitude
I2-3 Magnitude
I0-3 Magnitude
I1-4 Magnitude
I2-4 Magnitude
I0-4 Magnitude
I1-5 Magnitude
I2-5 Magnitude
I0-5 Magnitude
IA-HV Magnitude
CLO Parameter 4D B6 IB Magnitude
IB-HV Magnitude
IC-HV Magnitude
IN-HV Mea Mag
IN-HV Deriv Mag
IA-LV Magnitude
IB-LV Magnitude
IC-LV Magnitude
IN-LV Mea Mag
IN-LV Deriv Mag
IA-TV Magnitude
IB-TV Magnitude
IC-TV Magnitude
IN-TV Mea Mag
IN-TV Deriv Mag
VAB Magnitude
VBC Magnitude
VCA Magnitude
VAN Magnitude
VBN Magnitude
VCN Magnitude
Vx Magnitude
VN Derived Mag
V1 Magnitude
V2 Magnitude
V0 Magnitude
VAN RMS
VBN RMS
VCN RMS
Frequency
RTD 1
RTD 2
B204 P64x-TM-EN-4.1

DESCRIPTION
RTD 3
RTD 4
RTD 5
RTD 6
RTD 7
RTD 8
RTD 9
RTD 10
CL Input 1
CL Input 2
CL Input 3
CL Input 4
Volts/Hz 3ph
V/Hz W1 Thermal
Volts/Hz 1ph
V/Hz W2 Thermal
Hot Spot T
Top Oil T
Ambient T
LOL status
[Indexed String]
This setting defines the measured quantity assigned to current loop output 1
CLO Minimum 4D B8
Current loop output 1 minimum setting. Defines the lower range of the measurement
CLO Maximum 4D BA
Current loop output 1 maximum setting. Defines the upper range of the measurement
CLO OUTPUT3 4D BF Sub-Heading
Disabled
CLO Status 4D C0 Disabled Enabled
[Indexed String]
0-1mA
0-10mA
CLO Type 4D C2 4-20mA 0-20mA
4-20mA
[Indexed String]
Primary
CLO Set Values 4D C4 Primary Secondary
[Indexed String]
IA-1 Magnitude
IB-1 Magnitude
IC-1 Magnitude
IA-2 Magnitude
IB-2 Magnitude
IC-2 Magnitude
IA-3 Magnitude
IB-3 Magnitude
IC-3 Magnitude
IA-4 Magnitude
CLO Parameter 4D C6 IC Magnitude
IB-4 Magnitude
IC-4 Magnitude
IA-5 Magnitude
IB-5 Magnitude
IC-5 Magnitude
I1-1 Magnitude
I2-1 Magnitude
I0-1 Magnitude
I1-2 Magnitude
I2-2 Magnitude
P64x-TM-EN-4.1 B205

DESCRIPTION
I0-2 Magnitude
I1-3 Magnitude
I2-3 Magnitude
I0-3 Magnitude
I1-4 Magnitude
I2-4 Magnitude
I0-4 Magnitude
I1-5 Magnitude
I2-5 Magnitude
I0-5 Magnitude
IA-HV Magnitude
IB-HV Magnitude
IC-HV Magnitude
IN-HV Mea Mag
IN-HV Deriv Mag
IA-LV Magnitude
IB-LV Magnitude
IC-LV Magnitude
IN-LV Mea Mag
IN-LV Deriv Mag
IA-TV Magnitude
IB-TV Magnitude
IC-TV Magnitude
IN-TV Mea Mag
IN-TV Deriv Mag
VAB Magnitude
VBC Magnitude
VCA Magnitude
VAN Magnitude
VBN Magnitude
VCN Magnitude
Vx Magnitude
VN Derived Mag
V1 Magnitude
V2 Magnitude
V0 Magnitude
VAN RMS
VBN RMS
VCN RMS
Frequency
RTD 1
RTD 2
RTD 3
RTD 4
RTD 5
RTD 6
RTD 7
RTD 8
RTD 9
RTD 10
CL Input 1
CL Input 2
CL Input 3
CL Input 4
Volts/Hz 3ph
V/Hz W1 Thermal
Volts/Hz 1ph
V/Hz W2 Thermal
Hot Spot T
Top Oil T
Ambient T
LOL status
[Indexed String]
B206 P64x-TM-EN-4.1

DESCRIPTION
CLO Minimum 4D C8
CLO Maximum 4D CA
CLO OUTPUT4 4D CF Sub-Heading
Disabled
CLO Status 4D D0 Disabled Enabled
[Indexed String]
0-1mA
0-10mA
CLO Type 4D D2 4-20mA 0-20mA
4-20mA
[Indexed String]
Primary
CLO Set Values 4D D4 Primary Secondary
[Indexed String]
IA-1 Magnitude
IB-1 Magnitude
IC-1 Magnitude
IA-2 Magnitude
IB-2 Magnitude
IC-2 Magnitude
IA-3 Magnitude
IB-3 Magnitude
IC-3 Magnitude
IA-4 Magnitude
IB-4 Magnitude
IC-4 Magnitude
IA-5 Magnitude
IB-5 Magnitude
IC-5 Magnitude
I1-1 Magnitude
I2-1 Magnitude
I0-1 Magnitude
I1-2 Magnitude
I2-2 Magnitude
CLO Parameter 4D D6 Vx Magnitude I0-2 Magnitude
I1-3 Magnitude
I2-3 Magnitude
I0-3 Magnitude
I1-4 Magnitude
I2-4 Magnitude
I0-4 Magnitude
I1-5 Magnitude
I2-5 Magnitude
I0-5 Magnitude
IA-HV Magnitude
IB-HV Magnitude
IC-HV Magnitude
IN-HV Mea Mag
IN-HV Deriv Mag
IA-LV Magnitude
IB-LV Magnitude
IC-LV Magnitude
IN-LV Mea Mag
IN-LV Deriv Mag
IA-TV Magnitude
P64x-TM-EN-4.1 B207

DESCRIPTION
IB-TV Magnitude
IC-TV Magnitude
IN-TV Mea Mag
IN-TV Deriv Mag
VAB Magnitude
VBC Magnitude
VCA Magnitude
VAN Magnitude
VBN Magnitude
VCN Magnitude
Vx Magnitude
VN Derived Mag
V1 Magnitude
V2 Magnitude
V0 Magnitude
VAN RMS
VBN RMS
VCN RMS
Frequency
RTD 1
RTD 2
RTD 3
RTD 4
RTD 5
RTD 6
RTD 7
RTD 8
RTD 9
RTD 10
CL Input 1
CL Input 2
CL Input 3
CL Input 4
Volts/Hz 3ph
V/Hz W1 Thermal
Volts/Hz 1ph
V/Hz W2 Thermal
Hot Spot T
Top Oil T
Ambient T
LOL status
[Indexed String]
IA-1 Magnitude
IB-1 Magnitude
IC-1 Magnitude
IA-2 Magnitude
IB-2 Magnitude
IC-2 Magnitude
IA-3 Magnitude
IB-3 Magnitude
IC-3 Magnitude
IA-4 Magnitude
CLO Parameter 4D D6 IN Derived Mag
IB-4 Magnitude
IC-4 Magnitude
IA-5 Magnitude
IB-5 Magnitude
IC-5 Magnitude
I1-1 Magnitude
I2-1 Magnitude
I0-1 Magnitude
I1-2 Magnitude
I2-2 Magnitude
B208 P64x-TM-EN-4.1

DESCRIPTION
I0-2 Magnitude
I1-3 Magnitude
I2-3 Magnitude
I0-3 Magnitude
I1-4 Magnitude
I2-4 Magnitude
I0-4 Magnitude
I1-5 Magnitude
I2-5 Magnitude
I0-5 Magnitude
IA-HV Magnitude
IB-HV Magnitude
IC-HV Magnitude
IN-HV Mea Mag
IN-HV Deriv Mag
IA-LV Magnitude
IB-LV Magnitude
IC-LV Magnitude
IN-LV Mea Mag
IN-LV Deriv Mag
IA-TV Magnitude
IB-TV Magnitude
IC-TV Magnitude
IN-TV Mea Mag
IN-TV Deriv Mag
VAB Magnitude
VBC Magnitude
VCA Magnitude
VAN Magnitude
VBN Magnitude
VCN Magnitude
Vx Magnitude
VN Derived Mag
V1 Magnitude
V2 Magnitude
V0 Magnitude
VAN RMS
VBN RMS
VCN RMS
Frequency
RTD 1
RTD 2
RTD 3
RTD 4
RTD 5
RTD 6
RTD 7
RTD 8
RTD 9
RTD 10
CL Input 1
CL Input 2
CL Input 3
CL Input 4
Volts/Hz 3ph
V/Hz W1 Thermal
Volts/Hz 1ph
V/Hz W2 Thermal
Hot Spot T
Top Oil T
Ambient T
LOL status
[Indexed String]
P64x-TM-EN-4.1 B209

DESCRIPTION
P642 only.
CLO Minimum 4D D8
CLO Maximum 4D DA
Select Record B1 01
[UINT16]
Select Record
Time and Date
Time and Date B1 02
[IEC Date and Time]
Time and Date
Record Text
Record Text B1 03
[ASCII Text]
Text Description of Error
Type
Type B1 04
[UINT32]
Error Code
Data
Data B1 05
[UINT32]
Error Code
Hot Spot T
Hot Spot T B1 E0
[UINT32]
auto extraction event record
Top Oil T
Top Oil T B1 E1
[UINT32]
Ambient T
Ambient T B1 E2
[UINT32]
EF1 Derived
EF1 Derived B1 E3
[UINT32]
EF2 Derived
EF2 Derived B1 E4
[UINT32]
EF3 Derived
EF3 Derived B1 E5
[UINT32]
EF1 Measured
EF1 Measured B1 E6
[UINT32]
EF2 Measured
EF2 Measured B1 E7
[UINT32]
EF3 Measured
EF3 Measured B1 E8
[UINT32]
3ph V/Hz
3ph V/Hz B1 E9
[UINT32]
1ph V/Hz
1ph V/Hz B1 EA
[UINT32]
PSL Settings
Domain B2 04 PSL Settings PSL Configuration
[Indexed String]
Domain
Sub-Domain B2 08 Group 1 Group 1
B210 P64x-TM-EN-4.1

DESCRIPTION
Group 2
Group 3
Group 4
[Indexed String]
Sub-Domain
Version B2 0C 256
[Unsigned Integer (2 Bytes)]
Version
Data Transfer
B2 18
Reference
Data Transfer Reference
Prepare Rx
Complete Rx
Prepare Tx
Complete Tx
Transfer Mode B2 1C 6 Rx Prepared
Tx Prepared
OK
Error
[Unsigned Integer Indexed Strings]
Transfer Mode
Data Transfer B2 20
Data Transfer
Recorder Source
Recorder Source B3 02 Samples
[Indexed String]
Recorder Source
03-
Reserved for future use B3 Reserved for future use
1F
Reserved for future use
Select Record B4 01 0
[Unsigned Integer]
Select Record
Trigger Time
Trigger Time B4 02
Trigger Time
Active Channels
Active Channels B4 03
[Binary Flag]
Active Channels
Channel Types
Channel Types B4 04
[Binary Flag]
Channel Types
Channel Offsets
Channel Offsets B4 05
Channel Offsets
Channel Scaling
Channel Scaling B4 06
Channel Scaling
Channel SkewVal
Channel SkewVal B4 07
[Integer]
Channel SkewVal
Channel MinVal
Channel MinVal B4 08
[Integer]
Channel MinVal
Channel MaxVal
Channel MaxVal B4 09
[Integer]
Channel MaxVal
Format
Format B4 0A
[Unsigned Integer]
Format
Upload B4 0B Upload
P64x-TM-EN-4.1 B211

DESCRIPTION
[Unsigned Integer]
Upload
No. Of Samples
No. Of Samples B4 10
[Unsigned Integer]
No. Of Samples
Trig Position
Trig Position B4 11
[Unsigned Integer]
Trig Position
Time Base
Time Base B4 12
Time Base
Sample Timer
Sample Timer B4 14
[Unsigned Integer]
Sample Timer
Dist. Channel 1
Dist. Channel 1 B4 20
[Integer]
Dist. Channel 1
Dist. Channel 2
[Integer]
Dist. Channel 2
Dist. Channel 3
[Integer]
Dist. Channel 3
Dist. Channel 4
[Integer]
Dist. Channel 4
Dist. Channel 5
[Integer]
Dist. Channel 5
Dist. Channel 6
[Integer]
Dist. Channel 6
Dist. Channel 7
[Integer]
Dist. Channel 7
Dist. Channel 8
[Integer]
Dist. Channel 8
Dist. Channel 9
[Integer]
Dist. Channel 9
Dist. Channel 10
[Integer]
Dist. Channel 10
Dist. Channel 11
Dist. Channel 11 B4 2A
[Integer]
Dist. Channel 11
Dist. Channel 12
Dist. Channel 12 B4 2B
[Integer]
Dist. Channel 12
Dist. Channel 13
Dist. Channel 13 B4 2C
[Integer]
Dist. Channel 13
Dist. Channel 31
Dist. Channel 31 B4 3E
[Binary Flag]
Dist. Channel 31
Dist. Channel 32
Dist. Channel 32 B4 3F
[Binary Flag]
Dist. Channel 32
B212 P64x-TM-EN-4.1

DESCRIPTION
Comms Diagnostics
B6 00
(Hidden)
This column contains Comms Diagnostics (Hidden)
Bus Comms Err Count Bus Comms Err Count Front
B6 01
Front [UINT32]
This records the Bus Comms Err Count Front parameter
Bus Message Count Bus Message Count Front
B6 02
Front [UINT32]
This records the Bus Message Count Front parameter
Protocol Err Count Protocol Err Count Front
B6 03
Front [UINT32]
This records the Protocol Error Count Front parameter
Reset front count
Reset front count B6 05
[(Reset Menu Cell cmd only)]
This records the Reset Count Front parameter
Bus Comms Err Count Bus Comms Err Count Rear
B6 06
Rear [UINT32]
This records the Bus Comms Error Count Rear parameter
Protocol Err Count Rear
Protocol Err Count Rear B6 07
[UINT32]
This records the Protocol Error Count Rear parameter
Busy Count Rear
Busy Count Rear B6 09
[UINT32]
This records the Busy Count Rear parameter
Reset Rear Count
Reset Rear Count B6 0A
[(Reset Menu Cell cmd only)]
This records the Reset Count Rear parameter
Grp 1 PSL Ref
Grp 1 PSL Ref B7 01
[ASCII Text (32 Chars)]
Grp 1 PSL Ref
Date/Time
Date/Time B7 02
[IEC 870 Date & Time]
Date/Time
Grp 1 PSL ID
Grp 1 PSL ID B7 03
Grp 1 PSL ID
Grp 2 PSL Ref
Grp 2 PSL Ref B7 11
Grp 2 PSL Ref
Date/Time
Date/Time B7 12
Date/Time
Grp 2 PSL ID
Grp 2 PSL ID B7 13
Grp 2 PSL ID
Grp 3 PSL Ref
Grp 3 PSL Ref B7 21
Grp 3 PSL Ref
Date/Time
Date/Time B7 22
Date/Time
Grp 3 PSL ID
Grp 3 PSL ID B7 23
Grp 3 PSL ID
Grp 4 PSL Ref
Grp 4 PSL Ref B7 31
Grp 4 PSL Ref
Date/Time
Date/Time B7 32
P64x-TM-EN-4.1 B213

DESCRIPTION
Date/Time
Grp 4 PSL ID
Grp 4 PSL ID B7 33
Grp 4 PSL ID
COMMS SYS DATA BF 00
This column contains COMMS SYS DATA parameters
Record Cntl Ref
Record Cntl Ref BF 01 B300
[Menu Cell(2)]
Dist Record Cntrl Ref
Record Ext Ref
Record Ext Ref BF 02 B400
[Menu Cell(2)]
Dist Record Extract Ref
Setting Transfer BF 03
This records the Setting Transfer parameter
Reset Demand BF 04
Reset Demand - this is data but it supports the Reset Menu cell.
Block Xfer Ref
Block Xfer Ref BF 06 B200
[Menu Cell(2)]
Block Xfer Ref
Read Only Mode
Read Only Mode BF 07
8 registers for reading 16 character encryption key

Encryption Key BF 10 first character of a pair
[Foreign Data]
Front Port
Rear Port 1
Rear Port 2
Ethernet Port
Connected i/face BF 11
Courier Tunnel
IEC61850
DNP3OE
Security Column
Security Column BF 12 25 00
[Menu Cell]
Port Disable
Port Disable BF 13 25 05
[Menu Cell]
Port Disable end

Port Disable end BF 14 25 0B
[Menu Cell]

PW Entry Needed BF 15 0
Password Reset BF F0
B214 P64x-TM-EN-4.1
ORDINAL SIGNAL NAME ELEMENT NAME

DESCRIPTION
0 Relay 1 DDB_OUTPUT_RELAY_1
DDB signal connected to output relay contact 1
64 Opto Input 1 DDB_OPTO_ISOLATOR_1
DDB signal connected to opto-input 1
P64x-TM-EN-4.1 B215

DESCRIPTION
B216 P64x-TM-EN-4.1

DESCRIPTION
128 Relay Cond 1 DDB_OUTPUT_CON_1
DDB signal connected to output relay conditioner 1
P64x-TM-EN-4.1 B217

DESCRIPTION
192 LED1 Red DDB_OUTPUT_TRI_LED_1_RED
DDB signal indicates that the red LED is active
193 LED1 Grn DDB_OUTPUT_TRI_LED_1_GRN
DDB signal indicates that the green LED is active
208 FnKey LED1 Red DDB_OUTPUT_TRI_LED_9_RED
209 FnKey LED1 Grn DDB_OUTPUT_TRI_LED_9_GRN
B218 P64x-TM-EN-4.1

DESCRIPTION
256 LED1 Con R DDB_TRI_LED_RED_CON_1
This DDB signal drives the red LED Conditioner 1
257 LED1 Con G DDB_TRI_LED_GRN_CON_1
This DDB signal drives the green LED Conditioner 1
P64x-TM-EN-4.1 B219

DESCRIPTION
272 FnKey LED1 ConR DDB_TRI_LED_RED_CON_9
273 FnKey LED1 ConG DDB_TRI_LED_GRN_CON_9
320 LED 1 DDB_OUTPUT_LED_1
DDB signal indicates that the single-colour LED is active
B220 P64x-TM-EN-4.1

DESCRIPTION
328 LED Cond IN 1 DDB_LED_CON_1
This DDB signal drives the single-colour LED Conditioner 1
352 Function Key 1 DDB_FN_KEY_1
DDB signal indicates that Function key 1 is active
384 Timer out 1 DDB_TIMEROUT_1
DDB signal connected to timer 1 output
P64x-TM-EN-4.1 B221

DESCRIPTION
DDB signal connected to timer 11output
DDB signal connected to timer 1 4 output
416 Timer in 1 DDB_TIMERIN_1
DDB signal connected to timer 1 input
432 Init Trip CB1 DDB_LOGIC_INPUT_TRIP_1
Initiate tripping of circuit breaker 1 from a manual command
437 Init Close CB1 DDB_LOGIC_INPUT_CLOSE_1
Initiate closing of circuit breaker 1 from a manual command
B222 P64x-TM-EN-4.1

DESCRIPTION
450 SG-DDB Invalid DDB_ILLEGAL_OPTO_SETTINGS_GROUP
This DDB signal indicates that the Setting Group selection via opto-input is invalid
451 CB Status Alarm DDB_CB_STATUS_ALARM
This DDB signal indicates that the CB is in an invalid state
452 Any RTD Alarm DDB_RTD_ALARM
This DDB signal is the RTD Thermal Alarm
453 RTD Open Cct DDB_RTD_OPEN_CCT
This DDB signal indicates RTD Open Circuit Failure
454 RTD short Cct DDB_RTD_SHORT_CCT
This DDB signal indicates RTD Short Circuit Failure
455 RTD Data Error DDB_RTD_DATA_ERROR
This DDB signal indicates RTD Data Inconsistency Error
456 RTD Board Fail DDB_RTD_BOARD_FAILURE
This DDB signal indicates RTD Board Failure
457 CLI1 Alarm DDB_CL_INPUT_1_ALARM
This DDB signal is the Current Loop Input 1 Alarm
461 CLI1 I< Fail Alm DDB_CLI_1_UNDERCURRENT_ALARM
This DDB signal is the Current Loop Input 1 Undercurrent Fail Alarm
465 Prot'n Disabled DDB_OOS_ALARM
This DDB signal indicates an Out-of-Service condition
466 F out of range DDB_FREQ_ALARM
This DDB signal indicates a 'Frequency out of range' condition
467 Prot'n Disabled DDB_PROTECTION_DISABLED
Prot'n Disabled
468 ManCB1 Unhealthy DDB_CONTROL_CB1_UNHEALTHY
ManCB1 Unhealthy - alarm set if CB1 remains "unhealthy" for CB Control set time "CB Healthy Time" when operator controlled CB1 close
sequence is initiated. (Please see description for CB Control setting "CB Healthy Time").
470 CL Card I/P Fail DDB_CLIO_CARD_INPUT_FAIL
This DDB signal indicates CLIO Card Input Failure
471 CL Card O/P Fail DDB_CLIO_CARD_OUTPUT_FAIL
This DDB signal indicates CLIO Card IOutput Failure
472 VCO>1 Config err DDB_VCO_1_CONFIG_ALARM
The VCO terminal input does not correspond to the location of the main VT
473 VCO>2 Config err DDB_VCO_2_CONFIG_ALARM
The VCO terminal input does not correspond to the location of the main VT
P64x-TM-EN-4.1 B223

DESCRIPTION
475 CT Fail Alarm DDB_CTS_INDICATION
This DDB signal indicates a Current Transformer Fail condition
476 Cct Fail Alarm DDB_CIRCUITRY_FLT_ALM
this DDB signal is a circuity fault alarm
477 VT Fail Alarm DDB_VTS_INDICATION
This DDB signal indicates a Voltage Transformer Fail condition
478 ThermalPtrp Alm DDB_TOL_PRETRIP_ALARM
This DDB signal is used for issuing a thermal protection pre-trip alarm.
479 FAA alarm DDB_FAA_ALARM
This DDB signal is used for issuing a thermal protection aging acceleration factor alarm.
480 LOL alarm DDB_LOL_ALARM
This DDB signal is the Loss of Life alarm
481 Breaker Fail DDB_BREAKER_FAIL_ALARM
This DDB signal is an alarm indicating CB Failure
482 Ct para mismatch DDB_CT_MISMATCH_ALARM
This DDB signal is used for indicating that one or more CTs matching factors are out of range.
483 CT Selection Alm DDB_CT_REPEATED_SELECTED_ALARM
This DDB signal is used for indicating that the same current input is assigned to more than one terminal.
484 SinglePha CT Alm DDB_SINGLEPHASE_CT_ALARM
This DDB signal is used for indicating that the same single phase CT is assigned simultaneously to high impedance REF as well as another
protection function.
485 insuff No. of CT DDB_INSUFF_NO_OF_CT
This DDB signal is used to indicate that there are insufficient CTs to be assigned to differential protection.
486 Disc CT invalid DDB_DISC_CT_INVALID
This DDB signal is used to indicate that the CT stored status does not match prior to and after restoration of the auxiliary supply.
487 HV-LZREF sf OOR DDB_HV_SCALING_FACTOR_ALARM
This DDB signal is used for indicating that the scaling factor used for HV low impedance REF is out of range.
488 LV-LZREF sf OOR DDB_LV_SCALING_FACTOR_ALARM
This DDB signal is used for indicating that the scaling factor used for LV low impedance REF is out of range.
489 TV-LZREF sf OOR DDB_TV_SCALING_FACTOR_ALARM
This DDB signal is used for indicating that the scaling factor used for TV low impedance REF is out of range.
490 AutoLZREF sf OOR DDB_AUTO_SCALING_FACTOR_ALARM
This DDB signal is used for indicating that the scaling factor used for autotransformer low impedance REF is out of range.
491 VRO>1 Config err DDB_VRO_1_CONFIG_ALARM
The VRO terminal input does not correspond to the location of the main VT
492 VRO>2 Config err DDB_VRO_2_CONFIG_ALARM
The VRO terminal input does not correspond to the location of the main VT
ManCB4Unhealthy - alarm set if CB1 remains "unhealthy" for CB Control set time "CB Healthy Time" when operator controlled CB4 close
495 CB1 Trip Fail DDB_CB1_FAILED_TO_TRIP
CB1 Failed to Trip - alarm set if CB1 does not trip within set Trip Pulse Time when CB1 trip command is issued.
500 CB1 Close Fail DDB_CB1_FAILED_TO_CLOSE
CB1 Failed to Close - alarm set if CB1 fails to close within set Close Pulse Time when CB1 close command is issued
B224 P64x-TM-EN-4.1

DESCRIPTION
501 3Ph V/Hz> Alarm DDB_VPERHZ_ALARM_1
This DDB signal is used for indicating an overfluxing condition when three phase VT is used.
502 3Ph V/Hz> PrTrp DDB_VPERHZ_PRETRP_ALARM_1
This DDB signal is used to issue a pre-trip alarm for an overfluxing condition when the time left to trip is equal to the pre-trip time setting.
503 1Ph V/Hz> Alarm DDB_VPERHZ_ALARM_2
This DDB signal is used for indicating an overfluxing condition.
504 1Ph V/Hz> PrTrp DDB_VPERHZ_PRETRP_ALARM_2
This DDB signal is used to issue a pre-trip alarm for an overfluxing condition when the time left to trip is equal to the pre-trip time set in the
setting.
507 Freq Prot Alm DDB_FREQ_PROT_ALM
This is the Frequency Protection Alarm
508 Throu fault Alm DDB_THROUGH_FAULT_ALARM
This is the Through fault Alarm
512 Battery Fail DDB_BATTERY_FAIL_ALARM
This DDB signal indicates failure of the backup battery
513 Field Volts Fail DDB_FIELD_VOLTS_FAIL
This DDB signal indicates failure of the field voltage
515 GOOSE IED Absent DDB_GOOSE_MISSING_IED_ALARM
This is a GOOSE alarm indicating that the IED is absent.
516 NIC Not Fitted DDB_ECARD_NOT_FITTED_ALARM
This DDB signal indicates that an Ethernet card is not fitted
517 NIC No Response DDB_NIC_NOT_RESPONDING_ALARM
This DDB signal indicates that the Ethernet card is not responding
518 NIC Fatal Error DDB_NIC_FATAL_ERROR_ALARM
This DDB signal indicates that the Ethernet card has a fatal error
519 NIC Soft. Reload DDB_NIC_SOFTWARE_RELOAD_ALARM
This DDB signal is the Ethernet card software reload Alarm
520 Bad TCP/IP Cfg. DDB_INVALID_TCP_IP_CONFIG_ALARM
This DDB signal indicates that the TCP/IP configuration is invalid
521 Bad OSI Config. DDB_INVALID_OSI_CONFIG_ALARM
This is the bad OSI Configuration Alarm
522 NIC Link Fail DDB_NIC_LINK_FAIL_ALARM
This DDB signal indicates that there is a commnication failure on the Etherent card
523 NIC SW Mis-Match DDB_SW_MISMATCH_ALARM
This DDB signal is the main card/Ethernet card software mismatch Alarm
524 IP Addr Conflict DDB_IP_ADDRESS_CONFLICT_ALARM
This DDB signal indicates that thre is an IP Address conflict
525 Trip LED Trigger DDB_TRIP_LED_TRIGGER
This DDB triggers the fixed trip LED
532 SNTP Failure DDB_SNTP_FAIL_ALARM
This DDB signal indicates SNTP failure
533 NIC MemAllocFail DDB_NIC_MEM_ALLOC_FAIL_ALARM
This DDB signal indicates that the MMS libraries memory allocation has failed
534 PTP Sync Fail DDB_PTP_FAIL_ALARM
Indicates PTP sync failed
537 BBRAM Failure DDB_BBRAM_VERIFY_FAIL
BBRAM Verify Fail
545 Block Contacts DDB_CONTACTS_BLOCKED_IP
DDB to block output contacts, same as setting Commissioning Column -> Test Mode -> Contacts Blocked
546 Contacts Blocked DDB_CONTACTS_BLOCKED_OP
P64x-TM-EN-4.1 B225

DESCRIPTION
Indicates contacts blocked mode enabled. Can be mapped in PSL and sent via InterMiCOM/IM64 to block contacts at the remote end.
551 Block Transdiff DDB_BLK_TRANS_DIFF
This DDB signal blocks the Transformer Differential protection
552 IA2H Diff Start DDB_2ND_HAR_BLKA
This DDB signal provides 2nd Harmonic blocking for phase A
553 IB2H Diff Start DDB_2ND_HAR_BLKB
This DDB signal provides 2nd Harmonic blocking for phase B
554 IC2H Diff Start DDB_2ND_HAR_BLKC
This DDB signal provides 2nd Harmonic blocking for phase C
555 IA5H Diff Start DDB_5TH_HAR_BLKA
This DDB signal provides 5th Harmonic blocking for phase A
556 IB5H Diff Start DDB_5TH_HAR_BLKB
This DDB signal provides 5th Harmonic blocking for phase B
557 IC5H Diff Start DDB_5TH_HAR_BLKC
This DDB signal provides 5th Harmonic blocking for phase C
558 Phs Comp BlkA DDB_PHASE_COMP_BLKA
This DDB signal provides phase comparson blocking for phase A
559 Phs Comp BlkB DDB_PHASE_COMP_BLKB
This DDB signal provides phase comparson blocking for phase B
560 Phs Comp BlkC DDB_PHASE_COMP_BLKC
This DDB signal provides phase comparson blocking for phase C
562 V<1 Timer Block DDB_PUV_1_TIMER_BLOCK
This DDB signal blocks the first stage Phase Undervoltage time delay
563 V<2 Timer Block DDB_PUV_2_TIMER_BLOCK
This DDB signal blocks the second stage Phase Undervoltage time delay
564 V>1 Timer Block DDB_POV_1_TIMER_BLOCK
This DDB signal blocks the first stage Phase Overvoltage time delay
565 V>2 Timer Block DDB_POV_2_TIMER_BLOCK
This DDB signal blocks the second stage Phase Overvoltage time delay
566 VN>1 Timer Blk DDB_RESOV_1_TIMER_BLOCK
This DDB signal blocks the first stage Residual Overvoltage time delay
567 VN>2 Timer Blk DDB_RESOV_2_TIMER_BLOCK
This DDB signal blocks the first stage Residual Overvoltage time delay
571 Inhibit CTS DDB_INHIBIT_CTS
This DDB signal inhibits the Current Transformer Supervision function
572 CTS Block DDB_CTS_BLK
This DDB signal blocks current transformer supervision
573 CTS CT1 DDB_CTS_CT1
This DDB signal is generated by the CTS logic (when set to restraint mode) and used for alarming that the CT1 circuit has some issues.
578 CT1 Fail DDB_CTS_CT1_IND
This DDB signals indicates failure of CT1
588 Blk TOL DDB_BLK_TOL
B226 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal can be used to block the thermal overcurrent element.
589 CTS HV DDB_CTS_HV
This DDB signal is generated by the HV winding CTS logic (if set to restraint mode) when any of the CTS associated with the HV current inputs
is asserted.
590 CTS LV DDB_CTS_LV
This DDB signal is generated by the LV winding CTS logic (if set to restraint mode) when any of the CTS associated with the LV current inputs is
asserted.
591 CTS TV DDB_CTS_TV
This DDB signal is generated by the TV winding CTS logic (if set to restraint mode) when any of the CTS associated with the TV current inputs is
asserted.
592 Inhibit VTS DDB_INHIBIT_VTS
This DDB signal inhibits the VTS function
594 Blk REF HV DDB_BLK_REF_HV
This DDB signal blocks REF protection for the HV winding
595 Blk REF LV DDB_BLK_REF_LV
This DDB signal blocks REF protection for the LV winding
596 Blk REF TV DDB_BLK_REF_TV
This DDB signal blocks REF protection for the TV winding
597 Blk REF Auto DDB_BLK_REF_AUTO
This DDB signal blocks REF protection for Autotransformer configuration
598 POC 1 I>1 TBlk DDB_POC1_STAGE1_TIMER_BLOCK
This DDB signal blocks the first stage time delay for the first Overcurrent element
This DDB signal blocks the second stage time delay for the first Overcurrent element
This DDB signal blocks the third stage time delay for the first Overcurrent element
This DDB signal blocks the fourth stage time delay for the first Overcurrent element
This DDB signal blocks the first stage time delay for the second Overcurrent element
This DDB signal blocks the second stage time delay for the second Overcurrent element
This DDB signal blocks the third stage time delay for the second Overcurrent element
This DDB signal blocks the fourth stage time delay for the second Overcurrent element
This DDB signal blocks the first stage time delay for the third Overcurrent element
This DDB signal blocks the second stage time delay for the third Overcurrent element
This DDB signal blocks the third stage time delay for the third Overcurrent element
This DDB signal blocks the fourth stage time delay for the third Overcurrent element
612 CBF1 Timer1 Blk DDB_T1_TBF1_TIMER_BLOCK
This is the first stage CB fail timer block for CB1
This is the second stage CB fail timer block for CB1
P64x-TM-EN-4.1 B227

DESCRIPTION
622 F<1 Timer Block DDB_UFREQ_1_TIMER_BLOCK
This DDB signal blocks the Underfrequency Stage 1 Timer
626 F>1 Timer Block DDB_OFREQ_1_TIMER_BLOCK
This DDB signal blocks the Overfrequency Stage 1 Timer
627 F>2 Timer Block DDB_OFREQ_2_TIMER_BLOCK
This DDB signal blocks the Overfrequency Stage 2 Timer
628 HV StubBus Enabl DDB_STUB_BUS_HV_ENABLED
This DDB signal enables Stub Bus for the HV winding
629 LV StubBus Enabl DDB_STUB_BUS_LV_ENABLED
This DDB signal enables Stub Bus for the LV winding
630 TV StubBus Enabl DDB_STUB_BUS_TV_ENABLED
This DDB signal enables Stub Bus for the TV winding
631 HV StubBus Act DDB_STUB_BUS_HV_ACTIVED
This signal indicates that the HV Stub Bus is activated
632 LV StubBus Act DDB_STUB_BUS_LV_ACTIVED
This signal indicates that the LV Stub Bus is activated
633 TV StubBus Act DDB_STUB_BUS_TV_ACTIVED
This signal indicates that the TV Stub Bus is activated
634 Stop Freq Track DDB_FREQ_STOP_TRACK
Stop Freq Track
635 EF 1 IN>1 TBlk DDB_EF1_STAGE1_TIMER_BLOCK
This DDB signal blocks the first stage time delay for the first Earth Fault element
This DDB signal blocks the second stage time delay for the first Earth Fault element
This DDB signal blocks the third stage time delay for the first Earth Fault element
This DDB signal blocks the fourth stage time delay for the first Earth Fault element
This DDB signal blocks the first stage time delay for the second Earth Fault element
This DDB signal blocks the second stage time delay for the second Earth Fault element
This DDB signal blocks the third stage time delay for the second Earth Fault element
This DDB signal blocks the fourth stage time delay for the second Earth Fault element
This DDB signal blocks the first stage time delay for the third Earth Fault element
This DDB signal blocks the second stage time delay for the third Earth Fault element
This DDB signal blocks the third stage time delay for the third Earth Fault element
This DDB signal blocks the fourth stage time delay for the third Earth Fault element
This DDB signal blocks the first stage time delay for the third Earth Fault element
B228 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal blocks the second stage time delay for the third Earth Fault element
This DDB signal blocks the third stage time delay for the third Earth Fault element
This DDB signal blocks the fourth stage time delay for the third Earth Fault element
651 V2> Accelerate DDB_NPSOV_1_ACCELERATE
This DDB accerelates the operating time of NPS Over Voltage (when set to instantaneous)
652 VCO VAB<1 Start DDB_VCO_1_PH_AB_START
This DDB is asserted when the first stage of Voltage Controlled Overcurrent start signal is picked up on phase A
653 VCO VBC<1 Start DDB_VCO_1_PH_BC_START
This DDB is asserted when the first stage of Voltage Controlled Overcurrent start signal is picked up on phase B
654 VCO VCA<1 Start DDB_VCO_1_PH_CA_START
This DDB is asserted when the first stage of Voltage Controlled Overcurrent start signal is picked up on phase C
655 VCO VAB<2 Start DDB_VCO_2_PH_AB_START
This DDB is asserted when the second stage of Voltage Controlled Overcurrent start signal is picked up on phase A
656 VCO VBC<2 Start DDB_VCO_2_PH_BC_START
This DDB is asserted when the second stage of Voltage Controlled Overcurrent start signal is picked up on phase B
657 VCO VCA<2 Start DDB_VCO_2_PH_CA_START
This DDB is asserted when the second stage of Voltage Controlled Overcurrent start signal is picked up on phase C
658 VCO>1 TimeBlk DDB_VCO_1_TIMER_BLOCK
This DDB signal blocks the first stage Voltage Controlled Overcurrent timer
659 VCO>2 TimeBlk DDB_VCO_2_TIMER_BLOCK
This DDB signal blocks the second stage Voltage Controlled Overcurrent timer
660 Virtual Output01 DDB_GOOSEOUT_1
This DDB signal is a GOOSE virtual output
P64x-TM-EN-4.1 B229

DESCRIPTION
692 CT1 Excluded DDB_CT1_EXCLUDED
Assertion of this DDB excludes CT1 from protection functions.
697 CM Select 1X DDB_CM_SELECTOR_1X
By using this DDB ,together with the relavant X1 DDB, in the PSL one of the four cooling modes can be selected.
698 CM Select X1 DDB_CM_SELECTOR_X1
By using this DDB ,together with the relavant 1X DDB, in the PSL one of the four cooling modes can be selected.
700 Blk 3Ph V/Hz>1 DDB_INHIBIT_VPERHZ_1
DDB signal used for blocking the first stage of overfluxing element when three phase VT is used.
701 Blk 1Ph V/Hz>1 DDB_INHIBIT_VPERHZ_2
DDB signal used for blocking the first stage of overfluxing element when single phase VT is used.
702 CLI1 Block DDB_CL_INPUT_1_BLOCK
This DDB signal blocks Current Loop Input 1 protection
706 CB1 Alarm DDB_CB1_AUX_3PH_ALARM
Circuit Breaker 1 alarm indication.
B230 P64x-TM-EN-4.1

DESCRIPTION
707 CB1 Closed DDB_CB1_AUX_3PH_CLOSED
Monitors the status of Circuit Breaker 1. The status of CB1 is required by the dead pole logic.
Monitors the status of Circuit Breaker 2. The status of CB2 is required by the dead pole logic.
Monitors the status of Circuit Breaker3. The status of CB3 is required by the dead pole logic.
716 RP1 Read Only DDB_RP1_READ_ONLY
This DDB signal enables Read-only mode for rear port 1 (RP1)
717 RP2 Read Only DDB_RP2_READ_ONLY
This DDB signal enables Read-only mode for the optional rear port 2 (RP2)
718 NIC Read Only DDB_NIC_READ_ONLY
This DDB signal enables Read-only mode for the optional network interface Card (NIC)
719 103 MonitorBlock DDB_MONITOR_BLOCKING
IEC60870-5-103 Monitor Block. This DDB can be used in the PSL to block messages in the monitor direction.
720 103 CommandBlock DDB_COMMAND_BLOCKING
IEC60870-5-103 Command Block. This DDB can be used in the PSL to block messages in the command direction.
724 CT Exclu Ena DDB_CT_EXCLUSION_ENABLED
This DDB is used to exclude CTs (assigned to T1/2/3/4/5) from the protection functions. Other conditions should be satisfied as well.
725 CT1 Exclu Ena DDB_CT1_EXCLUSION_ENABLED
This DDB is used to exclude CT1 (assigned to T1) from the protection functions. Other conditions should be satisfied as well.
730 CT Saturation A DDB_CT_SATURATION_A
This DDB signal is the A-phase saturation flag
731 CT Saturation B DDB_CT_SATURATION_B
732 CT Saturation C DDB_CT_SATURATION_C
733 MAX_OVER_A DDB_MAX_OVER_A
maximum value of phase A is more than positive limitation
734 MAX_OVER_B DDB_MAX_OVER_B
maximum value of phase B is more than positive limitation
735 MAX_OVER_C DDB_MAX_OVER_C
maximum value of phase C is more than positive limitation
736 MIN_UNDER_A DDB_MIN_UNDER_A
minimum value of phase A is less than negative limitation
737 MIN_UNDER_B DDB_MIN_UNDER_B
minimum value of phase B is less than negative limitation
738 MIN_UNDER_C DDB_MIN_UNDER_C
minimum value of phase C is less than negative limitation
P64x-TM-EN-4.1 B231

DESCRIPTION
739 SEG_VALID_A DDB_SEG_VALID_A
the width of detected segment of phase A is valid
740 SEG_VALID_B DDB_SEG_VALID_B
the width of detected segment of phase B is valid
741 SEG_VALID_C DDB_SEG_VALID_C
the width of detected segment of phase C is valid
742 1_MAX_DEL3_A DDB_1_MAX_DEL3_A
the maximum 3rd difference of 1st half locates at the first 3 points
743 1_MAX_DEL3_B DDB_1_MAX_DEL3_B
744 1_MAX_DEL3_C DDB_1_MAX_DEL3_C
745 MAX_DEL1_A DDB_MAX_DEL1_A
the maximum 1st difference locates at the first 3 points
746 MAX_DEL1_B DDB_MAX_DEL1_B
747 MAX_DEL1_C DDB_MAX_DEL1_C
748 DEL3 > Thres A DDB_MAX_DEL3_OVER_THRES_A
maximum 3rd difference exceeds threshold
749 DEL3 > Thres B DDB_MAX_DEL3_OVER_THRES_B
750 DEL3 > Thres C DDB_MAX_DEL3_OVER_THRES_C
751 1>2K DEL3 A DDB_1_OVER_2K_MAXDEL3_A
the 1st of maximum 3rd difference is greater than k times of 2nd one
752 1>2K DEL3 B DDB_1_OVER_2K_MAXDEL3_B
753 1>2K DEL3 C DDB_1_OVER_2K_MAXDEL3_C
757 VRO1 VAB<1 Start DDB_VRO_1_V_1_PH_AB_START
This DDB is asserted when the Measure voltage is less than (V<1) Voltage setting for first stage of Voltage Restrained Overcurrent start signal
for phase A
758 VRO1 VBC<1 Start DDB_VRO_1_V_1_PH_BC_START
for phase B
759 VRO1 VCA<1Start DDB_VRO_1_V_1_PH_CA_START
for phase C
This DDB is asserted when the Measure voltage is less than (V<1) Voltage setting for Second stage of Voltage Restrained Overcurrent start
signal for phase A
761 VRO2 VBC<1Start DDB_VRO_2_V_1_PH_BC_START
signal for phase B
762 VRO2 VCA<1 Start DDB_VRO_2_V_1_PH_CA_START
signal for phase C
763 External Fault A DDB_DIFF_EXTERNAL_FAULT_A
This DDB when asserted indicates that there is external fault on phase A
764 External Fault B DDB_DIFF_EXTERNAL_FAULT_B
This DDB when asserted indicates that there is external fault on phase B
765 External Fault C DDB_DIFF_EXTERNAL_FAULT_C
This DDB when asserted indicates that there is external fault on phase C
766 VCO>1 TimeBlk DDB_VRO_1_TIMER_BLOCK
This DDB signal blocks the first stage Voltage Restrained Overcurrent timer
767 VCO>2 TimeBlk DDB_VRO_2_TIMER_BLOCK
This DDB signal blocks the second stage Voltage Restrained Overcurrent timer
B232 P64x-TM-EN-4.1

DESCRIPTION
768 User Alarm 1 DDB_USER_ALARM_1
This DDB signal can be configured as a user-defined Alarm
P64x-TM-EN-4.1 B233

DESCRIPTION
800 User Alarm in 1 DDB_USER_ALARM_INPUT_1
User Alarm in 1
User Alarm in 2
User Alarm in 3
User Alarm in 4
User Alarm in 5
User Alarm in 6
User Alarm in 7
User Alarm in 8
User Alarm in 9
User Alarm in 10
User Alarm in 11
User Alarm in 12
User Alarm in 13
User Alarm in 14
User Alarm in 15
User Alarm in 16
User Alarm in 17
User Alarm in 18
User Alarm in 19
User Alarm in 20
User Alarm in 21
User Alarm in 22
User Alarm in 23
User Alarm in 24
User Alarm in 25
User Alarm in 26
B234 P64x-TM-EN-4.1

DESCRIPTION
User Alarm in 27
User Alarm in 28
User Alarm in 29
User Alarm in 30
User Alarm in 31
User Alarm in 32
833 CctFail Blk A DDB_CIR_FLT_A
This DDB when asserted indicates that there is a problem in AC wiring of phase A
834 CctFail Blk B DDB_CIR_FLT_B
This DDB when asserted indicates that there is a problem in AC wiring of phase B
835 CctFail Blk C DDB_CIR_FLT_C
This DDB when asserted indicates that there is a problem in AC wiring of phase C
837 NPOC1 Inhibit DDB_INHIBIT_NPSOC1
This DDB signal inhibits the first Negative Phase Overcurrent protection element
838 NPOC1 I2>1 TBlk DDB_NPSOC1_STAGE1_TIMER_BLOCK
This DDB signal blocks the first stage Negative Phase Overcurrent timer for the first element
This DDB signal blocks the second stage Negative Phase Overcurrent timer for the first element
This DDB signal blocks the third stage Negative Phase Overcurrent timer for the first element
This DDB signal blocks the fourth stage Negative Phase Overcurrent timer for the first element
This DDB signal inhibits the second Negative Phase Overcurrent protection element
This DDB signal blocks the first stage Negative Phase Overcurrent timer for the second element
This DDB signal blocks the second stage Negative Phase Overcurrent timer for the second element
This DDB signal blocks the third stage Negative Phase Overcurrent timer for the second element
This DDB signal blocks the fourth stage Negative Phase Overcurrent timer for the second element
This DDB signal inhibits the third Negative Phase Overcurrent protection element
This DDB signal blocks the first stage Negative Phase Overcurrent timer for the third element
This DDB signal blocks the second stage Negative Phase Overcurrent timer for the third element
This DDB signal blocks the third stage Negative Phase Overcurrent timer for the third element
This DDB signal blocks the fourth stage Negative Phase Overcurrent timer for the third element
852 Monitor Bit 1 DDB_MONITOR_PORT_1
This DDB signal can be assigned to any other DDB for commissioning purposes
P64x-TM-EN-4.1 B235

DESCRIPTION
862 MCB/VTS DDB_VTS_MCB_OPTO
This DDB signal initiates a VTS condition from a 3phase miniture circuit breaker
864 Reset Relays/LED DDB_RESET_RELAYS_LEDS
This DDB resets all latched output relays and LEDs
866 TFR De-energised DDB_TFR_DE_ENERGISED
This DDB monitors energization of the transformer. Warning; do not remove from PSL
867 Monitor Blocked DDB_CS103_BLOCK
IEC60870-5-103 Monitor Block. This DDB can be used in the PSL to block messages in the monitor direction.
868 Command Blocked DDB_CS103_CMD_BLOCK
IEC60870-5-103 Command Block. This DDB can be used in the PSL to block messages in the command direction.
869 Time Synch DDB_TIME_SYNCH
This DDB is used for time syncronisation with a resolution of one minuted when used in conjunction with an Opto input.
870 Test Mode DDB_TEST_MODE
This DDB signal initiates the test mode
871 Fault REC TRIG DDB_FAULT_RECORDER_START
This DDB triggers the fault recorder
872 SG Select x1 DDB_SG_SELECTOR_X1
This DDB signal sets the setting group
873 SG Select 1x DDB_SG_SELECTOR_1X
This DDB signal sets the setting group
874 Any Trip DDB_ANY_TRIP
This DDB signal is the trip Command In signal, which triggers the fixed trip LED and is mapped to the trip Command Out signal in the FSL.
875 Reset LOL DDB_RESET_LOL
This DDB signal resets the Lost of Life accumulator
876 Reset Thermal DDB_RESET_THERMAL
This DDB signal resets the Thermal State
877 3Ph Reset V/Hz DDB_RESET_VPERHZ_1
This DDB (available in P643/5) when asserted resets Overflux element when three phase VT input is used.
878 1Ph Reset V/Hz DDB_RESET_VPERHZ_2
This DDB (available in P642/3/5) when asserted resets Overflux element when two single phase VT input is used in P642 or a three phase VT
input is used in P643/5..
879 Trip Initial DDB_TRIP_INITIAL
This input DDB is equivalent to the output DDB Any trip.
for phase A
for phase B
882 VRO1 VCA<2Start DDB_VRO_1_V_2_PH_CA_START
for phase C
This DDB is asserted when the Measure voltage is less than (V<2) Voltage setting for second stage of Voltage Restrained Overcurrent start
signal for phase A
signal for phase B
885 VRO2 VCA<2 Start DDB_VRO_2_V_2_PH_CA_START
signal for phase C
887 Idiff Trip A DDB_IDIFF_TRIPA
B236 P64x-TM-EN-4.1

DESCRIPTION
This is the trip signal for the A-phase current differential element. This signal is the ORed function of biased differential trip and high set trips
(HS1 and HS2).
888 Idiff Trip B DDB_IDIFF_TRIPB
This is the trip signal for the B-phase current differential element. This signal is the ORed function of biased differential trip and high set trips
(HS1 and HS2).
889 Idiff Trip C DDB_IDIFF_TRIPC
This is the trip signal for the C-phase current differential element. This signal is the ORed function of biased differential trip and high set trips
(HS1 and HS2).
890 Idiff Trip DDB_IDIFF_TRIP
This is the trip signal for the first Any-phase current differential element. This signal is the ORed function of biased differential trip and high
set trips (HS1 and HS2).
891 Idiff HS1 Trip A DDB_IDIFF_HS1_TRIPA
This is the High Set 1 trip signal for the A-phase current differential element
892 Idiff HS1 Trip B DDB_IDIFF_HS1_TRIPB
This is the High Set 1 trip signal for the B-phase current differential element
893 Idiff HS1 Trip C DDB_IDIFF_HS1_TRIPC
This is the High Set 1 trip signal for the C-phase current differential element
894 Idiff HS2 Trip A DDB_IDIFF_HS2_TRIPA
This is the High Set 2 trip signal for the A-phase current differential element
895 Idiff HS2 Trip B DDB_IDIFF_HS2_TRIPB
This is the High Set 2 trip signal for the B-phase current differential element
896 Idiff HS2 Trip C DDB_IDIFF_HS2_TRIPC
This is the High Set 2 trip signal for the C-phase current differential element
897 Id Bias Trip A DDB_IDIFF_BIAS_TRIPA
This is the Bias trip signal for the A-phase current differential element
898 Id Bias Trip B DDB_IDIFF_BIAS_TRIPB
This is the Bias trip signal for the B-phase current differential element
899 Id Bias Trip C DDB_IDIFF_BIAS_TRIPC
This is the Bias trip signal for the C-phase current differential element
900 No Gap A DDB_NO_GAP_A
This signal indicates is asserted when there was no gap in the Gap detection algorithm during the last cycle of phase A
901 No Gap B DDB_NO_GAP_B
This signal indicates is asserted when there was no gap in the Gap detection algorithm during the last cycle of phase B
902 No Gap C DDB_NO_GAP_C
This signal indicates is asserted when there was no gap in the Gap detection algorithm during the last cycle of phase C
938 REF Trip HV DDB_REF_TRIP_HV
This DDB signal is the Restricted Earth Fault trip signal for the HV winding
939 REF Trip LV DDB_REF_TRIP_LV
This DDB signal is the Restricted Earth Fault trip signal for the LV winding
940 REF Trip TV DDB_REF_TRIP_TV
This DDB signal is the Restricted Earth Fault trip signal for the TV winding
941 REF Trip Auto DDB_REF_TRIP_AUTO
This DDB signal is the Restricted Earth Fault trip signal for autotransformer configuration
942 Hot Spot >1 Trip DDB_HOT_SPOT_1_TRIP
This DDB signal is the Hot Spot trip signal for the first thermal overload element
This DDB signal is the Hot Spot trip signal for the second thermal overload element
This DDB signal is the Hot Spot trip signal for the third thermal overload element
945 Top Oil >1 Trip DDB_TOP_OIL_1_TRIP
This DDB signal is the Oil overtemperature trip signal for the first thermal overload element
This DDB signal is the Oil overtemperature trip signal for the second thermal overload element
This DDB signal is the Oil overtemperature trip signal for the third thermal overload element
948 POC 1 I>1 Trip DDB_POC1_STAGE1_3PH_TRIP
This DDB signal is the first stage any-phase Phase Overcurrent trip signal for the first element
949 POC 1 I>1 Trip A DDB_POC1_STAGE1_PH_A_TRIP
P64x-TM-EN-4.1 B237

DESCRIPTION
This DDB signal is the first stage A-phase Phase Overcurrent trip signal for the first element
950 POC 1 I>1 Trip B DDB_POC1_STAGE1_PH_B_TRIP
This DDB signal is the first stage B-phase Phase Overcurrent trip signal for the first element
951 POC 1 I>1 Trip C DDB_POC1_STAGE1_PH_C_TRIP
This DDB signal is the first stage C-phase Phase Overcurrent trip signal for the first element
This DDB signal is the second stage any-phase Phase Overcurrent trip signal for the first element
This DDB signal is the second stage A-phase Phase Overcurrent trip signal for the first element
This DDB signal is the second stage B-phase Phase Overcurrent trip signal for the first element
This DDB signal is the second stage C-phase Phase Overcurrent trip signal for the first element
This DDB signal is the third stage any-phase Phase Overcurrent trip signal for the first element
This DDB signal is the third stage A-phase Phase Overcurrent trip signal for the first element
This DDB signal is the third stage B-phase Phase Overcurrent trip signal for the first element
This DDB signal is the third stage C-phase Phase Overcurrent trip signal for the first element
This DDB signal is the fourth stage any-phase Phase Overcurrent trip signal for the first element
This DDB signal is the fourth stage A-phase Phase Overcurrent trip signal for the first element
This DDB signal is the fourth stage B-phase Phase Overcurrent trip signal for the first element
This DDB signal is the fourth stage C-phase Phase Overcurrent trip signal for the first element
This DDB signal is the first stage any-phase Phase Overcurrent trip signal for the second element
This DDB signal is the first stage A-phase Phase Overcurrent trip signal for the second element
This DDB signal is the first stage B-phase Phase Overcurrent trip signal for the second element
This DDB signal is the first stage C-phase Phase Overcurrent trip signal for the second element
This DDB signal is the second stage any-phase Phase Overcurrent trip signal for the second element
This DDB signal is the second stage A-phase Phase Overcurrent trip signal for the second element
This DDB signal is the second stage B-phase Phase Overcurrent trip signal for the second element
This DDB signal is the second stage C-phase Phase Overcurrent trip signal for the second element
This DDB signal is the third stage any-phase Phase Overcurrent trip signal for the second element
This DDB signal is the third stage A-phase Phase Overcurrent trip signal for the second element
This DDB signal is the third stage B-phase Phase Overcurrent trip signal for the second element
This DDB signal is the third stage C-phase Phase Overcurrent trip signal for the second element
This DDB signal is the fourth stage any-phase Phase Overcurrent trip signal for the second element
This DDB signal is the fourth stage A-phase Phase Overcurrent trip signal for the second element
B238 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal is the fourth stage B-phase Phase Overcurrent trip signal for the second element
This DDB signal is the fourth stage C-phase Phase Overcurrent trip signal for the second element
This DDB signal is the first stage any-phase Phase Overcurrent trip signal for the third element
This DDB signal is the first stage A-phase Phase Overcurrent trip signal for the third element
This DDB signal is the first stage B-phase Phase Overcurrent trip signal for the third element
This DDB signal is the first stage C-phase Phase Overcurrent trip signal for the third element
This DDB signal is the second stage any-phase Phase Overcurrent trip signal for the third element
This DDB signal is the second stage A-phase Phase Overcurrent trip signal for the third element
This DDB signal is the second stage B-phase Phase Overcurrent trip signal for the third element
This DDB signal is the second stage C-phase Phase Overcurrent trip signal for the third element
This DDB signal is the third stage any-phase Phase Overcurrent trip signal for the third element
This DDB signal is the third stage A-phase Phase Overcurrent trip signal for the third element
This DDB signal is the third stage B-phase Phase Overcurrent trip signal for the third element
This DDB signal is the third stage C-phase Phase Overcurrent trip signal for the third element
This DDB signal is the fourth stage any-phase Phase Overcurrent trip signal for the third element
This DDB signal is the fourth stage A-phase Phase Overcurrent trip signal for the third element
This DDB signal is the fourth stage B-phase Phase Overcurrent trip signal for the third element
This DDB signal is the fourth stage C-phase Phase Overcurrent trip signal for the third element
996 VCO>1 Trip DDB_VCO_1_3PH_TRIP
This DDB signal is the first stage any-phase Phase VCO trip signal
997 VCO>1 Trip A DDB_VCO_1_PH_A_TRIP
This DDB signal is the first stage A-phase Phase VCO trip signal
998 VCO>1 Trip B DDB_VCO_1_PH_B_TRIP
This DDB signal is the first stage B-phase Phase VCO trip signal
999 VCO>1 Trip C DDB_VCO_1_PH_C_TRIP
This DDB signal is the first stage C-phase Phase VCO trip signal
1000 VCO>2 Trip DDB_VCO_2_3PH_TRIP
This DDB signal is the second stage any-phase Phase VCO trip signal
1001 VCO>2 Trip A DDB_VCO_2_PH_A_TRIP
This DDB signal is the second stage A-phase Phase VCO trip signal
1002 VCO>2 Trip B DDB_VCO_2_PH_B_TRIP
This DDB signal is the second stage B-phase Phase VCO trip signal
1003 VCO>2 Trip C DDB_VCO_2_PH_C_TRIP
This DDB signal is the second stage C-phase Phase VCO trip signal
1004 VRO>1 Trip DDB_VRO_1_3PH_TRIP
This DDB signal is the first stage any-phase Phase VRO trip signal
1005 VRO>1 Trip A DDB_VRO_1_PH_A_TRIP
This DDB signal is the first stage A-phase Phase VRO trip signal
1006 VRO>1 Trip B DDB_VRO_1_PH_B_TRIP
This DDB signal is the first stage B-phase Phase VRO trip signal
1007 VRO>1 Trip C DDB_VRO_1_PH_C_TRIP
P64x-TM-EN-4.1 B239

DESCRIPTION
This DDB signal is the first stage C-phase Phase VRO trip signal
1008 VRO>2 Trip DDB_VRO_2_3PH_TRIP
This DDB signal is the second stage any-phase Phase VRO trip signal
1009 VRO>2 Trip A DDB_VRO_2_PH_A_TRIP
This DDB signal is the second stage A-phase Phase VRO trip signal
1010 VRO>2 Trip B DDB_VRO_2_PH_B_TRIP
This DDB signal is the second stage B-phase Phase VRO trip signal
1011 VRO>2 Trip C DDB_VRO_2_PH_C_TRIP
This DDB signal is the second stage C-phase Phase VRO trip signal
1032 EF 1 IN>1 Trip DDB_EF1_STAGE1_TRIP
This DDB signal is the first stage Earth Fault trip signal for the first element
This DDB signal is the second stage measured Earth Fault trip signal for the first element
This DDB signal is the third stage measured Earth Fault trip signal for the first element
This DDB signal is the fourth stage measured Earth Fault trip signal for the first element
This DDB signal is the first stage Earth Fault trip signal for the second element
This DDB signal is the second stage measured Earth Fault trip signal for the second element
This DDB signal is the third stage measured Earth Fault trip signal for the second element
This DDB signal is the fourth stage measured Earth Fault trip signal for the second element
This DDB signal is the first stage Earth Fault trip signal for the third element
This DDB signal is the second stage measured Earth Fault trip signal for the third element
This DDB signal is the third stage measured Earth Fault trip signal for the third element
This DDB signal is the fourth stage measured Earth Fault trip signal for the third element
This DDB signal is the first stage Earth Fault trip signal for the third element
This DDB signal is the second stage measured Earth Fault trip signal for the third element
This DDB signal is the third stage measured Earth Fault trip signal for the third element
This DDB signal is the fourth stage measured Earth Fault trip signal for the third element
1048 Quality VIP 1 DDB_VIP_QUALITY_1
GOOSE Virtual input quality bit 1
B240 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B241

DESCRIPTION
1112 PubPres VIP 1 DDB_VIP_PUB_PRES_1
GOOSE Virtual input publisher bit 1
B242 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B243

DESCRIPTION
B244 P64x-TM-EN-4.1

DESCRIPTION
1176 Active Group 1 DDB_CS103_GROUP1_CHANGED
This DDB signal indicates that the setting group 1 has changed
1180 RTD 1 Trip DDB_RTD_1_TRIP
This is the RTD 1 trip signal
1190 Any RTD Trip DDB_ANY_RTD_TRIP
This is the Any RTD trip signal
1191 CLI1 Trip DDB_CL_INPUT_1_TRIP
This is the Current Loop Input 1 trip signal
This is the Current Loop Input41 trip signal
1195 V<1 Trip A/AB DDB_PUV_1_PH_A_TRIP
This DDB signal is the first stage A-phase Undervoltage trip signal
1196 V<1 Trip B/BC DDB_PUV_1_PH_B_TRIP
This DDB signal is the first stage B-phase Undervoltage trip signal
1197 V<1 Trip C/CA DDB_PUV_1_PH_C_TRIP
This DDB signal is the first stage C-phase Undervoltage trip signal
1198 V<2 Trip A/AB DDB_PUV_2_PH_A_TRIP
This DDB signal is the second stage A-phase Undervoltage trip signal
1199 V<2 Trip B/BC DDB_PUV_2_PH_B_TRIP
This DDB signal is the second stage B-phase Undervoltage trip signal
1200 V<2 Trip C/CA DDB_PUV_2_PH_C_TRIP
This DDB signal is the second stage C-phase Undervoltage trip signal
1201 V>1 Trip A/AB DDB_POV_1_PH_A_TRIP
P64x-TM-EN-4.1 B245

DESCRIPTION
This DDB signal is the first stage A-phase Overvoltage trip signal
1202 V>1 Trip B/BC DDB_POV_1_PH_B_TRIP
This DDB signal is the first stage B-phase Overvoltage trip signal
1203 V>1 Trip C/CA DDB_POV_1_PH_C_TRIP
This DDB signal is the first stage C-phase Overvoltage trip signal
1204 V>2 Trip A/AB DDB_POV_2_PH_A_TRIP
This DDB signal is the second stage A-phase Overvoltage trip signal
1205 V>2 Trip B/BC DDB_POV_2_PH_B_TRIP
This DDB signal is the second stage B-phase Overvoltage trip signal
1206 V>2 Trip C/CA DDB_POV_2_PH_C_TRIP
This DDB signal is the second stage C-phase Overvoltage trip signal
1207 V2> Trip DDB_NPSOV_1_TRIP
This DDB signal is the negative Sequence Overvoltage trip signal
1208 NPOC1 I2>1 Trip DDB_NPSOC1_STAGE1_TRIP
This DDB signal is the first stage NPSOC trip signal for the first element
This DDB signal is the second stage NPSOC trip signal for the first element
This DDB signal is the third stage NPSOC trip signal for the first element
This DDB signal is the fourth stage NPSOC trip signal for the first element
This DDB signal is the first stage NPSOC trip signal for the second element
This DDB signal is the second stage NPSOC trip signal for the second element
This DDB signal is the third stage NPSOC trip signal for the second element
This DDB signal is the fourth stage NPSOC trip signal for the second element
This DDB signal is the first stage NPSOC trip signal for the third element
This DDB signal is the second stage NPSOC trip signal for the third element
This DDB signal is the third stage NPSOC trip signal for the third element
This DDB signal is the fourth stage NPSOC trip signal for the third element
1220 F>1 Trip DDB_OFREQ_1_TRIP
This is the first stage Overfrequency trip signal
1221 F>2 Trip DDB_OFREQ_2_TRIP
This is the second stage Overfrequency trip signal
1222 F<1 Trip DDB_UFREQ_1_TRIP
This is the first stage Underfrequency trip signal
This is the second stage Underfrequency trip signal
This is the third stage Underfrequency trip signal
This is the fourth stage Underfrequency trip signal
1226 V<1 Trip DDB_PUV_1_3PH_TRIP
This is the first stage Phase Undervoltage 3-phase trip signal
1227 V<2 Trip DDB_PUV_2_3PH_TRIP
This is the second stage Phase Undervoltage 3-phase trip signal
1228 V>1 Trip DDB_POV_1_3PH_TRIP
This is the first stage Phase Overvoltage 3-phase trip signal
1229 V>2 Trip DDB_POV_2_3PH_TRIP
This is the second stage Phase Overvoltage 3-phase trip signal
1230 VN>1 Trip DDB_RESOV_1_TRIP
B246 P64x-TM-EN-4.1

DESCRIPTION
This is the first stage Residual Overvoltage trip signal
1231 VN>2 Trip DDB_RESOV_2_TRIP
This is the second stage Residual Overvoltage trip signal
1232 3Ph V/Hz>1 Trip DDB_VPERHZ_1_TRIP_1
This is the first stage overfluxing trip signal for the 3-phase VT
This is the second stage overfluxing trip signal for the 3-phase VT
This is the third stage overfluxing trip signal for the 3-phase VT
This is the fourth stage overfluxing trip signal for the 3-phase VT
This is the first stage overfluxing trip signal for the 1-phase VT
This is the second stage overfluxing trip signal for the 1-phase VT
This is the third stage overfluxing trip signal for the 1-phase VT
This is the fourth stage overfluxing trip signal for the 1-phase VT
1240 HMI Access Lvl 1 DDB_UIPASSWORD_ONE
bit 0 of the level access for HMI interface
1241 HMI Access Lvl 2 DDB_UIPASSWORD_TWO
bit 1 of the level access for HMI interface
1242 FPort AccessLvl1 DDB_FCURPASSWORD_ONE
bit 0 of the level access for the front port interface
1243 FPort AccessLvl2 DDB_FCURPASSWORD_TWO
bit 1 of the level access for the front port interface
1244 RPrt1 AccessLvl1 DDB_REMOTEPASSWORD_ONE
bit 0 of the level access for the rear port 1 interface
1245 RPrt1 AccessLvl2 DDB_REMOTEPASSWORD_TWO
1246 RPrt2 AccessLvl1 DDB_REMOTE2PASSWORD_ONE
1247 RPrt2 AccessLvl2 DDB_REMOTE2PASSWORD_TWO
1249 Extern CB1 Trip DDB_EXT_3PH_TRIP1
This DDB signal receives an external three-phase trip signal from T1
1274 Control TripCB1 DDB_CONTROL_TRIP_1
Control trip - operator trip instruction to circuit breaker 1, via menu, or SCADA. (Does not operate for protection element trips)
1279 Control CloseCB1 DDB_CONTROL_CLOSE_1
Control close command to circuit breaker 1. Operates for a manual close command (menu, SCADA), and additionally is driven by the auto-
reclose close command
P64x-TM-EN-4.1 B247

DESCRIPTION
1289 CB1 Healthy DDB_CB1_HEALTHY
Circuit breaker healthy (input to auto-recloser - that the CB1 has enough energy to allow re-closing)
1303 Any Start DDB_ANY_START
This DDB signal is the Any start signal originating from the fixed scheme logic
1304 Id Bias Start A DDB_IDIFF_BIAS_STARTA
This is the start signal for the A-phase current differential Bias element
1305 Id Bias Start B DDB_IDIFF_BIAS_STARTB
This is the start signal for the B-phase current differential Bias element
1306 Id Bias Start C DDB_IDIFF_BIAS_STARTC
This is the start signal for the C-phase current differential Bias element
1307 CB1 Close inProg DDB_CB1_CONTROL_CLOSE_IN_PROG
Control close in progress CB1 - the relay has been given an instruction to close the circuit breaker, but the manual close timer delay has not
yet finished timing out
1317 Rst CB1 CloseDly DDB_RESET_CB1_CLOSE_DELAY
DDB mapped in PSL. Reset Manual CB1 Close Timer Delay (stop & reset Manual Close Delay time for closing CB1).
1325 Hot Spot>1 Start DDB_HOT_SPOT_1_START
This DDB signal is the Hot Spot start signal for the first thermal overload element
B248 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal is the Hot Spot start signal for the second thermal overload element
This DDB signal is the Hot Spot start signal for the third thermal overload element
1328 Top Oil >1 start DDB_TOP_OIL_1_START
This DDB signal is the Oil overtemperature start signal for the first thermal overload element
This DDB signal is the Oil overtemperature start signal for the second thermal overload element
This DDB signal is the Oil overtemperature start signal for the third thermal overload element
1331 POC1 I>1 Start DDB_POC1_STAGE1_3PH_START
This DDB signal is the first stage any-phase Phase Overcurrent start signal for the first element
1332 POC1 I>1 Start A DDB_POC1_STAGE1_PH_A_START
This DDB signal is the first stage A-phase Phase Overcurrent start signal for the first element
1333 POC1 I>1 Start B DDB_POC1_STAGE1_PH_B_START
This DDB signal is the first stage B-phase Phase Overcurrent start signal for the first element
1334 POC1 I>1 Start C DDB_POC1_STAGE1_PH_C_START
This DDB signal is the first stage C-phase Phase Overcurrent start signal for the first element
This DDB signal is the second stage any-phase Phase Overcurrent start signal for the first element
This DDB signal is the second stage A-phase Phase Overcurrent start signal for the first element
This DDB signal is the second stage B-phase Phase Overcurrent start signal for the first element
This DDB signal is the second stage C-phase Phase Overcurrent start signal for the first element
This DDB signal is the third stage any-phase Phase Overcurrent start signal for the first element
This DDB signal is the third stage A-phase Phase Overcurrent start signal for the first element
This DDB signal is the third stage B-phase Phase Overcurrent start signal for the first element
This DDB signal is the third stage C-phase Phase Overcurrent start signal for the first element
This DDB signal is the fourth stage any-phase Phase Overcurrent start signal for the first element
This DDB signal is the fourth stage A-phase Phase Overcurrent start signal for the first element
This DDB signal is the fourth stage B-phase Phase Overcurrent start signal for the first element
This DDB signal is the fourth stage C-phase Phase Overcurrent start signal for the first element
This DDB signal is the first stage any-phase Phase Overcurrent start signal for the second element
This DDB signal is the first stage A-phase Phase Overcurrent start signal for the second element
This DDB signal is the first stage B-phase Phase Overcurrent start signal for the second element
This DDB signal is the first stage C-phase Phase Overcurrent start signal for the second element
This DDB signal is the second stage any-phase Phase Overcurrent start signal for the second element
This DDB signal is the second stage A-phase Phase Overcurrent start signal for the second element
This DDB signal is the second stage B-phase Phase Overcurrent start signal for the second element
This DDB signal is the second stage C-phase Phase Overcurrent start signal for the second element
P64x-TM-EN-4.1 B249

DESCRIPTION
This DDB signal is the third stage any-phase Phase Overcurrent start signal for the second element
This DDB signal is the third stage A-phase Phase Overcurrent start signal for the second element
This DDB signal is the third stage B-phase Phase Overcurrent start signal for the second element
This DDB signal is the third stage C-phase Phase Overcurrent start signal for the second element
This DDB signal is the fourth stage any-phase Phase Overcurrent start signal for the second element
This DDB signal is the fourth stage A-phase Phase Overcurrent start signal for the second element
This DDB signal is the fourth stage B-phase Phase Overcurrent start signal for the second element
This DDB signal is the fourth stage C-phase Phase Overcurrent start signal for the second element
This DDB signal is the first stage any-phase Phase Overcurrent start signal for the third element
This DDB signal is the first stage A-phase Phase Overcurrent start signal for the third element
This DDB signal is the first stage B-phase Phase Overcurrent start signal for the third element
This DDB signal is the first stage C-phase Phase Overcurrent start signal for the third element
This DDB signal is the second stage any-phase Phase Overcurrent start signal for the third element
This DDB signal is the second stage A-phase Phase Overcurrent start signal for the third element
This DDB signal is the second stage B-phase Phase Overcurrent start signal for the third element
This DDB signal is the second stage C-phase Phase Overcurrent start signal for the third element
This DDB signal is the third stage any-phase Phase Overcurrent start signal for the third element
This DDB signal is the third stage A-phase Phase Overcurrent start signal for the third element
This DDB signal is the third stage B-phase Phase Overcurrent start signal for the third element
This DDB signal is the third stage C-phase Phase Overcurrent start signal for the third element
This DDB signal is the fourth stage any-phase Phase Overcurrent start signal for the third element
This DDB signal is the fourth stage A-phase Phase Overcurrent start signal for the third element
This DDB signal is the fourth stage B-phase Phase Overcurrent start signal for the third element
This DDB signal is the fourth stage C-phase Phase Overcurrent start signal for the third element
1379 VCO>1 Start DDB_VCO_1_3PH_START
This DDB signal is the first stage any-phase Phase VCO start signal
1380 VCO>1 Start A DDB_VCO_1_PH_A_START
This DDB signal is the first stage A-phase Phase VCO start signal
1381 VCO>1 Start B DDB_VCO_1_PH_B_START
This DDB signal is the first stage B-phase Phase VCO start signal
1382 VCO>1 Start C DDB_VCO_1_PH_C_START
This DDB signal is the first stage C-phase Phase VCO start signal
1383 VCO>2 Start DDB_VCO_2_3PH_START
This DDB signal is the second stage any-phase Phase VCO start signal
1384 VCO>2 Start A DDB_VCO_2_PH_A_START
B250 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal is the second stage A-phase Phase VCO start signal
1385 VCO>2 Start B DDB_VCO_2_PH_B_START
This DDB signal is the second stage B-phase Phase VCO start signal
1386 VCO>2 Start C DDB_VCO_2_PH_C_START
This DDB signal is the second stage C-phase Phase VCO start signal
1387 POC1 IA2H Start DDB_POC1_2ND_HAR_BLKA
This is the phase-A 2nd harmonic blocking start signal for the first phase overcurrent element
1388 POC1 IB2H Start DDB_POC1_2ND_HAR_BLKB
This is the phase-B 2nd harmonic blocking start signal for the first phase overcurrent element
1389 POC1 IC2H Start DDB_POC1_2ND_HAR_BLKC
This is the phase-C 2nd harmonic blocking start signal for the first phase overcurrent element
This is the phase-A 2nd harmonic blocking start signal for the second phase overcurrent element
This is the phase-B 2nd harmonic blocking start signal for the second phase overcurrent element
This is the phase-C 2nd harmonic blocking start signal for the second phase overcurrent element
This is the phase-A 2nd harmonic blocking start signal for the third phase overcurrent element
This is the phase-B 2nd harmonic blocking start signal for the third phase overcurrent element
This is the phase-C 2nd harmonic blocking start signal for the third phase overcurrent element
1396 EF1 IH2 Start DDB_EF1_2ND_HAR_BLK
This is the 2nd harmonic blocking start signal for the first earth fault element
This is the 2nd harmonic blocking start signal for the second earth fault element
This is the 2nd harmonic blocking start signal for the third earth fault element
This is the 2nd harmonic blocking start signal for the third earth fault element
1400 REF IH2 Start HV DDB_HV_REF_2ND_HAR_BLK
This is the 2nd harmonic blocking start signal for REF protection for the HV winding
1401 REF IH2 Start LV DDB_LV_REF_2ND_HAR_BLK
This is the 2nd harmonic blocking start signal for REF protection for the LV winding
1402 REF IH2 Start TV DDB_TV_REF_2ND_HAR_BLK
This is the 2nd harmonic blocking start signal for REF protection for the TV winding
1403 REF IH2 Start AT DDB_AUTO_REF_2ND_HAR_BLK
This is the 2nd harmonic blocking start signal for REF protection for Autotransformer configuration
1404 POC1 IH2 Any St DDB_POC1_2ND_HAR_BLKANY
This is the Any Start (phase A OR phase B OR phase C) 2nd harmonic blocking signal for the first phase overcurrent element
This is the Any Start (phase A OR phase B OR phase C) 2nd harmonic blocking signal for the second phase overcurrent element
This is the Any Start (phase A OR phase B OR phase C) 2nd harmonic blocking signal for the third phase overcurrent element
1407 VRO>1 Start DDB_VRO_1_3PH_START
This DDB signal is the first stage any-phase Phase VRO start signal
1408 VRO>1 Start A DDB_VRO_1_PH_A_START
This DDB signal is the first stage A-phase Phase VRO start signal
1409 VRO>1 Start B DDB_VRO_1_PH_B_START
This DDB signal is the first stage B-phase Phase VRO start signal
1410 VRO>1 Start C DDB_VRO_1_PH_C_START
This DDB signal is the first stage C-phase Phase VRO start signal
1411 VRO>2 Start DDB_VRO_2_3PH_START
This DDB signal is the second stage any-phase Phase VRO start signal
1412 VRO>2 Start A DDB_VRO_2_PH_A_START
This DDB signal is the second stage A-phase Phase VRO start signal
1413 VRO>2 Start B DDB_VRO_2_PH_B_START
P64x-TM-EN-4.1 B251

DESCRIPTION
This DDB signal is the second stage B-phase Phase VRO start signal
1414 VRO>2 Start C DDB_VRO_2_PH_C_START
This DDB signal is the second stage C-phase Phase VRO start signal
1420 Intlock CB1 OPN DDB_INTERLOCK_CB1_OPN_ENABLED
CB1 open enabled (interlock)
1421 Intlock CB1 CLS DDB_INTERLOCK_CB1_CLS_ENABLED
CB1 close enabled (interlock)
1476 EF 1 IN>1 Start DDB_EF1_STAGE1_START
This DDB signal is the first stage Earth Fault start signal for the first element
This DDB signal is the second stage measured Earth Fault start signal for the first element
This DDB signal is the third stage measured Earth Fault start signal for the first element
This DDB signal is the fourth stage measured Earth Fault start signal for the first element
This DDB signal is the first stage Earth Fault start signal for the second element
This DDB signal is the second stage measured Earth Fault start signal for the second element
This DDB signal is the third stage measured Earth Fault start signal for the second element
This DDB signal is the fourth stage measured Earth Fault start signal for the second element
This DDB signal is the first stage Earth Fault start signal for the third element
This DDB signal is the second stage measured Earth Fault start signal for the third element
This DDB signal is the third stage measured Earth Fault start signal for the third element
This DDB signal is the fourth stage measured Earth Fault start signal for the third element
This DDB signal is the first stage Earth Fault start signal for the third element
This DDB signal is the second stage measured Earth Fault start signal for the third element
This DDB signal is the third stage measured Earth Fault start signal for the third element
This DDB signal is the fourth stage measured Earth Fault start signal for the third element
1504 Any Diff Start DDB_ANY_DIFF_START
This is the Any-phase start signal for the differential current protection
1507 REF HV Start DDB_REF_START_HV
B252 P64x-TM-EN-4.1

DESCRIPTION
This is the REF protection start signal for the HV winding
1508 REF LV Start DDB_REF_START_LV
This is the REF protection start signal for the LV winding
1509 REF TV Start DDB_REF_START_TV
This is the REF protection start signal for the TV winding
1510 REF Auto Start DDB_REF_START_AUTO
This is the REF protection start signal for autotransformer configuration
1524 CB1 ReTrip 3ph DDB_CB1_3PH_RETRIP
This is the 3-phase re-trip signal for CB1.
1525 CB1 BkTrip 3ph DDB_CB1_3PH_BKTRIP
This is the 3-phase back-trip signal for CB1.
This is the 3-phase re-trip signal for CB2
This is the 3-phase back-trip signal for CB2
1564 NPOC1 I2>1 Start DDB_NPSOC1_STAGE1_START
This DDB signal is the first stage NPSOC start signal for the first element
This DDB signal is the second stage NPSOC start signal for the first element
This DDB signal is the third stage NPSOC start signal for the first element
This DDB signal is the fourth stage NPSOC start signal for the first element
This DDB signal is the first stage NPSOC start signal for the second element
This DDB signal is the second stage NPSOC start signal for the second element
This DDB signal is the third stage NPSOC start signal for the second element
This DDB signal is the fourth stage NPSOC start signal for the second element
This DDB signal is the first stage NPSOC start signal for the third element
This DDB signal is the second stage NPSOC start signal for the third element
This DDB signal is the third stage NPSOC start signal for the third element
This DDB signal is the fourth stage NPSOC start signal for the third element
1576 V<1 Start DDB_PUV_1_3PH_START
This is the first stage Phase Undervoltage 3-phase start signal
1577 V<1 Start A/AB DDB_PUV_1_PH_A_START
This is the first stage Phase Undervoltage A-phase start signal
1578 V<1 Start B/BC DDB_PUV_1_PH_B_START
This is the first stage Phase Undervoltage B-phase start signal
1579 V<1 Start C/CA DDB_PUV_1_PH_C_START
P64x-TM-EN-4.1 B253

DESCRIPTION
This is the first stage Phase Undervoltage C-phase start signal
1580 V<2 Start DDB_PUV_2_3PH_START
This is the second stage Phase Undervoltage 3-phase start signal
1581 V<2 Start A/AB DDB_PUV_2_PH_A_START
This is the second stage Phase Undervoltage A-phase start signal
1582 V<2 Start B/BC DDB_PUV_2_PH_B_START
This is the second stage Phase Undervoltage B-phase start signal
1583 V<2 Start C/CA DDB_PUV_2_PH_C_START
This is the second stage Phase Undervoltage C-phase start signal
1584 V>1 Start DDB_POV_1_3PH_START
This is the first stage Phase Overvoltage 3-phase start signal
1585 V>1 Start A/AB DDB_POV_1_PH_A_START
This is the first stage Phase Overvoltage A-phase start signal
1586 V>1 Start B/BC DDB_POV_1_PH_B_START
This is the first stage Phase Overvoltage B-phase start signal
1587 V>1 Start C/CA DDB_POV_1_PH_C_START
This is the first stage Phase Overvoltage C-phase start signal
1588 V>2 Start DDB_POV_2_3PH_START
This is the second stage Phase Overvoltage 3-phase start signal
1589 V>2 Start A/AB DDB_POV_2_PH_A_START
This is the second stage Phase Overvoltage A-phase start signal
1590 V>2 Start B/BC DDB_POV_2_PH_B_START
This is the second stage Phase Overvoltage B-phase start signal
1591 V>2 Start C/CA DDB_POV_2_PH_C_START
This is the second stage Phase Overvoltage C-phase start signal
1592 VN>1 Start DDB_RESOV_1_START
This is the first stage Residual Overvoltage start signal
1593 VN>2 Start DDB_RESOV_2_START
This is the second stage Residual Overvoltage start signal
1594 3Ph V/Hz> AlmSt DDB_VPERHZ_ALARM_START_1
This is the overfluxing alarm start signal for the 3-phase VT
1595 3Ph V/Hz>1 Start DDB_VPERHZ_1_START_1
This is the first stage overfluxing start signal for the 3-phase VT
This is the second stage overfluxing start signal for the 3-phase VT
This is the third stage overfluxing start signal for the 3-phase VT
This is the fourth stage overfluxing start signal for the 3-phase VT
1599 1Ph V/Hz> AlmSt DDB_VPERHZ_ALARM_START_2
This is the overfluxing alarm start signal for the 1-phase VT
This is the first stage overfluxing start signal for the 1-phase VT
This is the second stage overfluxing start signal for the 1-phase VT
This is the third stage overfluxing start signal for the 1-phase VT
This is the fourth stage overfluxing start signal for the 1-phase VT
1604 F<1 Start DDB_UFREQ_1_START
This is the first stage Underfrequency start signal
This is the second stage Underfrequency start signal
This is the third stage Underfrequency start signal
This is the fourth stage Underfrequency start signal
1608 F>1 Start DDB_OFREQ_1_START
B254 P64x-TM-EN-4.1

DESCRIPTION
This is the first stage Overfrequency start signal
1609 F>2 Start DDB_OFREQ_2_START
This is the second stage Overfrequency start signal
1610 CLI1 Alarm Start DDB_CL_INPUT_1_ALARM_START
This is the Current Loop Input 1 Alarm start signal
1614 CLI1 Start DDB_CL_INPUT_1_TRIP_START
This is the Current Loop Input 1 trip start signal
1618 V2> Start DDB_NPSOV_1_START
This is the Negative Sequence Over Voltage start signal
1654 CT1A ZCD DDB_CT1_PHASE_A_ZCD
This is the A-phase Zero Cross Detector signal for T1
1655 CT1B ZCD DDB_CT1_PHASE_B_ZCD
This is the B-phase Zero Cross Detector signal for T1
1656 CT1C ZCD DDB_CT1_PHASE_C_ZCD
This is the C-phase Zero Cross Detector signal for T1
1669 CT1 In ZCD DDB_CT1_IN_ZCD
This is the Neutral current Zero Cross Detector signal for T1
P64x-TM-EN-4.1 B255

DESCRIPTION
1674 T1 IA< Start DDB_CT1_PHASE_A_UNDERCURRENT
This is the A-phase Undercurrent signal for T1
1675 T1 IB< Start DDB_CT1_PHASE_B_UNDERCURRENT
This is the B-phase Undercurrent signal for T1
1676 T1 IC< Start DDB_CT1_PHASE_C_UNDERCURRENT
This is the C-phase Undercurrent signal for T1
1689 HV UndCurrent DDB_HV_UNDERCURRENT
This is the Fast Undercurrent signal for the HV winding
1690 LV UndCurrent DDB_LV_UNDERCURRENT
This is the Fast Undercurrent signal for the LV winding
1691 TV UndCurrent DDB_TV_UNDERCURRENT
This is the Fast Undercurrent signal for the TV winding
1692 CT1 PhA UnderCur DDB_CT1_PHS_A_UC_CT_EXCLUSION
CT1 Phase A Undercurrent
1693 CT1 PhB UnderCur DDB_CT1_PHS_B_UC_CT_EXCLUSION
CT1 Phase B Undercurrent
1694 CT1 PhC UnderCur DDB_CT1_PHS_C_UC_CT_EXCLUSION
CT1 Phase C Undercurrent
B256 P64x-TM-EN-4.1

DESCRIPTION
1707 T1 IN< Start DDB_CT1_IN_UNDERCURRENT
This is the neutral Undercurrent signal for T1
1719 CTexcl disa prot DDB_CT_EXCLU_DISABLE_PROT
When this DDB is asserted, all the current protection functions are disabled
1721 VTS VAB> DDB_VTS_VAB_OPERATED
This DDB signal indicates that the VAB VTS has operated
1722 VTS VBC> DDB_VTS_VBC_OPERATED
This DDB signal indicates that the VAB VTS has operated
1723 VTS VCA> DDB_VTS_VCA_OPERATED
This DDB signal indicates that the VCA VTS has operated
1724 RTD 1 Alarm DDB_RTD_1_ALARM
This is the alarm signal for RTD1
1734 VTS Acc Ind DDB_VTS_ACCELERATE_INPUT
This DDB signal indicates that the VTS accelarate function is active
1735 VTS Volt Dep DDB_VTS_ANY_VOLTAGE_DEP_FN
This DDB signal indicates that the Voltage Dependent Overcurrent Protection has started
1736 VTS IA> DDB_VTS_IA_OPERATED
This DDB signal indicates that phase A current is over threhold (VTS I>Inhibit)
1737 VTS IB> DDB_VTS_IB_OPERATED
This DDB signal indicates that phase B current is over threhold (VTS I>Inhibit)
1738 VTS IC> DDB_VTS_IC_OPERATED
P64x-TM-EN-4.1 B257

DESCRIPTION
This DDB signal indicates that phase C current is over threhold (VTS I>Inhibit)
1739 VTS VA> DDB_VTS_VA_OPERATED
This DDB signal indicates that phase A voltage is over threhold (VTS Pickup Thresh)
1740 VTS VB> DDB_VTS_VB_OPERATED
This DDB signal indicates that phase B voltage is over threhold (VTS Pickup Thresh)
1741 VTS VC> DDB_VTS_VC_OPERATED
This DDB signal indicates that phase C voltage is over threhold (VTS Pickup Thresh)
1742 VTS I2> DDB_VTS_I2_OPERATED
This DDB signal indicates that negative sequence current is over threhold (VTS I2>Inhibit)
1743 VTS V2> DDB_VTS_V2_OPERATED
This DDB signal indicates that negative sequence current is over threshold
1744 VTS IA delta> DDB_VTS_DELTA_IA_OPERATED
This DDB signal indicates that phase A superimposed current is overthreshold (0.1In)
1745 VTS IB delta> DDB_VTS_DELTA_IB_OPERATED
This DDB signal indicates that phase B superimposed current is overthreshold (0.1In)
1746 VTS IC delta> DDB_VTS_DELTA_IC_OPERATED
This DDB signal indicates that phase C superimposed current is overthreshold (0.1In)
1747 Freq High DDB_FREQ_ABOVE_RANGE_LIMIT
This DDB signal indicates that the frequency is above 70Hz
1748 Freq Low DDB_FREQ_BELOW_RANGE_LIMIT
This DDB signal indicates that the frequency is below 40Hz
1749 Freq Not found DDB_FREQ_NOT_FOUND
This DDB signal indicates that no frequency has been found
1768 All Poles Dead DDB_ALL_POLEDEAD
This DDB signal indicates that all poles are dead
1769 Any Pole Dead DDB_ANY_POLEDEAD
This DDB signal indicates that one or more of the poles is dead.
1770 Pole Dead A DDB_PHASE_A_POLEDEAD
This DDB signal indicates that the A-phase pole is dead.
1771 Pole Dead B DDB_PHASE_B_POLEDEAD
This DDB signal indicates that the B-phase pole is dead.
1772 Pole Dead C DDB_PHASE_C_POLEDEAD
This DDB signal indicates that the C-phase pole is dead.
1773 TF OC Start DDB_THROUGH_FAULT_OC_START
This is the Through fault protection start signal
1774 TF OC End DDB_THROUGH_FAULT_OC_RESET
This DDB signal resets the Through fault protection
1775 TF Recorder trig DDB_THROUGH_FAULT_RECORDER
This is the Through fault protection trigger signal
1786 BFail Non I Tr-1 DDB_CBF_NON_CURRENT_STAGE_TRIP
This DDB signal is the Fixed Scheme Logic CBF Non Current Protection Stage Trip
1787 BFail Non I Trip DDB_CBF_NON_CURRENT_PROT_TRIP
This DDB signal is the non-current CBF Protection Trip
1796 VTS Fast Block DDB_VTS_FAST_BLOCK
This DDB signal is an instantaneously blocking output from the VTS which can block other functions
1797 VTS Slow Block DDB_VTS_SLOW_BLOCK
This DDB signal is a purposely delayed output from the VTS which can block other functions
1802 P/Word Block UI DDB_PASSWORD_BLK_UI
This DDB indicates the Pass Word is blocked on the UI
1803 P/Word Block FP DDB_PASSWORD_BLK_FP
This DDB indicates the Pass Word is blocked on the Front Port
1804 P/Word Block RP1 DDB_PASSWORD_BLK_RP1
This DDB indicates the Pass Word is blocked on the first rear port
1805 P/Word Block RP2 DDB_PASSWORD_BLK_RP2
This DDB indicates the Pass Word is blocked on the second rear port
1808 Security Bypass DDB_PASSWORD_BYPASS
Cyber Security Bypass is Enabled
1824 Control Input 1 DDB_CONTROL_1
B258 P64x-TM-EN-4.1

DESCRIPTION
This DDB signal is a control input signal
P64x-TM-EN-4.1 B259

DESCRIPTION
1856 Virtual Input 01 DDB_GOOSEIN_1
This DDB signal is a GOOSE virtual input
B260 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B261

DESCRIPTION
1920 PSL Int. 1 DDB_PSLINT_1
This DDB signal is assigned to a PSL node used internally, and is defined by the Programmable Scheme Logic
B262 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B263

DESCRIPTION
B264 P64x-TM-EN-4.1

DESCRIPTION
P64x-TM-EN-4.1 B265

DESCRIPTION
B266 P64x-TM-EN-4.1
APPENDIX C
WIRING DIAGRAMS
Appendix C - Wiring Diagrams P64x
528 P64x-TM-EN-4.1
P64x Appendix C – Wiring Diagrams
Model Cortec Option* External Connection Diagram Title Drawing-Sheet Issue

All - COMMS OPTIONS MICOM Px40 PLATFORM 10Px4001-1 J
IO Option A 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P) WITH 1 POLE VT INPUT (40TE) 10P64201-1 K
IO Option A HIGH Z REF FOR 2 BIAS I/P TRANSFORMER DIFF SAME APPLIES TO WIRE HIGH Z REF FOR T2 10P64201-2 G
IO Option A 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P) WITH 2 POLE VT INPUT (40TE) 10P64206-1 G
IO Option B 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P + RTD) WITH 1 POLE VT INPUT (40TE) 10P64202-1 J
IO Option B 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P + RTD) WITH 2 POLE VT INPUT (40TE) 10P64207-1 G
P642 IO Option C 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P + CLIO) WITH 1 POLE VT INPUT (40TE) 10P64203-1 J
IO Option C 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P & 8 O/P + CLIO) WITH 2 POLE VT INPUT (40TE) 10P64208-1 G
IO Option D 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (12 I/P & 12 O/P) WITH 1 POLE VT INPUT (40TE) 10P64204-1 J
IO Option D 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (12 I/P & 12 O/P) WITH 2 POLE VT INPUT (40TE) 10P64209-1 G
IO Option E 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P 12 O/P) WITH 1 POLE INPUT (40TE) 10P64205-1 J
IO Option E 2 BIAS INPUT TRANSFORMER DIFFERENTIAL (8 I/P 12 O/P) WITH 2 POLE INPUT (40TE) 10P64210-1 G
IO Option A 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/O & 16 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64301-1, 10P64301-2 F, I
IO Option A HIGH Z REF FOR 3 BIAS I/P TRANSFORMER DIFF SAME APPLIES TO WIRE HIGH Z REF FOR T2 &T3 10P64301-3 D
IO Option B 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/O & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE) 10P64302-1, 10P64302-2 F, I
IO Option C 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/O & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE) 10P64303-1, 10P64303-2 G, I
IO Option D 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (24 I/O & 16 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64304-1, 10P64304-2 G, I
IO Option E 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/O & 24 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64305-1, 10P64305-2 F, I
IO Option F 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/P 20 O/P) WITH 4 POLE VT INPUT (60TE) 10P64306-1, 10P64306-2 F, I
P643
IO Option G 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 24 O/P) WITH 4 POLE VT INPUTS (80TE) 10P64307-1, 10P64307-2 C, D
IO Option H 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE) 10P64308-1, 10P64308-2 D, D
IO Option J 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE) 10P64309-1, 10P64309-2 C, D
IO Option K 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 8 O/P+RTD+CLIO) WITH 4 POLE VT I/P (80TE) 10P64310-1, 10P64310-2 C, D
IO Option L 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 20 O/P) WITH 4 POLE VT INPUTS (80TE) 10P64311-1, 10P64311-2 C, D
IO Option M 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 12 O/P+RTD) WITH 4 POLE VT INPUTS (80TE) 10P64312-1, 10P64312-2 C, D
IO Option N 3 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/O & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE) 10P64313-1, 10P64313-2 C, D
IO Option A 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/P & 16 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64501-1, 10P64501-2 E, J
IO Option A HIGH Z REF FOR 5 BIAS I/P TRANSFORMER DIFF. SAME APPLIES TO WIRE HIGH Z REF FOR T2,T3,T4,T5 10P64501-3 G
IO Option B 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/P & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE) 10P64502-1, 10P64502-2 E, I
IO Option C 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/P & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE) 10P64503-1, 10P64503-2 E, I
IO Option D 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (24 I/P & 16 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64504-1, 10P64504-2 E, I
IO Option E 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (16 I/P & 24 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64505-1, 10P64505-2 E, I
IO Option J 5 BIAS INPUT TRANSFORMER DIFF. (24 I/P & 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE) 10P64506-1, 10P64506-2 F, I
IO Option K 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (24 I/P 20 O/P) WITH 4 POLE VT INPUTS (60TE) 10P64507-1, 10P64507-2 E, H
P645 IO Option P 5 BIAS INPUT TRANSFORMER DIFF. (24 I/P 20 O/P + CLIO & RTD)) WITH 4 POLE VT INPUTS (80TE) 10P64508-1, 10P64508-2 E, H
IO Option T 5 BIAS INPUT TRANSFORMER DIFF. (16 I/P 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE) 10P64509-1, 10P64509-2 E, H
IO Option U 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 24 O/P) WITH 4 POLE VT INPUTS (80TE) 10P64514-1, 10P64514-2 C, D
IO Option V 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE) 10P64515-1, 10P64515-2 C, D
IO Option W 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE) 10P64516-1, 10P64516-2 D, D
IO Option X 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 8 O/P+CLIO+RTD) WITH 4 POLE VT INPUTS (80TE) 10P64517-1, 10P64517-2 C, D
IO Option Y 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 20 O/P) WITH 4 POLE VT INPUTS (80TE) 10P64518-1, 10P64518-2 C, D
IO Option Z 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 12 O/P+RTD) WITH 4 POLE VT INPUTS (80TE) 10P64519-1, 10P64519-2 C, C
IO Option 1 5 BIAS INPUT TRANSFORMER DIFFERENTIAL (40 I/P & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE) 10P64520-1, 10P64520-2 C, D
* When selecting the applicable wiring diagram(s), refer to appropriate model’s Cortec.
P64x-TM-EN-4.1 C1
GE PROPRIETARY AND CONFIDENTIAL INFORMATION PART DESCRIPTION MATERIAL
This document is the property of General Electric Company ("GE") and contains proprietary information of GE. This document is loaned on the express condition that neither it nor the information contained therein shall be disclosed to others
without the express written consent of GE, and that the information shall be used by the recipient only as approved expressly by GE. This document shall be returned to GE upon its request. This document may be subject to certain restrictions
Date: Name: Drg Next Stage: Drg ECN No: Revision: Iteration:
Title: No:
Date: Chkd: 10PX4001 K 3
Sub-contractor reference: Linear Tol PLM Sht: Status:
CAD DATA 1:1 DIMENSIONS: mm mm: No:
Finish: Angular Tol
Grid Solutions A20022917 Next IN WORK
DO NOT SCALE
deg: Sht:
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED
TRANSFORMER MiCOM P642 (PART) N
T1 C24 NOTE 3
A (1) n
C23
a
MiCOM P642 (PART)
b c
C26
C3
B (1) F11
WATCHDOG
C25 VFLUX CONTACT F12
C4 F13
C28 WATCHDOG
CONTACT F14
C (1) E1
D1
C27 RELAY 1 E2
D2 OPTO 1
E3
T2 C18
D3 RELAY 2 E4
A (2) OPTO 2 E5
D4
C17 RELAY 3 E6
D5
E7
C20 D6 OPTO 3
RELAY 4 E8
B (2) D7 E9
C19 D8 OPTO 4 RELAY 5 E10
D9 E11
C22
OPTO 5 RELAY 6 E12
C (2)
D10
E13
D11
C21 E14
OPTO 6 RELAY 7
D12 E15
GROUNDED WYE D13 E16
NEUTRAL TAILS D14 OPTO 7 E17
RELAY 8
E18
HV LV D15
NOTE 4 D16 OPTO 8
NOTE 2
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17
TN2 C14 SEE DRAWING EIA485/

P1 S1
10Px4001 KBUS NOTES:
P2 S2 Y (LV) F18
PORT
C13 F16 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
SCN
P1 S1 TN1 C16
F1 (b) TERMINAL.
Y (HV) AC OR DC
C15 F2 x AUX SUPPLY (c) PIN TERMINAL (P.C.B. TYPE)
2. WYE GROUND INPUTS APPLICABLE FOR GROUNDED (EARTHED) WINDINGS.

3. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.
(USED BY V/Hz W2 PROTECTION ONLY).
CASE 4. FOR COMMS OPTIONS SEE DRAWING 10Px4001.

EARTH
* POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY
Issue: Revision: Title:

CID SWOO-AA2EBH. VT CONNECTIONS WERE C1, C2 EXTERNAL CONNECTION DIAGRAM: 2 BIAS INPUT TRANSFORMER
K DIFFERENTIAL (8 I/P & 8 O/P) WITH 1 POLE VT INPUT (40TE)
Drg
Date: 26/05/2016 Name: S.WOOTTON Sht: 1
CAD DATA 1:1 DIMENSIONS: mm No:
DO NOT SCALE Next
Date: Chkd: 10P64201 2
Sht:
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED
TRANSFORMER N
T1 C24 NOTE 3
A (1) n
C23
a
MiCOM P642 (PART)
b c
C26
C3
B (1) F11
WATCHDOG
C4 F13
C28 WATCHDOG
CONTACT F14
C (1) E1
D1
C27 RELAY 1 E2
D2 OPTO 1
E3
T2 C18
D3 RELAY 2 E4
A (2) OPTO 2 E5
D4
C17 RELAY 3 E6
D5
E7
C20 D6 OPTO 3
RELAY 4 E8
B (2) D7 E9
D9 E11
C22
OPTO 5 RELAY 6 E12
C (2) D10
E13
D11
C21 E14
OPTO 6 RELAY 7
D12 E15
RELAY 8
E18
HV LV D15
NOTE 4 D16 OPTO 8
NOTE 2
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17
NOTES:
P1 S1
10Px4001 KBUS
P2 S2 Y (LV) F18 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
PORT
C13 F16
R ST SCN (b) TERMINAL.
P1 S1 TN1 C16
F1 (c) PIN TERMINAL (P.C.B. TYPE)
Y (HV)
AC OR DC
C15 F2 x AUX SUPPLY
METROSIL (USED BY V/Hz W2 PROTECTION ONLY).
4. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
CASE
EARTH

CID SWOO-AA2EBH. VT CONNECTIONS WERE C1, C2 EXT CONN DIAG:HIGH Z REF FOR 2 BIAS I/P TRANSFORMER DIFF
G SAME PRINCIPAL APPLIES TO WIRE HIGH Z REF FOR T2
Drg
DO NOT SCALE Next -
Date: Chkd: 10P64201 Sht:
A
B
A
P1 P2 P2 P1 C
A A A A A B C
S1 S2 S2 S1
T2 B B B B T1
C C C C C B N
PHASE ROTATION NOTE 3
PROTECTED n
TRANSFORMER MiCOM P642 (PART)
T1 C24
a b c
A (1)
C1
C23
MiCOM P642 (PART)
C26 Vab OPTIONAL
C2
B (1) F11
C4 WATCHDOG
C25 CONTACT F12
Vflux F13
C28 WATCHDOG
C3 F14
CONTACT
C (1) E1
D1
C27 RELAY 1 E2
D2 OPTO 1
E3
T2 C18
D3 RELAY 2 E4
A (2) OPTO 2 E5
D4
C17 RELAY 3 E6
D5
E7
C20 D6 OPTO 3
RELAY 4 E8
B (2) D7 E9
D9 E11
C22
OPTO 5 RELAY 6 E12
C (2) D10
E13
D11
C21 E14
OPTO 6 RELAY 7
D12 E15
RELAY 8
E18
HV LV D15
NOTE 4 D16 OPTO 8
NOTE 2
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17

P1 S1 NOTES:
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
SCN
P1 S1 TN1 C16
(b) TERMINAL.
F1
Y (HV)
AC OR DC
F2 x AUX SUPPLY (c) PIN TERMINAL (P.C.B. TYPE)
C15
3. C3-C4 ARE USED BY V/Hz W2 PROTECTION. C1-C2 IS OPTIONAL.

C3-C4 AND C1-C2 ARE USED BY THE NPS OVERVOLTAGE AND VCO PROTECTIONS.
THEY ALSO MAY DIRECTIONALIZE THE OVERCURRENT, EARTH FAULT AND
CASE NPS OVERCURRENT ELEMENTS.
EARTH

CID SWOO-ACUGQ4. C1, C2 'VFLUX' is to be 'Vab OPTIONAL'. C4, C3 'Vbc OPTIONAL' to be Vflux'
G DIFFERENTIAL (8 I/P & 8 O/P) WITH 2 POLE VT INPUT (40TE)
Drg
DO NOT SCALE Next -
Date: Chkd: G.KAPOOR 10P64206 Sht:
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED
T1 C24 NOTE 3
A (1) n
C23 MiCOM P642 (PART)
a b c
C26
C3
B (1) F11
WATCHDOG
B1
C4 F13
C28 WATCHDOG B2 RTD 1
CONTACT F14
C (1) B3
E1
D1 B4
C27 RELAY 1 E2
D2 OPTO 1 B5 RTD 2
E3
T2 C18 B6
D3 RELAY 2 E4
A (2) B7
D4 OPTO 2 E5
RELAY 3 B8 RTD 3
C17 E6
D5 B9
E7
C20 D6 OPTO 3
RELAY 4 E8
B (2) D7 E9
C19 D8 OPTO 4 RELAY 5 E10 B28
B29 RTD 10
D9 E11
C22 B30
OPTO 5 RELAY 6 E12
C (2) D10
E13
D11
C21 E14
OPTO 6 RELAY 7
D12 E15
RELAY 8
E18
HV LV D15
NOTE 4 D16 OPTO 8
NOTE 2
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17
NOTES:
P1 S1
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
C13 F16
SCN (b) TERMINAL.
P1 S1 TN1 C16
F1 (c) PIN TERMINAL (P.C.B. TYPE)
Y (HV) AC OR DC
C15 F2 x AUX SUPPLY
CASE
EARTH

J DIFFERENTIAL (8 I/P & 8 O/P + RTD) WITH 1 POLE VT INPUT (40TE)
Drg
DO NOT SCALE Next -
A
B
A
P1 P2 P2 P1 C
A A A A A B C
T2 S1 S2 S2 S1
B B B B T1
C C C C C B N
PROTECTED n MiCOM P642 (PART)
T1 C24
a b c
A (1)
C1 B1
C23
B2 RTD 1
C26 Vab OPTIONAL B3
C2
B (1) B4
C4 B5 RTD 2
C25
B6
Vflux
C28 B7
C3
C (1) B8 RTD 3
F11 B9
D1 WATCHDOG
C27 F12
OPTO 1 CONTACT B10
D2
T2 C18 F13 B11 RTD 4
D3 WATCHDOG
CONTACT F14 B12
A (2) OPTO 2
D4 E1 B13
C17 RELAY 1 E2
D5 B14 RTD 5
C20 OPTO 3 E3 B15
D6
RELAY 2 E4 B16
B (2) D7
E5 B17 RTD 6
C19 D8 OPTO 4 RELAY 3 E6 B
B18
C22 D9 E7 B19
D10 OPTO 5 RELAY 4 E8 RTD 7
C (2) B20
E9 B21
D11
C21 RELAY 5 E10
OPTO 6 B22
D12
E11 B23 RTD 8
GROUNDED WYE D13 RELAY 6 E12 B24
NEUTRAL TAILS D14 OPTO 7 E13 B25
D15 E14 B26 RTD 9
HV LV RELAY 7
OPTO 8 E15 B27
B
NOTE 4 D16
NOTE 2 E16
COMMS B28
D17 E17
COMMON RELAY 8 B29 RTD 10
D18 CONNECTION E18 B30
P2 S2
F17

P1 S1
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT NOTES:
C13 F16
SCN 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
P1 S1 TN1 C16
F1
Y (HV) (b) TERMINAL.
AC OR DC
C15 F2 x AUX SUPPLY
(c) PIN TERMINAL (P.C.B. TYPE)

CASE C3-C4 AND C1-C2 ARE USED BY THE NPS OVERVOLTAGE AND VCO PROTECTIONS.
EARTH THEY ALSO MAY DIRECTIONALIZE THE OVERCURRENT, EARTH FAULT AND
NPS OVERCURRENT ELEMENTS.

G
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED B1
20mA
TRANSFORMER MiCOM P642 (PART) N B2
T1 C24 NOTE 3 1mA OUTPUT 1
B3
A (1) n
B5
C23 20mA
F11 B6
a b c WATCHDOG 1mA OUTPUT 2
C26 F12
CONTACT B7
C3 F13
B (1) B9
WATCHDOG 20mA
CONTACT F14
C25 VFLUX B10
E1 1mA OUTPUT 3
C4
C28 RELAY 1 E2 B11
C (1) E3 B13
20mA
D1 RELAY 2 E4 B14
C27 1mA OUTPUT 4
D2 OPTO 1 E5
B15
T2 C18 RELAY 3 E6 CLIO
D3 B16
A (2) E7 20mA CURRENT LOOP
D4 OPTO 2
RELAY 4 E8 B17 INPUTS & OUTPUTS
C17 1mA INPUT 1
D5 E9 B18 NOTE 5
C20 D6 OPTO 3 RELAY 5 E10 B20
20mA
B (2) D7 E11
B21
RELAY 6 E12 1mA INPUT 2
C19 D8 OPTO 4
B22
E13
C22 D9 B24
E14 20mA
OPTO 5 RELAY 7
C (2) D10 E15 B25
1mA INPUT 3
D11 E16 B26
C21
D12 OPTO 6 E17
RELAY 8 B28
E18 20mA
GROUNDED WYE D13 B29
1mA INPUT 4
NEUTRAL TAILS D14 OPTO 7
B30
HV LV D15
NOTE 4 D16 OPTO 8 MiCOM P642 (PART)
NOTE 2
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17 NOTES:

P1 S1 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
C13 F16 (b) TERMINAL.
SCN
P1 S1 TN1 C16 (c) PIN TERMINAL (P.C.B. TYPE)
F1
Y (HV)
AC OR DC 2. WYE GROUND INPUTS APPLICABLE FOR GROUNDED (EARTHED) WINDINGS.
C15 F2 x AUX SUPPLY
5. FOR 0-10mA, 0-20mA, 4-20mA RANGE USE 20mA INPUTS & OUTPUTS
FOR 0-1mA RANGE USE 1mA INPUTS & OUTPUTS.
CASE
EARTH

J DIFFERENTIAL (8 I/P & 8 O/P + CLIO) WITH 1 POLE VT INPUT (40TE)
Drg
DO NOT SCALE Next -
A
B
A
P1 P2 P2 P1 C
A A A A A B C
S1 S2 S2 S1
T2 B B B B T1
C C C C C B N
PROTECTED n
T1 C24 B1
20mA
a b c B2
A (1) 1mA OUTPUT 1
C1 B3
C23
B5
C26 Vab OPTIONAL 20mA
C2 F11 B6
B (1) WATCHDOG 1mA OUTPUT 2
C4 CONTACT F12 B7
C25 F13
WATCHDOG B9
Vflux F14 20mA
C28 CONTACT B10
C3 E1 1mA OUTPUT 3
C (1) RELAY 1 B11
E2
D1
C27 E3 B13
OPTO 1 20mA
D2 RELAY 2 E4
T2 C18 B14
1mA OUTPUT 4
D3 E5
A (2) B15
D4 OPTO 2 RELAY 3 E6 CLIO
B16
C17 E7 20mA CURRENT LOOP
D5
RELAY 4 E8 B17 INPUTS & OUTPUTS
C20 OPTO 3 1mA INPUT 1
D6 NOTE 5
E9 B18
B (2) D7 RELAY 5 E10 B20
OPTO 4 20mA
C19 D8 E11
B21
RELAY 6 E12 1mA INPUT 2
C22 D9
B22
OPTO 5 E13
C (2) D10
E14 B24
RELAY 7 20mA
D11
C21 E15 B25
OPTO 6 1mA INPUT 3
D12 E16 B26
RELAY 8 B28
OPTO 7 E18 20mA
NEUTRAL TAILS D14
B29
1mA INPUT 4
HV LV D15
B30
NOTE 4 D16 OPTO 8
NOTE 2
COMMS
D17 MiCOM P642 (PART)
COMMON
D18 CONNECTION
P2 S2
F17 NOTES:

P1 S1
10Px4001 KBUS 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
P2 S2 Y (LV) F18
PORT
C13 F16 (b) TERMINAL.
SCN
P1 S1 TN1 C16 (c) PIN TERMINAL (P.C.B. TYPE)
F1
Y (HV)
AC OR DC
F2 x AUX SUPPLY 2. WYE GROUND INPUTS APPLICABLE FOR GROUNDED (EARTHED) WINDINGS.
C15

THEY ALSO MAY DIRECTIONALIZE THE OVERCURRENT, EARTH FAULT AND
NPS OVERCURRENT ELEMENTS.
CASE
EARTH 4. FOR COMMS OPTIONS SEE DRAWING 10Px4001.

G
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED
T1 C24 NOTE 3
A (1) n
C23
a b c
MiCOM P642 (PART)
C26
C3
B (1)
C25 VFLUX B1
F11
C4 WATCHDOG B2 OPTO 9
C28 CONTACT F12
F13 B3
C (1) WATCHDOG
D1 CONTACT F14 B4 OPTO 10
C27
OPTO 1 E1
D2 B5
T2 C18 RELAY 1 E2
D3 B6 OPTO 11
E3
A (2) OPTO 2
D4 RELAY 2 E4 B7
C17 OPTO 12
D5 E5 B8
C20 OPTO 3 RELAY 3 E6
D6
E7
B (2) D7
RELAY 4 E8 B9
C19 D8 OPTO 4 RELAY 9
E9 B10
C22 D9 RELAY 5 E10 B11

OPTO 5 B12 RELAY 10
D10 E11
C (2)
RELAY 6 E12 B13
D11
C21 E13 B14
OPTO 6 RELAY 11
D12 B15
E14
D13 RELAY 7
GROUNDED WYE E15 B16
NEUTRAL TAILS D14 OPTO 7 B17
E16 RELAY 12
D15 E17 B18
HV LV RELAY 8
D16 OPTO 8 E18
NOTE 2 NOTE 4
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17

P1 S1
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
C13
NOTES:
F16
SCN
P1 S1 TN1 C16 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
F1
Y (HV)
AC OR DC
C15 F2 x AUX SUPPLY (b) TERMINAL.

CASE (USED BY V/Hz W2 PROTECTION ONLY).
EARTH

J DIFFERENTIAL (12 I/P & 12 O/P) WITH 1 POLE VT INPUT (40TE)
Drg
DO NOT SCALE Next
Sht:
A
B
A
P1 P2 P2 P1 C
A A A A A B C
S1 S2 S2 S1
T2 B B B B T1
C C C C C B N
PROTECTED n
T1 C24
a b c
A (1)
C1
C23
MiCOM P642 (PART)
C26 Vab OPTIONAL
C2
B (1)
C4
C25 B1
F11
Vflux WATCHDOG B2 OPTO 9
C28 CONTACT F12
C3
F13 B3
C (1) WATCHDOG
D1 CONTACT F14 B4 OPTO 10
C27
OPTO 1 E1
D2 B5
T2 C18 RELAY 1 E2
D3 B6 OPTO 11
E3
A (2) OPTO 2
D4 RELAY 2 E4 B7
C17 OPTO 12
D5 E5 B8
C20 OPTO 3 RELAY 3 E6
D6
E7
B (2) D7
RELAY 4 E8 B9
E9 B10
OPTO 5 B12 RELAY 10
D10 E11
C (2)
RELAY 6 E12 B13
D11
C21 E13 B14
OPTO 6 RELAY 11
D12 B15
E14
D13 RELAY 7
GROUNDED WYE E15 B16
NEUTRAL TAILS D14 OPTO 7 B17
E16 RELAY 12
D15 E17 B18
HV LV RELAY 8
D16 OPTO 8 E18
NOTE 2 NOTE 4
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17

P1 S1 NOTES:
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
SCN
P1 S1 TN1 C16
(b) TERMINAL.
F1
Y (HV)
AC OR DC
C15

CASE THEY ALSO MAY DIRECTIONALIZE THE OVERCURRENT, EARTH FAULT AND
EARTH NPS OVERCURRENT ELEMENTS.

G
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1 A
A A A A
S1 S2 S2 S1 B
T2 B B B B T1
C
C C C C C B A B C
PHASE ROTATION
PROTECTED
T1 C24 NOTE 3
A (1) n
C23
a b c
MiCOM P642 (PART)
C26
C3
B (1)
C25 VFLUX F11
C4 WATCHDOG
C28 CONTACT F12
F13
C (1) WATCHDOG
D1 CONTACT F14
C27 B3
OPTO 1 E1
D2
T2 C18 RELAY 1 E2 RELAY 9
D3 B4
E3
A (2) OPTO 2
D4 RELAY 2 E4 B7
C17
D5 E5 RELAY 10
C20 OPTO 3 RELAY 3 E6 B8
D6 HIGH BREAK
E7 B11 CONTACTS
B (2) D7
RELAY 4 E8
E9 B12
D10 OPTO 5 E11
C (2) RELAY 12
RELAY 6 E12
D11 B16
C21 E13
D12 OPTO 6
E14
D13 RELAY 7
GROUNDED WYE E15
E16
D15 E17
HV LV RELAY 8
D16 OPTO 8 E18
NOTE 2 NOTE 4
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17

P1 S1
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
C13
NOTES:
F16
SCN
P1 S1 TN1 C16 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
F1
Y (HV) AC OR DC
C15 F2 x AUX SUPPLY (b) TERMINAL.

CASE (USED BY V/Hz W2 PROTECTION ONLY).
EARTH

J DIFFERENTIAL (8 I/P 12 O/P) WITH 1 POLE INPUT (40TE)
Drg
DO NOT SCALE Next -
A
B
A
P1 P2 P2 P1 C
A A A A A B C
S1 S2 S2 S1
T2 B B B B T1
C C C C C B N
PROTECTED n
T1 C24
a b c
A (1)
C1
C23
MiCOM P642 (PART)
C26 Vab OPTIONAL
C2
B (1)
C4
C25
F11
Vflux WATCHDOG
C28 CONTACT F12
C3
F13
C (1) WATCHDOG
D1 CONTACT F14
C27 B3
OPTO 1 E1
D2
T2 C18 RELAY 1 E2 RELAY 9
D3 B4
E3
A (2) OPTO 2
D4 RELAY 2 E4 B7
C17
D5 E5 RELAY 10
C20 OPTO 3 RELAY 3 E6 B8
D6 HIGH BREAK
E7 B11 CONTACTS
B (2) D7
RELAY 4 E8
E9 B12
D10 OPTO 5 E11
C (2) RELAY 12
D11 RELAY 6 E12 B16
C21 E13
D12 OPTO 6
E14
D13 RELAY 7
GROUNDED WYE E15
E16
D15 E17
HV LV RELAY 8
D16 OPTO 8 E18
NOTE 2 NOTE 4
COMMS
D17
COMMON
D18 CONNECTION
P2 S2
F17

P1 S1 NOTES:
10Px4001 KBUS
P2 S2 Y (LV) F18
PORT
SCN
P1 S1 TN1 C16
(b) TERMINAL.
F1
Y (HV)
AC OR DC
C15

CASE THEY ALSO MAY DIRECTIONALIZE THE OVERCURRENT, EARTH FAULT AND
EARTH NPS OVERCURRENT ELEMENTS.

G
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
S1 S2 PROTECTED S2 S1
T3 B B TRANSFORMER B B T1
C C C C C B
C B A PHASE ROTATION
MiCOM P643 (PART)

T2 T1
C24 D1
A (1) D2 OPTO 1 J11
WATCHDOG
C23 D3 CONTACT J12
OPTO 2 J13
C26 D4 WATCHDOG
CONTACT J14
B (1) D5
H1
D6 OPTO 3
C25 RELAY 1 H2
D7 H3
C28
D8 OPTO 4 RELAY 2 H4
C (1) H5
D9
NOTE 2 C27 RELAY 3 H6
D10 OPTO 5
T2 H7
C18 D11 RELAY 4 H8
P2 A (2) D12 OPTO 6 H9
S2 C17 RELAY 5 H10
D13
OPTO 7 H11
C20 D14
RELAY 6 H12
S1 B (2) D15
H13
D16 OPTO 8
P1 C19 H14
RELAY 7
D17 H15
C22 COMMON
D18 H16
CONNECTION
C (2) H17
F1 RELAY 8
C21 H18
F2 OPTO 9
T3 G1
E24 F3
RELAY 9 G2 NOTE 7
A (3) F4 OPTO 10 COMMS
G3
E23 F5 RELAY 10 G4
F6 OPTO 11 G5 J17
E26
RELAY 11 G6 SEE DRAWING
B (3) F7 EIA485/
G7 10Px4001 KBUS
TN2 F8 OPTO 12 J18
E25 RELAY 12 G8 PORT
F9 G9 J16
E28
F10 OPTO 13 RELAY 13 SCN
G10
C (3)
TN1 F11 G11 J1
E27 OPTO 14 RELAY 14 G12 AC OR DC
F12 J2 x AUX SUPPLY
G13
F13
G14
F14 OPTO 15 RELAY 15
G15
F15 G16
F16 OPTO 16 G17
RELAY 16
SEE SHEET 2 FOR NOTES F17 G18
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

CID HONG-9CRNL3 EXTERNAL CONNECTION DIAGRAM: 3 BIAS INPUT TRANSFORMER
F DIFFERENTIAL (16 I/O & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
Date: 04/12/2013 Name: H.ONG Sht: 1
DO NOT SCALE Next
Sht:
CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. EXTERNAL CONNECTION DIAGRAM: 3 BIAS INPUT TRANSFORMER
I DIFFERENTIAL (16 I/O & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1 * POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY
A A A A
T3 B B TRANSFORMER B B T1 J11 MiCOM P643 (PART)
WATCHDOG
C C C C C B CONTACT J12
C B A PHASE ROTATION J13
WATCHDOG
CONTACT J14
H1
T2 T1 C24 RELAY 1 H2
D1
A (1) D2 OPTO 1 H3
RELAY 2 H4
C23 D3
H5
D4 OPTO 2
C26 RELAY 3 H6
B (1) D5 H7
C25
D7 H9
C28 RELAY 5 H10
D8 OPTO 4
C (1) H11
D9 RELAY 6 H12
C27 OPTO 5
D10 H13
T2 C18 D11 H14
RELAY 7
P2 A (2) D12 OPTO 6 H15
S2 H16
C17 D13
H17
D14 OPTO 7 RELAY 8
C20 H18
S1 B (2) D15
G1
D16 OPTO 8
P1 C19 RELAY 9 G2 NOTE 7
D17 G3 COMMS
C22 COMMON
D18 RELAY 10 G4
CONNECTION
C (2) G5 J17
F1
C21 RELAY 11 G6 SEE DRAWING
F2 OPTO 9 EIA485/
G7 10Px4001 KBUS
T3 E24 J18
F3 RELAY 12 G8 PORT
A (3) F4 OPTO 10 G9 J16
RELAY 13 SCN
E23 F5 G10
OPTO 11 G11 J1
E26 F6
RELAY 14 G12 AC OR DC
B (3) F7 J2 x AUX SUPPLY
G13
F8 OPTO 12
GROUNDED WYE E25 G14
RELAY 15
NEUTRAL TAILS F9 G15
E28
F10 OPTO 13 G16
HV LV TV C (3) G17
F11 RELAY 16
E27 G18
P2 S2 F12 OPTO 14
F13
OPTO 15
NOTES: 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
F14
P1 S1 TN3 C12 F15
P2 S2 (b) TERMINAL.
Y (TV) F16 OPTO 16
C11 F17
2. SEE TABLE 1 FOR BIAS ASSIGNMENT TO ACTUAL WINDINGS. T1
COMMON
TN2 C14 F18 CONNECTION IS ALWAYS AN HV WINDING CONNECTION.
P1 S1
P2 S2 3. WYE GROUND INPUTS APPLICABLE FOR GROUNDED (EARTHED) WINDINGS.
Y (LV)
C13 (USED BY V/Hz W2 PROTECTION ONLY).
RST 5. (x2) DENOTES WINDINGS ENERGISED VIA TWO CT SETS. THE RELAY SOFTWARE
P1 S1 TN1 C16
SUMMATES A VIRTUAL WINDING CURRENT FROM THE TWO BIAS INPUTS.
Y (HV) 6. TV INPUTS ARE NOT MANDATORY IF THE TERTIARY HAS NO LOAD.
C15 7. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
CASE 8. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.
EARTH MiCOM P643 (PART)
METROSIL 9. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
(USED BY V/Hz W1 PROTECTION AND OTHER VOLTAGE PROTECTION).
10. DERIVED NEUTRAL POINT. SEE P64X/EN T/- - FOR DETAILS OF RESISTORS.

UP ISSUED TO D. CID HONG-95RDV7 EXT CONN DIAG:HIGH Z REF FOR 3 BIAS I/P TRANSFORMER DIFF
D SAME PRINCIPAL APPLIES TO WIRE HIGH Z REF FOR T2 &T3.
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
MiCOM P643 (PART)

T2 T1 C24 D1
A (1) D2 OPTO 1 J11
WATCHDOG
C23 D3 CONTACT J12
J13 B1
D4 OPTO 2
C26 WATCHDOG B2 RTD 1
CONTACT J14
B (1) D5 B3
H1
D6 OPTO 3 B4
C25 RELAY 1 H2
D7 H3 B5 RTD 2
C28 B6
C (1) H5 B7
D9
NOTE 2 RELAY 3 H6 B8 RTD 3
C27 OPTO 5
D10 B9
H7
T2 C18 D11 RELAY 4 H8
P2 A (2) D12 OPTO 6 H9
S2 C17 RELAY 5 H10 B28
D13
H11 B29 RTD 10
D14 OPTO 7
C20 B30
RELAY 6 H12
S1 B (2) D15
H13
D16 OPTO 8
P1 C19 H14
RELAY 7
D17 H15
C22 COMMON
D18 H16
CONNECTION
C (2) H17
F1 RELAY 8
C21 H18 NOTE 7
F2 OPTO 9 COMMS
T3 E24 G1
F3
RELAY 9 G2
A (3) F4 OPTO 10
G3
E23 F5 RELAY 10 G4
F6 OPTO 11 G5 J17
E26
B (3) F7 EIA485/
G7 10Px4001 KBUS
F8 OPTO 12 J18
F9 G9 J16
E28
G10
C (3)
F11 G11 J1
F12 J2 x AUX SUPPLY
G13
F13
G14
G15
F15 G16
F16 OPTO 16 G17
RELAY 16
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

F DIFFERENTIAL (16 I/O & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
I DIFFERENTIAL (16 I/O & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
T3 B B TRANSFORMER B B T1 MiCOM P643 (PART)
B1
C C C C C B 20mA
PHASE ROTATION B2
C B A 1mA OUTPUT 1
B3
B5
T2 T1 C24 20mA
D1 B6
J11 1mA OUTPUT 2
A (1) D2 OPTO 1 WATCHDOG
J12 B7
CONTACT
C23 D3 J13 B9
OPTO 2 WATCHDOG 20mA
C26 D4 J14 B10
CONTACT 1mA OUTPUT 3
B (1) D5 H1
B11
OPTO 3 RELAY 1 H2
C25 D6 B13
H3 20mA
D7 B14
C28 RELAY 2 H4 1mA OUTPUT 4
D8 OPTO 4
H5 B15
C (1) CLIO
D9 RELAY 3 H6 B16
NOTE 2 C27 OPTO 5 20mA CURRENT LOOP
D10 H7 INPUTS & OUTPUTS
B17
T2 C18 RELAY 4 H8 1mA INPUT 1
D11 B18 NOTE 11
P2 A (2) OPTO 6 H9
D12 B20
RELAY 5 H10 20mA
S2 C17 D13 H11 B21
OPTO 7 1mA INPUT 2
C20 D14 RELAY 6 H12 B22
D15 H13
S1 B (2) B24
OPTO 8 H14 20mA
C19 D16 RELAY 7 B25
P1 H15 1mA INPUT 3
D17 B26
C22 COMMON H16
D18 CONNECTION H17 B28
C (2) RELAY 8 20mA
F1 H18 B29
C21 1mA INPUT 4
F2 OPTO 9
G1 B30
T3 E24 RELAY 9
F3 G2
A (3) F4 OPTO 10 G3
RELAY 10 G4 NOTE 7
E23 F5 COMMS
G5
F6 OPTO 11
E26 RELAY 11 G6
F7 J17
B (3) G7
F8 OPTO 12 RELAY 12 G8 SEE DRAWING
E25 EIA485/
G9 10Px4001 KBUS
F9 J18
F10 OPTO 13
C (3) G11 J16
F11 SCN
RELAY 14 G12
E27 OPTO 14
F12 G13 J1
F13 G14 AC OR DC
RELAY 15 J2 x AUX SUPPLY
F14 OPTO 15 G15
G16
F15
G17
G18
SEE SHEET 2 FOR NOTES F17
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

G DIFFERENTIAL (16 I/O & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
I DIFFERENTIAL (16 I/O & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
T1
MiCOM P643 (PART)
T2 C24 D1
A (1) D2 OPTO 1 J11 B1
WATCHDOG
C23 D3 CONTACT J12 B2 OPTO 17
OPTO 2 J13
C26 D4 WATCHDOG B3
CONTACT J14
D5 B4 OPTO 18
B (1) H1
D6 OPTO 3 B5
C25 RELAY 1 H2
D7 H3 B6 OPTO 19
C28
D8 OPTO 4 RELAY 2 H4 B7
C (1) H5
D9 B8 OPTO 20
D10 OPTO 5 B9
T2 H7
C18 D11 B10 OPTO 21
RELAY 4 H8
P2 A (2) D12 OPTO 6 H9 B11
S2 C17 RELAY 5 H10 OPTO 22
D13 B12
OPTO 7 H11
C20 D14 B13
RELAY 6 H12
D15 B14 OPTO 23
S1 B (2) H13
D16 OPTO 8 B15
P1 C19 H14
RELAY 7
D17 H15 B16 OPTO 24
C22 COMMON
D18 H16 B17
CONNECTION
C (2) H17 COMMON
F1 RELAY 8 B18 CONNECTION
C21 H18
F2 OPTO 9
T3 E24 G1
F3
RELAY 9 G2
A (3) F4 OPTO 10 NOTE 7
G3 COMMS
E23 F5 RELAY 10 G4
F6 OPTO 11 G5 J17
E26
RELAY 11 G6
B (3) F7 SEE DRAWING
G7 EIA485/
F8 OPTO 12 10Px4001 KBUS
E25 RELAY 12 G8 J18
PORT
F9 G9
E28 J16
F10 OPTO 13 RELAY 13 G10 SCN
C (3)
F11 G11
E27 RELAY 14 J1
F12 OPTO 14 G12 AC OR DC
G13 J2 x AUX SUPPLY
F13
G14
G15
F15 G16
F16 OPTO 16 G17
RELAY 16
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

G DIFFERENTIAL (24 I/O & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
T1
MiCOM P643 (PART)
T2 C24 D1
A (1) D2 OPTO 1 J11
WATCHDOG
C23 D3 CONTACT J12
OPTO 2 J13 B1
C26 D4 WATCHDOG
J14 B2 RELAY 17
CONTACT
B (1) D5
H1 B3
D6 OPTO 3 RELAY 18
C25 RELAY 1 H2 B4
D7 H3 B5
C28 RELAY 19
C (1) H5 B7
D9
NOTE 2 C27 RELAY 3 H6 B8 RELAY 20
D10 OPTO 5
T2 H7 B9
C18 D11 RELAY 4 H8 B10 RELAY 21
P2 A (2) D12 OPTO 6 H9 B11
S2 C17 RELAY 5 H10 B12 RELAY 22
D13
OPTO 7 H11 B13
C20 D14
RELAY 6 H12 B14
D15 RELAY 23
S1 B (2) H13 B15
D16 OPTO 8
P1 C19 H14 B16
RELAY 7
D17 H15 B17
C22 RELAY 24
COMMON H16 B18
D18 CONNECTION
C (2) H17
F1 RELAY 8
C21 H18
F2 OPTO 9
T3 G1
E24 F3 NOTE 7
RELAY 9 G2 COMMS
A (3) F4 OPTO 10
G3
E23 F5 RELAY 10 G4
F6 OPTO 11 G5 J17
E26
B (3) F7 EIA485/
G7 10Px4001 KBUS
F8 OPTO 12 J18
F9 G9 J16
E28
G10
C (3)
F11 G11 J1
F12 J2 x AUX SUPPLY
G13
F13
G14
G15
F15 G16
F16 OPTO 16 G17
RELAY 16
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

F DIFFERENTIAL (16 I/O & 24 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
MiCOM P643 (PART)

T2 T1
C24 D1
A (1) D2 OPTO 1 J11
WATCHDOG
C23 D3 CONTACT J12
OPTO 2 J13
C26 D4 WATCHDOG
CONTACT J14
B (1) D5 B3
H1
D6 OPTO 3 RELAY 17
C25 RELAY 1 H2
B4
D7 H3
C28 B7
C (1) H5 RELAY 18
D9 B8
D10 OPTO 5 HIGH BREAK
T2 H7 B11 CONTACTS
C18 D11 RELAY 4 H8 RELAY 19
P2 A (2) D12 OPTO 6 H9 B12
S2 C17 RELAY 5 H10
D13 B15
OPTO 7 H11
C20 D14 RELAY 20
RELAY 6 H12 B16
S1 B (2) D15
H13
D16 OPTO 8
P1 C19 H14
RELAY 7
D17 H15
C22 COMMON
D18 H16
CONNECTION
C (2) H17
F1 RELAY 8
C21 H18 NOTE 7
F2 OPTO 9 COMMS
T3 E24 G1
F3
RELAY 9 G2
A (3) F4 OPTO 10
G3
E23 F5 RELAY 10 G4
F6 OPTO 11 G5 J17
E26
B (3) F7 EIA485/
G7 10Px4001 KBUS
F8 OPTO 12 J18
F9 G9 J16
E28
G10
C (3)
F11 G11 J1
F12 J2 x AUX SUPPLY
G13
F13
G14
G15
F15 G16
F16 OPTO 16 G17
RELAY 16
COMMON
F18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

F DIFFERENTIAL (16 I/P 20 O/P) WITH 4 POLE VT INPUT (60TE)
Drg
DO NOT SCALE Next
Sht:
I DIFFERENTIAL (16 I/P 20 O/P) WITH 4 POLE VT INPUT (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C B
C C C C PHASE ROTATION
C B A T1
T2 D24 E1 MiCOM P643 (PART)
A (1) E2 OPTO 1 M11 C1
WATCHDOG
D23 E3 CONTACT M12 C2 OPTO 25
OPTO 2 M13
D26 E4 WATCHDOG C3
CONTACT M14
E5 C4 OPTO 26
B (1) L1
E6 OPTO 3 C5
D25 RELAY 1 L2
E7 L3 C6 OPTO 27
D28
E8 OPTO 4 RELAY 2 L4 C7
C (1) L5
E9 C8 OPTO 28
NOTE 2 D27 RELAY 3 L6
E10 OPTO 5 C9
T2 L7
D18 E11 C10 OPTO 29
RELAY 4 L8
P2 A (2) E12 OPTO 6 L9 C11
S2 D17 RELAY 5 L10 OPTO 30
E13 C12
OPTO 7 L11
D20 E14 C13
RELAY 6 L12
E15 C14 OPTO 31
S1 B (2) L13
E16 OPTO 8 C15
P1 D19 L14
RELAY 7
E17 L15 C16 OPTO 32
D22 COMMON
E18 L16 C17
CONNECTION
C (2) L17 COMMON
G1 RELAY 8 C18 CONNECTION
D21 L18
G2 OPTO 9 B1
T3 F24 K1
G3 B2 OPTO 33
RELAY 9 K2
A (3) G4 OPTO 10 B3
K3
F23 G5 RELAY 10 K4 B4 OPTO 34
G6 OPTO 11 K5 B5
F26
RELAY 11 K6 OPTO 35
B (3) G7 B6
OPTO 12 K7
F25 G8 B7
RELAY 12 K8
G9 B8 OPTO 36
F28 K9
G10 OPTO 13 RELAY 13 K10 B9
C (3)
G11 K11 B10 OPTO 37
F27 OPTO 14 RELAY 14 K12
G12 B11
K13 OPTO 38
G13 B12
K14
G14 OPTO 15 RELAY 15 B13
K15
G15 K16 B14 OPTO 39
G16 OPTO 16 K17 B15

RELAY 16
SEE SHEET 2 FOR NOTES G17 K18 B16 OPTO 40
COMMON
G18 J1 B17
CONNECTION
RELAY 17 J2 COMMON
H1 B18 CONNECTION
J3
H2 OPTO 17
RELAY 18 J4
H3 J5 NOTE 7
H4 OPTO 18 RELAY 19 J6 COMMS
H5 J7
OPTO 19 RELAY 20 J8 M17
H6
J9
H7 SEE DRAWING EIA485/
RELAY 21 J10 10Px4001
OPTO 20 KBUS
H8 J11 M18
PORT
H9 RELAY 22 J12 M16
H10 OPTO 21 J13 SCN
J14
H11 RELAY 23 M1
OPTO 22 J15 AC OR DC
H12 M2
J16 x AUX SUPPLY
H13 J17
OPTO 23 RELAY 24
H14 J18
H15
H16 OPTO 24
H17
CASE COMMON
EARTH H18 CONNECTION
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 24 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C
MiCOM P643 (PART) N N

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4
VFLUX VEE CONNECTED VTs (ALTERNATIVE)

F3 NOTES:
1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.

GROUNDED WYE
NEUTRAL TAILS (b) TERMINAL.
TV LV HV (c) PIN TERMINAL (P.C.B. TYPE)

NOTE 3
S2 P2 IS ALWAYS AN HV WINDING CONNECTION.
D12 TN3 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.

S1 P1
Y (TV) S2 P2
D11
6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.
D14 TN2
S1 P1
7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
Y (LV) S2 P2 (USED BY V/Hz W1 PROTECTION AND OTHER VOLTAGE PROTECTION).
D13 8. DERIVED NEUTRAL POINT. SEE P64X/EN T/- - FOR DETAILS OF RESISTORS.
D16 TN1
S1 P1
Y (HV)
D15

D DIFFERENTIAL (40 I/O & 24 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
S1 S2 PROTECTED S2 S1 T1
T3 B B TRANSFORMER B B
C B
C C C C PHASE ROTATION
C B A
T1 MiCOM P643 (PART)
T2 D24 E1 C1
A (1) E2 OPTO 1 M11 C2 OPTO 33
WATCHDOG
D23 E3 CONTACT M12 C3
OPTO 2 M13 OPTO 34
D26 E4 WATCHDOG C4
CONTACT M14
B (1) E5 C5
L1
E6 OPTO 3 C6 OPTO 35
D25 RELAY 1 L2
E7 L3 C7
D28
E8 OPTO 4 RELAY 2 L4 C8 OPTO 36
C (1) L5
E9 C9
T2 L7
D18 E11 C11
RELAY 4 L8
P2 A (2) E12 OPTO 6 L9 C12 OPTO 38
S2 D17 RELAY 5 L10
E13 C13
OPTO 7 L11 OPTO 39
D20 E14 C14
RELAY 6 L12
S1 B (2) E15 L13 C15
P1 D19 L14
RELAY 7
E17 L15 C17
D22 COMMON COMMON
E18 L16 C18
CONNECTION CONNECTION
C (2) L17
G1 RELAY 8
D21 L18
G2 OPTO 9
T3 K1
F24 G3
RELAY 9 K2
A (3) G4 OPTO 10
K3
F23 G5 RELAY 10 K4
G6 OPTO 11 K5
F26
RELAY 11 K6
B (3) G7
OPTO 12 K7
G8 B1
F25 RELAY 12 K8
G9 B2 RTD 1
F28 K9
OPTO 13 B3
G10 RELAY 13 K10
C (3) B4
G11 K11
B5 RTD 2
F27 OPTO 14 RELAY 14 K12
G12 B6
K13
G13 B7
K14
G14 OPTO 15 RELAY 15 B8 RTD 3
K15
B9
G15 K16
G16 OPTO 16 K17
RELAY 16
SEE SHEET 2 FOR NOTES G17 K18
B28
COMMON
G18 CONNECTION B29 RTD 10
H1 J1 B30
H2 OPTO 17 OPTO 25 J2
H3 J3
H5 J5
H6 OPTO 19 OPTO 27 J6 NOTE 7
COMMS
H7 J7
H9 J9
H10 OPTO 21 OPTO 29 J10 M17
H11 J11
SEE DRAWING EIA485/
H12 OPTO 22 OPTO 30 J12 10Px4001 KBUS
M18
H13 J13 PORT
OPTO 23 OPTO 31 M16
H14 J14 SCN
H15 J15
OPTO 24 OPTO 32 M1
H16 J16 AC OR DC
M2 x AUX SUPPLY
H17 J17
COMMON COMMON
H18 CONNECTION CONNECTION J18
CASE
EARTH
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:

GROUNDED WYE
NOTE 3
TN3 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.
D12 S1 P1
Y (TV) S2 P2
D11
TN2 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.
D14 S1 P1
TN1
D16 S1 P1
Y (HV)
D15

D DIFFERENTIAL (40 I/O & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C1
C C C C C B
PHASE ROTATION C2 OPTO 33
C B A
C3
C4 OPTO 34
T2 T1
D24 E1
M11 C5
A (1) E2 OPTO 1 WATCHDOG
M12 C6 OPTO 35
CONTACT
D23 E3 M13 C7
E4 OPTO 2 WATCHDOG
D26 CONTACT M14 OPTO 36
C8
E5 L1
B (1) C9
OPTO 3 RELAY 1 L2
D25 E6 OPTO 37
L3 C10
E7
D28 RELAY 2 L4 C11
E8 OPTO 4
L5 C12 OPTO 38
C (1)
E9 RELAY 3 L6
NOTE 2 D27 C13
E10 OPTO 5 L7
C14 OPTO 39
T2 RELAY 4 L8
D18 E11
L9 C15
P2 A (2) E12 OPTO 6
RELAY 5 L10 C16 OPTO 40
S2 D17 E13 L11 C17
E14 OPTO 7 RELAY 6 COMMON
D20 L12
C18 CONNECTION
S1 E15 L13
B (2)
OPTO 8 L14
D19 E16 RELAY 7
P1 L15
E17
D22 COMMON L16
E18 CONNECTION L17
C (2) RELAY 8 B1
G1 L18 20mA
D21 B2
G2 OPTO 9 1mA OUTPUT 1
K1
T3 F24 B3
G3 RELAY 9 K2
A (3) G4 OPTO 10 K3 B5
20mA
RELAY 10 K4 B6
F23 G5 1mA OUTPUT 2
K5 B7
G6 OPTO 11
F26 RELAY 11 K6
G7 B9
B (3) K7 20mA
F25 1mA OUTPUT 3
G9 K9 B11
F28 RELAY 13 K10
G10 OPTO 13 B13
20mA
C (3) K11 B14
G11 RELAY 14 1mA OUTPUT 4
F27 K12
G12 OPTO 14 B15
K13 CLIO
G13 K14 B16
20mA CURRENT LOOP
RELAY 15
G14 OPTO 15 K15 B17 INPUTS & OUTPUTS
1mA INPUT 1
K16 B18 NOTE 11
G15
K17 B20
G16 OPTO 16 RELAY 16
K18 20mA
SEE SHEET 2 FOR NOTES G17 B21
1mA INPUT 2
COMMON B22
G18 CONNECTION
J1 H1 J1 B24
20mA
OPTO 25 J2 H2 OPTO 17 OPTO 25 J2 B25
1mA INPUT 3
J3 H3 J3 B26
20mA
J5 H5 J5 B29
1mA INPUT 4
J7 H7 J7
OPTO 28 J8 H8 OPTO 20 OPTO 28 J8
J9 H9 J9 NOTE 7
OPTO 29 J10 H10 OPTO 21 OPTO 29 J10 COMMS
J11 H11 J11

OPTO 30 J12 H12 OPTO 22 OPTO 30 J12
M17
J13 H13 J13
SEE DRAWING EIA485/
OPTO 31 J14 H14 OPTO 23 OPTO 31 J14 10Px4001 KBUS
M18
J15 H15 J15 PORT
OPTO 32 J16 H16 OPTO 24 OPTO 32 J16 M16
SCN
J17 H17 J17
COMMON COMMON COMMON M1
CONNECTION J18 H18 CONNECTION CONNECTION J18
AC OR DC
M2 x AUX SUPPLY
CASE
EARTH
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:

GROUNDED WYE
NOTE 3
D12 TN3 S1 P1 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.

Y (TV) S2 P2
D11
D14 TN2 S1 P1
D16 TN1 S1 P1 9. FOR 0-10mA, 0-20mA, 4-20mA RANGE USE 20mA INPUTS & OUTPUTS
Y (HV)
D15

D DIFFERENTIAL (40 I/O & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
T2 T1
D24 E1 MiCOM P643 (PART)
A (1) E2 OPTO 1 M11
WATCHDOG
D23 E3 CONTACT M12 B1
OPTO 2 M13
D26 E4 WATCHDOG B2 RTD 1
CONTACT M14
E5 B3
B (1) L1
OPTO 3 B4
D25 E6 RELAY 1 L2
B5 RTD 2
E7 L3
B6
D28
E8 OPTO 4 RELAY 2 L4
B7
C (1) L5
E9 B8 RTD 3
E10 OPTO 5 B9
T2 L7
D18 E11 RELAY 4 L8
P2 A (2) E12 OPTO 6 L9
B28
S2 D17 RELAY 5 L10
E13 B29 RTD 10
OPTO 7 L11
D20 E14 B30
RELAY 6 L12
S1 B (2) E15
L13
E16 OPTO 8
D19 L14
P1 RELAY 7
E17 L15 C1
D22 COMMON 20mA
E18 L16 C2
CONNECTION 1mA OUTPUT 1
C (2) L17
G1 RELAY 8 C3
D21 L18
G2 OPTO 9 C5
T3 20mA
F24 G3 C6
J1 1mA OUTPUT 2
A (3) G4 OPTO 10 OPTO 25 C7
J2
F23 G5 J3 C9
20mA
G6 OPTO 11 OPTO 26 C10
F26 J4 1mA OUTPUT 3
B (3) G7 J5 C11
F25 J6 20mA
G9 J7 C14
F28 1mA OUTPUT 4
J8
C (3) CLIO
G11 J9 C16
F27 20mA CURRENT LOOP
G12 OPTO 14 OPTO 29 C17 INPUTS & OUTPUTS
J10 1mA INPUT 1
G13 C18 NOTE 11
J11
J12 20mA
G15 J13 C21
1mA INPUT 2
J14
SEE SHEET 2 FOR NOTES G17 J15 C24
COMMON 20mA
G18 CONNECTION OPTO 32 J16 C25
1mA INPUT 3
H1 J17 C26
OPTO 17 COMMON
H2 J18 C28
CONNECTION 20mA
H3 K1 C29
1mA INPUT 4
H4 OPTO 18 OPTO 33 C30
K2
H5 K3
H6 OPTO 19 OPTO 34 K4
H7 K5
H8 OPTO 20 OPTO 35 NOTE 7
K6
COMMS
H9 K7
H11 K9
OPTO 22 M17
H12 OPTO 37 K10
K11 10Px4001 KBUS
H14 OPTO 23 OPTO 38 M18
K12 PORT
H15 K13 M16
OPTO 24 SCN
H16 OPTO 39 K14
H17 K15 M1
COMMON AC OR DC
H18 CONNECTION OPTO 40 K16 M2 x AUX SUPPLY
CASE
EARTH K17
COMMON
CONNECTION K18
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 8 O/P+RTD+CLIO) WITH 4 POLE VT I/P (80TE)
Drg
DO NOT SCALE Next
Sht:
D DIFFERENTIAL (40 I/O & 8 O/P+RTD+CLIO) WITH 4 POLE VT I/P (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
T2 T1 D24 E1 MiCOM P643 (PART)
A (1) E2 OPTO 1 M11 C1
WATCHDOG
D23 E3 CONTACT M12 OPTO 25
C2
OPTO 2 M13
D26 E4 WATCHDOG C3
CONTACT M14
B (1) E5 C4 OPTO 26
L1
E6 OPTO 3
D25 RELAY 1 L2 C5
E7 L3 C6 OPTO 27
D28
C7
C (1) L5
E9 C8 OPTO 28
E10 OPTO 5
L7 C9
T2 D18 OPTO 29
E11 RELAY 4 L8 C10
P2 A (2) E12 OPTO 6 L9 C11
S2 D17 RELAY 5 L10 OPTO 30
E13 C12
OPTO 7 L11
D20 E14 C13
RELAY 6 L12
S1 E15 C14 OPTO 31
B (2) L13
E16 OPTO 8
D19 L14 C15
P1 RELAY 7
E17 L15 C16 OPTO 32
D22 COMMON
E18 L16
CONNECTION C17
C (2) L17 COMMON
G1 RELAY 8 C18
L18 CONNECTION
D21
G2 OPTO 9
T3 F24 K1 B1
G3
RELAY 9 K2 B2 OPTO 33
A (3) G4 OPTO 10
K3 B3
F23 G5 RELAY 10 K4
B4 OPTO 34
G6 OPTO 11 K5
F26
RELAY 11 K6 B5
B (3) G7
K7 B6 OPTO 35
G8 OPTO 12
F25 RELAY 12 K8 B7
G9
F28 K9 B8 OPTO 36
G10 OPTO 13 RELAY 13 K10
C (3) B9
G11 K11
F27 B10 OPTO 37
OPTO 14 RELAY 14 K12
G12
K13 B11
G13
K14 B12 OPTO 38
K15 B13
G15 K16
B14 OPTO 39
G16 OPTO 16 K17
RELAY 16 B15
SEE SHEET 2 FOR NOTES G17 K18
COMMON B16 OPTO 40
G18 CONNECTION
B17
H1 COMMON
B18 CONNECTION
H2 OPTO 17
H3
H4 OPTO 18
H5 J3
H6 OPTO 19
RELAY 17 NOTE 7
J4
H7 COMMS
H8 OPTO 20 J7
H9 RELAY 18
J8
H10 OPTO 21
J11 M17
H11
RELAY 19 SEE DRAWING
H12 OPTO 22 J12 EIA485/
10Px4001 KBUS
H13 J15 M18
PORT
H14 OPTO 23 M16
RELAY 20
J16 SCN
H15
H16 OPTO 24 M1
AC OR DC
H17 M2 x AUX SUPPLY
COMMON
H18 CONNECTION
CASE
EARTH
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 20 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:

GROUNDED WYE
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV
NOTE 3

Y (TV) (USED BY V/Hz W2 PROTECTION ONLY).
S2 P2
D11 5. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
D14 TN2 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.

S1 P1
Y (LV) 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
S2 P2
D13
D16 TN1 S1 P1
Y (HV)
D15

D DIFFERENTIAL (40 I/O & 20 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C C C C C B
E1 MiCOM P643 (PART)

T1
T2 D24 OPTO 1
E2
A (1) E3 M11 C1
WATCHDOG
D23 OPTO 2 CONTACT M12 OPTO 33
E4 C2
M13
D26 E5 WATCHDOG C3
CONTACT M14
B (1) E6 OPTO 3 C4 OPTO 34
L1
D25 E7 RELAY 1 L2 C5
E8 OPTO 4 L3 C6 OPTO 35
D28
RELAY 2 L4
E9 C7
C (1) L5
E11 L7 C9
T2
D18 OPTO 6 OPTO 37
E12 RELAY 4 L8 C10
P2 A (2) L9
E13 C11
S2 D17 OPTO 7 RELAY 5 L10 OPTO 38
E14 C12
L11
D20 E15 C13
RELAY 6 L12
S1 B (2) E16 OPTO 8 C14 OPTO 39
L13
P1 D19 E17 L14 C15

COMMON RELAY 7
E18 L15 C16 OPTO 40
D22 CONNECTION
L16
G1 C17
C (2) L17 COMMON
G2 OPTO 9 RELAY 8 C18
L18 CONNECTION
D21
G3
T3 F24
G4 OPTO 10
A (3) G5
K3
F23 G6 OPTO 11
RELAY 9
F26 G7 K4
B (3) G8 OPTO 12 K7 B1
F25 G9 RELAY 10 B2 RTD 1
OPTO 13 K8 B3
G10
F28
K11 B4
G11
C (3) B5 RTD 2
F27 K12 B6
G13 B7
K15
G14 OPTO 15 B8 RTD 3
RELAY 12
G15 K16 B9
G16 OPTO 16
G17
COMMON B28
SEE SHEET 2 FOR NOTES G18 CONNECTION RTD 10
B29
H1 B30
J1
H3 J3
COMMS
H5 J5
H7 J7
H8 OPTO 20 OPTO 28 J8 M17
H9 J9 SEE DRAWING EIA485/
H10 OPTO 21 OPTO 29 J10 10Px4001 KBUS
M18
PORT
H11 J11
M16
H12 OPTO 22 OPTO 30 J12 SCN
H13 J13
M1
H14 OPTO 23 OPTO 31 J14 AC OR DC
M2 x AUX SUPPLY
H15 J15
H17 J17
COMMON COMMON
CASE
EARTH
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 12 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:

GROUNDED WYE
NOTE 3

Y (TV) S2 P2
D11
D14 TN2 S1 P1
D16 TN1 S1 P1
Y (HV)
D15

D DIFFERENTIAL (40 I/O & 12 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A A
C1
C C C C C B
PHASE ROTATION C2 OPTO 33
C B A
C3
E1 C4 OPTO 34
T2 T1 D24
E2 OPTO 1
M11 C5
A (1) E3 WATCHDOG
M12 C6 OPTO 35
CONTACT
D23 E4 OPTO 2
M13 C7
WATCHDOG
D26 E5 CONTACT M14 OPTO 36
C8
E6 OPTO 3 L1
B (1) C9
RELAY 1 L2
D25 E7 C10 OPTO 37
L3
E8 OPTO 4
D28 RELAY 2 L4 C11
E9 L5 C12 OPTO 38
C (1)
NOTE 2 D27 C13
E11 L7
C14 OPTO 39
T2 D18 RELAY 4 L8
E12 OPTO 6
L9 C15
P2 A (2) E13 RELAY 5 C16 OPTO 40
S2 L10
D17 E14 OPTO 7
L11 C17
D20 E15 RELAY 6 L12 COMMON
C18 CONNECTION
S1 E16 OPTO 8 L13
B (2)
L14
D19 E17 RELAY 7
P1 L15
COMMON
E18 CONNECTION B1
D22 L16
20mA
G1 L17 B2
C (2) RELAY 8 1mA OUTPUT 1
G2 OPTO 9 L18
D21 B3
G3 B5
T3 F24 OPTO 10 20mA
G4 B6
A (3) 1mA OUTPUT 2
G5 B7
K3
F23 G6 OPTO 11
RELAY 9 B9
20mA
F26 G7 K4
B10
OPTO 12 1mA OUTPUT 3
B (3) G8 K7 B11
F25 G9 RELAY 10 B13
K8 20mA
G10 OPTO 13
F28 B14
K11 1mA OUTPUT 4
G11 B15
C (3)
G12 OPTO 14 RELAY 11 CLIO
F27 K12 B16
20mA CURRENT LOOP
G13 B17 INPUTS & OUTPUTS
K15 1mA INPUT 1
G14 OPTO 15 NOTE 11
RELAY 12 B18
G15 K16
B20
OPTO 16 20mA
G16 B21
1mA INPUT 2
G17 B22
SEE SHEET 2 FOR NOTES COMMON
G18 CONNECTION B24
20mA
H1 J1 B25
1mA INPUT 3
H2 OPTO 17 OPTO 25 J2 B26
H3 J3 B28
OPTO 18 OPTO 26 20mA
H4 J4 B29
1mA INPUT 4
H5 J5 B30
H7 J7
H9 J9 COMMS

H11 J11 M17
SEE DRAWING EIA485/
H13 J13 10Px4001 KBUS
M18
H14 OPTO 23 OPTO 31 J14 PORT
M16
H15 J15 SCN
M1
H17 J17 AC OR DC
COMMON COMMON M2 x AUX SUPPLY
CASE
EARTH
MiCOM P643 (PART)

C DIFFERENTIAL (40 I/O & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:

GROUNDED WYE
NOTE 3
D12 TN3 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.

S1 P1
Y (TV) S2 P2
D11
D14 TN2
S1 P1
D16 TN1 9. FOR 0-10mA, 0-20mA, 4-20mA RANGE USE 20mA INPUTS & OUTPUTS
S1 P1
Y (HV)
D15

CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. TERMINAL F1 WAS E1. EXTERNAL CONNECTION DIAGRAM: 3 BIAS INPUT TRANSFORMER
D DIFFERENTIAL (40 I/O & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
B PROTECTED TRANSFORMER B B
T5 T1
C C C C B
C B A C B A C B A PHASE ROTATION
T4 T3 T1
T2 C24
A (1)
C23
C26
B (1)
C25
D2 OPTO 1
C28
D3 J11
WATCHDOG
C (1) OPTO 2 CONTACT J12
D4
NOTE 2 C27 J13
D5 WATCHDOG
T2 CONTACT J14
C18 D6 OPTO 3
H1
P2 A (2) D7 RELAY 1 H2
S2 C17 D8 OPTO 4 H3
RELAY 2 H4
C20 D9
OPTO 5 H5
S1 D10
B (2) RELAY 3 H6
D11 H7
P1 C19
C22
D13 H9
C (2) OPTO 7 RELAY 5 H10
D14
C21 H11
D15
RELAY 6 H12
T3 E24 OPTO 8
D16 H13
P2 A (3) D17 H14
COMMON RELAY 7
S2 E23 D18 H15
CONNECTION
H16
E26 F1
H17
F2 OPTO 9 RELAY 8
S1 B (3) H18
F3
P1 E25 G1
F4 OPTO 10
RELAY 9 G2
E28
F5 G3
C (3) OPTO 11
F6 RELAY 10 G4
E27 G5 NOTE 7
F7
T4 RELAY 11 COMMS
E18 OPTO 12 G6
F8
G7
P2 A (4) F9
RELAY 12 G8
S2 E17 F10 OPTO 13
G9
F11 RELAY 13 G10
E20 J17
F12 OPTO 14 G11
S1 B (4) SEE DRAWING
RELAY 14 G12 EIA485/
F13 10Px4001. KBUS
P1 E19 G13 J18
F14 OPTO 15 PORT
E22 G14
RELAY 15 J16
F15 G15 SCN
C (4) OPTO 16
F16 G16
E21 G17 J1
F17 RELAY 16 AC OR DC
T5 COMMON G18 J2 x AUX SUPPLY
E12 F18 CONNECTION
A (5)
E11
E14
B (5)
E13
E16
C (5) * POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY
CASE
E15 EARTH
SEE SHEET 2 FOR NOTES MiCOM P645 (PART)

E DIFFERENTIAL (16 I/P & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
C2 VA C2 VA
a b c
C1 C1
C4 VB C4 VB
OPTIONAL
C3 C3
NOTE 6
E2 VC E2 VC
NOTE 8
E1 VN E1 VN
E4

E3 NOTES:
1.
(a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
GROUNDED WYE

NOTE 3 2. SEE TABLE 1 FOR BIAS ASSIGNMENT TO ACTUAL WINDINGS. T1
IS ALWAYS AN HV WINDING CONNECTION.
S2 P2
C12 TN3 S1 P1 (USED BY V/Hz W2 PROTECTION ONLY).
Y (TV) S2 P2 5. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
C11
C14 TN2 S1 P1 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
C13 8. DERIVED NEUTRAL POINT. SEE P64X/EN T/- - FOR DETAILS OF RESISTORS.
C16 TN1 S1 P1
Y (HV)
C15

CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. TMLS C1-C4 & E1-E2 CHANGED. EXTERNAL CONNECTION DIAGRAM: 5 BIAS INPUT TRANSFORMER
J DIFFERENTIAL (16 I/P & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 B PROTECTED TRANSFORMER B B T1 MiCOM P645 (PART)
J11
C C C C B WATCHDOG
CONTACT J12
J13
WATCHDOG
CONTACT J14
T4 T3 T2 T1 C24 H1
D1 RELAY 1 H2
A (1) D2 OPTO 1
H3
C23 D3 RELAY 2 H4
C26 D4 OPTO 2 H5
RELAY 3 H6
B (1) D5
H7
D6 OPTO 3
C25 RELAY 4 H8
D7 H9
C28
C (1)
D9 H11
C27 OPTO 5 RELAY 6 H12
1 2 D10
T2 H13
C18
TO R ST D11
H14
P2 A (2) OPTO 6 RELAY 7
D12 H15
S2 C17 D13 H16
C20 D14 OPTO 7 H17 NOTE 5
RELAY 8
H18 COMMS
S1 B (2) D15
D16 OPTO 8 G1
P1 C19
RELAY 9 G2
D17
C22 COMMON G3
D18 CONNECTION RELAY 10
C (2) G4 J17
F1 G5
C21 SEE DRAWING
F2 OPTO 9 RELAY 11 G6 EIA485/
10Px4001. KBUS
T3 E24 F3 G7 J18
PORT
P2 OPTO 10 RELAY 12 G8
A (3) F4 J16
S2 G9 SCN
E23 F5 RELAY 13 G10
F6 OPTO 11 J1
E26 G11
AC OR DC
S1 F7 RELAY 14 G12 J2 x AUX SUPPLY
B (3)
F8 OPTO 12 G13
P1 E25 G14
F9 RELAY 15
E28 G15
F10 OPTO 13
G16
C (3) F11 G17
RELAY 16
E27 F12 OPTO 14 G18
T4 E18 F13
P2 OPTO 15
A (4) F14
S2 * POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY
E17 F15
NOTES:
F16 OPTO 16
E20 GROUNDED WYE
F17
S1 COMMON NEUTRAL TAILS 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
B (4)
F18 CONNECTION
P1 E19 TV LV HV
(b) TERMINAL.
E22 NOTE 3
C (4) S2 P2
E21
T5 E12 TN3
C12 S1 P1 3. WYE GROUND INPUTS APPLICABLE FOR GROUNDED (EARTHED) WINDINGS.
A (5)
Y (TV) S2 P2 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.
E11 (USED BY V/Hz W2 PROTECTION ONLY).
C11
E14 TN2 5. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
C14 S1 P1
B (5) 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.
Y (LV) S2 P2
E13 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
C13 1 2
E16 RST
C16 TN1 S1 P1
C (5) 8. DERIVED NEUTRAL POINT. SEE P64X/EN T/- - FOR DETAILS OF RESISTORS.
Y (HV)
E15
C15
MiCOM P645 (PART) CASE METROSIL

EARTH

CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. EXT CONN DIAG:HIGH Z REF FOR 5 BIAS I/P TRANSFORMER DIFF.
G SAME PRINCIPAL APPLIES TO WIRE HIGH Z REF FOR T2,T3,T4,T5
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 B PROTECTED TRANSFORMER B B T1
C C C C B
T4 T3 T2 T1 C24
A (1)
C23
C26
B (1)
C25
D2 OPTO 1
C28
D3 J11
WATCHDOG
C (1) OPTO 2 J12
D4 CONTACT
NOTE 2 C27 J13
D5 WATCHDOG
CONTACT J14 B1
T2 C18 OPTO 3
D6 H1 B2 RTD 1
P2 A (2) D7 RELAY 1 H2 B3
S2 C17 D8 OPTO 4 H3 B4
RELAY 2 H4 B5 RTD 2
C20 D9
OPTO 5 H5 B6
S1 D10
B (2) RELAY 3 H6 B7
D11 H7 B8 RTD 3
P1 C19
C22
D13 H9
D14
C21 H11 B28
D15
RELAY 6 H12 B29 RTD 10
T3 E24 D16 OPTO 8
H13 B30
P2 A (3) D17 H14
COMMON RELAY 7
S2 E23 D18 H15
CONNECTION
H16
E26 F1
H17
F2 OPTO 9 RELAY 8
S1 B (3) H18
F3
P1 E25 G1
F4 OPTO 10
RELAY 9 G2
E28
F5 G3
C (3) OPTO 11
F6 RELAY 10 G4
E27 G5 NOTE 7
F7
RELAY 11 COMMS
T4 E18 OPTO 12 G6
F8
G7
P2 A (4) F9
RELAY 12 G8
S2 E17 F10 OPTO 13
G9
F11 RELAY 13 G10
E20 J17
F12 OPTO 14 G11
F13 10Px4001. KBUS
P1 E19 G13 J18
F14 OPTO 15 PORT
E22 G14
RELAY 15 J16
F15 G15 SCN
C (4) OPTO 16
F16 G16
E21 G17 J1
E12 F18 CONNECTION
A (5)
E11
E14
B (5)
E13 CASE
EARTH
E16
CASE
E15 EARTH

E DIFFERENTIAL (16 I/P & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
C2 VA C2 VA
a b c
C1 C1
C4 VB C4 VB
OPTIONAL
C3 C3
NOTE 6
E2 VC E2 VC
NOTE 8
E1 VN E1 VN
E4

E3 NOTES:

GROUNDED WYE
NOTE 3
C12 TN3 S1 P1 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.

Y (TV) S2 P2
C11
C14 TN2 S1 P1
C13 8. DERIVED NEUTRAL POINT. SEE P64X/EN T/- - FOR DETAILS OF RESISTORS.
C16 TN1 S1 P1
Y (HV)
C15

CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED.C11-C16 WAS D11-D16 EXTERNAL CONNECTION DIAGRAM: 5 BIAS INPUT TRANSFORMER
I DIFFERENTIAL (16 I/P & 16 O/P + RTD) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 B PROTECTED TRANSFORMER B B T1
C C C C B
T4 T3 T2 T1
C24
A (1)
C23
C26
B (1)
MiCOM P645 (PART)
D1
C25 B1
OPTO 1 20mA
D2
C28 B2
D3 J11 1mA OUTPUT 1
WATCHDOG B3
D4
NOTE 2 C27 J13 B5
WATCHDOG 20mA
D5 J14
T2 CONTACT B6
C18 D6 OPTO 3 1mA OUTPUT 2
H1
B7
P2 A (2) D7 RELAY 1 H2
B9
S2 D8 OPTO 4 H3 20mA
C17
RELAY 2 H4 B10
D9 1mA OUTPUT 3
C20 H5 B11
D10 OPTO 5
S1 B (2) RELAY 3 H6 B13
20mA
D11 H7
P1 C19 B14
D12 OPTO 6 RELAY 4 H8 1mA OUTPUT 4
C22 B15
D13 H9 CLIO
C (2) RELAY 5 H10 B16
OPTO 7 20mA CURRENT LOOP
D14
H11 B17 INPUTS & OUTPUTS
C21 1mA INPUT 1
D15 RELAY 6 H12 NOTE 11
B18
T3 E24 OPTO 8
D16 H13
B20
P2 A (3) H14 20mA
D17 RELAY 7
COMMON B21
S2 D18 H15 1mA INPUT 2
E23 CONNECTION
H16 B22
E26 F1
H17 B24
OPTO 9 RELAY 8 20mA
S1 F2 H18
B (3) B25
1mA INPUT 3
F3
P1 E25 G1 B26
F4 OPTO 10
RELAY 9 G2
E28 B28
F5 20mA
G3
C (3) B29
OPTO 11 RELAY 10 G4 1mA INPUT 4
F6
G5 B30
E27
F7
T4 RELAY 11 G6
E18 F8 OPTO 12
G7
P2 A (4) F9 NOTE 7
RELAY 12 G8 COMMS
S2 E17 F10 OPTO 13 G9
F11 RELAY 13 G10
E20 J17
OPTO 14 G11
S1 F12 SEE DRAWING
B (4) RELAY 14 G12 EIA485/
F13 10Px4001. KBUS
P1 E19 G13 J18
OPTO 15 PORT
F14 G14
E22 RELAY 15 J16
F15 G15 SCN
C (4) OPTO 16 G16
F16
E21 G17 J1
COMMON G18 J2 x AUX SUPPLY
T5 E12 F18 CONNECTION
A (5)
E11
E14
B (5)
E13
E16
CASE
E15 EARTH

E DIFFERENTIAL (16 I/P & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. TMLS C11-C16 WERE D11-D16. EXTERNAL CONNECTION DIAGRAM: 5 BIAS INPUT TRANSFORMER
I DIFFERENTIAL (16 I/P & 16 O/P + CLIO) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 T1
C C C C B
T1
T4 T3 T2 C24
A (1)
C23
C26
B (1)
C25
D2 OPTO 1
C28
D3 J11
WATCHDOG
D4
NOTE 2 C27 J13
D5 WATCHDOG B1
T2 CONTACT J14
C18 D6 OPTO 3 OPTO 17
H1 B2
P2 A (2) D7 RELAY 1 H2 B3
S2 C17 D8 OPTO 4 H3 OPTO 18
B4
RELAY 2 H4
C20 D9 B5
OPTO 5 H5
S1 D10 B6 OPTO 19
B (2) RELAY 3 H6
D11 H7 B7
P1 C19
D12 OPTO 6 RELAY 4 H8 OPTO 20
B8
C22
D13 H9
B9
D14 B10 OPTO 21
C21 H11
D15 B11
RELAY 6 H12
T3 E24 OPTO 8
D16 H13 B12 OPTO 22
P2 A (3) D17 H14
RELAY 7 B13
S2 COMMON
E23 D18 CONNECTION H15 OPTO 23
B14
H16
E26 F1 B15
H17
F2 OPTO 9 RELAY 8 OPTO 24
S1 B (3) H18 B16
F3 B17
P1 E25 G1
F4 OPTO 10 COMMON
RELAY 9 G2 B18 CONNECTION
E28
F5 G3
C (3) OPTO 11
F6 RELAY 10 G4
E27 G5
F7
T4 OPTO 12 RELAY 11 G6
E18 F8 NOTE 7
G7 COMMS
P2 A (4) F9
RELAY 12 G8
S2 E17 F10 OPTO 13
G9
F11 RELAY 13 G10
E20 J17
F12 OPTO 14 G11
F13 10Px4001. KBUS
P1 E19 G13 J18
F14 OPTO 15 PORT
E22 G14
RELAY 15 J16
F15 G15 SCN
C (4) OPTO 16
F16 G16
E21 G17 J1
E12 F18 CONNECTION
A (5)
E11
E14
B (5)
E13
E16
CASE
E15 EARTH

Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
C2 VA C2 VA
a b c
C1 C1
C4 VB C4 VB
OPTIONAL
C3 C3
NOTE 6
E2 VC E2 VC
NOTE 8
E1 VN E1 VN
E4

E3
NOTES:

GROUNDED WYE
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV
NOTE 3
S2 P2
C12 TN3 S1 P1 4. THE VT MAY BE CONNECTED ACROSS ANY PHASE-PHASE PAIR.
Y (TV) S2 P2 (USED BY V/Hz W2 PROTECTION ONLY).
C14 TN2 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.

S1 P1
Y (LV) 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
S2 P2
C13
C16 TN1 S1 P1
Y (HV)
C15

I DIFFERENTIAL (24 I/P & 16 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 T1
C C C C B
T1
T4 T3 T2 C24
A (1)
C23
C26
B (1)
C25
D2 OPTO 1
C28
D3 J11
WATCHDOG
D4
NOTE 2 C27 J13
D5 WATCHDOG
T2 CONTACT J14
C18 D6 OPTO 3
H1 B1
P2 A (2) D7 RELAY 1 H2 B2 RELAY 17
S2 C17 D8 OPTO 4 H3 B3
RELAY 2 H4 B4 RELAY 18
C20 D9
OPTO 5 H5 B5
S1 D10
B (2) RELAY 3 H6 B6 RELAY 19
D11 H7 B7
P1 C19
D12 OPTO 6 RELAY 4 H8 B8 RELAY 20
C22
D13 H9 B9
C (2) OPTO 7 RELAY 5 H10 B10 RELAY 21
D14
C21 H11 B11
D15
RELAY 6 H12 B12 RELAY 22
T3 OPTO 8
E24 D16 H13 B13
P2 A (3) D17 H14 B14
COMMON RELAY 7 RELAY 23
S2 E23 D18 H15 B15
CONNECTION
H16 B16
E26 F1
H17 B17
F2 OPTO 9 RELAY 8 RELAY 24
S1 B (3) H18 B18
F3
P1 E25 G1
F4 OPTO 10
RELAY 9 G2
E28
F5 G3
C (3) OPTO 11
F6 RELAY 10 G4
E27 G5
F7
T4 RELAY 11 G6
E18 F8 OPTO 12 NOTE 7
G7 COMMS
P2 A (4) F9
RELAY 12 G8
S2 E17 F10 OPTO 13
G9
F11 RELAY 13 G10
E20 J17
F12 OPTO 14 G11
F13 10Px4001. KBUS
P1 E19 G13 J18
F14 OPTO 15 PORT
E22 G14
RELAY 15 J16
F15 G15 SCN
C (4) OPTO 16
F16 G16
E21 G17 J1
E12 F18 CONNECTION
A (5)
E11
E14
B (5)
E13
E16

CASE
E15 EARTH

Drg
DO NOT SCALE Next
Sht:
A A
B B A
C C B
A B C A B C
C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
C2 VA
C2 VA
a b c
C1
C1
C4 VB
C4 VB
OPTIONAL
C3
NOTE 6 C3
E2 VC
E2 VC
NOTE 8
E1 VN
E1 VN
E4

E3
NOTES:
GROUNDED WYE 1. (a) C.T. SHORTING LINKS MAKE BEFORE (b) DISCONNECT.
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV
NOTE 3 (c) PIN TERMINAL (P.C.B. TYPE)
S2 P2 2. SEE TABLE 1 FOR BIAS ASSIGNMENT TO ACTUAL WINDINGS.T1

C12 TN3 S1 P1
C14 TN2 S1 P1 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.
Y (LV) S2 P2 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
C13 (USED BY V/Hz W1 PROTECTION AND OTHER VOLTAGE PROTECTION).
C16 TN1 S1 P1
Y (HV)
C15

I DIFFERENTIAL (16 I/P & 24 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A MiCOM P645 (PART) MiCOM P645 (PART)
S1 S2 S2 S1
B PROTECTED TRANSFORMER B B E1
T5 T1 B1
C C C C B E2 OPTO 1 M11 B2 RTD 1
PHASE ROTATION WATCHDOG
C B A C B A C B A E3 CONTACT M12 B3
OPTO 2 M13 B4
E4 WATCHDOG
T1 CONTACT M14 B5 RTD 2
T4 T3 T2 D24 E5
L1 B6
A (1) E6 OPTO 3
RELAY 1 L2 B7
E7 L3
OPTIONAL
D23 B8 RTD 3
E8 OPTO 4 RELAY 2 L4 B9
D26
L5
E9
B (1) RELAY 3 L6
E10 OPTO 5
D25 L7 B28
E11 RELAY 4 L8 RTD 10
B29
D28 OPTO 6
E12 L9 B30
C (1) RELAY 5 L10
E13
NOTE 2 D27 OPTO 7 L11
E14
T2 RELAY 6 L12 C1
D18 E15 20mA
L13 C2
P2 A (2) E16 OPTO 8 1mA OUTPUT 1
L14
RELAY 7 C3
S2 D17 E17 L15
COMMON C5
E18 L16 20mA
D20 CONNECTION
L17 C6
S1 B (2) L18 C7
G2 OPTO 9
P1 D19 K1 C9
G3 20mA
RELAY 9 K2 C10
D22 OPTO 10 1mA OUTPUT 3
G4 K3
C (2) C11
G5 RELAY 10 K4
C13
D21 G6 OPTO 11 K5 20mA
T3 RELAY 11 C14
F24 G7 K6 1mA OUTPUT 4 OPTIONAL
K7 C15
P2 A (3) G8 OPTO 12 CLIO
RELAY 12 K8 C16
S2 G9 20mA CURRENT LOOP
F23 K9 C17 INPUTS & OUTPUTS
G10 OPTO 13 RELAY 13 1mA INPUT 1
F26 K10 NOTE 11
C18
G11 K11
S1 B (3) C20
OPTO 14 RELAY 14 K12 20mA
G12
P1 F25 K13 C21
G13 1mA INPUT 2
F28 K14 C22
K15 C24
C (3) 20mA
G15 K16
C25
F27 G16 OPTO 16 K17 1mA INPUT 3
RELAY 16 C26
T4 K18
F18 G17
COMMON C28
P2 A (4) G18 J1 20mA
CONNECTION
RELAY 17 J2 C29
S2 H1 1mA INPUT 4
F17
J3 C30
H2 OPTO 17
F20 RELAY 18 J4
H3 J5
S1 B (4)
H4 OPTO 18 RELAY 19 J6 NOTE 7
P1 F19 COMMS
H5 J7
F22 OPTO 19 RELAY 20 J8
H6
J9 M17
C (4)
H7 RELAY 21 J10 SEE DRAWING
F21 OPTO 20 EIA485/
H8 J11 10Px4001 KBUS
M18
T5 F12 H9 RELAY 22 J12 PORT
H10 OPTO 21 J13 M16

A (5)
SCN
J14
F11 H11 RELAY 23
J15 M1
H12 OPTO 22
F14 J16 AC OR DC
H13 M2 x AUX SUPPLY
B (5) J17
RELAY 24
H14 OPTO 23 J18
F13
H15
F16 OPTO 24
H16
C (5)
H17
F15 COMMON
H18 CONNECTION CASE
EARTH
SEE SHEET 2 FOR NOTES

CID HONG-9CRNL3 EXT. CONN. DIAG: 5 BIAS INPUT TRANSFORMER DIFFERENTIAL
F (24 I/P & 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV
S2 P2 2. SEE TABLE 1 FOR BIAS ASSIGNMENT TO ACTUAL WINDINGS. T1

D12 TN3 S1 P1
D14 TN2 S1 P1 6. THE VT STAR POINT MUST BE MADE EXTERNALLY AS SHOWN.

D13
D16 TN1 S1 P1
Y (HV) FOR 0-1mA RANGE USE 1mA INPUTS & OUTPUTS.
D15

CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. EXT. CONNECTION DIAG: 5 BIAS INPUT TRANSFORMER DIFFERENTIAL
I (24 I/P & 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
A A A
S1 S2 S2 S1
T5 T1
C C C C B
MiCOM P645 (PART)

T4 T3 T2 T1 C24
A (1)
C23
D1
C26 OPTO 1
D2
B (1) D3 MiCOM P645 (PART)
C25 D4 OPTO 2
C28 D5 J11
WATCHDOG
D6 OPTO 3 CONTACT J12
C (1)
J13
NOTE 2 C27 D7 WATCHDOG
OPTO 4 CONTACT J14
T2 D8 B3
C18 H1
D9 RELAY 1 H2 RELAY 17
P2 A (2) B4
D10 OPTO 5 H3
S2 C17
RELAY 2 H4 B7
D11
C20 OPTO 6 H5 RELAY 18
D12
RELAY 3 H6 B8
S1 B (2) HIGH BREAK
D13
H7 B11 CONTACTS
P1 C19 D14 OPTO 7
RELAY 4 H8 RELAY 19
C22 D15 H9 B12
C (2)
H11
C21 D17 RELAY 20
COMMON RELAY 6 H12 B16
T3 D18 CONNECTION
E24 H13
F1 H14
P2 A (3) RELAY 7
F2 OPTO 9 H15
S2 E23
F3 H16
E26 OPTO 10 H17
F4 RELAY 8
S1 B (3) H18 NOTE 7
F5 COMMS
E25 OPTO 11 G1
P1 F6
RELAY 9 G2
E28 F7
G3
F8 OPTO 12 RELAY 10
C (3) G4
F9 G5 J17
E27
F10 OPTO 13 RELAY 11 G6 SEE DRAWING
T4 E18 EIA485/
G7 10Px4001 KBUS
F11 J18
P2 A (4) RELAY 12 G8 PORT
F12 OPTO 14
S2 E17 G9 J16
F13 RELAY 13 SCN
G10
E20 OPTO 15
F14 G11 J1
S1 B (4) RELAY 14 G12 AC OR DC
F15
J2 x AUX SUPPLY
E19 OPTO 16 G13
P1 F16
G14
E22 F17 RELAY 15
COMMON G15
C (4) F18 CONNECTION G16
E21 G17
RELAY 16
G18
T5 E12
A (5)
E11
E14
B (5)
E13
E16 CASE
EARTH
C (5)
E15

E DIFFERENTIAL (24 I/P 20 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next
Sht:
H DIFFERENTIAL (24 I/P 20 O/P) WITH 4 POLE VT INPUTS (60TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1 B1
OPTO 2 M13 B4
E4 WATCHDOG
T1 CONTACT M14 B5 RTD 2
T4 T3 T2 D24 E5
L1 B6
A (1) E6 OPTO 3
RELAY 1 L2 B7
E7 L3
OPTIONAL
D23 B8 RTD 3
D26
L5
E9
B (1) RELAY 3 L6
E10 OPTO 5
D25 L7 B28
B29
D28 OPTO 6
E12 L9 B30
C (1) RELAY 5 L10
E13
E14
T2 RELAY 6 L12 C1
D18 E15 20mA
L13 C2
L14
RELAY 7 C3
S2 D17 E17 L15
COMMON C5
E18 L16 20mA
D20 CONNECTION
L17 C6
S1 B (2) L18 C7
G2 OPTO 9
P1 D19 K1 C9
G3 20mA
RELAY 9 K2 C10
D22 OPTO 10 1mA OUTPUT 3
G4 K3
C (2) C11
G5 RELAY 10 K4
C13
D21 G6 OPTO 11 K5 20mA
T3 RELAY 11 C14
F24 G7 K6 1mA OUTPUT 4
OPTIONAL
K7 C15
P2 A (3) G8 OPTO 12 CLIO
RELAY 12 K8 C16
S2 G9 20mA CURRENT LOOP
F23 K9 C17 INPUTS & OUTPUTS
G10 OPTO 13 RELAY 13 1mA INPUT 1
F26 K10 NOTE 11
C18
G11 K11
S1 B (3) C20
OPTO 14 RELAY 14 K12 20mA
G12
P1 F25 K13 C21
G13 1mA INPUT 2
F28 K14 C22
K15 C24
C (3) 20mA
G15 K16
C25
F27 G16 OPTO 16 K17 1mA INPUT 3
RELAY 16 C26
T4 K18
F18 G17
COMMON C28
P2 A (4) G18 20mA
CONNECTION
C29
S2 H1 1mA INPUT 4
F17
C30
H2 OPTO 17 J3
F20
H3 RELAY 17
S1 B (4) J4
H4 OPTO 18 NOTE 7
P1 F19 J7 COMMS
H5
H6 J8 M17
C (4) HIGH BREAK
H7 J11
CONTACTS SEE DRAWING
F21 OPTO 20 EIA485/
H8 10Px4001 KBUS
RELAY 19 M18
T5 F12 H9 J12 PORT
H10 OPTO 21 J15 M16

A (5)
SCN
F11 H11 RELAY 20
OPTO 22 J16 M1
H12 AC OR DC
F14
H13 M2 x AUX SUPPLY
B (5)
H14 OPTO 23
F13
H15
F16 OPTO 24
H16
C (5)
H17
F15 COMMON
H18 CONNECTION CASE
EARTH

CID HONG-9CRNL3 EXT. CONNECTION DIAG: 5 BIAS INPUT TRANSFORMER DIFFERENTIAL
E (24 I/P 20 O/P + CLIO & RTD)) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:

GROUNDED WYE
NOTE 3
2. SEE TABLE 1 FOR BIAS ASSIGNMENT TO ACTUAL WINDINGS. BIAS INPUT 1

Y (TV) S2 P2
D11
D14 TN2 S1 P1
Y (HV) FOR 0-1mA RANGE USE 1mA INPUTS & OUTPUTS.
D15

H (24 I/P 20 O/P + CLIO & RTD)) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1 B1
C C C C B E1 M11 B2 RTD 1
C B A C B A C B A OPTO 1 CONTACT M12 B3
E2
M13 B4
E3 WATCHDOG
CONTACT M14 B5 RTD 2
T4 T3 T2 T1 D24 OPTO 2
E4 L1 B6
A (1) E5 RELAY 1 L2 B7
OPTO 3 L3
OPTIONAL
D23 E6 B8 RTD 3
RELAY 2 L4 B9
D26 E7
OPTO 4 L5
E8
B (1) RELAY 3 L6
E9 L7
D25 B28
E10 OPTO 5 RELAY 4 L8 B29 RTD 10
D28
E11 L9 B30
C (1) OPTO 6 RELAY 5 L10
E12
NOTE 2 D27 L11
E13
RELAY 6 L12 C1
T2 D18 OPTO 7 20mA
E14 L13 C2
P2 A (2) 1mA OUTPUT 1
E15 L14
RELAY 7 C3
S2 D17 E16 OPTO 8 L15
C5
L16 20mA
D20 E17
COMMON L17 C6
RELAY 8 1mA OUTPUT 2
S1 E18 CONNECTION
B (2) L18 C7
G1
P1 D19 K1 C9
OPTO 9 20mA
G2 RELAY 9
D22 K2 C10
1mA OUTPUT 3
G3 K3
C (2) C11
G4 OPTO 10 RELAY 10 K4
C13
D21 K5 20mA
G5
RELAY 11 K6 C14
T3 F24 OPTO 11 1mA OUTPUT 4
G6 OPTIONAL
K7 C15
P2 A (3) G7 CLIO
RELAY 12 K8 C16
S2 OPTO 12 20mA CURRENT LOOP
F23 G8 K9 C17 INPUTS & OUTPUTS
RELAY 13 1mA INPUT 1
F26 G9 K10 NOTE 11
C18
G10 OPTO 13 K11
S1 B (3) C20
RELAY 14 K12 20mA
G11
P1 F25 K13 C21
OPTO 14 1mA INPUT 2
G12
F28 K14 C22
RELAY 15
G13 K15
C (3) C24
OPTO 15 20mA
G14 K16
C25
F27 K17 1mA INPUT 3
G15 RELAY 16 C26
T4 F18 OPTO 16 K18
G16
C28
P2 A (4) 20mA
G17
COMMON C29
S2 1mA INPUT 4
F17 G18 CONNECTION C30
J3
F20
RELAY 17
S1 B (4) J4
NOTE 7
P1 F19 J7 COMMS
F22 RELAY 18
H3 J8 M17
C (4) HIGH BREAK
RELAY 21 CONTACTS J11
F21
RELAY 19 10Px4001 KBUS
H7 M18
T5 F12 J12 PORT
RELAY 22 J15 M16
A (5) H8 SCN
HIGH BREAK RELAY 20
F11 H11 CONTACTS J16 M1
H12 M2 x AUX SUPPLY
B (5)
H15
F13
RELAY 24
F16 H16
C (5)
F15
CASE
EARTH

CID HONG-9CRNL3 EXT. CONNECTION DIAG: 5 BIAS INPUT TRANSFORMER DIFFERENTIAL
E (16 I/P 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3 NOTES:
GROUNDED WYE

NOTE 3
S2 P2
D12 TN3 S1 P1 (USED BY V/Hz W2 PROTECTION ONLY).
Y (TV) S2 P2
D11
D14 TN2 S1 P1 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.
Y (HV)
D15

H (16 I/P 24 O/P + CLIO & RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 B PROTECTED TRANSFORMER B B T1 E1 C1
C C C C B E2 OPTO 1 M11 C2 OPTO 25
C B A C B A C B A E3 CONTACT M12 C3
OPTO 2 M13 OPTO 26
E4 WATCHDOG C4
T1 CONTACT M14
T4 T3 T2 D24 E5 C5
L1
A (1) E6 OPTO 3 C6 OPTO 27
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 30
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
NOTE 2 D27 OPTO 7 L11 OPTO 31
E14 C14
T2 RELAY 6 L12
D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 32
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
E18 CONNECTION C18 CONNECTION
D20
L17
G1 RELAY 8 B1
S1 B (2) L18
G2 OPTO 9 B2 OPTO 33
P1 D19 K1
G3 B3
RELAY 9 K2
D22 OPTO 10 OPTO 34
G4 B4
K3
C (2)
G5 RELAY 10 K4 B5
D21 G6 OPTO 11 K5 B6 OPTO 35
T3 RELAY 11 K6
F24 G7 B7
OPTO 12 K7 OPTO 36
P2 A (3) G8 B8
RELAY 12 K8
S2 F23 G9 B9
K9
G10 OPTO 13 RELAY 13 K10 B10 OPTO 37
F26
G11 K11 B11
S1 B (3)
OPTO 14 RELAY 14 K12 OPTO 38
G12 B12
P1 F25 K13
G13 B13
F28 K14
G14 OPTO 15 RELAY 15 B14 OPTO 39
K15
C (3)
G15 K16 B15
F27 G16 OPTO 16 K17 B16 OPTO 40
T4 RELAY 16
F18 G17 K18 B17
COMMON J1 COMMON
P2 A (4) G18 CONNECTION B18 CONNECTION
RELAY 17 J2
S2 F17 H1
J3
H2 OPTO 17
F20 RELAY 18 J4
H3 J5
S1 B (4)
OPTO 18 RELAY 19 NOTE 7
H4 J6
F19 COMMS
P1 J7
H5
F22 OPTO 19 RELAY 20 J8
H6
C (4) J9
H7 RELAY 21 M17
J10
F21 H8 OPTO 20
J11 SEE DRAWING
T5 EIA485/
F12 H9 RELAY 22 J12 10Px4001 KBUS
M18
A (5) H10 OPTO 21 J13 PORT
J14 M16
F11 H11 RELAY 23 SCN
J15
H12 OPTO 22
F14 J16
M1
H13 J17 AC OR DC
B (5) RELAY 24
OPTO 23 J18 M2 x AUX SUPPLY
H14
F13
H15
F16 OPTO 24
H16
C (5)
H17
F15 COMMON
H18 CONNECTION CASE
EARTH

C (40 I/P & 24 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
CID SWOO-9LNAWE. TABLE 1 REMOVED. NOTES 5&6 REMOVED. EXT. CONN. DIAG: 5 BIAS INPUT TRANSFORMER DIFFERENTIAL
D (40 I/P & 24 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
B PROTECTED TRANSFORMER B B E1 C1
T5 T1
OPTO 2 M13 OPTO 34
E4 WATCHDOG C4
CONTACT M14
T4 T3 T2 T1 D24 E5 C5
L1
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 38
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
E14 C14
RELAY 6 L12
T2 D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 40
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
D20
L17
G1 RELAY 8
S1 B (2) L18
G2 OPTO 9
P1 D19 K1
G3
RELAY 9 K2
D22 OPTO 10
G4 K3
C (2)
G5 RELAY 10 K4
B1
D21 G6 OPTO 11 K5
B2 RTD 1
RELAY 11 K6
T3 F24 G7 B3
OPTO 12 K7
P2 A (3) G8 B4
RELAY 12 K8
S2 G9 B5 RTD 2
F23 K9
OPTO 13 B6
G10 RELAY 13 K10
F26 B7
G11 K11 OPTIONAL
S1 B (3) B8 RTD 3
G12 B9
P1 F25 K13
G13
F28 K14
K15
C (3) B28
G15 K16
B29 RTD 10
F27 G16 OPTO 16 K17
RELAY 16 B30
T4 F18 G17 K18
COMMON J1
P2 A (4) G18 CONNECTION
OPTO 25 J2
S2 F17 H1
H2 OPTO 17 J3
F20 OPTO 26
H3 J4
S1 B (4)
H4 OPTO 18 J5
P1 F19 OPTO 27
H5 J6 NOTE 7
F22 COMMS
H6 OPTO 19 J7
C (4) OPTO 28 J8
H7 M17
F21 H8 OPTO 20 J9
SEE DRAWING EIA485/
OPTO 29 J10
T5 F12 H9 10Px4001 KBUS
M18
OPTO 21 J11 PORT
A (5) H10
OPTO 30 J12 M16
F11 H11 SCN
H12 OPTO 22 J13
F14 M1
OPTO 31 J14
H13 AC OR DC
B (5) M2 x AUX SUPPLY
H14 OPTO 23 J15
F13 OPTO 32
H15 J16
F16 OPTO 24 J17
H16
COMMON
C (5) CONNECTION J18
H17
F15 COMMON
H18 CONNECTION
CASE
SEE SHEET 2 FOR NOTES EARTH

C (40 I/P & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
D (40 I/P & 16 O/P+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1
OPTO 2 M13 OPTO 34
E4 WATCHDOG C4
CONTACT M14
T4 T3 T2 T1 D24 E5 C5
L1
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 38
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
E14 C14
RELAY 6 L12
T2 D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 40
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
D20
L17
G1 RELAY 8
S1 B (2) L18
G2 OPTO 9 B1
P1 D19 K1 20mA
G3 B2
RELAY 9 K2 1mA OUTPUT 1
D22 OPTO 10
G4 K3 B3
C (2)
G5 RELAY 10 K4 B5
20mA
D21 G6 OPTO 11 K5 B6
1mA OUTPUT 2
RELAY 11 K6
T3 F24 G7 B7
OPTO 12 K7
P2 A (3) G8 B9
RELAY 12 K8 20mA
S2 F23 G9 B10
K9 1mA OUTPUT 3
F26
G11 K11 B13
S1 B (3) 20mA
G12 B14
P1 F25 K13 1mA OUTPUT 4 OPTIONAL
G13 B15
F28 K14 CLIO
G14 OPTO 15 RELAY 15 B16
K15 20mA CURRENT LOOP
C (3)
G15 K16 B17 INPUTS & OUTPUTS
1mA INPUT 1
F27 G16 OPTO 16 K17 NOTE 11
RELAY 16 B18
T4 F18 G17 K18 B20
COMMON 20mA
P2 A (4) G18 J1 B21
CONNECTION 1mA INPUT 2
S2 OPTO 25 J2
F17 H1 B22
H2 OPTO 17 J3 B24
F20 20mA
OPTO 26 J4
H3 B25
S1 B (4) 1mA INPUT 3
H4 OPTO 18 J5 B26
P1 F19 OPTO 27
H5 J6 B28
F22
20mA
H6 OPTO 19 J7 B29
OPTO 28 1mA INPUT 4
C (4) J8
H7 B30
F21 H8 OPTO 20 J9
OPTO 29 J10
T5 F12 H9
OPTO 21 J11 NOTE 7
A (5) H10 COMMS
OPTO 30 J12
F11 H11
H12 OPTO 22 J13 M17
F14
OPTO 31 J14
B (5)
OPTO 23 J15 10Px4001 KBUS
H14 M18
F13 OPTO 32 PORT
H15 J16
M16
F16 OPTO 24 J17 SCN
H16
COMMON
C (5) J18
H17 CONNECTION
M1
F15 COMMON AC OR DC
H18 CONNECTION M2 x AUX SUPPLY

CASE
EARTH

C (40 I/P & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV

D12 TN3 S1 P1
D13 (USED BY V/Hz W1 PROTECTION AND OTHER VOLTAGE PROTECTION).

D16 TN1 S1 P1
Y (HV)
D15

D (40 I/P & 16 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1 B1
OPTO 2 M13 B4
E4 WATCHDOG
CONTACT M14 B5 RTD 2
T4 T3 T2 T1 D24 E5
L1 B6
A (1) E6 OPTO 3
RELAY 1 L2 B7
E7 L3
OPTIONAL
D23 B8 RTD 3
D26
L5
E9
B (1) RELAY 3 L6
E10 OPTO 5
D25 L7 B28
B29
D28 OPTO 6
E12 L9 B30
C (1) RELAY 5 L10
E13
E14
RELAY 6 L12 C1
T2 D18 E15 20mA
L13 C2
L14
RELAY 7 C3
S2 D17 E17 L15
COMMON C5
E18 L16 20mA
D20 CONNECTION
L17 C6
S1 B (2) L18 C7
G2 OPTO 9
P1 D19 C9
G3 J1 20mA
D22 C10
G4 OPTO 10 OPTO 25 J2 1mA OUTPUT 3
C (2) C11
G5 J3
C13
D21 G6 OPTO 11 OPTO 26 J4 20mA
C14
T3 F24 G7 J5 1mA OUTPUT 4
OPTIONAL
C15
P2 A (3) G8 OPTO 12 OPTO 27 J6 CLIO
C16
S2 G9 J7 20mA CURRENT LOOP
F23
C17 INPUTS & OUTPUTS
G10 OPTO 13 OPTO 28 J8 1mA INPUT 1
F26 C18 NOTE 11
G11 J9
S1 B (3) C20
G12 OPTO 14 OPTO 29 J10 20mA
P1 F25 C21
G13 J11 1mA INPUT 2
F28 C22
G14 OPTO 15 OPTO 30 J12
C (3) C24
G15 J13 20mA
C25
F27 G16 OPTO 16 OPTO 31 J14 1mA INPUT 3
C26
T4 F18 G17 J15
COMMON C28
P2 A (4) G18 OPTO 32 J16 20mA
CONNECTION
C29
S2 H1 J17 1mA INPUT 4
F17
COMMON C30
H2 OPTO 17 J18
F20 CONNECTION
H3 K1
S1 B (4)
H4 OPTO 18 OPTO 33 K2 NOTE 7
P1 F19 COMMS
H5 K3
F22 OPTO 19 OPTO 34
H6 K4
M17
C (4)
H7 K5
SEE DRAWING EIA485/
F21 H8 OPTO 20 OPTO 35 K6 10Px4001 KBUS
M18
T5 F12 H9 K7 PORT
H10 OPTO 21 OPTO 36 K8 M16

A (5)
SCN
F11 H11 K9
OPTO 22 OPTO 37 M1
H12 K10
F14 AC OR DC
H13 K11 M2 x AUX SUPPLY
B (5)
F13
H15 K13
F16 OPTO 24 OPTO 39
H16 K14
C (5)
H17 K15
F15 COMMON OPTO 40
H18 CONNECTION K16
K17
SEE SHEET 2 FOR NOTES COMMON
CONNECTION K18
CASE
EARTH
POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY

C (40 I/P & 8 O/P+CLIO+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV

D12 TN3 S1 P1
D13
D16 TN1 S1 P1
Y (HV)
D15

D (40 I/P & 8 O/P+CLIO+RTD) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1
OPTO 2 M13 OPTO 26
E4 WATCHDOG C4
CONTACT M14
T4 T3 T2 T1 D24 E5 C5
L1
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 30
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
E14 C14
RELAY 6 L12
T2 D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 32
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
D20
L17
G1 RELAY 8 B1
S1 B (2) L18
P1 D19 K1
G3 B3
D22
RELAY 9 K2
K3
C (2)
G5 RELAY 10 K4 B5
D21 G6 OPTO 11 K5 B6 OPTO 35
RELAY 11 K6
T3 F24 G7 B7
OPTO 12 K7 OPTO 36
P2 A (3) G8 B8
RELAY 12 K8
S2 F23 G9 B9
K9
G10 OPTO 13 RELAY 13 K10 B10 OPTO 37
F26
G11 K11 B11
S1 B (3)
OPTO 14 RELAY 14 K12 OPTO 38
G12 B12
P1 F25 K13
G13 B13
F28 K14
G14 OPTO 15 RELAY 15 B14 OPTO 39
K15
C (3)
G15 K16 B15
F27 G16 OPTO 16 K17 B16 OPTO 40
RELAY 16
T4 F18 G17 K18 B17
COMMON COMMON
P2 A (4) G18 CONNECTION B18 CONNECTION
S2 F17 H1
H2 OPTO 17 J3
F20
H3 RELAY 17
S1 B (4) J4 NOTE 7
H4 OPTO 18 COMMS
P1 F19 J7
H5
H6 J8 M17
C (4) HIGH BREAK
H7 J11
CONTACTS SEE DRAWING
F21 OPTO 20 EIA485/
H8 10Px4001 KBUS
RELAY 19 M18
T5 F12 H9 J12 PORT
H10 OPTO 21 J15 M16

A (5)
SCN
F11 H11 RELAY 20
OPTO 22 J16 M1
H12
F14 AC OR DC
H13 M2 x AUX SUPPLY
B (5)
H14 OPTO 23
F13
H15
F16 OPTO 24
H16
C (5)
H17
F15 COMMON
H18 CONNECTION CASE
EARTH

C (40 I/P & 20 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV

D12 TN3 S1 P1
I Y (TV) S2 P2 (USED BY V/Hz W2 PROTECTION ONLY).
I Y (LV) S2 P2 7. THE MONITORED THREE PHASE VOLTAGE MAY BE CONNECTED HV, TV OR LV SIDE.

D16 TN1 S1 P1
I Y (HV)
D15

D (40 I/P & 20 O/P) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1 MiCOM P645 (PART) MiCOM P645 (PART)
A A A
S1 S2 S2 S1
T5 B PROTECTED TRANSFORMER B B T1 E1 C1
OPTO 2 M13 OPTO 34
E4 WATCHDOG C4
CONTACT M14
T4 T3 T2 T1 D24 E5 C5
L1
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 38
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
E14 C14
RELAY 6 L12
T2 D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 40
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
D20
L17
G1 RELAY 8
S1 B (2) L18
G2 OPTO 9
P1 D19
G3
D22 OPTO 10
G4 K3
C (2) B1
G5
RELAY 9
D21 OPTO 11 K4 B2 RTD 1
G6
B3
T3 F24 G7 K7
B4
P2 A (3) G8 OPTO 12 RELAY 10
K8 B5 RTD 2
S2 F23 G9 HIGH BREAK B6
CONTACTS K11
G10 OPTO 13 B7
F26 OPTIONAL
RELAY 11 B8 RTD 3
G11 K12
S1 B (3) B9
G12 OPTO 14
K15
P1 F25
G13
RELAY 12
F28 OPTO 15 K16
G14 B28
C (3) B29 RTD 10
G15
F27 G16 OPTO 16 J1 B30
T4 F18 G17 OPTO 25 J2
COMMON J3
P2 A (4) G18 CONNECTION
S2 OPTO 26 J4
F17 H1
H2 OPTO 17 J5
F20
OPTO 27 J6
H3
S1 B (4)
H4 OPTO 18 J7
P1 F19 OPTO 28
H5 J8 NOTE 7
F22 COMMS
H6 OPTO 19 J9
C (4) OPTO 29 J10
H7 M17
F21 H8 OPTO 20 J11
SEE DRAWING EIA485/
T5 OPTO 30 J12 10Px4001
F12 H9 KBUS
M18
OPTO 21 J13 PORT
A (5) H10
OPTO 31 J14 M16
F11 H11 SCN
H12 OPTO 22 J15
F14 M1
OPTO 32 J16
H13 AC OR DC
B (5) M2
H14 OPTO 23 J17
x AUX SUPPLY
F13 COMMON
H15 CONNECTION J18
F16 OPTO 24
H16
C (5)
H17
F15 COMMON
H18 CONNECTION CASE
EARTH
*POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY
Drg
DO NOT SCALE Next
Sht:
A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV


D12 TN3 S1 P1
D16 TN1 S1 P1
I Y (HV)
D15

Drg
DO NOT SCALE Next -
A
P1 P2 P2 P1
S1 S2 S2 S1
T5 T1
OPTO 2 M13 OPTO 34
E4 WATCHDOG C4
T1 CONTACT M14
T4 T3 T2 D24 E5 C5
L1
RELAY 1 L2
D23 E7 L3 C7
D26
L5
E9 C9
B (1) RELAY 3 L6
D25 L7
E11 RELAY 4 L8 C11
D28 OPTO 6 OPTO 38
E12 L9 C12
C (1) RELAY 5 L10
E13 C13
E14 C14
RELAY 6 L12
T2 D18 E15 C15
L13
P2 A (2) E16 OPTO 8 C16 OPTO 40
L14
RELAY 7
S2 D17 E17 L15 C17
COMMON L16 COMMON
D20
L17
G1 RELAY 8
S1 B (2) L18
G2 OPTO 9 B1
P1 D19 20mA
G3 B2
1mA OUTPUT 1
D22 OPTO 10
G4 B3
C (2) K3
G5 B5
20mA
D21 G6 OPTO 11 RELAY 9
K4 B6
1mA OUTPUT 2
T3 F24 G7 B7
K7
P2 A (3) G8 OPTO 12 B9
RELAY 10 20mA
S2 F23 G9 K8 B10
HIGH BREAK 1mA OUTPUT 3
G10 OPTO 13 CONTACTS K11 B11
F26
G11 RELAY 11 B13
S1 B (3) 20mA
OPTO 14 K12
G12 B14
P1 F25 1mA OUTPUT 4
K15 OPTIONAL
G13 B15
F28 OPTO 15 RELAY 12 CLIO
G14 B16
K16 20mA CURRENT LOOP
C (3)
G15 B17 INPUTS & OUTPUTS
1mA INPUT 1
F27 G16 OPTO 16 B18 NOTE 11
T4
F18 G17 B20
COMMON J1 20mA
P2 A (4) G18 CONNECTION OPTO 25 B21
J2 1mA INPUT 2
S2 F17 H1 B22
J3
H2 OPTO 17 B24
F20 OPTO 26 J4 20mA
H3 B25
S1 B (4) J5 1mA INPUT 3
H4 OPTO 18 B26
F19 OPTO 27 J6
P1
H5 B28
J7 20mA
F22 OPTO 19
H6 OPTO 28 B29
J8 1mA INPUT 4
C (4)
H7 B30
J9
F21 H8 OPTO 20
OPTO 29 J10
T5 F12 H9
J11 NOTE 7
A (5) H10 OPTO 21
OPTO 30 J12 COMMS
F11 H11
J13
H12 OPTO 22 M17
F14 OPTO 31 J14
B (5) J15
OPTO 23 10Px4001 KBUS
H14 OPTO 32 M18
F13 J16 PORT
H15
J17 M16
F16 OPTO 24 SCN
H16 COMMON
CONNECTION J18
C (5)
H17 M1
F15 COMMON
H18 AC OR DC
CONNECTION M2 x AUX SUPPLY
SEE SHEET 2 FOR NOTES CASE

EARTH
*POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY

C (40 I/P & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next
Sht:
NEXT STAGE :- - A A
A
B B
B
C C
A B C A B C C
A B C

NOTE 7 NOTE 4
n n
a b c a b c
D2 VA D2 VA
a b c
D1 D1
D4 VB D4 VB
OPTIONAL
D3 D3
NOTE 6
F2 VC F2 VC
NOTE 8
F1 VN F1 VN
F4

F3
NOTES:
NEUTRAL TAILS
(b) TERMINAL.
TV LV HV

D12 TN3 S1 P1
D13
D16 TN1 S1 P1
I Y (HV) FOR 0-1mA RANGE USE 1mA INPUTS & OUTPUTS.
D15

D (40 I/P & 12 O/P+CLIO) WITH 4 POLE VT INPUTS (80TE)
Drg
DO NOT SCALE Next -
Imagination at work
Grid Solutions
St Leonards Building
Redhill Business Park
Stafford, ST16 1WT, UK
+44 (0) 1785 250 070
[email protected]
© 2019 General Electric. All rights reserved. Information contained in this document is indicative only. No representation or warranty is given or
should be relied on that it is complete or correct or will apply to any particular project. This will depend on the technical and commercial
circumstances. It is provided without liability and is subject to change without notice. Reproduction, use or disclosure to third parties, without
express written authority, is strictly prohibited.
P64x-TM-EN-4.1

Micom P40 Agile: Ge Grid Solutions

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GE

MiCOM P40 Agile

Chapter 2 Safety Information 13

Chapter 3 Hardware Design 27

4.1.7 Programable LEDs 36

Chapter 4 Software Design 61

3.1 Navigating the HMI Panel 78

Chapter 6 Transformer Differential Protection 97

3.8.5 No Gap Detection Technique 113

Chapter 7 Transformer Condition Monitoring 143

5.3 Application Notes 161

Chapter 8 Restricted Earth Fault Protection 169

Chapter 9 Current Protection Functions 197

2.2.1 Timer Hold Facility 208

Chapter 10 CB Fail Protection 235

Chapter 11 Voltage Protection Functions 245

Chapter 12 Frequency Protection Functions 261

Chapter 13 Monitoring and Control 273

2.1.8 Platform Events 282

Chapter 14 Supervision 297

Chapter 15 Digital I/O and PSL Configuration 313

3 Scheme Logic 317

Chapter 16 Communications 327

5.8.2 Setup 350

6.5.3 The IEC 61850 Data Model 388

Chapter 17 Cyber-Security 401

6.7 Device Users 417

Chapter 18 Installation 429

Chapter 19 Commissioning Instructions 443

1 Chapter Overview 445

7.3.4 Contact Test 468

Chapter 20 Maintenance and Troubleshooting 477

Chapter 21 Technical Specifications 493

2.4 Rear Serial Port 2 496

11.2 Current Transformer Inputs 512

Appendix A Ordering Options 523

Appendix B Settings and Signals 525

Appendix C Wiring Diagrams 527

Figure 39: Typical overflux current waveform 106

Figure 79: Low impedance restricted Earth Fault logic 181

Figure 118: Residual voltage for an impedance earthed system 257

2.1 TARGET AUDIENCE

2.2 TYPOGRAPHICAL CONVENTIONS

3.1 PRODUCT VERSIONS

Hardware version K (P645SV) Hardware version J (P642), K (P643/5)

Hardware version P (P642), M (P643/5)

Hardware version P (P642), M (P643/5)

Figure 1: P64x version evolution

3.2 ORDERING OPTIONS

4 FEATURES AND FUNCTIONS

4.1 PROTECTION FUNCTIONS

4.2 CONTROL FUNCTIONS

Feature IEC 61850 ANSI

Feature IEC 61850 ANSI

4.3 MEASUREMENT FUNCTIONS

Measurement Function IEC 61850 ANSI

4.4 COMMUNICATION FUNCTIONS

2nd Remote Remote Local

1. The three-phase VT input is optional.