MBI5041 Macroblock
MBI5041 Macroblock
MBI5041 Macroblock
Macroblock
16-Channel Constant Current LED Driver
With 16-bit PWM Control
Features
Small Outline Package
Backward compatible with MBI5026 and MBI5030 in package
16 constant-current output channels
16-bit color depth PWM control
Scrambled-PWM technology to improve refresh rate
6-bit programmable output current gain
Constant output current range: 2~30mA @ 5.0V / 3.3V supply voltage
GF: SOP24L-300-1.00
Output current accuracy:
Between channels: <±1.5% (typ.), and
Between ICs: <±3.0% (typ.) Shrink SOP
Product Description
MBI5041 is designed for LED video applications using internal Pulse Width Modulation (PWM) control with 16-bit
color depth. MBI5041 features a 16-bit shift register which converts serial input data into each pixel gray scale of
output port. At MBI5041 output port, sixteen regulated current ports are designed to provide uniform and constant
current sinks for driving LEDs with a wide range of VF variations. The output current can be preset through an
external resistor. Moreover, the preset current of MBI5041 can be further programmed to 64 gain steps for LED
global brightness adjustment.
With Scrambled-PWM (S-PWM) technology, MBI5041 enhances Pulse Width Modulation by scrambling the “on”
time into several “on” periods. The enhancement equivalently increases the visual refresh rate. When building a
16-bit color depth video, S-PWM reduces the flickers and improves the fidelity. MBI5041 offloads the signal timing
generation of the host controller which just needs to feed data into drivers. MBI5041 drives the corresponding LEDs
to the brightness specified by image data. With MBI5041, all output channels can be built with 16-bit color depth
(65,536 gray scales). Each LED’s brightness can be calibrated enough from minimum to maximum brightness with
compensated gamma correction or LED deviation information inside the 16-bit image data.
R-EXT IO Regulator
and DAC
Comparators
Comparators
Comparators
Comparators
16 bit
GCLK Counter
16 16 16 16
SYNC
Gray Scale Pixel
LE
Buffers
GND
16
16
DCLK
GND 1 24 VDD
SDI 2 23 R- EXT
DCLK 3 22 SDO
LE 4 21 GCLK
OUT 0 5 20 OUT 15
OUT 1 6 19 OUT 14
OUT 2 7 18 OUT 13
OUT 3 8 17 OUT 12
OUT 4 9 16 OUT 11
OUT 5 10 15 OUT 10
OUT 6 11 14 OUT 9
OUT 7 12 13 OUT 8
MBI5041GF/GP
Terminal Description
Pin Name Function
GND Ground terminal for control logic and current sink
SDI Serial-data input to the shift register
Clock input terminal used to shift data on rising edge and carries
DCLK
command information when LE is asserted
LE Data strobe terminal and controlling command with DCLK
IN IN
OUT
Maximum Rating
Characteristic Symbol Rating Unit
Supply Voltage VDD 7 V
Input Pin Voltage (SDI, LE, DCLK, GCLK) VIN -0.4~VDD+0.4 V
IDD VDD
IOUT
VIH,VIL VDD
SDI OUT0
VDS
Function DCLK
Generator LE OUT15
IOL
GCLK
SDO
R-EXT GND
IOH
Logic Input
Waveform
VIH=VDD
Rext
VIL=GND
IDD VDD C1
IOUT
VIH,VIL VDD
SDI OUT0
RL
Function DCLK VDS
CL
Generator LE OUT15 RL
GCLK
R-EXT GND SDO CL
Logic Input
Waveform VLED C2
VIH=VDD Rext CSDO
VIL=GND
tW(DCLK) tW(DCLK)
DCLK DCLK
tw(LE) tw(LE)
LE LE
SDI SDI
tPD0
tPD2
SDO SDO
(2)
GCLK
tPD1
OUT4n
tDL1
OUT4n+1
tDL2
OUT4n+2
tDL3
OUT4n+3
(3)
1/FGCLK
tW(GCLK)
GCLK
tOF tOR
Data Latch
DCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3
LE
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Next Data
SDI
Global Latch
DCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3
LE
MSB
Read Configuration
DCLK 1 10 11 12 13 14 15 16 N1 N2 N3 N4 N5 N6 N7 N8 N9
LE
1. Enable writing configuration 2. Start to shift register configuration data 3. Write command
DCLK 2 3 4 15 16 1 2 3 6 7 8 15 16 1 2 3
LE
SDI Don't Care D15 D14 D13 D12 Configuration Data D1 D0 Next Data
DCLK 2 3 4 5 13 14 15 16
LE
GCLK N N +1 1 2 N N +1 N +2 N +3
OUT0~15
DCLK 00 01 02 0E 0F 10 11 12 1E 1F 20 21 22 EE EF F0 F1 F2 FD FE FF 00 01 02
LE
SDI D0F D0E D0D D01 D00 D1F D1E D1D D11 D10 D2F D2E D2D D21 D20 DFF DFE DFD DF2 DF1 DF0 D0F D0E D0D
SDO Previous Data Previous Data D0F D0E D0D D01 D00 D1F D1E D1D DD1 DD0 DEF DEE DED DE2 DE1 DE0 DFF DFE DFD
DCLK 00 01 02 0E 0F 10 11 12 1E 1F 20 21 22 EE EF F0 F1 F2 FD FE FF T0 T1 T4 T5 T6
LE
SDI D0F D0E D0D D01 D00 D1F D1E D1D D11 D10 D2F D2E D2D D21 D20 DFF DFE DFD DF2 DF1 DF0 Don't Care
SDO Previous Data Previous Data D0F D0E D0D D01 D00 D1F D1E D1D DD1 DD0 DEF DEE DED DE2 DE1 DE0 Don't Care
The sequence of output ports is from port 15 to port 0; the sequence of bits is from bit 15 to bit 0.
DCLK: “00” represents the 0 DCLK of port 15; “FF” represents the 15 DCLK of port 0.
SDI: “D0F” represents the MSB SDI of port 15; “DF0” represents the LSB SDI of port 0.
Load data from SDI Update data in buffers Move data from buffers to outputs
DCLK
LE
GCLK 1 2 N N +1 N +2 N +3
OUT0~15
Output ports are switching acording
Output ports are switching according to previous data value
to next data value
When the bit “A” is set to “1”, MBI5041 will update the next image data into output buffer immediately, no matter the
counting status of previous image data is. In this mode, system controller will synchronize the GCLK according
image data outside MBI5041 by itself. Otherwise, the conflict of previous image data and next image data will cause
the data lost.
DCLK
LE
OUT0~15
Output ports are switching
Load data from SDI according to next data value
Global latch
command
35
30
25
20
IOUT (mA)
15
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDS (V)
Figure 1
40
35
30
25
20
15
10
5
0
200 800 1400 2000 2600 3200 3800 4400 5000 5600 6200 6800
Rext(Ω)
Figure 2
Gain Gain
1.938 0.488
1.615 0.406
Default
value: 1
0.877 0.218
0.125
0.508
(DA4~DA0)
(DA4~DA0)
0,0000
0,1000
1,0000
1,1000
1,1111
0,0000
0,1000
0,1011
1,1000
1,1111
1,0000
The bit 9 to bit 4 of the configuration register set the gain of output current, i.e., G. As totally 6-bit in number, i.e.,
ranged from 6’b000000 to 6’b111111, these bits allow the user to set the output current gain up to 64 levels.
These bits can be further defined inside Configuration Register as follows:
F E D C B A 9 8 7 6 5 4 3 2 1 0
- - - - - - HC DA4 DA3 DA2 DA1 DA0 - - - -
1. Bit 9 is HC bit. The setting is in low current band when HC=0, and in high current band when HC=1.
2. Bit 8 to bit 4 are DA4 ~ DA0.
The relationship between these bits and current gain G is:
HC=1, D=(65xG-33)/3
HC=0, D=(256xG-32)/3
and D in the above decimal numeration can be converted to its equivalent in binary form by the following equation:
4 3 2 1 0
D= DA4x2 +DA3x2 +DA2x2 +DA1x2 +DA0x2
In other words, these bits can be looked as a floating number with 1-bit exponent HC and 5-bit mantissa DA4~DA0.
For example,
HC=1, G=1.246, D=(65x1.246-33)/3=16
the D in binary form would be:
4 3 2 1 0
D=16=1x2 +0x2 +0x2 +0x2 +0x2
The 6 bits (bit 5~bit 0) of the configuration register are set to 6’b110000.
Temperature (℃)
300
255℃ 260℃+0℃
-5℃
250 245℃±5℃
240℃
217℃
30s max
200
Average ramp-up Ramp-down
rate= 0.7℃/s 6℃/s (max)
Average ramp-up
rate = 0.4℃/s Average ramp-up
50 rate= 3.3℃/s
25
3 3 3
Volume mm Volume mm Volume mm
Package Thickness
<350 350-2000 ≧2000
o o o
<1.6mm 260 +0 C 260 +0 C 260 +0 C
o o o
1.6mm – 2.5mm 260 +0 C 250 +0 C 245 +0 C
o o o
≧2.5mm 250 +0 C 245 +0 C 245 +0 C
*Note: For details, please refer to Macroblock’s “Policy on Pb-free & Green Package”.
Please see the follow table for PD and Rth(j-a) for different package
The maximum power dissipation, PD(max)=(Tj–Ta)/Rth(j-a), decreases as the ambient temperature increases.
2.5
2.0
1.5
Safe Operation Area
1.0
0.5
0.0
0 10 20 30 40 50 60 70 80 90 100
Ambient Temperature (°C)
Copper foil
L2 L1
L2 L1
W1
W1
W2
W2
VDrop VDrop
VF
VF VDS VDS
MBI5041 MBI5041
MBIXXXX ○ ○
Manufacture
Code Device Version Code
Product No. Package Code
Process Code
G: Green